i82365.c revision 1.16
1 /* $NetBSD: i82365.c,v 1.16 1998/11/27 21:59:18 thorpej Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 #include <sys/kthread.h> 41 42 #include <vm/vm.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 50 #include <dev/ic/i82365reg.h> 51 #include <dev/ic/i82365var.h> 52 53 #include "locators.h" 54 55 #ifdef PCICDEBUG 56 int pcic_debug = 0; 57 #define DPRINTF(arg) if (pcic_debug) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #endif 61 62 #define PCIC_VENDOR_UNKNOWN 0 63 #define PCIC_VENDOR_I82365SLR0 1 64 #define PCIC_VENDOR_I82365SLR1 2 65 #define PCIC_VENDOR_CIRRUS_PD6710 3 66 #define PCIC_VENDOR_CIRRUS_PD672X 4 67 68 /* 69 * Individual drivers will allocate their own memory and io regions. Memory 70 * regions must be a multiple of 4k, aligned on a 4k boundary. 71 */ 72 73 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 74 75 void pcic_attach_socket __P((struct pcic_handle *)); 76 void pcic_init_socket __P((struct pcic_handle *)); 77 78 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 79 int pcic_print __P((void *arg, const char *pnp)); 80 int pcic_intr_socket __P((struct pcic_handle *)); 81 82 void pcic_attach_card __P((struct pcic_handle *)); 83 void pcic_detach_card __P((struct pcic_handle *, int)); 84 void pcic_deactivate_card __P((struct pcic_handle *)); 85 86 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 87 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 88 89 void pcic_create_event_thread __P((void *)); 90 void pcic_event_thread __P((void *)); 91 92 void pcic_queue_event __P((struct pcic_handle *, int)); 93 94 static void pcic_wait_ready __P((struct pcic_handle *)); 95 96 int 97 pcic_ident_ok(ident) 98 int ident; 99 { 100 /* this is very empirical and heuristic */ 101 102 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 103 return (0); 104 105 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 106 #ifdef DIAGNOSTIC 107 printf("pcic: does not support memory and I/O cards, " 108 "ignored (ident=%0x)\n", ident); 109 #endif 110 return (0); 111 } 112 return (1); 113 } 114 115 int 116 pcic_vendor(h) 117 struct pcic_handle *h; 118 { 119 int reg; 120 121 /* 122 * the chip_id of the cirrus toggles between 11 and 00 after a write. 123 * weird. 124 */ 125 126 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 127 reg = pcic_read(h, -1); 128 129 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 130 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 131 reg = pcic_read(h, -1); 132 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 133 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 134 return (PCIC_VENDOR_CIRRUS_PD672X); 135 else 136 return (PCIC_VENDOR_CIRRUS_PD6710); 137 } 138 } 139 /* XXX how do I identify the GD6729? */ 140 141 reg = pcic_read(h, PCIC_IDENT); 142 143 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 144 return (PCIC_VENDOR_I82365SLR0); 145 else 146 return (PCIC_VENDOR_I82365SLR1); 147 148 return (PCIC_VENDOR_UNKNOWN); 149 } 150 151 char * 152 pcic_vendor_to_string(vendor) 153 int vendor; 154 { 155 switch (vendor) { 156 case PCIC_VENDOR_I82365SLR0: 157 return ("Intel 82365SL Revision 0"); 158 case PCIC_VENDOR_I82365SLR1: 159 return ("Intel 82365SL Revision 1"); 160 case PCIC_VENDOR_CIRRUS_PD6710: 161 return ("Cirrus PD6710"); 162 case PCIC_VENDOR_CIRRUS_PD672X: 163 return ("Cirrus PD672X"); 164 } 165 166 return ("Unknown controller"); 167 } 168 169 void 170 pcic_attach(sc) 171 struct pcic_softc *sc; 172 { 173 int vendor, count, i, reg; 174 175 /* now check for each controller/socket */ 176 177 /* 178 * this could be done with a loop, but it would violate the 179 * abstraction 180 */ 181 182 count = 0; 183 184 DPRINTF(("pcic ident regs:")); 185 186 sc->handle[0].sc = sc; 187 sc->handle[0].sock = C0SA; 188 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 189 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 190 count++; 191 } else { 192 sc->handle[0].flags = 0; 193 } 194 195 DPRINTF((" 0x%02x", reg)); 196 197 sc->handle[1].sc = sc; 198 sc->handle[1].sock = C0SB; 199 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 200 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 201 count++; 202 } else { 203 sc->handle[1].flags = 0; 204 } 205 206 DPRINTF((" 0x%02x", reg)); 207 208 sc->handle[2].sc = sc; 209 sc->handle[2].sock = C1SA; 210 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], PCIC_IDENT))) { 211 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 212 count++; 213 } else { 214 sc->handle[2].flags = 0; 215 } 216 217 DPRINTF((" 0x%02x", reg)); 218 219 sc->handle[3].sc = sc; 220 sc->handle[3].sock = C1SB; 221 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], PCIC_IDENT))) { 222 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 223 count++; 224 } else { 225 sc->handle[3].flags = 0; 226 } 227 228 DPRINTF((" 0x%02x\n", reg)); 229 230 if (count == 0) 231 panic("pcic_attach: attach found no sockets"); 232 233 /* establish the interrupt */ 234 235 /* XXX block interrupts? */ 236 237 for (i = 0; i < PCIC_NSLOTS; i++) { 238 SIMPLEQ_INIT(&sc->handle[i].events); 239 #if 0 240 /* 241 * this should work, but w/o it, setting tty flags hangs at 242 * boot time. 243 */ 244 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 245 #endif 246 { 247 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 248 pcic_read(&sc->handle[i], PCIC_CSC); 249 } 250 } 251 252 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 253 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 254 vendor = pcic_vendor(&sc->handle[0]); 255 256 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 257 pcic_vendor_to_string(vendor)); 258 259 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 260 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 261 printf("sockets A and B\n"); 262 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 263 printf("socket A only\n"); 264 else 265 printf("socket B only\n"); 266 267 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 268 sc->handle[0].vendor = vendor; 269 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 270 sc->handle[1].vendor = vendor; 271 } 272 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 273 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 274 vendor = pcic_vendor(&sc->handle[2]); 275 276 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 277 pcic_vendor_to_string(vendor)); 278 279 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 280 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 281 printf("sockets A and B\n"); 282 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 283 printf("socket A only\n"); 284 else 285 printf("socket B only\n"); 286 287 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 288 sc->handle[2].vendor = vendor; 289 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 290 sc->handle[3].vendor = vendor; 291 } 292 } 293 294 void 295 pcic_attach_sockets(sc) 296 struct pcic_softc *sc; 297 { 298 int i; 299 300 for (i = 0; i < PCIC_NSLOTS; i++) 301 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 302 pcic_attach_socket(&sc->handle[i]); 303 } 304 305 void 306 pcic_attach_socket(h) 307 struct pcic_handle *h; 308 { 309 struct pcmciabus_attach_args paa; 310 311 /* initialize the rest of the handle */ 312 313 h->shutdown = 0; 314 h->memalloc = 0; 315 h->ioalloc = 0; 316 h->ih_irq = 0; 317 318 /* now, config one pcmcia device per socket */ 319 320 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 321 paa.pch = (pcmcia_chipset_handle_t) h; 322 paa.iobase = h->sc->iobase; 323 paa.iosize = h->sc->iosize; 324 325 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 326 pcic_submatch); 327 328 /* if there's actually a pcmcia device attached, initialize the slot */ 329 330 if (h->pcmcia) 331 pcic_init_socket(h); 332 } 333 334 void 335 pcic_create_event_thread(arg) 336 void *arg; 337 { 338 struct pcic_handle *h = arg; 339 const char *cs; 340 341 switch (h->sock) { 342 case C0SA: 343 cs = "0,0"; 344 break; 345 case C0SB: 346 cs = "0,1"; 347 break; 348 case C1SA: 349 cs = "1,0"; 350 break; 351 case C1SB: 352 cs = "1,1"; 353 break; 354 default: 355 panic("pcic_create_event_thread: unknown pcic socket"); 356 } 357 358 if (kthread_create(pcic_event_thread, h, &h->event_thread, 359 "%s,%s", h->sc->dev.dv_xname, cs)) { 360 printf("%s: unable to create event thread for sock 0x%02x\n", 361 h->sc->dev.dv_xname, h->sock); 362 panic("pcic_create_event_thread"); 363 } 364 } 365 366 void 367 pcic_event_thread(arg) 368 void *arg; 369 { 370 struct pcic_handle *h = arg; 371 struct pcic_event *pe; 372 int s; 373 374 while (h->shutdown == 0) { 375 s = splhigh(); 376 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 377 splx(s); 378 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 379 continue; 380 } 381 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 382 splx(s); 383 384 switch (pe->pe_type) { 385 case PCIC_EVENT_INSERTION: 386 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 387 pcic_attach_card(h); 388 break; 389 390 case PCIC_EVENT_REMOVAL: 391 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 392 pcic_detach_card(h, DETACH_FORCE); 393 break; 394 395 default: 396 panic("pcic_event_thread: unknown event %d", 397 pe->pe_type); 398 } 399 free(pe, M_TEMP); 400 } 401 402 h->event_thread = NULL; 403 404 /* In case parent is waiting for us to exit. */ 405 wakeup(h->sc); 406 407 kthread_exit(0); 408 } 409 410 void 411 pcic_init_socket(h) 412 struct pcic_handle *h; 413 { 414 int reg; 415 416 /* 417 * queue creation of a kernel thread to handle insert/removal events. 418 */ 419 #ifdef DIAGNOSTIC 420 if (h->event_thread != NULL) 421 panic("pcic_attach_socket: event thread"); 422 #endif 423 kthread_create_deferred(pcic_create_event_thread, h); 424 425 /* set up the card to interrupt on card detect */ 426 427 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 428 PCIC_CSC_INTR_CD_ENABLE); 429 pcic_write(h, PCIC_INTR, 0); 430 pcic_read(h, PCIC_CSC); 431 432 /* unsleep the cirrus controller */ 433 434 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 435 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 436 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 437 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 438 DPRINTF(("%s: socket %02x was suspended\n", 439 h->sc->dev.dv_xname, h->sock)); 440 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 441 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 442 } 443 } 444 /* if there's a card there, then attach it. */ 445 446 reg = pcic_read(h, PCIC_IF_STATUS); 447 448 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 449 PCIC_IF_STATUS_CARDDETECT_PRESENT) 450 pcic_attach_card(h); 451 } 452 453 int 454 pcic_submatch(parent, cf, aux) 455 struct device *parent; 456 struct cfdata *cf; 457 void *aux; 458 { 459 460 struct pcmciabus_attach_args *paa = aux; 461 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 462 463 switch (h->sock) { 464 case C0SA: 465 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 466 PCMCIABUSCF_CONTROLLER_DEFAULT && 467 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 468 return 0; 469 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 470 PCMCIABUSCF_SOCKET_DEFAULT && 471 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 472 return 0; 473 474 break; 475 case C0SB: 476 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 477 PCMCIABUSCF_CONTROLLER_DEFAULT && 478 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 479 return 0; 480 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 481 PCMCIABUSCF_SOCKET_DEFAULT && 482 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 483 return 0; 484 485 break; 486 case C1SA: 487 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 488 PCMCIABUSCF_CONTROLLER_DEFAULT && 489 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 490 return 0; 491 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 492 PCMCIABUSCF_SOCKET_DEFAULT && 493 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 494 return 0; 495 496 break; 497 case C1SB: 498 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 499 PCMCIABUSCF_CONTROLLER_DEFAULT && 500 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 501 return 0; 502 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 503 PCMCIABUSCF_SOCKET_DEFAULT && 504 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 505 return 0; 506 507 break; 508 default: 509 panic("unknown pcic socket"); 510 } 511 512 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 513 } 514 515 int 516 pcic_print(arg, pnp) 517 void *arg; 518 const char *pnp; 519 { 520 struct pcmciabus_attach_args *paa = arg; 521 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 522 523 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 524 if (pnp) 525 printf("pcmcia at %s", pnp); 526 527 switch (h->sock) { 528 case C0SA: 529 printf(" controller 0 socket 0"); 530 break; 531 case C0SB: 532 printf(" controller 0 socket 1"); 533 break; 534 case C1SA: 535 printf(" controller 1 socket 0"); 536 break; 537 case C1SB: 538 printf(" controller 1 socket 1"); 539 break; 540 default: 541 panic("unknown pcic socket"); 542 } 543 544 return (UNCONF); 545 } 546 547 int 548 pcic_intr(arg) 549 void *arg; 550 { 551 struct pcic_softc *sc = arg; 552 int i, ret = 0; 553 554 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 555 556 for (i = 0; i < PCIC_NSLOTS; i++) 557 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 558 ret += pcic_intr_socket(&sc->handle[i]); 559 560 return (ret ? 1 : 0); 561 } 562 563 int 564 pcic_intr_socket(h) 565 struct pcic_handle *h; 566 { 567 int cscreg; 568 569 cscreg = pcic_read(h, PCIC_CSC); 570 571 cscreg &= (PCIC_CSC_GPI | 572 PCIC_CSC_CD | 573 PCIC_CSC_READY | 574 PCIC_CSC_BATTWARN | 575 PCIC_CSC_BATTDEAD); 576 577 if (cscreg & PCIC_CSC_GPI) { 578 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 579 } 580 if (cscreg & PCIC_CSC_CD) { 581 int statreg; 582 583 statreg = pcic_read(h, PCIC_IF_STATUS); 584 585 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 586 statreg)); 587 588 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 589 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 590 if (!(h->flags & PCIC_FLAG_CARDP)) { 591 DPRINTF(("%s: enqueing INSERTION event\n", 592 h->sc->dev.dv_xname)); 593 pcic_queue_event(h, PCIC_EVENT_INSERTION); 594 } 595 } else { 596 if (h->flags & PCIC_FLAG_CARDP) { 597 /* Deactivate the card now. */ 598 DPRINTF(("%s: deactivating card\n", 599 h->sc->dev.dv_xname)); 600 pcic_deactivate_card(h); 601 602 DPRINTF(("%s: enqueing REMOVAL event\n", 603 h->sc->dev.dv_xname)); 604 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 605 } 606 } 607 } 608 if (cscreg & PCIC_CSC_READY) { 609 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 610 /* shouldn't happen */ 611 } 612 if (cscreg & PCIC_CSC_BATTWARN) { 613 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 614 } 615 if (cscreg & PCIC_CSC_BATTDEAD) { 616 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 617 } 618 return (cscreg ? 1 : 0); 619 } 620 621 void 622 pcic_queue_event(h, event) 623 struct pcic_handle *h; 624 int event; 625 { 626 struct pcic_event *pe; 627 int s; 628 629 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 630 if (pe == NULL) 631 panic("pcic_queue_event: can't allocate event"); 632 633 pe->pe_type = event; 634 s = splhigh(); 635 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 636 splx(s); 637 wakeup(&h->events); 638 } 639 640 void 641 pcic_attach_card(h) 642 struct pcic_handle *h; 643 { 644 645 if (h->flags & PCIC_FLAG_CARDP) 646 panic("pcic_attach_card: already attached"); 647 648 /* call the MI attach function */ 649 pcmcia_card_attach(h->pcmcia); 650 651 h->flags |= PCIC_FLAG_CARDP; 652 } 653 654 void 655 pcic_detach_card(h, flags) 656 struct pcic_handle *h; 657 int flags; /* DETACH_* */ 658 { 659 660 if (!(h->flags & PCIC_FLAG_CARDP)) 661 panic("pcic_attach_card: already detached"); 662 663 h->flags &= ~PCIC_FLAG_CARDP; 664 665 /* call the MI detach function */ 666 pcmcia_card_detach(h->pcmcia, flags); 667 } 668 669 void 670 pcic_deactivate_card(h) 671 struct pcic_handle *h; 672 { 673 674 if (!(h->flags & PCIC_FLAG_CARDP)) 675 panic("pcic_deactivate_card: already detached"); 676 677 /* call the MI deactivate function */ 678 pcmcia_card_deactivate(h->pcmcia); 679 680 /* power down the socket */ 681 pcic_write(h, PCIC_PWRCTL, 0); 682 683 /* reset the socket */ 684 pcic_write(h, PCIC_INTR, 0); 685 } 686 687 int 688 pcic_chip_mem_alloc(pch, size, pcmhp) 689 pcmcia_chipset_handle_t pch; 690 bus_size_t size; 691 struct pcmcia_mem_handle *pcmhp; 692 { 693 struct pcic_handle *h = (struct pcic_handle *) pch; 694 bus_space_handle_t memh; 695 bus_addr_t addr; 696 bus_size_t sizepg; 697 int i, mask, mhandle; 698 699 /* out of sc->memh, allocate as many pages as necessary */ 700 701 /* convert size to PCIC pages */ 702 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 703 704 mask = (1 << sizepg) - 1; 705 706 addr = 0; /* XXX gcc -Wuninitialized */ 707 mhandle = 0; /* XXX gcc -Wuninitialized */ 708 709 for (i = 0; i < (PCIC_MEM_PAGES + 1 - sizepg); i++) { 710 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 711 if (bus_space_subregion(h->sc->memt, h->sc->memh, 712 i * PCIC_MEM_PAGESIZE, 713 sizepg * PCIC_MEM_PAGESIZE, &memh)) 714 return (1); 715 mhandle = mask << i; 716 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 717 h->sc->subregionmask &= ~(mhandle); 718 break; 719 } 720 } 721 722 if (i == (PCIC_MEM_PAGES + 1 - size)) 723 return (1); 724 725 DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 726 (u_long) size)); 727 728 pcmhp->memt = h->sc->memt; 729 pcmhp->memh = memh; 730 pcmhp->addr = addr; 731 pcmhp->size = size; 732 pcmhp->mhandle = mhandle; 733 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 734 735 return (0); 736 } 737 738 void 739 pcic_chip_mem_free(pch, pcmhp) 740 pcmcia_chipset_handle_t pch; 741 struct pcmcia_mem_handle *pcmhp; 742 { 743 struct pcic_handle *h = (struct pcic_handle *) pch; 744 745 h->sc->subregionmask |= pcmhp->mhandle; 746 } 747 748 static struct mem_map_index_st { 749 int sysmem_start_lsb; 750 int sysmem_start_msb; 751 int sysmem_stop_lsb; 752 int sysmem_stop_msb; 753 int cardmem_lsb; 754 int cardmem_msb; 755 int memenable; 756 } mem_map_index[] = { 757 { 758 PCIC_SYSMEM_ADDR0_START_LSB, 759 PCIC_SYSMEM_ADDR0_START_MSB, 760 PCIC_SYSMEM_ADDR0_STOP_LSB, 761 PCIC_SYSMEM_ADDR0_STOP_MSB, 762 PCIC_CARDMEM_ADDR0_LSB, 763 PCIC_CARDMEM_ADDR0_MSB, 764 PCIC_ADDRWIN_ENABLE_MEM0, 765 }, 766 { 767 PCIC_SYSMEM_ADDR1_START_LSB, 768 PCIC_SYSMEM_ADDR1_START_MSB, 769 PCIC_SYSMEM_ADDR1_STOP_LSB, 770 PCIC_SYSMEM_ADDR1_STOP_MSB, 771 PCIC_CARDMEM_ADDR1_LSB, 772 PCIC_CARDMEM_ADDR1_MSB, 773 PCIC_ADDRWIN_ENABLE_MEM1, 774 }, 775 { 776 PCIC_SYSMEM_ADDR2_START_LSB, 777 PCIC_SYSMEM_ADDR2_START_MSB, 778 PCIC_SYSMEM_ADDR2_STOP_LSB, 779 PCIC_SYSMEM_ADDR2_STOP_MSB, 780 PCIC_CARDMEM_ADDR2_LSB, 781 PCIC_CARDMEM_ADDR2_MSB, 782 PCIC_ADDRWIN_ENABLE_MEM2, 783 }, 784 { 785 PCIC_SYSMEM_ADDR3_START_LSB, 786 PCIC_SYSMEM_ADDR3_START_MSB, 787 PCIC_SYSMEM_ADDR3_STOP_LSB, 788 PCIC_SYSMEM_ADDR3_STOP_MSB, 789 PCIC_CARDMEM_ADDR3_LSB, 790 PCIC_CARDMEM_ADDR3_MSB, 791 PCIC_ADDRWIN_ENABLE_MEM3, 792 }, 793 { 794 PCIC_SYSMEM_ADDR4_START_LSB, 795 PCIC_SYSMEM_ADDR4_START_MSB, 796 PCIC_SYSMEM_ADDR4_STOP_LSB, 797 PCIC_SYSMEM_ADDR4_STOP_MSB, 798 PCIC_CARDMEM_ADDR4_LSB, 799 PCIC_CARDMEM_ADDR4_MSB, 800 PCIC_ADDRWIN_ENABLE_MEM4, 801 }, 802 }; 803 804 void 805 pcic_chip_do_mem_map(h, win) 806 struct pcic_handle *h; 807 int win; 808 { 809 int reg; 810 811 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 812 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 813 pcic_write(h, mem_map_index[win].sysmem_start_msb, 814 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 815 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 816 817 #if 0 818 /* XXX do I want 16 bit all the time? */ 819 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 820 #endif 821 822 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 823 ((h->mem[win].addr + h->mem[win].size) >> 824 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 825 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 826 (((h->mem[win].addr + h->mem[win].size) >> 827 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 828 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 829 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 830 831 pcic_write(h, mem_map_index[win].cardmem_lsb, 832 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 833 pcic_write(h, mem_map_index[win].cardmem_msb, 834 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 835 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 836 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 837 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 838 839 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 840 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 841 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 842 843 #ifdef PCICDEBUG 844 { 845 int r1, r2, r3, r4, r5, r6; 846 847 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 848 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 849 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 850 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 851 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 852 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 853 854 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 855 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 856 } 857 #endif 858 } 859 860 int 861 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 862 pcmcia_chipset_handle_t pch; 863 int kind; 864 bus_addr_t card_addr; 865 bus_size_t size; 866 struct pcmcia_mem_handle *pcmhp; 867 bus_addr_t *offsetp; 868 int *windowp; 869 { 870 struct pcic_handle *h = (struct pcic_handle *) pch; 871 bus_addr_t busaddr; 872 long card_offset; 873 int i, win; 874 875 win = -1; 876 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 877 i++) { 878 if ((h->memalloc & (1 << i)) == 0) { 879 win = i; 880 h->memalloc |= (1 << i); 881 break; 882 } 883 } 884 885 if (win == -1) 886 return (1); 887 888 *windowp = win; 889 890 /* XXX this is pretty gross */ 891 892 if (h->sc->memt != pcmhp->memt) 893 panic("pcic_chip_mem_map memt is bogus"); 894 895 busaddr = pcmhp->addr; 896 897 /* 898 * compute the address offset to the pcmcia address space for the 899 * pcic. this is intentionally signed. The masks and shifts below 900 * will cause TRT to happen in the pcic registers. Deal with making 901 * sure the address is aligned, and return the alignment offset. 902 */ 903 904 *offsetp = card_addr % PCIC_MEM_ALIGN; 905 card_addr -= *offsetp; 906 907 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 908 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 909 (u_long) card_addr)); 910 911 /* 912 * include the offset in the size, and decrement size by one, since 913 * the hw wants start/stop 914 */ 915 size += *offsetp - 1; 916 917 card_offset = (((long) card_addr) - ((long) busaddr)); 918 919 h->mem[win].addr = busaddr; 920 h->mem[win].size = size; 921 h->mem[win].offset = card_offset; 922 h->mem[win].kind = kind; 923 924 pcic_chip_do_mem_map(h, win); 925 926 return (0); 927 } 928 929 void 930 pcic_chip_mem_unmap(pch, window) 931 pcmcia_chipset_handle_t pch; 932 int window; 933 { 934 struct pcic_handle *h = (struct pcic_handle *) pch; 935 int reg; 936 937 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 938 panic("pcic_chip_mem_unmap: window out of range"); 939 940 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 941 reg &= ~mem_map_index[window].memenable; 942 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 943 944 h->memalloc &= ~(1 << window); 945 } 946 947 int 948 pcic_chip_io_alloc(pch, start, size, align, pcihp) 949 pcmcia_chipset_handle_t pch; 950 bus_addr_t start; 951 bus_size_t size; 952 bus_size_t align; 953 struct pcmcia_io_handle *pcihp; 954 { 955 struct pcic_handle *h = (struct pcic_handle *) pch; 956 bus_space_tag_t iot; 957 bus_space_handle_t ioh; 958 bus_addr_t ioaddr; 959 int flags = 0; 960 961 /* 962 * Allocate some arbitrary I/O space. 963 */ 964 965 iot = h->sc->iot; 966 967 if (start) { 968 ioaddr = start; 969 if (bus_space_map(iot, start, size, 0, &ioh)) 970 return (1); 971 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 972 (u_long) ioaddr, (u_long) size)); 973 } else { 974 flags |= PCMCIA_IO_ALLOCATED; 975 if (bus_space_alloc(iot, h->sc->iobase, 976 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 977 &ioaddr, &ioh)) 978 return (1); 979 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 980 (u_long) ioaddr, (u_long) size)); 981 } 982 983 pcihp->iot = iot; 984 pcihp->ioh = ioh; 985 pcihp->addr = ioaddr; 986 pcihp->size = size; 987 pcihp->flags = flags; 988 989 return (0); 990 } 991 992 void 993 pcic_chip_io_free(pch, pcihp) 994 pcmcia_chipset_handle_t pch; 995 struct pcmcia_io_handle *pcihp; 996 { 997 bus_space_tag_t iot = pcihp->iot; 998 bus_space_handle_t ioh = pcihp->ioh; 999 bus_size_t size = pcihp->size; 1000 1001 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1002 bus_space_free(iot, ioh, size); 1003 else 1004 bus_space_unmap(iot, ioh, size); 1005 } 1006 1007 1008 static struct io_map_index_st { 1009 int start_lsb; 1010 int start_msb; 1011 int stop_lsb; 1012 int stop_msb; 1013 int ioenable; 1014 int ioctlmask; 1015 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1016 } io_map_index[] = { 1017 { 1018 PCIC_IOADDR0_START_LSB, 1019 PCIC_IOADDR0_START_MSB, 1020 PCIC_IOADDR0_STOP_LSB, 1021 PCIC_IOADDR0_STOP_MSB, 1022 PCIC_ADDRWIN_ENABLE_IO0, 1023 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1024 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1025 { 1026 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1027 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1028 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1029 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1030 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1031 }, 1032 }, 1033 { 1034 PCIC_IOADDR1_START_LSB, 1035 PCIC_IOADDR1_START_MSB, 1036 PCIC_IOADDR1_STOP_LSB, 1037 PCIC_IOADDR1_STOP_MSB, 1038 PCIC_ADDRWIN_ENABLE_IO1, 1039 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1040 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1041 { 1042 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1043 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1044 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1045 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1046 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1047 }, 1048 }, 1049 }; 1050 1051 void 1052 pcic_chip_do_io_map(h, win) 1053 struct pcic_handle *h; 1054 int win; 1055 { 1056 int reg; 1057 1058 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1059 win, (long) h->io[win].addr, (long) h->io[win].size, 1060 h->io[win].width * 8)); 1061 1062 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1063 pcic_write(h, io_map_index[win].start_msb, 1064 (h->io[win].addr >> 8) & 0xff); 1065 1066 pcic_write(h, io_map_index[win].stop_lsb, 1067 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1068 pcic_write(h, io_map_index[win].stop_msb, 1069 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1070 1071 reg = pcic_read(h, PCIC_IOCTL); 1072 reg &= ~io_map_index[win].ioctlmask; 1073 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1074 pcic_write(h, PCIC_IOCTL, reg); 1075 1076 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1077 reg |= io_map_index[win].ioenable; 1078 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1079 } 1080 1081 int 1082 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1083 pcmcia_chipset_handle_t pch; 1084 int width; 1085 bus_addr_t offset; 1086 bus_size_t size; 1087 struct pcmcia_io_handle *pcihp; 1088 int *windowp; 1089 { 1090 struct pcic_handle *h = (struct pcic_handle *) pch; 1091 bus_addr_t ioaddr = pcihp->addr + offset; 1092 int i, win; 1093 #ifdef PCICDEBUG 1094 static char *width_names[] = { "auto", "io8", "io16" }; 1095 #endif 1096 1097 /* XXX Sanity check offset/size. */ 1098 1099 win = -1; 1100 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1101 if ((h->ioalloc & (1 << i)) == 0) { 1102 win = i; 1103 h->ioalloc |= (1 << i); 1104 break; 1105 } 1106 } 1107 1108 if (win == -1) 1109 return (1); 1110 1111 *windowp = win; 1112 1113 /* XXX this is pretty gross */ 1114 1115 if (h->sc->iot != pcihp->iot) 1116 panic("pcic_chip_io_map iot is bogus"); 1117 1118 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1119 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1120 1121 /* XXX wtf is this doing here? */ 1122 1123 printf(" port 0x%lx", (u_long) ioaddr); 1124 if (size > 1) 1125 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1126 1127 h->io[win].addr = ioaddr; 1128 h->io[win].size = size; 1129 h->io[win].width = width; 1130 1131 pcic_chip_do_io_map(h, win); 1132 1133 return (0); 1134 } 1135 1136 void 1137 pcic_chip_io_unmap(pch, window) 1138 pcmcia_chipset_handle_t pch; 1139 int window; 1140 { 1141 struct pcic_handle *h = (struct pcic_handle *) pch; 1142 int reg; 1143 1144 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1145 panic("pcic_chip_io_unmap: window out of range"); 1146 1147 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1148 reg &= ~io_map_index[window].ioenable; 1149 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1150 1151 h->ioalloc &= ~(1 << window); 1152 } 1153 1154 static void 1155 pcic_wait_ready(h) 1156 struct pcic_handle *h; 1157 { 1158 int i; 1159 1160 for (i = 0; i < 10000; i++) { 1161 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1162 return; 1163 delay(500); 1164 #ifdef PCICDEBUG 1165 if (pcic_debug) { 1166 if ((i>5000) && (i%100 == 99)) 1167 printf("."); 1168 } 1169 #endif 1170 } 1171 1172 #ifdef DIAGNOSTIC 1173 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1174 pcic_read(h, PCIC_IF_STATUS)); 1175 #endif 1176 } 1177 1178 void 1179 pcic_chip_socket_enable(pch) 1180 pcmcia_chipset_handle_t pch; 1181 { 1182 struct pcic_handle *h = (struct pcic_handle *) pch; 1183 int cardtype, reg, win; 1184 1185 /* this bit is mostly stolen from pcic_attach_card */ 1186 1187 /* power down the socket to reset it, clear the card reset pin */ 1188 1189 pcic_write(h, PCIC_PWRCTL, 0); 1190 1191 /* 1192 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1193 * we are changing Vcc (Toff). 1194 */ 1195 delay((300 + 100) * 1000); 1196 1197 /* power up the socket */ 1198 1199 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1200 | PCIC_PWRCTL_PWR_ENABLE); 1201 1202 /* 1203 * wait 100ms until power raise (Tpr) and 20ms to become 1204 * stable (Tsu(Vcc)). 1205 * 1206 * some machines require some more time to be settled 1207 * (another 200ms is added here). 1208 */ 1209 delay((100 + 20 + 200) * 1000); 1210 1211 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1212 | PCIC_PWRCTL_PWR_ENABLE); 1213 pcic_write(h, PCIC_INTR, 0); 1214 1215 /* 1216 * hold RESET at least 10us. 1217 */ 1218 delay(10); 1219 1220 /* clear the reset flag */ 1221 1222 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1223 1224 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1225 1226 delay(20000); 1227 1228 /* wait for the chip to finish initializing */ 1229 1230 pcic_wait_ready(h); 1231 1232 /* zero out the address windows */ 1233 1234 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1235 1236 /* set the card type */ 1237 1238 cardtype = pcmcia_card_gettype(h->pcmcia); 1239 1240 reg = pcic_read(h, PCIC_INTR); 1241 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1242 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1243 PCIC_INTR_CARDTYPE_IO : 1244 PCIC_INTR_CARDTYPE_MEM); 1245 reg |= h->ih_irq; 1246 pcic_write(h, PCIC_INTR, reg); 1247 1248 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1249 h->sc->dev.dv_xname, h->sock, 1250 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1251 1252 /* reinstall all the memory and io mappings */ 1253 1254 for (win = 0; win < PCIC_MEM_WINS; win++) 1255 if (h->memalloc & (1 << win)) 1256 pcic_chip_do_mem_map(h, win); 1257 1258 for (win = 0; win < PCIC_IO_WINS; win++) 1259 if (h->ioalloc & (1 << win)) 1260 pcic_chip_do_io_map(h, win); 1261 } 1262 1263 void 1264 pcic_chip_socket_disable(pch) 1265 pcmcia_chipset_handle_t pch; 1266 { 1267 struct pcic_handle *h = (struct pcic_handle *) pch; 1268 1269 DPRINTF(("pcic_chip_socket_disable\n")); 1270 1271 /* power down the socket */ 1272 1273 pcic_write(h, PCIC_PWRCTL, 0); 1274 1275 /* 1276 * wait 300ms until power fails (Tpf). 1277 */ 1278 delay(300 * 1000); 1279 } 1280
Indexes created Mon Sep 29 21:09:56 GMT 2025