i82365.c revision 1.17
1 /* $NetBSD: i82365.c,v 1.17 1998/12/20 17:53:28 nathanw Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 #include <sys/kthread.h> 41 42 #include <vm/vm.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 50 #include <dev/ic/i82365reg.h> 51 #include <dev/ic/i82365var.h> 52 53 #include "locators.h" 54 55 #ifdef PCICDEBUG 56 int pcic_debug = 0; 57 #define DPRINTF(arg) if (pcic_debug) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #endif 61 62 #define PCIC_VENDOR_UNKNOWN 0 63 #define PCIC_VENDOR_I82365SLR0 1 64 #define PCIC_VENDOR_I82365SLR1 2 65 #define PCIC_VENDOR_CIRRUS_PD6710 3 66 #define PCIC_VENDOR_CIRRUS_PD672X 4 67 68 /* 69 * Individual drivers will allocate their own memory and io regions. Memory 70 * regions must be a multiple of 4k, aligned on a 4k boundary. 71 */ 72 73 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 74 75 void pcic_attach_socket __P((struct pcic_handle *)); 76 void pcic_init_socket __P((struct pcic_handle *)); 77 78 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 79 int pcic_print __P((void *arg, const char *pnp)); 80 int pcic_intr_socket __P((struct pcic_handle *)); 81 82 void pcic_attach_card __P((struct pcic_handle *)); 83 void pcic_detach_card __P((struct pcic_handle *, int)); 84 void pcic_deactivate_card __P((struct pcic_handle *)); 85 86 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 87 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 88 89 void pcic_create_event_thread __P((void *)); 90 void pcic_event_thread __P((void *)); 91 92 void pcic_queue_event __P((struct pcic_handle *, int)); 93 94 static void pcic_wait_ready __P((struct pcic_handle *)); 95 96 int 97 pcic_ident_ok(ident) 98 int ident; 99 { 100 /* this is very empirical and heuristic */ 101 102 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 103 return (0); 104 105 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 106 #ifdef DIAGNOSTIC 107 printf("pcic: does not support memory and I/O cards, " 108 "ignored (ident=%0x)\n", ident); 109 #endif 110 return (0); 111 } 112 return (1); 113 } 114 115 int 116 pcic_vendor(h) 117 struct pcic_handle *h; 118 { 119 int reg; 120 121 /* 122 * the chip_id of the cirrus toggles between 11 and 00 after a write. 123 * weird. 124 */ 125 126 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 127 reg = pcic_read(h, -1); 128 129 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 130 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 131 reg = pcic_read(h, -1); 132 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 133 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 134 return (PCIC_VENDOR_CIRRUS_PD672X); 135 else 136 return (PCIC_VENDOR_CIRRUS_PD6710); 137 } 138 } 139 140 reg = pcic_read(h, PCIC_IDENT); 141 142 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 143 return (PCIC_VENDOR_I82365SLR0); 144 else 145 return (PCIC_VENDOR_I82365SLR1); 146 147 return (PCIC_VENDOR_UNKNOWN); 148 } 149 150 char * 151 pcic_vendor_to_string(vendor) 152 int vendor; 153 { 154 switch (vendor) { 155 case PCIC_VENDOR_I82365SLR0: 156 return ("Intel 82365SL Revision 0"); 157 case PCIC_VENDOR_I82365SLR1: 158 return ("Intel 82365SL Revision 1"); 159 case PCIC_VENDOR_CIRRUS_PD6710: 160 return ("Cirrus PD6710"); 161 case PCIC_VENDOR_CIRRUS_PD672X: 162 return ("Cirrus PD672X"); 163 } 164 165 return ("Unknown controller"); 166 } 167 168 void 169 pcic_attach(sc) 170 struct pcic_softc *sc; 171 { 172 int vendor, count, i, reg; 173 174 /* now check for each controller/socket */ 175 176 /* 177 * this could be done with a loop, but it would violate the 178 * abstraction 179 */ 180 181 count = 0; 182 183 DPRINTF(("pcic ident regs:")); 184 185 sc->handle[0].sc = sc; 186 sc->handle[0].sock = C0SA; 187 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 188 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 189 count++; 190 } else { 191 sc->handle[0].flags = 0; 192 } 193 194 DPRINTF((" 0x%02x", reg)); 195 196 sc->handle[1].sc = sc; 197 sc->handle[1].sock = C0SB; 198 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 199 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 200 count++; 201 } else { 202 sc->handle[1].flags = 0; 203 } 204 205 DPRINTF((" 0x%02x", reg)); 206 207 /* 208 * The CL-PD6729 has only one controller and always returns 0 209 * if you try to read from the second one. Maybe pcic_ident_ok 210 * shouldn't accept 0? 211 */ 212 sc->handle[2].sc = sc; 213 sc->handle[2].sock = C1SA; 214 if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X || 215 pcic_read(&sc->handle[2], PCIC_IDENT) != 0) { 216 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], 217 PCIC_IDENT))) { 218 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 219 count++; 220 } else { 221 sc->handle[2].flags = 0; 222 } 223 224 DPRINTF((" 0x%02x", reg)); 225 226 sc->handle[3].sc = sc; 227 sc->handle[3].sock = C1SB; 228 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], 229 PCIC_IDENT))) { 230 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 231 count++; 232 } else { 233 sc->handle[3].flags = 0; 234 } 235 236 DPRINTF((" 0x%02x\n", reg)); 237 } 238 239 if (count == 0) 240 panic("pcic_attach: attach found no sockets"); 241 242 /* establish the interrupt */ 243 244 /* XXX block interrupts? */ 245 246 for (i = 0; i < PCIC_NSLOTS; i++) { 247 SIMPLEQ_INIT(&sc->handle[i].events); 248 #if 0 249 /* 250 * this should work, but w/o it, setting tty flags hangs at 251 * boot time. 252 */ 253 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 254 #endif 255 { 256 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 257 pcic_read(&sc->handle[i], PCIC_CSC); 258 } 259 } 260 261 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 262 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 263 vendor = pcic_vendor(&sc->handle[0]); 264 265 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 266 pcic_vendor_to_string(vendor)); 267 268 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 269 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 270 printf("sockets A and B\n"); 271 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 272 printf("socket A only\n"); 273 else 274 printf("socket B only\n"); 275 276 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 277 sc->handle[0].vendor = vendor; 278 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 279 sc->handle[1].vendor = vendor; 280 } 281 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 282 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 283 vendor = pcic_vendor(&sc->handle[2]); 284 285 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 286 pcic_vendor_to_string(vendor)); 287 288 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 289 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 290 printf("sockets A and B\n"); 291 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 292 printf("socket A only\n"); 293 else 294 printf("socket B only\n"); 295 296 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 297 sc->handle[2].vendor = vendor; 298 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 299 sc->handle[3].vendor = vendor; 300 } 301 } 302 303 void 304 pcic_attach_sockets(sc) 305 struct pcic_softc *sc; 306 { 307 int i; 308 309 for (i = 0; i < PCIC_NSLOTS; i++) 310 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 311 pcic_attach_socket(&sc->handle[i]); 312 } 313 314 void 315 pcic_attach_socket(h) 316 struct pcic_handle *h; 317 { 318 struct pcmciabus_attach_args paa; 319 320 /* initialize the rest of the handle */ 321 322 h->shutdown = 0; 323 h->memalloc = 0; 324 h->ioalloc = 0; 325 h->ih_irq = 0; 326 327 /* now, config one pcmcia device per socket */ 328 329 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 330 paa.pch = (pcmcia_chipset_handle_t) h; 331 paa.iobase = h->sc->iobase; 332 paa.iosize = h->sc->iosize; 333 334 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 335 pcic_submatch); 336 337 /* if there's actually a pcmcia device attached, initialize the slot */ 338 339 if (h->pcmcia) 340 pcic_init_socket(h); 341 } 342 343 void 344 pcic_create_event_thread(arg) 345 void *arg; 346 { 347 struct pcic_handle *h = arg; 348 const char *cs; 349 350 switch (h->sock) { 351 case C0SA: 352 cs = "0,0"; 353 break; 354 case C0SB: 355 cs = "0,1"; 356 break; 357 case C1SA: 358 cs = "1,0"; 359 break; 360 case C1SB: 361 cs = "1,1"; 362 break; 363 default: 364 panic("pcic_create_event_thread: unknown pcic socket"); 365 } 366 367 if (kthread_create(pcic_event_thread, h, &h->event_thread, 368 "%s,%s", h->sc->dev.dv_xname, cs)) { 369 printf("%s: unable to create event thread for sock 0x%02x\n", 370 h->sc->dev.dv_xname, h->sock); 371 panic("pcic_create_event_thread"); 372 } 373 } 374 375 void 376 pcic_event_thread(arg) 377 void *arg; 378 { 379 struct pcic_handle *h = arg; 380 struct pcic_event *pe; 381 int s; 382 383 while (h->shutdown == 0) { 384 s = splhigh(); 385 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 386 splx(s); 387 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 388 continue; 389 } 390 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 391 splx(s); 392 393 switch (pe->pe_type) { 394 case PCIC_EVENT_INSERTION: 395 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 396 pcic_attach_card(h); 397 break; 398 399 case PCIC_EVENT_REMOVAL: 400 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 401 pcic_detach_card(h, DETACH_FORCE); 402 break; 403 404 default: 405 panic("pcic_event_thread: unknown event %d", 406 pe->pe_type); 407 } 408 free(pe, M_TEMP); 409 } 410 411 h->event_thread = NULL; 412 413 /* In case parent is waiting for us to exit. */ 414 wakeup(h->sc); 415 416 kthread_exit(0); 417 } 418 419 void 420 pcic_init_socket(h) 421 struct pcic_handle *h; 422 { 423 int reg; 424 425 /* 426 * queue creation of a kernel thread to handle insert/removal events. 427 */ 428 #ifdef DIAGNOSTIC 429 if (h->event_thread != NULL) 430 panic("pcic_attach_socket: event thread"); 431 #endif 432 kthread_create_deferred(pcic_create_event_thread, h); 433 434 /* set up the card to interrupt on card detect */ 435 436 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 437 PCIC_CSC_INTR_CD_ENABLE); 438 pcic_write(h, PCIC_INTR, 0); 439 pcic_read(h, PCIC_CSC); 440 441 /* unsleep the cirrus controller */ 442 443 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 444 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 445 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 446 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 447 DPRINTF(("%s: socket %02x was suspended\n", 448 h->sc->dev.dv_xname, h->sock)); 449 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 450 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 451 } 452 } 453 /* if there's a card there, then attach it. */ 454 455 reg = pcic_read(h, PCIC_IF_STATUS); 456 457 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 458 PCIC_IF_STATUS_CARDDETECT_PRESENT) 459 pcic_attach_card(h); 460 } 461 462 int 463 pcic_submatch(parent, cf, aux) 464 struct device *parent; 465 struct cfdata *cf; 466 void *aux; 467 { 468 469 struct pcmciabus_attach_args *paa = aux; 470 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 471 472 switch (h->sock) { 473 case C0SA: 474 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 475 PCMCIABUSCF_CONTROLLER_DEFAULT && 476 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 477 return 0; 478 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 479 PCMCIABUSCF_SOCKET_DEFAULT && 480 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 481 return 0; 482 483 break; 484 case C0SB: 485 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 486 PCMCIABUSCF_CONTROLLER_DEFAULT && 487 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 488 return 0; 489 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 490 PCMCIABUSCF_SOCKET_DEFAULT && 491 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 492 return 0; 493 494 break; 495 case C1SA: 496 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 497 PCMCIABUSCF_CONTROLLER_DEFAULT && 498 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 499 return 0; 500 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 501 PCMCIABUSCF_SOCKET_DEFAULT && 502 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 503 return 0; 504 505 break; 506 case C1SB: 507 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 508 PCMCIABUSCF_CONTROLLER_DEFAULT && 509 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 510 return 0; 511 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 512 PCMCIABUSCF_SOCKET_DEFAULT && 513 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 514 return 0; 515 516 break; 517 default: 518 panic("unknown pcic socket"); 519 } 520 521 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 522 } 523 524 int 525 pcic_print(arg, pnp) 526 void *arg; 527 const char *pnp; 528 { 529 struct pcmciabus_attach_args *paa = arg; 530 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 531 532 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 533 if (pnp) 534 printf("pcmcia at %s", pnp); 535 536 switch (h->sock) { 537 case C0SA: 538 printf(" controller 0 socket 0"); 539 break; 540 case C0SB: 541 printf(" controller 0 socket 1"); 542 break; 543 case C1SA: 544 printf(" controller 1 socket 0"); 545 break; 546 case C1SB: 547 printf(" controller 1 socket 1"); 548 break; 549 default: 550 panic("unknown pcic socket"); 551 } 552 553 return (UNCONF); 554 } 555 556 int 557 pcic_intr(arg) 558 void *arg; 559 { 560 struct pcic_softc *sc = arg; 561 int i, ret = 0; 562 563 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 564 565 for (i = 0; i < PCIC_NSLOTS; i++) 566 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 567 ret += pcic_intr_socket(&sc->handle[i]); 568 569 return (ret ? 1 : 0); 570 } 571 572 int 573 pcic_intr_socket(h) 574 struct pcic_handle *h; 575 { 576 int cscreg; 577 578 cscreg = pcic_read(h, PCIC_CSC); 579 580 cscreg &= (PCIC_CSC_GPI | 581 PCIC_CSC_CD | 582 PCIC_CSC_READY | 583 PCIC_CSC_BATTWARN | 584 PCIC_CSC_BATTDEAD); 585 586 if (cscreg & PCIC_CSC_GPI) { 587 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 588 } 589 if (cscreg & PCIC_CSC_CD) { 590 int statreg; 591 592 statreg = pcic_read(h, PCIC_IF_STATUS); 593 594 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 595 statreg)); 596 597 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 598 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 599 if (!(h->flags & PCIC_FLAG_CARDP)) { 600 DPRINTF(("%s: enqueing INSERTION event\n", 601 h->sc->dev.dv_xname)); 602 pcic_queue_event(h, PCIC_EVENT_INSERTION); 603 } 604 } else { 605 if (h->flags & PCIC_FLAG_CARDP) { 606 /* Deactivate the card now. */ 607 DPRINTF(("%s: deactivating card\n", 608 h->sc->dev.dv_xname)); 609 pcic_deactivate_card(h); 610 611 DPRINTF(("%s: enqueing REMOVAL event\n", 612 h->sc->dev.dv_xname)); 613 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 614 } 615 } 616 } 617 if (cscreg & PCIC_CSC_READY) { 618 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 619 /* shouldn't happen */ 620 } 621 if (cscreg & PCIC_CSC_BATTWARN) { 622 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 623 } 624 if (cscreg & PCIC_CSC_BATTDEAD) { 625 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 626 } 627 return (cscreg ? 1 : 0); 628 } 629 630 void 631 pcic_queue_event(h, event) 632 struct pcic_handle *h; 633 int event; 634 { 635 struct pcic_event *pe; 636 int s; 637 638 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 639 if (pe == NULL) 640 panic("pcic_queue_event: can't allocate event"); 641 642 pe->pe_type = event; 643 s = splhigh(); 644 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 645 splx(s); 646 wakeup(&h->events); 647 } 648 649 void 650 pcic_attach_card(h) 651 struct pcic_handle *h; 652 { 653 654 if (h->flags & PCIC_FLAG_CARDP) 655 panic("pcic_attach_card: already attached"); 656 657 /* call the MI attach function */ 658 pcmcia_card_attach(h->pcmcia); 659 660 h->flags |= PCIC_FLAG_CARDP; 661 } 662 663 void 664 pcic_detach_card(h, flags) 665 struct pcic_handle *h; 666 int flags; /* DETACH_* */ 667 { 668 669 if (!(h->flags & PCIC_FLAG_CARDP)) 670 panic("pcic_attach_card: already detached"); 671 672 h->flags &= ~PCIC_FLAG_CARDP; 673 674 /* call the MI detach function */ 675 pcmcia_card_detach(h->pcmcia, flags); 676 } 677 678 void 679 pcic_deactivate_card(h) 680 struct pcic_handle *h; 681 { 682 683 if (!(h->flags & PCIC_FLAG_CARDP)) 684 panic("pcic_deactivate_card: already detached"); 685 686 /* call the MI deactivate function */ 687 pcmcia_card_deactivate(h->pcmcia); 688 689 /* power down the socket */ 690 pcic_write(h, PCIC_PWRCTL, 0); 691 692 /* reset the socket */ 693 pcic_write(h, PCIC_INTR, 0); 694 } 695 696 int 697 pcic_chip_mem_alloc(pch, size, pcmhp) 698 pcmcia_chipset_handle_t pch; 699 bus_size_t size; 700 struct pcmcia_mem_handle *pcmhp; 701 { 702 struct pcic_handle *h = (struct pcic_handle *) pch; 703 bus_space_handle_t memh; 704 bus_addr_t addr; 705 bus_size_t sizepg; 706 int i, mask, mhandle; 707 708 /* out of sc->memh, allocate as many pages as necessary */ 709 710 /* convert size to PCIC pages */ 711 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 712 713 mask = (1 << sizepg) - 1; 714 715 addr = 0; /* XXX gcc -Wuninitialized */ 716 mhandle = 0; /* XXX gcc -Wuninitialized */ 717 718 for (i = 0; i < (PCIC_MEM_PAGES + 1 - sizepg); i++) { 719 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 720 if (bus_space_subregion(h->sc->memt, h->sc->memh, 721 i * PCIC_MEM_PAGESIZE, 722 sizepg * PCIC_MEM_PAGESIZE, &memh)) 723 return (1); 724 mhandle = mask << i; 725 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 726 h->sc->subregionmask &= ~(mhandle); 727 break; 728 } 729 } 730 731 if (i == (PCIC_MEM_PAGES + 1 - size)) 732 return (1); 733 734 DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 735 (u_long) size)); 736 737 pcmhp->memt = h->sc->memt; 738 pcmhp->memh = memh; 739 pcmhp->addr = addr; 740 pcmhp->size = size; 741 pcmhp->mhandle = mhandle; 742 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 743 744 return (0); 745 } 746 747 void 748 pcic_chip_mem_free(pch, pcmhp) 749 pcmcia_chipset_handle_t pch; 750 struct pcmcia_mem_handle *pcmhp; 751 { 752 struct pcic_handle *h = (struct pcic_handle *) pch; 753 754 h->sc->subregionmask |= pcmhp->mhandle; 755 } 756 757 static struct mem_map_index_st { 758 int sysmem_start_lsb; 759 int sysmem_start_msb; 760 int sysmem_stop_lsb; 761 int sysmem_stop_msb; 762 int cardmem_lsb; 763 int cardmem_msb; 764 int memenable; 765 } mem_map_index[] = { 766 { 767 PCIC_SYSMEM_ADDR0_START_LSB, 768 PCIC_SYSMEM_ADDR0_START_MSB, 769 PCIC_SYSMEM_ADDR0_STOP_LSB, 770 PCIC_SYSMEM_ADDR0_STOP_MSB, 771 PCIC_CARDMEM_ADDR0_LSB, 772 PCIC_CARDMEM_ADDR0_MSB, 773 PCIC_ADDRWIN_ENABLE_MEM0, 774 }, 775 { 776 PCIC_SYSMEM_ADDR1_START_LSB, 777 PCIC_SYSMEM_ADDR1_START_MSB, 778 PCIC_SYSMEM_ADDR1_STOP_LSB, 779 PCIC_SYSMEM_ADDR1_STOP_MSB, 780 PCIC_CARDMEM_ADDR1_LSB, 781 PCIC_CARDMEM_ADDR1_MSB, 782 PCIC_ADDRWIN_ENABLE_MEM1, 783 }, 784 { 785 PCIC_SYSMEM_ADDR2_START_LSB, 786 PCIC_SYSMEM_ADDR2_START_MSB, 787 PCIC_SYSMEM_ADDR2_STOP_LSB, 788 PCIC_SYSMEM_ADDR2_STOP_MSB, 789 PCIC_CARDMEM_ADDR2_LSB, 790 PCIC_CARDMEM_ADDR2_MSB, 791 PCIC_ADDRWIN_ENABLE_MEM2, 792 }, 793 { 794 PCIC_SYSMEM_ADDR3_START_LSB, 795 PCIC_SYSMEM_ADDR3_START_MSB, 796 PCIC_SYSMEM_ADDR3_STOP_LSB, 797 PCIC_SYSMEM_ADDR3_STOP_MSB, 798 PCIC_CARDMEM_ADDR3_LSB, 799 PCIC_CARDMEM_ADDR3_MSB, 800 PCIC_ADDRWIN_ENABLE_MEM3, 801 }, 802 { 803 PCIC_SYSMEM_ADDR4_START_LSB, 804 PCIC_SYSMEM_ADDR4_START_MSB, 805 PCIC_SYSMEM_ADDR4_STOP_LSB, 806 PCIC_SYSMEM_ADDR4_STOP_MSB, 807 PCIC_CARDMEM_ADDR4_LSB, 808 PCIC_CARDMEM_ADDR4_MSB, 809 PCIC_ADDRWIN_ENABLE_MEM4, 810 }, 811 }; 812 813 void 814 pcic_chip_do_mem_map(h, win) 815 struct pcic_handle *h; 816 int win; 817 { 818 int reg; 819 820 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 821 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 822 pcic_write(h, mem_map_index[win].sysmem_start_msb, 823 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 824 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 825 826 #if 0 827 /* XXX do I want 16 bit all the time? */ 828 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 829 #endif 830 831 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 832 ((h->mem[win].addr + h->mem[win].size) >> 833 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 834 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 835 (((h->mem[win].addr + h->mem[win].size) >> 836 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 837 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 838 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 839 840 pcic_write(h, mem_map_index[win].cardmem_lsb, 841 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 842 pcic_write(h, mem_map_index[win].cardmem_msb, 843 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 844 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 845 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 846 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 847 848 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 849 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 850 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 851 852 #ifdef PCICDEBUG 853 { 854 int r1, r2, r3, r4, r5, r6; 855 856 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 857 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 858 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 859 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 860 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 861 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 862 863 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 864 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 865 } 866 #endif 867 } 868 869 int 870 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 871 pcmcia_chipset_handle_t pch; 872 int kind; 873 bus_addr_t card_addr; 874 bus_size_t size; 875 struct pcmcia_mem_handle *pcmhp; 876 bus_addr_t *offsetp; 877 int *windowp; 878 { 879 struct pcic_handle *h = (struct pcic_handle *) pch; 880 bus_addr_t busaddr; 881 long card_offset; 882 int i, win; 883 884 win = -1; 885 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 886 i++) { 887 if ((h->memalloc & (1 << i)) == 0) { 888 win = i; 889 h->memalloc |= (1 << i); 890 break; 891 } 892 } 893 894 if (win == -1) 895 return (1); 896 897 *windowp = win; 898 899 /* XXX this is pretty gross */ 900 901 if (h->sc->memt != pcmhp->memt) 902 panic("pcic_chip_mem_map memt is bogus"); 903 904 busaddr = pcmhp->addr; 905 906 /* 907 * compute the address offset to the pcmcia address space for the 908 * pcic. this is intentionally signed. The masks and shifts below 909 * will cause TRT to happen in the pcic registers. Deal with making 910 * sure the address is aligned, and return the alignment offset. 911 */ 912 913 *offsetp = card_addr % PCIC_MEM_ALIGN; 914 card_addr -= *offsetp; 915 916 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 917 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 918 (u_long) card_addr)); 919 920 /* 921 * include the offset in the size, and decrement size by one, since 922 * the hw wants start/stop 923 */ 924 size += *offsetp - 1; 925 926 card_offset = (((long) card_addr) - ((long) busaddr)); 927 928 h->mem[win].addr = busaddr; 929 h->mem[win].size = size; 930 h->mem[win].offset = card_offset; 931 h->mem[win].kind = kind; 932 933 pcic_chip_do_mem_map(h, win); 934 935 return (0); 936 } 937 938 void 939 pcic_chip_mem_unmap(pch, window) 940 pcmcia_chipset_handle_t pch; 941 int window; 942 { 943 struct pcic_handle *h = (struct pcic_handle *) pch; 944 int reg; 945 946 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 947 panic("pcic_chip_mem_unmap: window out of range"); 948 949 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 950 reg &= ~mem_map_index[window].memenable; 951 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 952 953 h->memalloc &= ~(1 << window); 954 } 955 956 int 957 pcic_chip_io_alloc(pch, start, size, align, pcihp) 958 pcmcia_chipset_handle_t pch; 959 bus_addr_t start; 960 bus_size_t size; 961 bus_size_t align; 962 struct pcmcia_io_handle *pcihp; 963 { 964 struct pcic_handle *h = (struct pcic_handle *) pch; 965 bus_space_tag_t iot; 966 bus_space_handle_t ioh; 967 bus_addr_t ioaddr; 968 int flags = 0; 969 970 /* 971 * Allocate some arbitrary I/O space. 972 */ 973 974 iot = h->sc->iot; 975 976 if (start) { 977 ioaddr = start; 978 if (bus_space_map(iot, start, size, 0, &ioh)) 979 return (1); 980 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 981 (u_long) ioaddr, (u_long) size)); 982 } else { 983 flags |= PCMCIA_IO_ALLOCATED; 984 if (bus_space_alloc(iot, h->sc->iobase, 985 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 986 &ioaddr, &ioh)) 987 return (1); 988 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 989 (u_long) ioaddr, (u_long) size)); 990 } 991 992 pcihp->iot = iot; 993 pcihp->ioh = ioh; 994 pcihp->addr = ioaddr; 995 pcihp->size = size; 996 pcihp->flags = flags; 997 998 return (0); 999 } 1000 1001 void 1002 pcic_chip_io_free(pch, pcihp) 1003 pcmcia_chipset_handle_t pch; 1004 struct pcmcia_io_handle *pcihp; 1005 { 1006 bus_space_tag_t iot = pcihp->iot; 1007 bus_space_handle_t ioh = pcihp->ioh; 1008 bus_size_t size = pcihp->size; 1009 1010 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1011 bus_space_free(iot, ioh, size); 1012 else 1013 bus_space_unmap(iot, ioh, size); 1014 } 1015 1016 1017 static struct io_map_index_st { 1018 int start_lsb; 1019 int start_msb; 1020 int stop_lsb; 1021 int stop_msb; 1022 int ioenable; 1023 int ioctlmask; 1024 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1025 } io_map_index[] = { 1026 { 1027 PCIC_IOADDR0_START_LSB, 1028 PCIC_IOADDR0_START_MSB, 1029 PCIC_IOADDR0_STOP_LSB, 1030 PCIC_IOADDR0_STOP_MSB, 1031 PCIC_ADDRWIN_ENABLE_IO0, 1032 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1033 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1034 { 1035 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1036 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1037 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1038 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1039 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1040 }, 1041 }, 1042 { 1043 PCIC_IOADDR1_START_LSB, 1044 PCIC_IOADDR1_START_MSB, 1045 PCIC_IOADDR1_STOP_LSB, 1046 PCIC_IOADDR1_STOP_MSB, 1047 PCIC_ADDRWIN_ENABLE_IO1, 1048 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1049 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1050 { 1051 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1052 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1053 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1054 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1055 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1056 }, 1057 }, 1058 }; 1059 1060 void 1061 pcic_chip_do_io_map(h, win) 1062 struct pcic_handle *h; 1063 int win; 1064 { 1065 int reg; 1066 1067 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1068 win, (long) h->io[win].addr, (long) h->io[win].size, 1069 h->io[win].width * 8)); 1070 1071 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1072 pcic_write(h, io_map_index[win].start_msb, 1073 (h->io[win].addr >> 8) & 0xff); 1074 1075 pcic_write(h, io_map_index[win].stop_lsb, 1076 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1077 pcic_write(h, io_map_index[win].stop_msb, 1078 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1079 1080 reg = pcic_read(h, PCIC_IOCTL); 1081 reg &= ~io_map_index[win].ioctlmask; 1082 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1083 pcic_write(h, PCIC_IOCTL, reg); 1084 1085 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1086 reg |= io_map_index[win].ioenable; 1087 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1088 } 1089 1090 int 1091 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1092 pcmcia_chipset_handle_t pch; 1093 int width; 1094 bus_addr_t offset; 1095 bus_size_t size; 1096 struct pcmcia_io_handle *pcihp; 1097 int *windowp; 1098 { 1099 struct pcic_handle *h = (struct pcic_handle *) pch; 1100 bus_addr_t ioaddr = pcihp->addr + offset; 1101 int i, win; 1102 #ifdef PCICDEBUG 1103 static char *width_names[] = { "auto", "io8", "io16" }; 1104 #endif 1105 1106 /* XXX Sanity check offset/size. */ 1107 1108 win = -1; 1109 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1110 if ((h->ioalloc & (1 << i)) == 0) { 1111 win = i; 1112 h->ioalloc |= (1 << i); 1113 break; 1114 } 1115 } 1116 1117 if (win == -1) 1118 return (1); 1119 1120 *windowp = win; 1121 1122 /* XXX this is pretty gross */ 1123 1124 if (h->sc->iot != pcihp->iot) 1125 panic("pcic_chip_io_map iot is bogus"); 1126 1127 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1128 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1129 1130 /* XXX wtf is this doing here? */ 1131 1132 printf(" port 0x%lx", (u_long) ioaddr); 1133 if (size > 1) 1134 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1135 1136 h->io[win].addr = ioaddr; 1137 h->io[win].size = size; 1138 h->io[win].width = width; 1139 1140 pcic_chip_do_io_map(h, win); 1141 1142 return (0); 1143 } 1144 1145 void 1146 pcic_chip_io_unmap(pch, window) 1147 pcmcia_chipset_handle_t pch; 1148 int window; 1149 { 1150 struct pcic_handle *h = (struct pcic_handle *) pch; 1151 int reg; 1152 1153 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1154 panic("pcic_chip_io_unmap: window out of range"); 1155 1156 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1157 reg &= ~io_map_index[window].ioenable; 1158 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1159 1160 h->ioalloc &= ~(1 << window); 1161 } 1162 1163 static void 1164 pcic_wait_ready(h) 1165 struct pcic_handle *h; 1166 { 1167 int i; 1168 1169 for (i = 0; i < 10000; i++) { 1170 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1171 return; 1172 delay(500); 1173 #ifdef PCICDEBUG 1174 if (pcic_debug) { 1175 if ((i>5000) && (i%100 == 99)) 1176 printf("."); 1177 } 1178 #endif 1179 } 1180 1181 #ifdef DIAGNOSTIC 1182 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1183 pcic_read(h, PCIC_IF_STATUS)); 1184 #endif 1185 } 1186 1187 void 1188 pcic_chip_socket_enable(pch) 1189 pcmcia_chipset_handle_t pch; 1190 { 1191 struct pcic_handle *h = (struct pcic_handle *) pch; 1192 int cardtype, reg, win; 1193 1194 /* this bit is mostly stolen from pcic_attach_card */ 1195 1196 /* power down the socket to reset it, clear the card reset pin */ 1197 1198 pcic_write(h, PCIC_PWRCTL, 0); 1199 1200 /* 1201 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1202 * we are changing Vcc (Toff). 1203 */ 1204 delay((300 + 100) * 1000); 1205 1206 /* power up the socket */ 1207 1208 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1209 | PCIC_PWRCTL_PWR_ENABLE); 1210 1211 /* 1212 * wait 100ms until power raise (Tpr) and 20ms to become 1213 * stable (Tsu(Vcc)). 1214 * 1215 * some machines require some more time to be settled 1216 * (another 200ms is added here). 1217 */ 1218 delay((100 + 20 + 200) * 1000); 1219 1220 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1221 | PCIC_PWRCTL_PWR_ENABLE); 1222 pcic_write(h, PCIC_INTR, 0); 1223 1224 /* 1225 * hold RESET at least 10us. 1226 */ 1227 delay(10); 1228 1229 /* clear the reset flag */ 1230 1231 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1232 1233 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1234 1235 delay(20000); 1236 1237 /* wait for the chip to finish initializing */ 1238 1239 pcic_wait_ready(h); 1240 1241 /* zero out the address windows */ 1242 1243 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1244 1245 /* set the card type */ 1246 1247 cardtype = pcmcia_card_gettype(h->pcmcia); 1248 1249 reg = pcic_read(h, PCIC_INTR); 1250 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1251 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1252 PCIC_INTR_CARDTYPE_IO : 1253 PCIC_INTR_CARDTYPE_MEM); 1254 reg |= h->ih_irq; 1255 pcic_write(h, PCIC_INTR, reg); 1256 1257 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1258 h->sc->dev.dv_xname, h->sock, 1259 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1260 1261 /* reinstall all the memory and io mappings */ 1262 1263 for (win = 0; win < PCIC_MEM_WINS; win++) 1264 if (h->memalloc & (1 << win)) 1265 pcic_chip_do_mem_map(h, win); 1266 1267 for (win = 0; win < PCIC_IO_WINS; win++) 1268 if (h->ioalloc & (1 << win)) 1269 pcic_chip_do_io_map(h, win); 1270 } 1271 1272 void 1273 pcic_chip_socket_disable(pch) 1274 pcmcia_chipset_handle_t pch; 1275 { 1276 struct pcic_handle *h = (struct pcic_handle *) pch; 1277 1278 DPRINTF(("pcic_chip_socket_disable\n")); 1279 1280 /* power down the socket */ 1281 1282 pcic_write(h, PCIC_PWRCTL, 0); 1283 1284 /* 1285 * wait 300ms until power fails (Tpf). 1286 */ 1287 delay(300 * 1000); 1288 } 1289
Indexes created Sun Sep 28 16:09:52 GMT 2025