i82365.c revision 1.19
1 /* $NetBSD: i82365.c,v 1.19 1999/01/01 14:05:18 christos Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 #include <sys/kthread.h> 41 42 #include <vm/vm.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 50 #include <dev/ic/i82365reg.h> 51 #include <dev/ic/i82365var.h> 52 53 #include "locators.h" 54 55 #ifdef PCICDEBUG 56 int pcic_debug = 0; 57 #define DPRINTF(arg) if (pcic_debug) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #endif 61 62 #define PCIC_VENDOR_UNKNOWN 0 63 #define PCIC_VENDOR_I82365SLR0 1 64 #define PCIC_VENDOR_I82365SLR1 2 65 #define PCIC_VENDOR_CIRRUS_PD6710 3 66 #define PCIC_VENDOR_CIRRUS_PD672X 4 67 68 /* 69 * Individual drivers will allocate their own memory and io regions. Memory 70 * regions must be a multiple of 4k, aligned on a 4k boundary. 71 */ 72 73 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 74 75 void pcic_attach_socket __P((struct pcic_handle *)); 76 void pcic_init_socket __P((struct pcic_handle *)); 77 78 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 79 int pcic_print __P((void *arg, const char *pnp)); 80 int pcic_intr_socket __P((struct pcic_handle *)); 81 82 void pcic_attach_card __P((struct pcic_handle *)); 83 void pcic_detach_card __P((struct pcic_handle *, int)); 84 void pcic_deactivate_card __P((struct pcic_handle *)); 85 86 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 87 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 88 89 void pcic_create_event_thread __P((void *)); 90 void pcic_event_thread __P((void *)); 91 92 void pcic_queue_event __P((struct pcic_handle *, int)); 93 94 static void pcic_wait_ready __P((struct pcic_handle *)); 95 96 int 97 pcic_ident_ok(ident) 98 int ident; 99 { 100 /* this is very empirical and heuristic */ 101 102 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 103 return (0); 104 105 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 106 #ifdef DIAGNOSTIC 107 printf("pcic: does not support memory and I/O cards, " 108 "ignored (ident=%0x)\n", ident); 109 #endif 110 return (0); 111 } 112 return (1); 113 } 114 115 int 116 pcic_vendor(h) 117 struct pcic_handle *h; 118 { 119 int reg; 120 121 /* 122 * the chip_id of the cirrus toggles between 11 and 00 after a write. 123 * weird. 124 */ 125 126 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 127 reg = pcic_read(h, -1); 128 129 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 130 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 131 reg = pcic_read(h, -1); 132 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 133 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 134 return (PCIC_VENDOR_CIRRUS_PD672X); 135 else 136 return (PCIC_VENDOR_CIRRUS_PD6710); 137 } 138 } 139 140 reg = pcic_read(h, PCIC_IDENT); 141 142 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 143 return (PCIC_VENDOR_I82365SLR0); 144 else 145 return (PCIC_VENDOR_I82365SLR1); 146 147 return (PCIC_VENDOR_UNKNOWN); 148 } 149 150 char * 151 pcic_vendor_to_string(vendor) 152 int vendor; 153 { 154 switch (vendor) { 155 case PCIC_VENDOR_I82365SLR0: 156 return ("Intel 82365SL Revision 0"); 157 case PCIC_VENDOR_I82365SLR1: 158 return ("Intel 82365SL Revision 1"); 159 case PCIC_VENDOR_CIRRUS_PD6710: 160 return ("Cirrus PD6710"); 161 case PCIC_VENDOR_CIRRUS_PD672X: 162 return ("Cirrus PD672X"); 163 } 164 165 return ("Unknown controller"); 166 } 167 168 void 169 pcic_attach(sc) 170 struct pcic_softc *sc; 171 { 172 int vendor, count, i, reg; 173 174 /* now check for each controller/socket */ 175 176 /* 177 * this could be done with a loop, but it would violate the 178 * abstraction 179 */ 180 181 count = 0; 182 183 DPRINTF(("pcic ident regs:")); 184 185 sc->handle[0].sc = sc; 186 sc->handle[0].sock = C0SA; 187 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 188 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 189 count++; 190 } else { 191 sc->handle[0].flags = 0; 192 } 193 194 DPRINTF((" 0x%02x", reg)); 195 196 sc->handle[1].sc = sc; 197 sc->handle[1].sock = C0SB; 198 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 199 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 200 count++; 201 } else { 202 sc->handle[1].flags = 0; 203 } 204 205 DPRINTF((" 0x%02x", reg)); 206 207 /* 208 * The CL-PD6729 has only one controller and always returns 0 209 * if you try to read from the second one. Maybe pcic_ident_ok 210 * shouldn't accept 0? 211 */ 212 sc->handle[2].sc = sc; 213 sc->handle[2].sock = C1SA; 214 if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X || 215 pcic_read(&sc->handle[2], PCIC_IDENT) != 0) { 216 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], 217 PCIC_IDENT))) { 218 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 219 count++; 220 } else { 221 sc->handle[2].flags = 0; 222 } 223 224 DPRINTF((" 0x%02x", reg)); 225 226 sc->handle[3].sc = sc; 227 sc->handle[3].sock = C1SB; 228 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], 229 PCIC_IDENT))) { 230 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 231 count++; 232 } else { 233 sc->handle[3].flags = 0; 234 } 235 236 DPRINTF((" 0x%02x\n", reg)); 237 } 238 239 if (count == 0) 240 panic("pcic_attach: attach found no sockets"); 241 242 /* establish the interrupt */ 243 244 /* XXX block interrupts? */ 245 246 for (i = 0; i < PCIC_NSLOTS; i++) { 247 SIMPLEQ_INIT(&sc->handle[i].events); 248 #if 0 249 /* 250 * this should work, but w/o it, setting tty flags hangs at 251 * boot time. 252 */ 253 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 254 #endif 255 { 256 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 257 pcic_read(&sc->handle[i], PCIC_CSC); 258 } 259 } 260 261 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 262 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 263 vendor = pcic_vendor(&sc->handle[0]); 264 265 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 266 pcic_vendor_to_string(vendor)); 267 268 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 269 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 270 printf("sockets A and B\n"); 271 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 272 printf("socket A only\n"); 273 else 274 printf("socket B only\n"); 275 276 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 277 sc->handle[0].vendor = vendor; 278 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 279 sc->handle[1].vendor = vendor; 280 } 281 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 282 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 283 vendor = pcic_vendor(&sc->handle[2]); 284 285 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 286 pcic_vendor_to_string(vendor)); 287 288 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 289 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 290 printf("sockets A and B\n"); 291 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 292 printf("socket A only\n"); 293 else 294 printf("socket B only\n"); 295 296 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 297 sc->handle[2].vendor = vendor; 298 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 299 sc->handle[3].vendor = vendor; 300 } 301 } 302 303 void 304 pcic_attach_sockets(sc) 305 struct pcic_softc *sc; 306 { 307 int i; 308 309 for (i = 0; i < PCIC_NSLOTS; i++) 310 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 311 pcic_attach_socket(&sc->handle[i]); 312 } 313 314 void 315 pcic_attach_socket(h) 316 struct pcic_handle *h; 317 { 318 struct pcmciabus_attach_args paa; 319 320 /* initialize the rest of the handle */ 321 322 h->shutdown = 0; 323 h->memalloc = 0; 324 h->ioalloc = 0; 325 h->ih_irq = 0; 326 327 /* now, config one pcmcia device per socket */ 328 329 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 330 paa.pch = (pcmcia_chipset_handle_t) h; 331 paa.iobase = h->sc->iobase; 332 paa.iosize = h->sc->iosize; 333 334 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 335 pcic_submatch); 336 337 /* if there's actually a pcmcia device attached, initialize the slot */ 338 339 if (h->pcmcia) 340 pcic_init_socket(h); 341 } 342 343 void 344 pcic_create_event_thread(arg) 345 void *arg; 346 { 347 struct pcic_handle *h = arg; 348 const char *cs; 349 350 switch (h->sock) { 351 case C0SA: 352 cs = "0,0"; 353 break; 354 case C0SB: 355 cs = "0,1"; 356 break; 357 case C1SA: 358 cs = "1,0"; 359 break; 360 case C1SB: 361 cs = "1,1"; 362 break; 363 default: 364 panic("pcic_create_event_thread: unknown pcic socket"); 365 } 366 367 if (kthread_create(pcic_event_thread, h, &h->event_thread, 368 "%s,%s", h->sc->dev.dv_xname, cs)) { 369 printf("%s: unable to create event thread for sock 0x%02x\n", 370 h->sc->dev.dv_xname, h->sock); 371 panic("pcic_create_event_thread"); 372 } 373 } 374 375 void 376 pcic_event_thread(arg) 377 void *arg; 378 { 379 struct pcic_handle *h = arg; 380 struct pcic_event *pe; 381 int s; 382 383 while (h->shutdown == 0) { 384 s = splhigh(); 385 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 386 splx(s); 387 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 388 continue; 389 } 390 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 391 splx(s); 392 393 switch (pe->pe_type) { 394 case PCIC_EVENT_INSERTION: 395 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 396 pcic_attach_card(h); 397 break; 398 399 case PCIC_EVENT_REMOVAL: 400 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 401 pcic_detach_card(h, DETACH_FORCE); 402 break; 403 404 default: 405 panic("pcic_event_thread: unknown event %d", 406 pe->pe_type); 407 } 408 free(pe, M_TEMP); 409 } 410 411 h->event_thread = NULL; 412 413 /* In case parent is waiting for us to exit. */ 414 wakeup(h->sc); 415 416 kthread_exit(0); 417 } 418 419 void 420 pcic_init_socket(h) 421 struct pcic_handle *h; 422 { 423 int reg; 424 425 /* 426 * queue creation of a kernel thread to handle insert/removal events. 427 */ 428 #ifdef DIAGNOSTIC 429 if (h->event_thread != NULL) 430 panic("pcic_attach_socket: event thread"); 431 #endif 432 kthread_create_deferred(pcic_create_event_thread, h); 433 434 /* set up the card to interrupt on card detect */ 435 436 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 437 PCIC_CSC_INTR_CD_ENABLE); 438 pcic_write(h, PCIC_INTR, 0); 439 pcic_read(h, PCIC_CSC); 440 441 /* unsleep the cirrus controller */ 442 443 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 444 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 445 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 446 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 447 DPRINTF(("%s: socket %02x was suspended\n", 448 h->sc->dev.dv_xname, h->sock)); 449 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 450 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 451 } 452 } 453 /* if there's a card there, then attach it. */ 454 455 reg = pcic_read(h, PCIC_IF_STATUS); 456 457 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 458 PCIC_IF_STATUS_CARDDETECT_PRESENT) 459 pcic_attach_card(h); 460 } 461 462 int 463 pcic_submatch(parent, cf, aux) 464 struct device *parent; 465 struct cfdata *cf; 466 void *aux; 467 { 468 469 struct pcmciabus_attach_args *paa = aux; 470 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 471 472 switch (h->sock) { 473 case C0SA: 474 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 475 PCMCIABUSCF_CONTROLLER_DEFAULT && 476 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 477 return 0; 478 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 479 PCMCIABUSCF_SOCKET_DEFAULT && 480 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 481 return 0; 482 483 break; 484 case C0SB: 485 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 486 PCMCIABUSCF_CONTROLLER_DEFAULT && 487 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 488 return 0; 489 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 490 PCMCIABUSCF_SOCKET_DEFAULT && 491 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 492 return 0; 493 494 break; 495 case C1SA: 496 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 497 PCMCIABUSCF_CONTROLLER_DEFAULT && 498 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 499 return 0; 500 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 501 PCMCIABUSCF_SOCKET_DEFAULT && 502 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 503 return 0; 504 505 break; 506 case C1SB: 507 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 508 PCMCIABUSCF_CONTROLLER_DEFAULT && 509 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 510 return 0; 511 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 512 PCMCIABUSCF_SOCKET_DEFAULT && 513 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 514 return 0; 515 516 break; 517 default: 518 panic("unknown pcic socket"); 519 } 520 521 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 522 } 523 524 int 525 pcic_print(arg, pnp) 526 void *arg; 527 const char *pnp; 528 { 529 struct pcmciabus_attach_args *paa = arg; 530 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 531 532 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 533 if (pnp) 534 printf("pcmcia at %s", pnp); 535 536 switch (h->sock) { 537 case C0SA: 538 printf(" controller 0 socket 0"); 539 break; 540 case C0SB: 541 printf(" controller 0 socket 1"); 542 break; 543 case C1SA: 544 printf(" controller 1 socket 0"); 545 break; 546 case C1SB: 547 printf(" controller 1 socket 1"); 548 break; 549 default: 550 panic("unknown pcic socket"); 551 } 552 553 return (UNCONF); 554 } 555 556 int 557 pcic_intr(arg) 558 void *arg; 559 { 560 struct pcic_softc *sc = arg; 561 int i, ret = 0; 562 563 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 564 565 for (i = 0; i < PCIC_NSLOTS; i++) 566 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 567 ret += pcic_intr_socket(&sc->handle[i]); 568 569 return (ret ? 1 : 0); 570 } 571 572 int 573 pcic_intr_socket(h) 574 struct pcic_handle *h; 575 { 576 int cscreg; 577 578 cscreg = pcic_read(h, PCIC_CSC); 579 580 cscreg &= (PCIC_CSC_GPI | 581 PCIC_CSC_CD | 582 PCIC_CSC_READY | 583 PCIC_CSC_BATTWARN | 584 PCIC_CSC_BATTDEAD); 585 586 if (cscreg & PCIC_CSC_GPI) { 587 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 588 } 589 if (cscreg & PCIC_CSC_CD) { 590 int statreg; 591 592 statreg = pcic_read(h, PCIC_IF_STATUS); 593 594 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 595 statreg)); 596 597 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 598 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 599 if (!(h->flags & PCIC_FLAG_CARDP)) { 600 DPRINTF(("%s: enqueing INSERTION event\n", 601 h->sc->dev.dv_xname)); 602 pcic_queue_event(h, PCIC_EVENT_INSERTION); 603 } 604 } else { 605 if (h->flags & PCIC_FLAG_CARDP) { 606 /* Deactivate the card now. */ 607 DPRINTF(("%s: deactivating card\n", 608 h->sc->dev.dv_xname)); 609 pcic_deactivate_card(h); 610 611 DPRINTF(("%s: enqueing REMOVAL event\n", 612 h->sc->dev.dv_xname)); 613 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 614 } 615 } 616 } 617 if (cscreg & PCIC_CSC_READY) { 618 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 619 /* shouldn't happen */ 620 } 621 if (cscreg & PCIC_CSC_BATTWARN) { 622 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 623 } 624 if (cscreg & PCIC_CSC_BATTDEAD) { 625 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 626 } 627 return (cscreg ? 1 : 0); 628 } 629 630 void 631 pcic_queue_event(h, event) 632 struct pcic_handle *h; 633 int event; 634 { 635 struct pcic_event *pe; 636 int s; 637 638 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 639 if (pe == NULL) 640 panic("pcic_queue_event: can't allocate event"); 641 642 pe->pe_type = event; 643 s = splhigh(); 644 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 645 splx(s); 646 wakeup(&h->events); 647 } 648 649 void 650 pcic_attach_card(h) 651 struct pcic_handle *h; 652 { 653 654 if (h->flags & PCIC_FLAG_CARDP) 655 panic("pcic_attach_card: already attached"); 656 657 /* call the MI attach function */ 658 pcmcia_card_attach(h->pcmcia); 659 660 h->flags |= PCIC_FLAG_CARDP; 661 } 662 663 void 664 pcic_detach_card(h, flags) 665 struct pcic_handle *h; 666 int flags; /* DETACH_* */ 667 { 668 669 if (!(h->flags & PCIC_FLAG_CARDP)) 670 panic("pcic_detach_card: already detached"); 671 672 h->flags &= ~PCIC_FLAG_CARDP; 673 674 /* call the MI detach function */ 675 pcmcia_card_detach(h->pcmcia, flags); 676 } 677 678 void 679 pcic_deactivate_card(h) 680 struct pcic_handle *h; 681 { 682 683 if (!(h->flags & PCIC_FLAG_CARDP)) 684 panic("pcic_deactivate_card: already detached"); 685 686 /* call the MI deactivate function */ 687 pcmcia_card_deactivate(h->pcmcia); 688 689 /* power down the socket */ 690 pcic_write(h, PCIC_PWRCTL, 0); 691 692 /* reset the socket */ 693 pcic_write(h, PCIC_INTR, 0); 694 } 695 696 int 697 pcic_chip_mem_alloc(pch, size, pcmhp) 698 pcmcia_chipset_handle_t pch; 699 bus_size_t size; 700 struct pcmcia_mem_handle *pcmhp; 701 { 702 struct pcic_handle *h = (struct pcic_handle *) pch; 703 bus_space_handle_t memh; 704 bus_addr_t addr; 705 bus_size_t sizepg; 706 int i, mask, mhandle; 707 708 /* out of sc->memh, allocate as many pages as necessary */ 709 710 /* convert size to PCIC pages */ 711 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 712 if (sizepg > PCIC_MAX_MEM_PAGES) 713 return (1); 714 715 mask = (1 << sizepg) - 1; 716 717 addr = 0; /* XXX gcc -Wuninitialized */ 718 mhandle = 0; /* XXX gcc -Wuninitialized */ 719 720 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 721 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 722 if (bus_space_subregion(h->sc->memt, h->sc->memh, 723 i * PCIC_MEM_PAGESIZE, 724 sizepg * PCIC_MEM_PAGESIZE, &memh)) 725 return (1); 726 mhandle = mask << i; 727 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 728 h->sc->subregionmask &= ~(mhandle); 729 pcmhp->memt = h->sc->memt; 730 pcmhp->memh = memh; 731 pcmhp->addr = addr; 732 pcmhp->size = size; 733 pcmhp->mhandle = mhandle; 734 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 735 return (0); 736 } 737 } 738 739 return (1); 740 } 741 742 void 743 pcic_chip_mem_free(pch, pcmhp) 744 pcmcia_chipset_handle_t pch; 745 struct pcmcia_mem_handle *pcmhp; 746 { 747 struct pcic_handle *h = (struct pcic_handle *) pch; 748 749 h->sc->subregionmask |= pcmhp->mhandle; 750 } 751 752 static struct mem_map_index_st { 753 int sysmem_start_lsb; 754 int sysmem_start_msb; 755 int sysmem_stop_lsb; 756 int sysmem_stop_msb; 757 int cardmem_lsb; 758 int cardmem_msb; 759 int memenable; 760 } mem_map_index[] = { 761 { 762 PCIC_SYSMEM_ADDR0_START_LSB, 763 PCIC_SYSMEM_ADDR0_START_MSB, 764 PCIC_SYSMEM_ADDR0_STOP_LSB, 765 PCIC_SYSMEM_ADDR0_STOP_MSB, 766 PCIC_CARDMEM_ADDR0_LSB, 767 PCIC_CARDMEM_ADDR0_MSB, 768 PCIC_ADDRWIN_ENABLE_MEM0, 769 }, 770 { 771 PCIC_SYSMEM_ADDR1_START_LSB, 772 PCIC_SYSMEM_ADDR1_START_MSB, 773 PCIC_SYSMEM_ADDR1_STOP_LSB, 774 PCIC_SYSMEM_ADDR1_STOP_MSB, 775 PCIC_CARDMEM_ADDR1_LSB, 776 PCIC_CARDMEM_ADDR1_MSB, 777 PCIC_ADDRWIN_ENABLE_MEM1, 778 }, 779 { 780 PCIC_SYSMEM_ADDR2_START_LSB, 781 PCIC_SYSMEM_ADDR2_START_MSB, 782 PCIC_SYSMEM_ADDR2_STOP_LSB, 783 PCIC_SYSMEM_ADDR2_STOP_MSB, 784 PCIC_CARDMEM_ADDR2_LSB, 785 PCIC_CARDMEM_ADDR2_MSB, 786 PCIC_ADDRWIN_ENABLE_MEM2, 787 }, 788 { 789 PCIC_SYSMEM_ADDR3_START_LSB, 790 PCIC_SYSMEM_ADDR3_START_MSB, 791 PCIC_SYSMEM_ADDR3_STOP_LSB, 792 PCIC_SYSMEM_ADDR3_STOP_MSB, 793 PCIC_CARDMEM_ADDR3_LSB, 794 PCIC_CARDMEM_ADDR3_MSB, 795 PCIC_ADDRWIN_ENABLE_MEM3, 796 }, 797 { 798 PCIC_SYSMEM_ADDR4_START_LSB, 799 PCIC_SYSMEM_ADDR4_START_MSB, 800 PCIC_SYSMEM_ADDR4_STOP_LSB, 801 PCIC_SYSMEM_ADDR4_STOP_MSB, 802 PCIC_CARDMEM_ADDR4_LSB, 803 PCIC_CARDMEM_ADDR4_MSB, 804 PCIC_ADDRWIN_ENABLE_MEM4, 805 }, 806 }; 807 808 void 809 pcic_chip_do_mem_map(h, win) 810 struct pcic_handle *h; 811 int win; 812 { 813 int reg; 814 815 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 816 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 817 pcic_write(h, mem_map_index[win].sysmem_start_msb, 818 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 819 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 820 821 #if 0 822 /* XXX do I want 16 bit all the time? */ 823 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 824 #endif 825 826 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 827 ((h->mem[win].addr + h->mem[win].size) >> 828 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 829 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 830 (((h->mem[win].addr + h->mem[win].size) >> 831 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 832 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 833 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 834 835 pcic_write(h, mem_map_index[win].cardmem_lsb, 836 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 837 pcic_write(h, mem_map_index[win].cardmem_msb, 838 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 839 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 840 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 841 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 842 843 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 844 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 845 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 846 847 #ifdef PCICDEBUG 848 { 849 int r1, r2, r3, r4, r5, r6; 850 851 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 852 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 853 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 854 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 855 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 856 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 857 858 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 859 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 860 } 861 #endif 862 } 863 864 int 865 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 866 pcmcia_chipset_handle_t pch; 867 int kind; 868 bus_addr_t card_addr; 869 bus_size_t size; 870 struct pcmcia_mem_handle *pcmhp; 871 bus_addr_t *offsetp; 872 int *windowp; 873 { 874 struct pcic_handle *h = (struct pcic_handle *) pch; 875 bus_addr_t busaddr; 876 long card_offset; 877 int i, win; 878 879 win = -1; 880 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 881 i++) { 882 if ((h->memalloc & (1 << i)) == 0) { 883 win = i; 884 h->memalloc |= (1 << i); 885 break; 886 } 887 } 888 889 if (win == -1) 890 return (1); 891 892 *windowp = win; 893 894 /* XXX this is pretty gross */ 895 896 if (h->sc->memt != pcmhp->memt) 897 panic("pcic_chip_mem_map memt is bogus"); 898 899 busaddr = pcmhp->addr; 900 901 /* 902 * compute the address offset to the pcmcia address space for the 903 * pcic. this is intentionally signed. The masks and shifts below 904 * will cause TRT to happen in the pcic registers. Deal with making 905 * sure the address is aligned, and return the alignment offset. 906 */ 907 908 *offsetp = card_addr % PCIC_MEM_ALIGN; 909 card_addr -= *offsetp; 910 911 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 912 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 913 (u_long) card_addr)); 914 915 /* 916 * include the offset in the size, and decrement size by one, since 917 * the hw wants start/stop 918 */ 919 size += *offsetp - 1; 920 921 card_offset = (((long) card_addr) - ((long) busaddr)); 922 923 h->mem[win].addr = busaddr; 924 h->mem[win].size = size; 925 h->mem[win].offset = card_offset; 926 h->mem[win].kind = kind; 927 928 pcic_chip_do_mem_map(h, win); 929 930 return (0); 931 } 932 933 void 934 pcic_chip_mem_unmap(pch, window) 935 pcmcia_chipset_handle_t pch; 936 int window; 937 { 938 struct pcic_handle *h = (struct pcic_handle *) pch; 939 int reg; 940 941 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 942 panic("pcic_chip_mem_unmap: window out of range"); 943 944 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 945 reg &= ~mem_map_index[window].memenable; 946 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 947 948 h->memalloc &= ~(1 << window); 949 } 950 951 int 952 pcic_chip_io_alloc(pch, start, size, align, pcihp) 953 pcmcia_chipset_handle_t pch; 954 bus_addr_t start; 955 bus_size_t size; 956 bus_size_t align; 957 struct pcmcia_io_handle *pcihp; 958 { 959 struct pcic_handle *h = (struct pcic_handle *) pch; 960 bus_space_tag_t iot; 961 bus_space_handle_t ioh; 962 bus_addr_t ioaddr; 963 int flags = 0; 964 965 /* 966 * Allocate some arbitrary I/O space. 967 */ 968 969 iot = h->sc->iot; 970 971 if (start) { 972 ioaddr = start; 973 if (bus_space_map(iot, start, size, 0, &ioh)) 974 return (1); 975 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 976 (u_long) ioaddr, (u_long) size)); 977 } else { 978 flags |= PCMCIA_IO_ALLOCATED; 979 if (bus_space_alloc(iot, h->sc->iobase, 980 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 981 &ioaddr, &ioh)) 982 return (1); 983 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 984 (u_long) ioaddr, (u_long) size)); 985 } 986 987 pcihp->iot = iot; 988 pcihp->ioh = ioh; 989 pcihp->addr = ioaddr; 990 pcihp->size = size; 991 pcihp->flags = flags; 992 993 return (0); 994 } 995 996 void 997 pcic_chip_io_free(pch, pcihp) 998 pcmcia_chipset_handle_t pch; 999 struct pcmcia_io_handle *pcihp; 1000 { 1001 bus_space_tag_t iot = pcihp->iot; 1002 bus_space_handle_t ioh = pcihp->ioh; 1003 bus_size_t size = pcihp->size; 1004 1005 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1006 bus_space_free(iot, ioh, size); 1007 else 1008 bus_space_unmap(iot, ioh, size); 1009 } 1010 1011 1012 static struct io_map_index_st { 1013 int start_lsb; 1014 int start_msb; 1015 int stop_lsb; 1016 int stop_msb; 1017 int ioenable; 1018 int ioctlmask; 1019 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1020 } io_map_index[] = { 1021 { 1022 PCIC_IOADDR0_START_LSB, 1023 PCIC_IOADDR0_START_MSB, 1024 PCIC_IOADDR0_STOP_LSB, 1025 PCIC_IOADDR0_STOP_MSB, 1026 PCIC_ADDRWIN_ENABLE_IO0, 1027 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1028 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1029 { 1030 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1031 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1032 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1033 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1034 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1035 }, 1036 }, 1037 { 1038 PCIC_IOADDR1_START_LSB, 1039 PCIC_IOADDR1_START_MSB, 1040 PCIC_IOADDR1_STOP_LSB, 1041 PCIC_IOADDR1_STOP_MSB, 1042 PCIC_ADDRWIN_ENABLE_IO1, 1043 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1044 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1045 { 1046 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1047 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1048 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1049 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1050 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1051 }, 1052 }, 1053 }; 1054 1055 void 1056 pcic_chip_do_io_map(h, win) 1057 struct pcic_handle *h; 1058 int win; 1059 { 1060 int reg; 1061 1062 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1063 win, (long) h->io[win].addr, (long) h->io[win].size, 1064 h->io[win].width * 8)); 1065 1066 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1067 pcic_write(h, io_map_index[win].start_msb, 1068 (h->io[win].addr >> 8) & 0xff); 1069 1070 pcic_write(h, io_map_index[win].stop_lsb, 1071 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1072 pcic_write(h, io_map_index[win].stop_msb, 1073 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1074 1075 reg = pcic_read(h, PCIC_IOCTL); 1076 reg &= ~io_map_index[win].ioctlmask; 1077 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1078 pcic_write(h, PCIC_IOCTL, reg); 1079 1080 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1081 reg |= io_map_index[win].ioenable; 1082 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1083 } 1084 1085 int 1086 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1087 pcmcia_chipset_handle_t pch; 1088 int width; 1089 bus_addr_t offset; 1090 bus_size_t size; 1091 struct pcmcia_io_handle *pcihp; 1092 int *windowp; 1093 { 1094 struct pcic_handle *h = (struct pcic_handle *) pch; 1095 bus_addr_t ioaddr = pcihp->addr + offset; 1096 int i, win; 1097 #ifdef PCICDEBUG 1098 static char *width_names[] = { "auto", "io8", "io16" }; 1099 #endif 1100 1101 /* XXX Sanity check offset/size. */ 1102 1103 win = -1; 1104 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1105 if ((h->ioalloc & (1 << i)) == 0) { 1106 win = i; 1107 h->ioalloc |= (1 << i); 1108 break; 1109 } 1110 } 1111 1112 if (win == -1) 1113 return (1); 1114 1115 *windowp = win; 1116 1117 /* XXX this is pretty gross */ 1118 1119 if (h->sc->iot != pcihp->iot) 1120 panic("pcic_chip_io_map iot is bogus"); 1121 1122 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1123 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1124 1125 /* XXX wtf is this doing here? */ 1126 1127 printf(" port 0x%lx", (u_long) ioaddr); 1128 if (size > 1) 1129 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1130 1131 h->io[win].addr = ioaddr; 1132 h->io[win].size = size; 1133 h->io[win].width = width; 1134 1135 pcic_chip_do_io_map(h, win); 1136 1137 return (0); 1138 } 1139 1140 void 1141 pcic_chip_io_unmap(pch, window) 1142 pcmcia_chipset_handle_t pch; 1143 int window; 1144 { 1145 struct pcic_handle *h = (struct pcic_handle *) pch; 1146 int reg; 1147 1148 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1149 panic("pcic_chip_io_unmap: window out of range"); 1150 1151 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1152 reg &= ~io_map_index[window].ioenable; 1153 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1154 1155 h->ioalloc &= ~(1 << window); 1156 } 1157 1158 static void 1159 pcic_wait_ready(h) 1160 struct pcic_handle *h; 1161 { 1162 int i; 1163 1164 for (i = 0; i < 10000; i++) { 1165 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1166 return; 1167 delay(500); 1168 #ifdef PCICDEBUG 1169 if (pcic_debug) { 1170 if ((i>5000) && (i%100 == 99)) 1171 printf("."); 1172 } 1173 #endif 1174 } 1175 1176 #ifdef DIAGNOSTIC 1177 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1178 pcic_read(h, PCIC_IF_STATUS)); 1179 #endif 1180 } 1181 1182 void 1183 pcic_chip_socket_enable(pch) 1184 pcmcia_chipset_handle_t pch; 1185 { 1186 struct pcic_handle *h = (struct pcic_handle *) pch; 1187 int cardtype, reg, win; 1188 1189 /* this bit is mostly stolen from pcic_attach_card */ 1190 1191 /* power down the socket to reset it, clear the card reset pin */ 1192 1193 pcic_write(h, PCIC_PWRCTL, 0); 1194 1195 /* 1196 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1197 * we are changing Vcc (Toff). 1198 */ 1199 delay((300 + 100) * 1000); 1200 1201 /* power up the socket */ 1202 1203 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1204 | PCIC_PWRCTL_PWR_ENABLE); 1205 1206 /* 1207 * wait 100ms until power raise (Tpr) and 20ms to become 1208 * stable (Tsu(Vcc)). 1209 * 1210 * some machines require some more time to be settled 1211 * (another 200ms is added here). 1212 */ 1213 delay((100 + 20 + 200) * 1000); 1214 1215 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1216 | PCIC_PWRCTL_PWR_ENABLE); 1217 pcic_write(h, PCIC_INTR, 0); 1218 1219 /* 1220 * hold RESET at least 10us. 1221 */ 1222 delay(10); 1223 1224 /* clear the reset flag */ 1225 1226 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1227 1228 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1229 1230 delay(20000); 1231 1232 /* wait for the chip to finish initializing */ 1233 1234 pcic_wait_ready(h); 1235 1236 /* zero out the address windows */ 1237 1238 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1239 1240 /* set the card type */ 1241 1242 cardtype = pcmcia_card_gettype(h->pcmcia); 1243 1244 reg = pcic_read(h, PCIC_INTR); 1245 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1246 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1247 PCIC_INTR_CARDTYPE_IO : 1248 PCIC_INTR_CARDTYPE_MEM); 1249 reg |= h->ih_irq; 1250 pcic_write(h, PCIC_INTR, reg); 1251 1252 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1253 h->sc->dev.dv_xname, h->sock, 1254 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1255 1256 /* reinstall all the memory and io mappings */ 1257 1258 for (win = 0; win < PCIC_MEM_WINS; win++) 1259 if (h->memalloc & (1 << win)) 1260 pcic_chip_do_mem_map(h, win); 1261 1262 for (win = 0; win < PCIC_IO_WINS; win++) 1263 if (h->ioalloc & (1 << win)) 1264 pcic_chip_do_io_map(h, win); 1265 } 1266 1267 void 1268 pcic_chip_socket_disable(pch) 1269 pcmcia_chipset_handle_t pch; 1270 { 1271 struct pcic_handle *h = (struct pcic_handle *) pch; 1272 1273 DPRINTF(("pcic_chip_socket_disable\n")); 1274 1275 /* power down the socket */ 1276 1277 pcic_write(h, PCIC_PWRCTL, 0); 1278 1279 /* 1280 * wait 300ms until power fails (Tpf). 1281 */ 1282 delay(300 * 1000); 1283 } 1284
Indexes created Mon Sep 29 13:09:55 GMT 2025