i82365.c revision 1.2
1 /* $NetBSD: i82365.c,v 1.2 1997/10/16 23:21:46 thorpej Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 41 #include <vm/vm.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/i82365reg.h> 50 #include <dev/ic/i82365var.h> 51 52 #ifdef PCICDEBUG 53 int pcic_debug = 0; 54 #define DPRINTF(arg) if (pcic_debug) printf arg; 55 #else 56 #define DPRINTF(arg) 57 #endif 58 59 #define PCIC_VENDOR_UNKNOWN 0 60 #define PCIC_VENDOR_I82365SLR0 1 61 #define PCIC_VENDOR_I82365SLR1 2 62 #define PCIC_VENDOR_CIRRUS_PD6710 3 63 #define PCIC_VENDOR_CIRRUS_PD672X 4 64 65 /* 66 * Individual drivers will allocate their own memory and io regions. Memory 67 * regions must be a multiple of 4k, aligned on a 4k boundary. 68 */ 69 70 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 71 72 void pcic_attach_socket __P((struct pcic_handle *)); 73 void pcic_init_socket __P((struct pcic_handle *)); 74 75 #ifdef __BROKEN_INDIRECT_CONFIG 76 int pcic_submatch __P((struct device *, void *, void *)); 77 #else 78 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 79 #endif 80 int pcic_print __P((void *arg, const char *pnp)); 81 int pcic_intr_socket __P((struct pcic_handle *)); 82 83 void pcic_attach_card __P((struct pcic_handle *)); 84 void pcic_detach_card __P((struct pcic_handle *)); 85 86 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 87 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 88 89 struct cfdriver pcic_cd = { 90 NULL, "pcic", DV_DULL 91 }; 92 93 int 94 pcic_ident_ok(ident) 95 int ident; 96 { 97 /* this is very empirical and heuristic */ 98 99 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 100 return (0); 101 102 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 103 #ifdef DIAGNOSTIC 104 printf("pcic: does not support memory and I/O cards, " 105 "ignored (ident=%0x)\n", ident); 106 #endif 107 return (0); 108 } 109 return (1); 110 } 111 112 int 113 pcic_vendor(h) 114 struct pcic_handle *h; 115 { 116 int reg; 117 118 /* 119 * the chip_id of the cirrus toggles between 11 and 00 after a write. 120 * weird. 121 */ 122 123 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 124 reg = pcic_read(h, -1); 125 126 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 127 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 128 reg = pcic_read(h, -1); 129 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 130 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 131 return (PCIC_VENDOR_CIRRUS_PD672X); 132 else 133 return (PCIC_VENDOR_CIRRUS_PD6710); 134 } 135 } 136 /* XXX how do I identify the GD6729? */ 137 138 reg = pcic_read(h, PCIC_IDENT); 139 140 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 141 return (PCIC_VENDOR_I82365SLR0); 142 else 143 return (PCIC_VENDOR_I82365SLR1); 144 145 return (PCIC_VENDOR_UNKNOWN); 146 } 147 148 char * 149 pcic_vendor_to_string(vendor) 150 int vendor; 151 { 152 switch (vendor) { 153 case PCIC_VENDOR_I82365SLR0: 154 return ("Intel 82365SL Revision 0"); 155 case PCIC_VENDOR_I82365SLR1: 156 return ("Intel 82365SL Revision 1"); 157 case PCIC_VENDOR_CIRRUS_PD6710: 158 return ("Cirrus PD6710"); 159 case PCIC_VENDOR_CIRRUS_PD672X: 160 return ("Cirrus PD672X"); 161 } 162 163 return ("Unknown controller"); 164 } 165 166 void 167 pcic_attach(sc) 168 struct pcic_softc *sc; 169 { 170 int vendor, count, i, reg; 171 172 /* now check for each controller/socket */ 173 174 /* 175 * this could be done with a loop, but it would violate the 176 * abstraction 177 */ 178 179 count = 0; 180 181 DPRINTF(("pcic ident regs:")); 182 183 sc->handle[0].sc = sc; 184 sc->handle[0].sock = C0SA; 185 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 186 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 187 count++; 188 } else { 189 sc->handle[0].flags = 0; 190 } 191 192 DPRINTF((" 0x%02x", reg)); 193 194 sc->handle[1].sc = sc; 195 sc->handle[1].sock = C0SB; 196 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 197 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 198 count++; 199 } else { 200 sc->handle[1].flags = 0; 201 } 202 203 DPRINTF((" 0x%02x", reg)); 204 205 sc->handle[2].sc = sc; 206 sc->handle[2].sock = C1SA; 207 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], PCIC_IDENT))) { 208 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 209 count++; 210 } else { 211 sc->handle[2].flags = 0; 212 } 213 214 DPRINTF((" 0x%02x", reg)); 215 216 sc->handle[3].sc = sc; 217 sc->handle[3].sock = C1SB; 218 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], PCIC_IDENT))) { 219 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 220 count++; 221 } else { 222 sc->handle[3].flags = 0; 223 } 224 225 DPRINTF((" 0x%02x\n", reg)); 226 227 if (count == 0) 228 panic("pcic_attach: attach found no sockets"); 229 230 /* establish the interrupt */ 231 232 /* XXX block interrupts? */ 233 234 for (i = 0; i < PCIC_NSLOTS; i++) { 235 #if 0 236 /* 237 * this should work, but w/o it, setting tty flags hangs at 238 * boot time. 239 */ 240 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 241 #endif 242 { 243 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 244 pcic_read(&sc->handle[i], PCIC_CSC); 245 } 246 } 247 248 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 249 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 250 vendor = pcic_vendor(&sc->handle[0]); 251 252 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 253 pcic_vendor_to_string(vendor)); 254 255 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 256 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 257 printf("sockets A and B\n"); 258 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 259 printf("socket A only\n"); 260 else 261 printf("socket B only\n"); 262 263 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 264 sc->handle[0].vendor = vendor; 265 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 266 sc->handle[1].vendor = vendor; 267 } 268 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 269 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 270 vendor = pcic_vendor(&sc->handle[2]); 271 272 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 273 pcic_vendor_to_string(vendor)); 274 275 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 276 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 277 printf("sockets A and B\n"); 278 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 279 printf("socket A only\n"); 280 else 281 printf("socket B only\n"); 282 283 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 284 sc->handle[2].vendor = vendor; 285 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 286 sc->handle[3].vendor = vendor; 287 } 288 } 289 290 void 291 pcic_attach_sockets(sc) 292 struct pcic_softc *sc; 293 { 294 int i; 295 296 for (i = 0; i < PCIC_NSLOTS; i++) 297 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 298 pcic_attach_socket(&sc->handle[i]); 299 } 300 301 void 302 pcic_attach_socket(h) 303 struct pcic_handle *h; 304 { 305 struct pcmciabus_attach_args paa; 306 307 /* initialize the rest of the handle */ 308 309 h->memalloc = 0; 310 h->ioalloc = 0; 311 h->ih_irq = 0; 312 313 /* now, config one pcmcia device per socket */ 314 315 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 316 paa.pch = (pcmcia_chipset_handle_t) h; 317 paa.iobase = h->sc->iobase; 318 paa.iosize = h->sc->iosize; 319 320 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 321 pcic_submatch); 322 323 /* if there's actually a pcmcia device attached, initialize the slot */ 324 325 if (h->pcmcia) 326 pcic_init_socket(h); 327 } 328 329 void 330 pcic_init_socket(h) 331 struct pcic_handle *h; 332 { 333 int reg; 334 335 /* set up the card to interrupt on card detect */ 336 337 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 338 PCIC_CSC_INTR_CD_ENABLE); 339 pcic_write(h, PCIC_INTR, 0); 340 pcic_read(h, PCIC_CSC); 341 342 /* unsleep the cirrus controller */ 343 344 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 345 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 346 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 347 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 348 DPRINTF(("%s: socket %02x was suspended\n", 349 h->sc->dev.dv_xname, h->sock)); 350 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 351 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 352 } 353 } 354 /* if there's a card there, then attach it. */ 355 356 reg = pcic_read(h, PCIC_IF_STATUS); 357 358 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 359 PCIC_IF_STATUS_CARDDETECT_PRESENT) 360 pcic_attach_card(h); 361 } 362 363 int 364 #ifdef __BROKEN_INDIRECT_CONFIG 365 pcic_submatch(parent, match, aux) 366 #else 367 pcic_submatch(parent, cf, aux) 368 #endif 369 struct device *parent; 370 #ifdef __BROKEN_INDIRECT_CONFIG 371 void *match; 372 #else 373 struct cfdata *cf; 374 #endif 375 void *aux; 376 { 377 #ifdef __BROKEN_INDIRECT_CONFIG 378 struct cfdata *cf = match; 379 #endif 380 381 struct pcmciabus_attach_args *paa = 382 (struct pcmciabus_attach_args *) aux; 383 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 384 385 switch (h->sock) { 386 case C0SA: 387 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 0) 388 return 0; 389 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 0) 390 return 0; 391 392 break; 393 case C0SB: 394 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 0) 395 return 0; 396 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 1) 397 return 0; 398 399 break; 400 case C1SA: 401 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 1) 402 return 0; 403 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 0) 404 return 0; 405 406 break; 407 case C1SB: 408 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 1) 409 return 0; 410 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 1) 411 return 0; 412 413 break; 414 default: 415 panic("unknown pcic socket"); 416 } 417 418 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 419 } 420 421 int 422 pcic_print(arg, pnp) 423 void *arg; 424 const char *pnp; 425 { 426 struct pcmciabus_attach_args *paa = 427 (struct pcmciabus_attach_args *) arg; 428 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 429 430 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 431 if (pnp) 432 printf("pcmcia at %s", pnp); 433 434 switch (h->sock) { 435 case C0SA: 436 printf(" controller 0 socket 0"); 437 break; 438 case C0SB: 439 printf(" controller 0 socket 1"); 440 break; 441 case C1SA: 442 printf(" controller 1 socket 0"); 443 break; 444 case C1SB: 445 printf(" controller 1 socket 1"); 446 break; 447 default: 448 panic("unknown pcic socket"); 449 } 450 451 return (UNCONF); 452 } 453 454 int 455 pcic_intr(arg) 456 void *arg; 457 { 458 struct pcic_softc *sc = (struct pcic_softc *) arg; 459 int i, ret = 0; 460 461 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 462 463 for (i = 0; i < PCIC_NSLOTS; i++) 464 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 465 ret += pcic_intr_socket(&sc->handle[i]); 466 467 return (ret ? 1 : 0); 468 } 469 470 int 471 pcic_intr_socket(h) 472 struct pcic_handle *h; 473 { 474 int cscreg; 475 476 cscreg = pcic_read(h, PCIC_CSC); 477 478 cscreg &= (PCIC_CSC_GPI | 479 PCIC_CSC_CD | 480 PCIC_CSC_READY | 481 PCIC_CSC_BATTWARN | 482 PCIC_CSC_BATTDEAD); 483 484 if (cscreg & PCIC_CSC_GPI) { 485 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 486 } 487 if (cscreg & PCIC_CSC_CD) { 488 int statreg; 489 490 statreg = pcic_read(h, PCIC_IF_STATUS); 491 492 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 493 statreg)); 494 495 /* 496 * XXX This should probably schedule something to happen 497 * after the interrupt handler completes 498 */ 499 500 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 501 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 502 if (!(h->flags & PCIC_FLAG_CARDP)) 503 pcic_attach_card(h); 504 } else { 505 if (h->flags & PCIC_FLAG_CARDP) 506 pcic_detach_card(h); 507 } 508 } 509 if (cscreg & PCIC_CSC_READY) { 510 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 511 /* shouldn't happen */ 512 } 513 if (cscreg & PCIC_CSC_BATTWARN) { 514 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 515 } 516 if (cscreg & PCIC_CSC_BATTDEAD) { 517 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 518 } 519 return (cscreg ? 1 : 0); 520 } 521 522 void 523 pcic_attach_card(h) 524 struct pcic_handle *h; 525 { 526 if (h->flags & PCIC_FLAG_CARDP) 527 panic("pcic_attach_card: already attached"); 528 529 /* call the MI attach function */ 530 531 pcmcia_card_attach(h->pcmcia); 532 533 h->flags |= PCIC_FLAG_CARDP; 534 } 535 536 void 537 pcic_detach_card(h) 538 struct pcic_handle *h; 539 { 540 if (!(h->flags & PCIC_FLAG_CARDP)) 541 panic("pcic_attach_card: already detached"); 542 543 h->flags &= ~PCIC_FLAG_CARDP; 544 545 /* call the MI attach function */ 546 547 pcmcia_card_detach(h->pcmcia); 548 549 /* disable card detect resume and configuration reset */ 550 551 /* power down the socket */ 552 553 pcic_write(h, PCIC_PWRCTL, 0); 554 555 /* reset the card */ 556 557 pcic_write(h, PCIC_INTR, 0); 558 } 559 560 int 561 pcic_chip_mem_alloc(pch, size, pcmhp) 562 pcmcia_chipset_handle_t pch; 563 bus_size_t size; 564 struct pcmcia_mem_handle *pcmhp; 565 { 566 struct pcic_handle *h = (struct pcic_handle *) pch; 567 bus_space_handle_t memh; 568 bus_addr_t addr; 569 bus_size_t sizepg; 570 int i, mask, mhandle; 571 572 /* out of sc->memh, allocate as many pages as necessary */ 573 574 /* convert size to PCIC pages */ 575 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 576 577 mask = (1 << sizepg) - 1; 578 579 addr = 0; /* XXX gcc -Wuninitialized */ 580 mhandle = 0; /* XXX gcc -Wuninitialized */ 581 582 for (i = 0; i < (PCIC_MEM_PAGES + 1 - sizepg); i++) { 583 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 584 if (bus_space_subregion(h->sc->memt, h->sc->memh, 585 i * PCIC_MEM_PAGESIZE, 586 sizepg * PCIC_MEM_PAGESIZE, &memh)) 587 return (1); 588 mhandle = mask << i; 589 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 590 h->sc->subregionmask &= ~(mhandle); 591 break; 592 } 593 } 594 595 if (i == (PCIC_MEM_PAGES + 1 - size)) 596 return (1); 597 598 DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 599 (u_long) size)); 600 601 pcmhp->memt = h->sc->memt; 602 pcmhp->memh = memh; 603 pcmhp->addr = addr; 604 pcmhp->size = size; 605 pcmhp->mhandle = mhandle; 606 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 607 608 return (0); 609 } 610 611 void 612 pcic_chip_mem_free(pch, pcmhp) 613 pcmcia_chipset_handle_t pch; 614 struct pcmcia_mem_handle *pcmhp; 615 { 616 struct pcic_handle *h = (struct pcic_handle *) pch; 617 618 h->sc->subregionmask |= pcmhp->mhandle; 619 } 620 621 static struct mem_map_index_st { 622 int sysmem_start_lsb; 623 int sysmem_start_msb; 624 int sysmem_stop_lsb; 625 int sysmem_stop_msb; 626 int cardmem_lsb; 627 int cardmem_msb; 628 int memenable; 629 } mem_map_index[] = { 630 { 631 PCIC_SYSMEM_ADDR0_START_LSB, 632 PCIC_SYSMEM_ADDR0_START_MSB, 633 PCIC_SYSMEM_ADDR0_STOP_LSB, 634 PCIC_SYSMEM_ADDR0_STOP_MSB, 635 PCIC_CARDMEM_ADDR0_LSB, 636 PCIC_CARDMEM_ADDR0_MSB, 637 PCIC_ADDRWIN_ENABLE_MEM0, 638 }, 639 { 640 PCIC_SYSMEM_ADDR1_START_LSB, 641 PCIC_SYSMEM_ADDR1_START_MSB, 642 PCIC_SYSMEM_ADDR1_STOP_LSB, 643 PCIC_SYSMEM_ADDR1_STOP_MSB, 644 PCIC_CARDMEM_ADDR1_LSB, 645 PCIC_CARDMEM_ADDR1_MSB, 646 PCIC_ADDRWIN_ENABLE_MEM1, 647 }, 648 { 649 PCIC_SYSMEM_ADDR2_START_LSB, 650 PCIC_SYSMEM_ADDR2_START_MSB, 651 PCIC_SYSMEM_ADDR2_STOP_LSB, 652 PCIC_SYSMEM_ADDR2_STOP_MSB, 653 PCIC_CARDMEM_ADDR2_LSB, 654 PCIC_CARDMEM_ADDR2_MSB, 655 PCIC_ADDRWIN_ENABLE_MEM2, 656 }, 657 { 658 PCIC_SYSMEM_ADDR3_START_LSB, 659 PCIC_SYSMEM_ADDR3_START_MSB, 660 PCIC_SYSMEM_ADDR3_STOP_LSB, 661 PCIC_SYSMEM_ADDR3_STOP_MSB, 662 PCIC_CARDMEM_ADDR3_LSB, 663 PCIC_CARDMEM_ADDR3_MSB, 664 PCIC_ADDRWIN_ENABLE_MEM3, 665 }, 666 { 667 PCIC_SYSMEM_ADDR4_START_LSB, 668 PCIC_SYSMEM_ADDR4_START_MSB, 669 PCIC_SYSMEM_ADDR4_STOP_LSB, 670 PCIC_SYSMEM_ADDR4_STOP_MSB, 671 PCIC_CARDMEM_ADDR4_LSB, 672 PCIC_CARDMEM_ADDR4_MSB, 673 PCIC_ADDRWIN_ENABLE_MEM4, 674 }, 675 }; 676 677 void 678 pcic_chip_do_mem_map(h, win) 679 struct pcic_handle *h; 680 int win; 681 { 682 int reg; 683 684 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 685 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 686 pcic_write(h, mem_map_index[win].sysmem_start_msb, 687 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 688 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 689 690 #if 0 691 /* XXX do I want 16 bit all the time? */ 692 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 693 #endif 694 695 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 696 ((h->mem[win].addr + h->mem[win].size) >> 697 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 698 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 699 (((h->mem[win].addr + h->mem[win].size) >> 700 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 701 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 702 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 703 704 pcic_write(h, mem_map_index[win].cardmem_lsb, 705 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 706 pcic_write(h, mem_map_index[win].cardmem_msb, 707 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 708 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 709 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 710 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 711 712 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 713 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 714 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 715 716 #ifdef PCICDEBUG 717 { 718 int r1, r2, r3, r4, r5, r6; 719 720 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 721 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 722 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 723 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 724 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 725 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 726 727 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 728 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 729 } 730 #endif 731 } 732 733 int 734 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 735 pcmcia_chipset_handle_t pch; 736 int kind; 737 bus_addr_t card_addr; 738 bus_size_t size; 739 struct pcmcia_mem_handle *pcmhp; 740 bus_addr_t *offsetp; 741 int *windowp; 742 { 743 struct pcic_handle *h = (struct pcic_handle *) pch; 744 bus_addr_t busaddr; 745 long card_offset; 746 int i, win; 747 748 win = -1; 749 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 750 i++) { 751 if ((h->memalloc & (1 << i)) == 0) { 752 win = i; 753 h->memalloc |= (1 << i); 754 break; 755 } 756 } 757 758 if (win == -1) 759 return (1); 760 761 *windowp = win; 762 763 /* XXX this is pretty gross */ 764 765 if (h->sc->memt != pcmhp->memt) 766 panic("pcic_chip_mem_map memt is bogus"); 767 768 busaddr = pcmhp->addr; 769 770 /* 771 * compute the address offset to the pcmcia address space for the 772 * pcic. this is intentionally signed. The masks and shifts below 773 * will cause TRT to happen in the pcic registers. Deal with making 774 * sure the address is aligned, and return the alignment offset. 775 */ 776 777 *offsetp = card_addr % PCIC_MEM_ALIGN; 778 card_addr -= *offsetp; 779 780 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 781 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 782 (u_long) card_addr)); 783 784 /* 785 * include the offset in the size, and decrement size by one, since 786 * the hw wants start/stop 787 */ 788 size += *offsetp - 1; 789 790 card_offset = (((long) card_addr) - ((long) busaddr)); 791 792 h->mem[win].addr = busaddr; 793 h->mem[win].size = size; 794 h->mem[win].offset = card_offset; 795 h->mem[win].kind = kind; 796 797 pcic_chip_do_mem_map(h, win); 798 799 return (0); 800 } 801 802 void 803 pcic_chip_mem_unmap(pch, window) 804 pcmcia_chipset_handle_t pch; 805 int window; 806 { 807 struct pcic_handle *h = (struct pcic_handle *) pch; 808 int reg; 809 810 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 811 panic("pcic_chip_mem_unmap: window out of range"); 812 813 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 814 reg &= ~mem_map_index[window].memenable; 815 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 816 817 h->memalloc &= ~(1 << window); 818 } 819 820 int 821 pcic_chip_io_alloc(pch, start, size, align, pcihp) 822 pcmcia_chipset_handle_t pch; 823 bus_addr_t start; 824 bus_size_t size; 825 bus_size_t align; 826 struct pcmcia_io_handle *pcihp; 827 { 828 struct pcic_handle *h = (struct pcic_handle *) pch; 829 bus_space_tag_t iot; 830 bus_space_handle_t ioh; 831 bus_addr_t ioaddr; 832 int flags = 0; 833 834 /* 835 * Allocate some arbitrary I/O space. 836 */ 837 838 iot = h->sc->iot; 839 840 if (start) { 841 ioaddr = start; 842 if (bus_space_map(iot, start, size, 0, &ioh)) 843 return (1); 844 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 845 (u_long) ioaddr, (u_long) size)); 846 } else { 847 flags |= PCMCIA_IO_ALLOCATED; 848 if (bus_space_alloc(iot, h->sc->iobase, 849 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 850 &ioaddr, &ioh)) 851 return (1); 852 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 853 (u_long) ioaddr, (u_long) size)); 854 } 855 856 pcihp->iot = iot; 857 pcihp->ioh = ioh; 858 pcihp->addr = ioaddr; 859 pcihp->size = size; 860 pcihp->flags = flags; 861 862 return (0); 863 } 864 865 void 866 pcic_chip_io_free(pch, pcihp) 867 pcmcia_chipset_handle_t pch; 868 struct pcmcia_io_handle *pcihp; 869 { 870 bus_space_tag_t iot = pcihp->iot; 871 bus_space_handle_t ioh = pcihp->ioh; 872 bus_size_t size = pcihp->size; 873 874 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 875 bus_space_free(iot, ioh, size); 876 else 877 bus_space_unmap(iot, ioh, size); 878 } 879 880 881 static struct io_map_index_st { 882 int start_lsb; 883 int start_msb; 884 int stop_lsb; 885 int stop_msb; 886 int ioenable; 887 int ioctlmask; 888 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 889 } io_map_index[] = { 890 { 891 PCIC_IOADDR0_START_LSB, 892 PCIC_IOADDR0_START_MSB, 893 PCIC_IOADDR0_STOP_LSB, 894 PCIC_IOADDR0_STOP_MSB, 895 PCIC_ADDRWIN_ENABLE_IO0, 896 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 897 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 898 { 899 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 900 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 901 | PCIC_IOCTL_IO0_DATASIZE_8BIT, 902 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 903 | PCIC_IOCTL_IO0_DATASIZE_16BIT, 904 }, 905 }, 906 { 907 PCIC_IOADDR1_START_LSB, 908 PCIC_IOADDR1_START_MSB, 909 PCIC_IOADDR1_STOP_LSB, 910 PCIC_IOADDR1_STOP_MSB, 911 PCIC_ADDRWIN_ENABLE_IO1, 912 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 913 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 914 { 915 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 916 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 917 PCIC_IOCTL_IO1_DATASIZE_8BIT, 918 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 919 PCIC_IOCTL_IO1_DATASIZE_16BIT, 920 }, 921 }, 922 }; 923 924 void 925 pcic_chip_do_io_map(h, win) 926 struct pcic_handle *h; 927 int win; 928 { 929 int reg; 930 931 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 932 win, (long) h->io[win].addr, (long) h->io[win].size, 933 h->io[win].width * 8)); 934 935 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 936 pcic_write(h, io_map_index[win].start_msb, 937 (h->io[win].addr >> 8) & 0xff); 938 939 pcic_write(h, io_map_index[win].stop_lsb, 940 (h->io[win].addr + h->io[win].size - 1) & 0xff); 941 pcic_write(h, io_map_index[win].stop_msb, 942 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 943 944 reg = pcic_read(h, PCIC_IOCTL); 945 reg &= ~io_map_index[win].ioctlmask; 946 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 947 pcic_write(h, PCIC_IOCTL, reg); 948 949 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 950 reg |= io_map_index[win].ioenable; 951 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 952 } 953 954 int 955 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 956 pcmcia_chipset_handle_t pch; 957 int width; 958 bus_addr_t offset; 959 bus_size_t size; 960 struct pcmcia_io_handle *pcihp; 961 int *windowp; 962 { 963 struct pcic_handle *h = (struct pcic_handle *) pch; 964 bus_addr_t ioaddr = pcihp->addr + offset; 965 static char *width_names[] = { "auto", "io8", "io16" }; 966 int i, win; 967 968 /* XXX Sanity check offset/size. */ 969 970 win = -1; 971 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 972 if ((h->ioalloc & (1 << i)) == 0) { 973 win = i; 974 h->ioalloc |= (1 << i); 975 break; 976 } 977 } 978 979 if (win == -1) 980 return (1); 981 982 *windowp = win; 983 984 /* XXX this is pretty gross */ 985 986 if (h->sc->iot != pcihp->iot) 987 panic("pcic_chip_io_map iot is bogus"); 988 989 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 990 win, width_names[width], (u_long) ioaddr, (u_long) size)); 991 992 /* XXX wtf is this doing here? */ 993 994 printf(" port 0x%lx", (u_long) ioaddr); 995 if (size > 1) 996 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 997 998 h->io[win].addr = ioaddr; 999 h->io[win].size = size; 1000 h->io[win].width = width; 1001 1002 pcic_chip_do_io_map(h, win); 1003 1004 return (0); 1005 } 1006 1007 void 1008 pcic_chip_io_unmap(pch, window) 1009 pcmcia_chipset_handle_t pch; 1010 int window; 1011 { 1012 struct pcic_handle *h = (struct pcic_handle *) pch; 1013 int reg; 1014 1015 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1016 panic("pcic_chip_io_unmap: window out of range"); 1017 1018 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1019 reg &= ~io_map_index[window].ioenable; 1020 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1021 1022 h->ioalloc &= ~(1 << window); 1023 } 1024 1025 void 1026 pcic_chip_socket_enable(pch) 1027 pcmcia_chipset_handle_t pch; 1028 { 1029 struct pcic_handle *h = (struct pcic_handle *) pch; 1030 int cardtype, reg, win; 1031 1032 /* this bit is mostly stolen from pcic_attach_card */ 1033 1034 /* power down the socket to reset it, clear the card reset pin */ 1035 1036 pcic_write(h, PCIC_PWRCTL, 0); 1037 1038 /* power up the socket */ 1039 1040 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_PWR_ENABLE); 1041 delay(10000); 1042 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_OE); 1043 1044 /* clear the reset flag */ 1045 1046 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1047 1048 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1049 1050 delay(20000); 1051 1052 /* wait for the chip to finish initializing */ 1053 1054 pcic_wait_ready(h); 1055 1056 /* zero out the address windows */ 1057 1058 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1059 1060 /* set the card type */ 1061 1062 cardtype = pcmcia_card_gettype(h->pcmcia); 1063 1064 reg = pcic_read(h, PCIC_INTR); 1065 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1066 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1067 PCIC_INTR_CARDTYPE_IO : 1068 PCIC_INTR_CARDTYPE_MEM); 1069 reg |= h->ih_irq; 1070 pcic_write(h, PCIC_INTR, reg); 1071 1072 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1073 h->sc->dev.dv_xname, h->sock, 1074 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1075 1076 /* reinstall all the memory and io mappings */ 1077 1078 for (win = 0; win < PCIC_MEM_WINS; win++) 1079 if (h->memalloc & (1 << win)) 1080 pcic_chip_do_mem_map(h, win); 1081 1082 for (win = 0; win < PCIC_IO_WINS; win++) 1083 if (h->ioalloc & (1 << win)) 1084 pcic_chip_do_io_map(h, win); 1085 } 1086 1087 void 1088 pcic_chip_socket_disable(pch) 1089 pcmcia_chipset_handle_t pch; 1090 { 1091 struct pcic_handle *h = (struct pcic_handle *) pch; 1092 1093 DPRINTF(("pcic_chip_socket_disable\n")); 1094 1095 /* power down the socket */ 1096 1097 pcic_write(h, PCIC_PWRCTL, 0); 1098 } 1099
Indexes created Fri Sep 26 20:09:58 GMT 2025