i82365.c revision 1.25
1 /* $NetBSD: i82365.c,v 1.25 1999/10/15 06:07:27 haya Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <vm/vm.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/pcmcia/pcmciareg.h> 49 #include <dev/pcmcia/pcmciavar.h> 50 51 #include <dev/ic/i82365reg.h> 52 #include <dev/ic/i82365var.h> 53 54 #include "locators.h" 55 56 #ifdef PCICDEBUG 57 int pcic_debug = 0; 58 #define DPRINTF(arg) if (pcic_debug) printf arg; 59 #else 60 #define DPRINTF(arg) 61 #endif 62 63 #define PCIC_VENDOR_UNKNOWN 0 64 #define PCIC_VENDOR_I82365SLR0 1 65 #define PCIC_VENDOR_I82365SLR1 2 66 #define PCIC_VENDOR_CIRRUS_PD6710 3 67 #define PCIC_VENDOR_CIRRUS_PD672X 4 68 69 /* 70 * Individual drivers will allocate their own memory and io regions. Memory 71 * regions must be a multiple of 4k, aligned on a 4k boundary. 72 */ 73 74 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 75 76 void pcic_attach_socket __P((struct pcic_handle *)); 77 void pcic_init_socket __P((struct pcic_handle *)); 78 79 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 80 int pcic_print __P((void *arg, const char *pnp)); 81 int pcic_intr_socket __P((struct pcic_handle *)); 82 83 void pcic_attach_card __P((struct pcic_handle *)); 84 void pcic_detach_card __P((struct pcic_handle *, int)); 85 void pcic_deactivate_card __P((struct pcic_handle *)); 86 87 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 88 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 89 90 void pcic_create_event_thread __P((void *)); 91 void pcic_event_thread __P((void *)); 92 93 void pcic_queue_event __P((struct pcic_handle *, int)); 94 95 static void pcic_wait_ready __P((struct pcic_handle *)); 96 97 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 98 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 99 100 int 101 pcic_ident_ok(ident) 102 int ident; 103 { 104 /* this is very empirical and heuristic */ 105 106 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 107 return (0); 108 109 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 110 #ifdef DIAGNOSTIC 111 printf("pcic: does not support memory and I/O cards, " 112 "ignored (ident=%0x)\n", ident); 113 #endif 114 return (0); 115 } 116 return (1); 117 } 118 119 int 120 pcic_vendor(h) 121 struct pcic_handle *h; 122 { 123 int reg; 124 125 /* 126 * the chip_id of the cirrus toggles between 11 and 00 after a write. 127 * weird. 128 */ 129 130 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 131 reg = pcic_read(h, -1); 132 133 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 134 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 135 reg = pcic_read(h, -1); 136 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 137 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 138 return (PCIC_VENDOR_CIRRUS_PD672X); 139 else 140 return (PCIC_VENDOR_CIRRUS_PD6710); 141 } 142 } 143 144 reg = pcic_read(h, PCIC_IDENT); 145 146 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 147 return (PCIC_VENDOR_I82365SLR0); 148 else 149 return (PCIC_VENDOR_I82365SLR1); 150 151 return (PCIC_VENDOR_UNKNOWN); 152 } 153 154 char * 155 pcic_vendor_to_string(vendor) 156 int vendor; 157 { 158 switch (vendor) { 159 case PCIC_VENDOR_I82365SLR0: 160 return ("Intel 82365SL Revision 0"); 161 case PCIC_VENDOR_I82365SLR1: 162 return ("Intel 82365SL Revision 1"); 163 case PCIC_VENDOR_CIRRUS_PD6710: 164 return ("Cirrus PD6710"); 165 case PCIC_VENDOR_CIRRUS_PD672X: 166 return ("Cirrus PD672X"); 167 } 168 169 return ("Unknown controller"); 170 } 171 172 void 173 pcic_attach(sc) 174 struct pcic_softc *sc; 175 { 176 int vendor, count, i, reg; 177 178 /* now check for each controller/socket */ 179 180 /* 181 * this could be done with a loop, but it would violate the 182 * abstraction 183 */ 184 185 count = 0; 186 187 DPRINTF(("pcic ident regs:")); 188 189 sc->handle[0].ph_parent = (struct device *)sc; 190 sc->handle[0].sock = C0SA; 191 /* initialise pcic_read and pcic_write functions */ 192 sc->handle[0].ph_read = st_pcic_read; 193 sc->handle[0].ph_write = st_pcic_write; 194 sc->handle[0].ph_bus_t = sc->iot; 195 sc->handle[0].ph_bus_h = sc->ioh; 196 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 197 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 198 count++; 199 } else { 200 sc->handle[0].flags = 0; 201 } 202 sc->handle[0].laststate = PCIC_LASTSTATE_EMPTY; 203 204 DPRINTF((" 0x%02x", reg)); 205 206 sc->handle[1].ph_parent = (struct device *)sc; 207 sc->handle[1].sock = C0SB; 208 /* initialise pcic_read and pcic_write functions */ 209 sc->handle[1].ph_read = st_pcic_read; 210 sc->handle[1].ph_write = st_pcic_write; 211 sc->handle[1].ph_bus_t = sc->iot; 212 sc->handle[1].ph_bus_h = sc->ioh; 213 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 214 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 215 count++; 216 } else { 217 sc->handle[1].flags = 0; 218 } 219 sc->handle[1].laststate = PCIC_LASTSTATE_EMPTY; 220 221 DPRINTF((" 0x%02x", reg)); 222 223 /* 224 * The CL-PD6729 has only one controller and always returns 0 225 * if you try to read from the second one. Maybe pcic_ident_ok 226 * shouldn't accept 0? 227 */ 228 sc->handle[2].ph_parent = (struct device *)sc; 229 sc->handle[2].sock = C1SA; 230 /* initialise pcic_read and pcic_write functions */ 231 sc->handle[2].ph_read = st_pcic_read; 232 sc->handle[2].ph_write = st_pcic_write; 233 sc->handle[2].ph_bus_t = sc->iot; 234 sc->handle[2].ph_bus_h = sc->ioh; 235 if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X || 236 pcic_read(&sc->handle[2], PCIC_IDENT) != 0) { 237 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], 238 PCIC_IDENT))) { 239 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 240 count++; 241 } else { 242 sc->handle[2].flags = 0; 243 } 244 sc->handle[2].laststate = PCIC_LASTSTATE_EMPTY; 245 246 DPRINTF((" 0x%02x", reg)); 247 248 sc->handle[3].ph_parent = (struct device *)sc; 249 sc->handle[3].sock = C1SB; 250 /* initialise pcic_read and pcic_write functions */ 251 sc->handle[3].ph_read = st_pcic_read; 252 sc->handle[3].ph_write = st_pcic_write; 253 sc->handle[3].ph_bus_t = sc->iot; 254 sc->handle[3].ph_bus_h = sc->ioh; 255 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], 256 PCIC_IDENT))) { 257 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 258 count++; 259 } else { 260 sc->handle[3].flags = 0; 261 } 262 sc->handle[3].laststate = PCIC_LASTSTATE_EMPTY; 263 264 DPRINTF((" 0x%02x\n", reg)); 265 } else { 266 sc->handle[2].flags = 0; 267 sc->handle[3].flags = 0; 268 } 269 270 if (count == 0) 271 panic("pcic_attach: attach found no sockets"); 272 273 /* establish the interrupt */ 274 275 /* XXX block interrupts? */ 276 277 for (i = 0; i < PCIC_NSLOTS; i++) { 278 /* 279 * this should work, but w/o it, setting tty flags hangs at 280 * boot time. 281 */ 282 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 283 { 284 SIMPLEQ_INIT(&sc->handle[i].events); 285 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 286 pcic_read(&sc->handle[i], PCIC_CSC); 287 } 288 } 289 290 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 291 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 292 vendor = pcic_vendor(&sc->handle[0]); 293 294 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 295 pcic_vendor_to_string(vendor)); 296 297 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 298 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 299 printf("sockets A and B\n"); 300 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 301 printf("socket A only\n"); 302 else 303 printf("socket B only\n"); 304 305 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 306 sc->handle[0].vendor = vendor; 307 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 308 sc->handle[1].vendor = vendor; 309 } 310 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 311 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 312 vendor = pcic_vendor(&sc->handle[2]); 313 314 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 315 pcic_vendor_to_string(vendor)); 316 317 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 318 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 319 printf("sockets A and B\n"); 320 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 321 printf("socket A only\n"); 322 else 323 printf("socket B only\n"); 324 325 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 326 sc->handle[2].vendor = vendor; 327 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 328 sc->handle[3].vendor = vendor; 329 } 330 } 331 332 void 333 pcic_attach_sockets(sc) 334 struct pcic_softc *sc; 335 { 336 int i; 337 338 for (i = 0; i < PCIC_NSLOTS; i++) 339 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 340 pcic_attach_socket(&sc->handle[i]); 341 } 342 343 void 344 pcic_attach_socket(h) 345 struct pcic_handle *h; 346 { 347 struct pcmciabus_attach_args paa; 348 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 349 350 /* initialize the rest of the handle */ 351 352 h->shutdown = 0; 353 h->memalloc = 0; 354 h->ioalloc = 0; 355 h->ih_irq = 0; 356 357 /* now, config one pcmcia device per socket */ 358 359 paa.paa_busname = "pcmcia"; 360 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 361 paa.pch = (pcmcia_chipset_handle_t) h; 362 paa.iobase = sc->iobase; 363 paa.iosize = sc->iosize; 364 365 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, 366 pcic_submatch); 367 368 /* if there's actually a pcmcia device attached, initialize the slot */ 369 370 if (h->pcmcia) 371 pcic_init_socket(h); 372 } 373 374 void 375 pcic_create_event_thread(arg) 376 void *arg; 377 { 378 struct pcic_handle *h = arg; 379 const char *cs; 380 381 switch (h->sock) { 382 case C0SA: 383 cs = "0,0"; 384 break; 385 case C0SB: 386 cs = "0,1"; 387 break; 388 case C1SA: 389 cs = "1,0"; 390 break; 391 case C1SB: 392 cs = "1,1"; 393 break; 394 default: 395 panic("pcic_create_event_thread: unknown pcic socket"); 396 } 397 398 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 399 "%s,%s", h->ph_parent->dv_xname, cs)) { 400 printf("%s: unable to create event thread for sock 0x%02x\n", 401 h->ph_parent->dv_xname, h->sock); 402 panic("pcic_create_event_thread"); 403 } 404 } 405 406 void 407 pcic_event_thread(arg) 408 void *arg; 409 { 410 struct pcic_handle *h = arg; 411 struct pcic_event *pe; 412 int s; 413 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 414 415 while (h->shutdown == 0) { 416 s = splhigh(); 417 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 418 splx(s); 419 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 420 continue; 421 } else { 422 splx(s); 423 /* sleep .25s to be enqueued chatterling interrupts */ 424 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, "pcicss", hz/4); 425 } 426 s = splhigh(); 427 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 428 splx(s); 429 430 switch (pe->pe_type) { 431 case PCIC_EVENT_INSERTION: 432 s = splhigh(); 433 while (1) { 434 struct pcic_event *pe1, *pe2; 435 436 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 437 break; 438 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 439 break; 440 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 441 break; 442 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 443 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, pe_q); 444 free(pe1, M_TEMP); 445 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, pe_q); 446 free(pe2, M_TEMP); 447 } 448 } 449 splx(s); 450 451 DPRINTF(("%s: insertion event\n", h->ph_parent->dv_xname)); 452 pcic_attach_card(h); 453 break; 454 455 case PCIC_EVENT_REMOVAL: 456 s = splhigh(); 457 while (1) { 458 struct pcic_event *pe1, *pe2; 459 460 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 461 break; 462 if (pe1->pe_type != PCIC_EVENT_INSERTION) 463 break; 464 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 465 break; 466 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 467 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, pe_q); 468 free(pe1, M_TEMP); 469 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, pe_q); 470 free(pe2, M_TEMP); 471 } 472 } 473 splx(s); 474 475 DPRINTF(("%s: removal event\n", h->ph_parent->dv_xname)); 476 pcic_detach_card(h, DETACH_FORCE); 477 break; 478 479 default: 480 panic("pcic_event_thread: unknown event %d", 481 pe->pe_type); 482 } 483 free(pe, M_TEMP); 484 } 485 486 h->event_thread = NULL; 487 488 /* In case parent is waiting for us to exit. */ 489 wakeup(sc); 490 491 kthread_exit(0); 492 } 493 494 void 495 pcic_init_socket(h) 496 struct pcic_handle *h; 497 { 498 int reg; 499 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 500 501 /* 502 * queue creation of a kernel thread to handle insert/removal events. 503 */ 504 #ifdef DIAGNOSTIC 505 if (h->event_thread != NULL) 506 panic("pcic_attach_socket: event thread"); 507 #endif 508 kthread_create(pcic_create_event_thread, h); 509 510 /* set up the card to interrupt on card detect */ 511 512 pcic_write(h, PCIC_CSC_INTR, (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 513 PCIC_CSC_INTR_CD_ENABLE); 514 pcic_write(h, PCIC_INTR, 0); 515 pcic_read(h, PCIC_CSC); 516 517 /* unsleep the cirrus controller */ 518 519 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 520 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 521 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 522 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 523 DPRINTF(("%s: socket %02x was suspended\n", 524 h->ph_parent->dv_xname, h->sock)); 525 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 526 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 527 } 528 } 529 /* if there's a card there, then attach it. */ 530 531 reg = pcic_read(h, PCIC_IF_STATUS); 532 533 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 534 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 535 pcic_attach_card(h); 536 h->laststate = PCIC_LASTSTATE_PRESENT; 537 } else { 538 h->laststate = PCIC_LASTSTATE_EMPTY; 539 } 540 } 541 542 int 543 pcic_submatch(parent, cf, aux) 544 struct device *parent; 545 struct cfdata *cf; 546 void *aux; 547 { 548 549 struct pcmciabus_attach_args *paa = aux; 550 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 551 552 switch (h->sock) { 553 case C0SA: 554 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 555 PCMCIABUSCF_CONTROLLER_DEFAULT && 556 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 557 return 0; 558 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 559 PCMCIABUSCF_SOCKET_DEFAULT && 560 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 561 return 0; 562 563 break; 564 case C0SB: 565 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 566 PCMCIABUSCF_CONTROLLER_DEFAULT && 567 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 568 return 0; 569 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 570 PCMCIABUSCF_SOCKET_DEFAULT && 571 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 572 return 0; 573 574 break; 575 case C1SA: 576 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 577 PCMCIABUSCF_CONTROLLER_DEFAULT && 578 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 579 return 0; 580 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 581 PCMCIABUSCF_SOCKET_DEFAULT && 582 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 583 return 0; 584 585 break; 586 case C1SB: 587 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 588 PCMCIABUSCF_CONTROLLER_DEFAULT && 589 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 590 return 0; 591 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 592 PCMCIABUSCF_SOCKET_DEFAULT && 593 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 594 return 0; 595 596 break; 597 default: 598 panic("unknown pcic socket"); 599 } 600 601 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 602 } 603 604 int 605 pcic_print(arg, pnp) 606 void *arg; 607 const char *pnp; 608 { 609 struct pcmciabus_attach_args *paa = arg; 610 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 611 612 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 613 if (pnp) 614 printf("pcmcia at %s", pnp); 615 616 switch (h->sock) { 617 case C0SA: 618 printf(" controller 0 socket 0"); 619 break; 620 case C0SB: 621 printf(" controller 0 socket 1"); 622 break; 623 case C1SA: 624 printf(" controller 1 socket 0"); 625 break; 626 case C1SB: 627 printf(" controller 1 socket 1"); 628 break; 629 default: 630 panic("unknown pcic socket"); 631 } 632 633 return (UNCONF); 634 } 635 636 int 637 pcic_intr(arg) 638 void *arg; 639 { 640 struct pcic_softc *sc = arg; 641 int i, ret = 0; 642 643 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 644 645 for (i = 0; i < PCIC_NSLOTS; i++) 646 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 647 ret += pcic_intr_socket(&sc->handle[i]); 648 649 return (ret ? 1 : 0); 650 } 651 652 int 653 pcic_intr_socket(h) 654 struct pcic_handle *h; 655 { 656 int cscreg; 657 658 cscreg = pcic_read(h, PCIC_CSC); 659 660 cscreg &= (PCIC_CSC_GPI | 661 PCIC_CSC_CD | 662 PCIC_CSC_READY | 663 PCIC_CSC_BATTWARN | 664 PCIC_CSC_BATTDEAD); 665 666 if (cscreg & PCIC_CSC_GPI) { 667 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 668 } 669 if (cscreg & PCIC_CSC_CD) { 670 int statreg; 671 672 statreg = pcic_read(h, PCIC_IF_STATUS); 673 674 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 675 statreg)); 676 677 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 678 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 679 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 680 DPRINTF(("%s: enqueing INSERTION event\n", 681 h->ph_parent->dv_xname)); 682 pcic_queue_event(h, PCIC_EVENT_INSERTION); 683 } 684 h->laststate = PCIC_LASTSTATE_PRESENT; 685 } else { 686 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 687 /* Deactivate the card now. */ 688 DPRINTF(("%s: deactivating card\n", 689 h->ph_parent->dv_xname)); 690 pcic_deactivate_card(h); 691 692 DPRINTF(("%s: enqueing REMOVAL event\n", 693 h->ph_parent->dv_xname)); 694 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 695 } 696 h->laststate = ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) 697 ? PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 698 } 699 } 700 if (cscreg & PCIC_CSC_READY) { 701 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 702 /* shouldn't happen */ 703 } 704 if (cscreg & PCIC_CSC_BATTWARN) { 705 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, h->sock)); 706 } 707 if (cscreg & PCIC_CSC_BATTDEAD) { 708 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, h->sock)); 709 } 710 return (cscreg ? 1 : 0); 711 } 712 713 void 714 pcic_queue_event(h, event) 715 struct pcic_handle *h; 716 int event; 717 { 718 struct pcic_event *pe; 719 int s; 720 721 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 722 if (pe == NULL) 723 panic("pcic_queue_event: can't allocate event"); 724 725 pe->pe_type = event; 726 s = splhigh(); 727 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 728 splx(s); 729 wakeup(&h->events); 730 } 731 732 void 733 pcic_attach_card(h) 734 struct pcic_handle *h; 735 { 736 737 if (!(h->flags & PCIC_FLAG_CARDP)) { 738 /* call the MI attach function */ 739 pcmcia_card_attach(h->pcmcia); 740 741 h->flags |= PCIC_FLAG_CARDP; 742 } else { 743 DPRINTF(("pcic_attach_card: already attached")); 744 } 745 } 746 747 void 748 pcic_detach_card(h, flags) 749 struct pcic_handle *h; 750 int flags; /* DETACH_* */ 751 { 752 753 if (h->flags & PCIC_FLAG_CARDP) { 754 h->flags &= ~PCIC_FLAG_CARDP; 755 756 /* call the MI detach function */ 757 pcmcia_card_detach(h->pcmcia, flags); 758 } else { 759 DPRINTF(("pcic_detach_card: already detached")); 760 } 761 } 762 763 void 764 pcic_deactivate_card(h) 765 struct pcic_handle *h; 766 { 767 768 /* call the MI deactivate function */ 769 pcmcia_card_deactivate(h->pcmcia); 770 771 /* power down the socket */ 772 pcic_write(h, PCIC_PWRCTL, 0); 773 774 /* reset the socket */ 775 pcic_write(h, PCIC_INTR, 0); 776 } 777 778 int 779 pcic_chip_mem_alloc(pch, size, pcmhp) 780 pcmcia_chipset_handle_t pch; 781 bus_size_t size; 782 struct pcmcia_mem_handle *pcmhp; 783 { 784 struct pcic_handle *h = (struct pcic_handle *) pch; 785 bus_space_handle_t memh; 786 bus_addr_t addr; 787 bus_size_t sizepg; 788 int i, mask, mhandle; 789 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 790 791 /* out of sc->memh, allocate as many pages as necessary */ 792 793 /* convert size to PCIC pages */ 794 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 795 if (sizepg > PCIC_MAX_MEM_PAGES) 796 return (1); 797 798 mask = (1 << sizepg) - 1; 799 800 addr = 0; /* XXX gcc -Wuninitialized */ 801 mhandle = 0; /* XXX gcc -Wuninitialized */ 802 803 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 804 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 805 if (bus_space_subregion(sc->memt, sc->memh, 806 i * PCIC_MEM_PAGESIZE, 807 sizepg * PCIC_MEM_PAGESIZE, &memh)) 808 return (1); 809 mhandle = mask << i; 810 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 811 sc->subregionmask &= ~(mhandle); 812 pcmhp->memt = sc->memt; 813 pcmhp->memh = memh; 814 pcmhp->addr = addr; 815 pcmhp->size = size; 816 pcmhp->mhandle = mhandle; 817 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 818 return (0); 819 } 820 } 821 822 return (1); 823 } 824 825 void 826 pcic_chip_mem_free(pch, pcmhp) 827 pcmcia_chipset_handle_t pch; 828 struct pcmcia_mem_handle *pcmhp; 829 { 830 struct pcic_handle *h = (struct pcic_handle *) pch; 831 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 832 833 sc->subregionmask |= pcmhp->mhandle; 834 } 835 836 static struct mem_map_index_st { 837 int sysmem_start_lsb; 838 int sysmem_start_msb; 839 int sysmem_stop_lsb; 840 int sysmem_stop_msb; 841 int cardmem_lsb; 842 int cardmem_msb; 843 int memenable; 844 } mem_map_index[] = { 845 { 846 PCIC_SYSMEM_ADDR0_START_LSB, 847 PCIC_SYSMEM_ADDR0_START_MSB, 848 PCIC_SYSMEM_ADDR0_STOP_LSB, 849 PCIC_SYSMEM_ADDR0_STOP_MSB, 850 PCIC_CARDMEM_ADDR0_LSB, 851 PCIC_CARDMEM_ADDR0_MSB, 852 PCIC_ADDRWIN_ENABLE_MEM0, 853 }, 854 { 855 PCIC_SYSMEM_ADDR1_START_LSB, 856 PCIC_SYSMEM_ADDR1_START_MSB, 857 PCIC_SYSMEM_ADDR1_STOP_LSB, 858 PCIC_SYSMEM_ADDR1_STOP_MSB, 859 PCIC_CARDMEM_ADDR1_LSB, 860 PCIC_CARDMEM_ADDR1_MSB, 861 PCIC_ADDRWIN_ENABLE_MEM1, 862 }, 863 { 864 PCIC_SYSMEM_ADDR2_START_LSB, 865 PCIC_SYSMEM_ADDR2_START_MSB, 866 PCIC_SYSMEM_ADDR2_STOP_LSB, 867 PCIC_SYSMEM_ADDR2_STOP_MSB, 868 PCIC_CARDMEM_ADDR2_LSB, 869 PCIC_CARDMEM_ADDR2_MSB, 870 PCIC_ADDRWIN_ENABLE_MEM2, 871 }, 872 { 873 PCIC_SYSMEM_ADDR3_START_LSB, 874 PCIC_SYSMEM_ADDR3_START_MSB, 875 PCIC_SYSMEM_ADDR3_STOP_LSB, 876 PCIC_SYSMEM_ADDR3_STOP_MSB, 877 PCIC_CARDMEM_ADDR3_LSB, 878 PCIC_CARDMEM_ADDR3_MSB, 879 PCIC_ADDRWIN_ENABLE_MEM3, 880 }, 881 { 882 PCIC_SYSMEM_ADDR4_START_LSB, 883 PCIC_SYSMEM_ADDR4_START_MSB, 884 PCIC_SYSMEM_ADDR4_STOP_LSB, 885 PCIC_SYSMEM_ADDR4_STOP_MSB, 886 PCIC_CARDMEM_ADDR4_LSB, 887 PCIC_CARDMEM_ADDR4_MSB, 888 PCIC_ADDRWIN_ENABLE_MEM4, 889 }, 890 }; 891 892 void 893 pcic_chip_do_mem_map(h, win) 894 struct pcic_handle *h; 895 int win; 896 { 897 int reg; 898 899 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 900 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 901 pcic_write(h, mem_map_index[win].sysmem_start_msb, 902 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 903 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 904 905 #if 0 906 /* XXX do I want 16 bit all the time? */ 907 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 908 #endif 909 910 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 911 ((h->mem[win].addr + h->mem[win].size) >> 912 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 913 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 914 (((h->mem[win].addr + h->mem[win].size) >> 915 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 916 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 917 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 918 919 pcic_write(h, mem_map_index[win].cardmem_lsb, 920 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 921 pcic_write(h, mem_map_index[win].cardmem_msb, 922 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 923 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 924 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 925 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 926 927 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 928 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 929 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 930 931 delay(100); 932 933 #ifdef PCICDEBUG 934 { 935 int r1, r2, r3, r4, r5, r6; 936 937 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 938 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 939 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 940 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 941 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 942 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 943 944 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 945 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 946 } 947 #endif 948 } 949 950 int 951 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 952 pcmcia_chipset_handle_t pch; 953 int kind; 954 bus_addr_t card_addr; 955 bus_size_t size; 956 struct pcmcia_mem_handle *pcmhp; 957 bus_addr_t *offsetp; 958 int *windowp; 959 { 960 struct pcic_handle *h = (struct pcic_handle *) pch; 961 bus_addr_t busaddr; 962 long card_offset; 963 int i, win; 964 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 965 966 win = -1; 967 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 968 i++) { 969 if ((h->memalloc & (1 << i)) == 0) { 970 win = i; 971 h->memalloc |= (1 << i); 972 break; 973 } 974 } 975 976 if (win == -1) 977 return (1); 978 979 *windowp = win; 980 981 /* XXX this is pretty gross */ 982 983 if (sc->memt != pcmhp->memt) 984 panic("pcic_chip_mem_map memt is bogus"); 985 986 busaddr = pcmhp->addr; 987 988 /* 989 * compute the address offset to the pcmcia address space for the 990 * pcic. this is intentionally signed. The masks and shifts below 991 * will cause TRT to happen in the pcic registers. Deal with making 992 * sure the address is aligned, and return the alignment offset. 993 */ 994 995 *offsetp = card_addr % PCIC_MEM_ALIGN; 996 card_addr -= *offsetp; 997 998 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 999 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1000 (u_long) card_addr)); 1001 1002 /* 1003 * include the offset in the size, and decrement size by one, since 1004 * the hw wants start/stop 1005 */ 1006 size += *offsetp - 1; 1007 1008 card_offset = (((long) card_addr) - ((long) busaddr)); 1009 1010 h->mem[win].addr = busaddr; 1011 h->mem[win].size = size; 1012 h->mem[win].offset = card_offset; 1013 h->mem[win].kind = kind; 1014 1015 pcic_chip_do_mem_map(h, win); 1016 1017 return (0); 1018 } 1019 1020 void 1021 pcic_chip_mem_unmap(pch, window) 1022 pcmcia_chipset_handle_t pch; 1023 int window; 1024 { 1025 struct pcic_handle *h = (struct pcic_handle *) pch; 1026 int reg; 1027 1028 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1029 panic("pcic_chip_mem_unmap: window out of range"); 1030 1031 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1032 reg &= ~mem_map_index[window].memenable; 1033 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1034 1035 h->memalloc &= ~(1 << window); 1036 } 1037 1038 int 1039 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1040 pcmcia_chipset_handle_t pch; 1041 bus_addr_t start; 1042 bus_size_t size; 1043 bus_size_t align; 1044 struct pcmcia_io_handle *pcihp; 1045 { 1046 struct pcic_handle *h = (struct pcic_handle *) pch; 1047 bus_space_tag_t iot; 1048 bus_space_handle_t ioh; 1049 bus_addr_t ioaddr; 1050 int flags = 0; 1051 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1052 1053 /* 1054 * Allocate some arbitrary I/O space. 1055 */ 1056 1057 iot = sc->iot; 1058 1059 if (start) { 1060 ioaddr = start; 1061 if (bus_space_map(iot, start, size, 0, &ioh)) 1062 return (1); 1063 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1064 (u_long) ioaddr, (u_long) size)); 1065 } else { 1066 flags |= PCMCIA_IO_ALLOCATED; 1067 if (bus_space_alloc(iot, sc->iobase, 1068 sc->iobase + sc->iosize, size, align, 0, 0, 1069 &ioaddr, &ioh)) 1070 return (1); 1071 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1072 (u_long) ioaddr, (u_long) size)); 1073 } 1074 1075 pcihp->iot = iot; 1076 pcihp->ioh = ioh; 1077 pcihp->addr = ioaddr; 1078 pcihp->size = size; 1079 pcihp->flags = flags; 1080 1081 return (0); 1082 } 1083 1084 void 1085 pcic_chip_io_free(pch, pcihp) 1086 pcmcia_chipset_handle_t pch; 1087 struct pcmcia_io_handle *pcihp; 1088 { 1089 bus_space_tag_t iot = pcihp->iot; 1090 bus_space_handle_t ioh = pcihp->ioh; 1091 bus_size_t size = pcihp->size; 1092 1093 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1094 bus_space_free(iot, ioh, size); 1095 else 1096 bus_space_unmap(iot, ioh, size); 1097 } 1098 1099 1100 static struct io_map_index_st { 1101 int start_lsb; 1102 int start_msb; 1103 int stop_lsb; 1104 int stop_msb; 1105 int ioenable; 1106 int ioctlmask; 1107 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1108 } io_map_index[] = { 1109 { 1110 PCIC_IOADDR0_START_LSB, 1111 PCIC_IOADDR0_START_MSB, 1112 PCIC_IOADDR0_STOP_LSB, 1113 PCIC_IOADDR0_STOP_MSB, 1114 PCIC_ADDRWIN_ENABLE_IO0, 1115 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1116 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1117 { 1118 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1119 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1120 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1121 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1122 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1123 }, 1124 }, 1125 { 1126 PCIC_IOADDR1_START_LSB, 1127 PCIC_IOADDR1_START_MSB, 1128 PCIC_IOADDR1_STOP_LSB, 1129 PCIC_IOADDR1_STOP_MSB, 1130 PCIC_ADDRWIN_ENABLE_IO1, 1131 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1132 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1133 { 1134 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1135 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1136 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1137 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1138 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1139 }, 1140 }, 1141 }; 1142 1143 void 1144 pcic_chip_do_io_map(h, win) 1145 struct pcic_handle *h; 1146 int win; 1147 { 1148 int reg; 1149 1150 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1151 win, (long) h->io[win].addr, (long) h->io[win].size, 1152 h->io[win].width * 8)); 1153 1154 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1155 pcic_write(h, io_map_index[win].start_msb, 1156 (h->io[win].addr >> 8) & 0xff); 1157 1158 pcic_write(h, io_map_index[win].stop_lsb, 1159 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1160 pcic_write(h, io_map_index[win].stop_msb, 1161 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1162 1163 reg = pcic_read(h, PCIC_IOCTL); 1164 reg &= ~io_map_index[win].ioctlmask; 1165 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1166 pcic_write(h, PCIC_IOCTL, reg); 1167 1168 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1169 reg |= io_map_index[win].ioenable; 1170 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1171 } 1172 1173 int 1174 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1175 pcmcia_chipset_handle_t pch; 1176 int width; 1177 bus_addr_t offset; 1178 bus_size_t size; 1179 struct pcmcia_io_handle *pcihp; 1180 int *windowp; 1181 { 1182 struct pcic_handle *h = (struct pcic_handle *) pch; 1183 bus_addr_t ioaddr = pcihp->addr + offset; 1184 int i, win; 1185 #ifdef PCICDEBUG 1186 static char *width_names[] = { "auto", "io8", "io16" }; 1187 #endif 1188 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1189 1190 /* XXX Sanity check offset/size. */ 1191 1192 win = -1; 1193 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1194 if ((h->ioalloc & (1 << i)) == 0) { 1195 win = i; 1196 h->ioalloc |= (1 << i); 1197 break; 1198 } 1199 } 1200 1201 if (win == -1) 1202 return (1); 1203 1204 *windowp = win; 1205 1206 /* XXX this is pretty gross */ 1207 1208 if (sc->iot != pcihp->iot) 1209 panic("pcic_chip_io_map iot is bogus"); 1210 1211 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1212 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1213 1214 /* XXX wtf is this doing here? */ 1215 1216 printf(" port 0x%lx", (u_long) ioaddr); 1217 if (size > 1) 1218 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1219 1220 h->io[win].addr = ioaddr; 1221 h->io[win].size = size; 1222 h->io[win].width = width; 1223 1224 pcic_chip_do_io_map(h, win); 1225 1226 return (0); 1227 } 1228 1229 void 1230 pcic_chip_io_unmap(pch, window) 1231 pcmcia_chipset_handle_t pch; 1232 int window; 1233 { 1234 struct pcic_handle *h = (struct pcic_handle *) pch; 1235 int reg; 1236 1237 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1238 panic("pcic_chip_io_unmap: window out of range"); 1239 1240 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1241 reg &= ~io_map_index[window].ioenable; 1242 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1243 1244 h->ioalloc &= ~(1 << window); 1245 } 1246 1247 static void 1248 pcic_wait_ready(h) 1249 struct pcic_handle *h; 1250 { 1251 int i; 1252 1253 for (i = 0; i < 10000; i++) { 1254 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1255 return; 1256 delay(500); 1257 #ifdef PCICDEBUG 1258 if (pcic_debug) { 1259 if ((i>5000) && (i%100 == 99)) 1260 printf("."); 1261 } 1262 #endif 1263 } 1264 1265 #ifdef DIAGNOSTIC 1266 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1267 pcic_read(h, PCIC_IF_STATUS)); 1268 #endif 1269 } 1270 1271 void 1272 pcic_chip_socket_enable(pch) 1273 pcmcia_chipset_handle_t pch; 1274 { 1275 struct pcic_handle *h = (struct pcic_handle *) pch; 1276 int cardtype, reg, win; 1277 1278 /* this bit is mostly stolen from pcic_attach_card */ 1279 1280 /* power down the socket to reset it, clear the card reset pin */ 1281 1282 pcic_write(h, PCIC_PWRCTL, 0); 1283 1284 /* 1285 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1286 * we are changing Vcc (Toff). 1287 */ 1288 delay((300 + 100) * 1000); 1289 1290 #ifdef VADEM_POWER_HACK 1291 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1292 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1293 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1294 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1295 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1296 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1297 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1298 #endif 1299 1300 /* power up the socket */ 1301 1302 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1303 | PCIC_PWRCTL_PWR_ENABLE); 1304 1305 /* 1306 * wait 100ms until power raise (Tpr) and 20ms to become 1307 * stable (Tsu(Vcc)). 1308 * 1309 * some machines require some more time to be settled 1310 * (300ms is added here). 1311 */ 1312 delay((100 + 20 + 300) * 1000); 1313 1314 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1315 | PCIC_PWRCTL_PWR_ENABLE); 1316 pcic_write(h, PCIC_INTR, 0); 1317 1318 /* 1319 * hold RESET at least 10us. 1320 */ 1321 delay(10); 1322 1323 /* clear the reset flag */ 1324 1325 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1326 1327 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1328 1329 delay(20000); 1330 1331 /* wait for the chip to finish initializing */ 1332 1333 #ifdef DIAGNOSTIC 1334 reg = pcic_read(h, PCIC_IF_STATUS); 1335 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1336 printf("pcic_chip_socket_enable: status %x", reg); 1337 } 1338 #endif 1339 1340 pcic_wait_ready(h); 1341 1342 /* zero out the address windows */ 1343 1344 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1345 1346 /* set the card type */ 1347 1348 cardtype = pcmcia_card_gettype(h->pcmcia); 1349 1350 reg = pcic_read(h, PCIC_INTR); 1351 reg &= ~(PCIC_INTR_CARDTYPE_MASK | PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1352 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1353 PCIC_INTR_CARDTYPE_IO : 1354 PCIC_INTR_CARDTYPE_MEM); 1355 reg |= h->ih_irq; 1356 pcic_write(h, PCIC_INTR, reg); 1357 1358 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1359 h->ph_parent->dv_xname, h->sock, 1360 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1361 1362 /* reinstall all the memory and io mappings */ 1363 1364 for (win = 0; win < PCIC_MEM_WINS; win++) 1365 if (h->memalloc & (1 << win)) 1366 pcic_chip_do_mem_map(h, win); 1367 1368 for (win = 0; win < PCIC_IO_WINS; win++) 1369 if (h->ioalloc & (1 << win)) 1370 pcic_chip_do_io_map(h, win); 1371 } 1372 1373 void 1374 pcic_chip_socket_disable(pch) 1375 pcmcia_chipset_handle_t pch; 1376 { 1377 struct pcic_handle *h = (struct pcic_handle *) pch; 1378 1379 DPRINTF(("pcic_chip_socket_disable\n")); 1380 1381 /* power down the socket */ 1382 1383 pcic_write(h, PCIC_PWRCTL, 0); 1384 1385 /* 1386 * wait 300ms until power fails (Tpf). 1387 */ 1388 delay(300 * 1000); 1389 } 1390 1391 1392 1393 1394 static u_int8_t 1395 st_pcic_read(h, idx) 1396 struct pcic_handle *h; 1397 int idx; 1398 { 1399 if (idx != -1) { 1400 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, h->sock + idx); 1401 } 1402 1403 return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA); 1404 } 1405 1406 static void 1407 st_pcic_write(h, idx, data) 1408 struct pcic_handle *h; 1409 int idx; 1410 u_int8_t data; 1411 { 1412 if (idx != -1) { 1413 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, h->sock + idx); 1414 } 1415 1416 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1417 } 1418
Indexes created Tue Sep 30 11:09:46 GMT 2025