i82365.c revision 1.27
1 /* $NetBSD: i82365.c,v 1.27 2000/01/02 02:08:07 sommerfeld Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <vm/vm.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/pcmcia/pcmciareg.h> 49 #include <dev/pcmcia/pcmciavar.h> 50 51 #include <dev/ic/i82365reg.h> 52 #include <dev/ic/i82365var.h> 53 54 #include "locators.h" 55 56 #ifdef PCICDEBUG 57 int pcic_debug = 0; 58 #define DPRINTF(arg) if (pcic_debug) printf arg; 59 #else 60 #define DPRINTF(arg) 61 #endif 62 63 #define PCIC_VENDOR_UNKNOWN 0 64 #define PCIC_VENDOR_I82365SLR0 1 65 #define PCIC_VENDOR_I82365SLR1 2 66 #define PCIC_VENDOR_CIRRUS_PD6710 3 67 #define PCIC_VENDOR_CIRRUS_PD672X 4 68 69 /* 70 * Individual drivers will allocate their own memory and io regions. Memory 71 * regions must be a multiple of 4k, aligned on a 4k boundary. 72 */ 73 74 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 75 76 void pcic_attach_socket __P((struct pcic_handle *)); 77 void pcic_init_socket __P((struct pcic_handle *)); 78 79 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 80 int pcic_print __P((void *arg, const char *pnp)); 81 int pcic_intr_socket __P((struct pcic_handle *)); 82 83 void pcic_attach_card __P((struct pcic_handle *)); 84 void pcic_detach_card __P((struct pcic_handle *, int)); 85 void pcic_deactivate_card __P((struct pcic_handle *)); 86 87 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 88 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 89 90 void pcic_create_event_thread __P((void *)); 91 void pcic_event_thread __P((void *)); 92 93 void pcic_queue_event __P((struct pcic_handle *, int)); 94 void pcic_power __P((int, void *)); 95 96 static void pcic_wait_ready __P((struct pcic_handle *)); 97 98 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 99 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 100 101 int 102 pcic_ident_ok(ident) 103 int ident; 104 { 105 /* this is very empirical and heuristic */ 106 107 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 108 return (0); 109 110 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 111 #ifdef DIAGNOSTIC 112 printf("pcic: does not support memory and I/O cards, " 113 "ignored (ident=%0x)\n", ident); 114 #endif 115 return (0); 116 } 117 return (1); 118 } 119 120 int 121 pcic_vendor(h) 122 struct pcic_handle *h; 123 { 124 int reg; 125 126 /* 127 * the chip_id of the cirrus toggles between 11 and 00 after a write. 128 * weird. 129 */ 130 131 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 132 reg = pcic_read(h, -1); 133 134 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 135 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 136 reg = pcic_read(h, -1); 137 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 138 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 139 return (PCIC_VENDOR_CIRRUS_PD672X); 140 else 141 return (PCIC_VENDOR_CIRRUS_PD6710); 142 } 143 } 144 145 reg = pcic_read(h, PCIC_IDENT); 146 147 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 148 return (PCIC_VENDOR_I82365SLR0); 149 else 150 return (PCIC_VENDOR_I82365SLR1); 151 152 return (PCIC_VENDOR_UNKNOWN); 153 } 154 155 char * 156 pcic_vendor_to_string(vendor) 157 int vendor; 158 { 159 switch (vendor) { 160 case PCIC_VENDOR_I82365SLR0: 161 return ("Intel 82365SL Revision 0"); 162 case PCIC_VENDOR_I82365SLR1: 163 return ("Intel 82365SL Revision 1"); 164 case PCIC_VENDOR_CIRRUS_PD6710: 165 return ("Cirrus PD6710"); 166 case PCIC_VENDOR_CIRRUS_PD672X: 167 return ("Cirrus PD672X"); 168 } 169 170 return ("Unknown controller"); 171 } 172 173 void 174 pcic_attach(sc) 175 struct pcic_softc *sc; 176 { 177 int vendor, count, i, reg; 178 179 /* now check for each controller/socket */ 180 181 /* 182 * this could be done with a loop, but it would violate the 183 * abstraction 184 */ 185 186 count = 0; 187 188 DPRINTF(("pcic ident regs:")); 189 190 sc->handle[0].ph_parent = (struct device *)sc; 191 sc->handle[0].sock = C0SA; 192 /* initialise pcic_read and pcic_write functions */ 193 sc->handle[0].ph_read = st_pcic_read; 194 sc->handle[0].ph_write = st_pcic_write; 195 sc->handle[0].ph_bus_t = sc->iot; 196 sc->handle[0].ph_bus_h = sc->ioh; 197 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 198 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 199 count++; 200 } else { 201 sc->handle[0].flags = 0; 202 } 203 sc->handle[0].laststate = PCIC_LASTSTATE_EMPTY; 204 205 DPRINTF((" 0x%02x", reg)); 206 207 sc->handle[1].ph_parent = (struct device *)sc; 208 sc->handle[1].sock = C0SB; 209 /* initialise pcic_read and pcic_write functions */ 210 sc->handle[1].ph_read = st_pcic_read; 211 sc->handle[1].ph_write = st_pcic_write; 212 sc->handle[1].ph_bus_t = sc->iot; 213 sc->handle[1].ph_bus_h = sc->ioh; 214 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 215 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 216 count++; 217 } else { 218 sc->handle[1].flags = 0; 219 } 220 sc->handle[1].laststate = PCIC_LASTSTATE_EMPTY; 221 222 DPRINTF((" 0x%02x", reg)); 223 224 /* 225 * The CL-PD6729 has only one controller and always returns 0 226 * if you try to read from the second one. Maybe pcic_ident_ok 227 * shouldn't accept 0? 228 */ 229 sc->handle[2].ph_parent = (struct device *)sc; 230 sc->handle[2].sock = C1SA; 231 /* initialise pcic_read and pcic_write functions */ 232 sc->handle[2].ph_read = st_pcic_read; 233 sc->handle[2].ph_write = st_pcic_write; 234 sc->handle[2].ph_bus_t = sc->iot; 235 sc->handle[2].ph_bus_h = sc->ioh; 236 if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X || 237 pcic_read(&sc->handle[2], PCIC_IDENT) != 0) { 238 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], 239 PCIC_IDENT))) { 240 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 241 count++; 242 } else { 243 sc->handle[2].flags = 0; 244 } 245 sc->handle[2].laststate = PCIC_LASTSTATE_EMPTY; 246 247 DPRINTF((" 0x%02x", reg)); 248 249 sc->handle[3].ph_parent = (struct device *)sc; 250 sc->handle[3].sock = C1SB; 251 /* initialise pcic_read and pcic_write functions */ 252 sc->handle[3].ph_read = st_pcic_read; 253 sc->handle[3].ph_write = st_pcic_write; 254 sc->handle[3].ph_bus_t = sc->iot; 255 sc->handle[3].ph_bus_h = sc->ioh; 256 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], 257 PCIC_IDENT))) { 258 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 259 count++; 260 } else { 261 sc->handle[3].flags = 0; 262 } 263 sc->handle[3].laststate = PCIC_LASTSTATE_EMPTY; 264 265 DPRINTF((" 0x%02x\n", reg)); 266 } else { 267 sc->handle[2].flags = 0; 268 sc->handle[3].flags = 0; 269 } 270 271 if (count == 0) 272 panic("pcic_attach: attach found no sockets"); 273 274 /* establish the interrupt */ 275 276 /* XXX block interrupts? */ 277 278 for (i = 0; i < PCIC_NSLOTS; i++) { 279 /* 280 * this should work, but w/o it, setting tty flags hangs at 281 * boot time. 282 */ 283 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 284 { 285 SIMPLEQ_INIT(&sc->handle[i].events); 286 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 287 pcic_read(&sc->handle[i], PCIC_CSC); 288 } 289 } 290 291 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 292 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 293 vendor = pcic_vendor(&sc->handle[0]); 294 295 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 296 pcic_vendor_to_string(vendor)); 297 298 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 299 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 300 printf("sockets A and B\n"); 301 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 302 printf("socket A only\n"); 303 else 304 printf("socket B only\n"); 305 306 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 307 sc->handle[0].vendor = vendor; 308 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 309 sc->handle[1].vendor = vendor; 310 } 311 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 312 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 313 vendor = pcic_vendor(&sc->handle[2]); 314 315 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 316 pcic_vendor_to_string(vendor)); 317 318 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 319 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 320 printf("sockets A and B\n"); 321 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 322 printf("socket A only\n"); 323 else 324 printf("socket B only\n"); 325 326 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 327 sc->handle[2].vendor = vendor; 328 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 329 sc->handle[3].vendor = vendor; 330 } 331 } 332 333 void 334 pcic_attach_sockets(sc) 335 struct pcic_softc *sc; 336 { 337 int i; 338 339 for (i = 0; i < PCIC_NSLOTS; i++) 340 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 341 pcic_attach_socket(&sc->handle[i]); 342 } 343 344 void 345 pcic_power (why, arg) 346 int why; 347 void *arg; 348 { 349 struct pcic_handle *h = (struct pcic_handle *)arg; 350 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 351 352 if (h->flags & PCIC_FLAG_SOCKETP) { 353 if ((why == PWR_RESUME) && 354 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 355 #ifdef PCICDEBUG 356 char bitbuf[64]; 357 #endif 358 pcic_write(h, PCIC_CSC_INTR, 359 (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 360 PCIC_CSC_INTR_CD_ENABLE); 361 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 362 sc->dev.dv_xname, 363 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 364 PCIC_CSC_INTR_FORMAT, 365 bitbuf, sizeof(bitbuf)))); 366 } 367 } 368 } 369 370 371 void 372 pcic_attach_socket(h) 373 struct pcic_handle *h; 374 { 375 struct pcmciabus_attach_args paa; 376 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 377 378 /* initialize the rest of the handle */ 379 380 h->shutdown = 0; 381 h->memalloc = 0; 382 h->ioalloc = 0; 383 h->ih_irq = 0; 384 385 /* now, config one pcmcia device per socket */ 386 387 paa.paa_busname = "pcmcia"; 388 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 389 paa.pch = (pcmcia_chipset_handle_t) h; 390 paa.iobase = sc->iobase; 391 paa.iosize = sc->iosize; 392 393 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, 394 pcic_submatch); 395 396 /* if there's actually a pcmcia device attached, initialize the slot */ 397 398 if (h->pcmcia) 399 pcic_init_socket(h); 400 } 401 402 void 403 pcic_create_event_thread(arg) 404 void *arg; 405 { 406 struct pcic_handle *h = arg; 407 const char *cs; 408 409 switch (h->sock) { 410 case C0SA: 411 cs = "0,0"; 412 break; 413 case C0SB: 414 cs = "0,1"; 415 break; 416 case C1SA: 417 cs = "1,0"; 418 break; 419 case C1SB: 420 cs = "1,1"; 421 break; 422 default: 423 panic("pcic_create_event_thread: unknown pcic socket"); 424 } 425 426 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 427 "%s,%s", h->ph_parent->dv_xname, cs)) { 428 printf("%s: unable to create event thread for sock 0x%02x\n", 429 h->ph_parent->dv_xname, h->sock); 430 panic("pcic_create_event_thread"); 431 } 432 } 433 434 void 435 pcic_event_thread(arg) 436 void *arg; 437 { 438 struct pcic_handle *h = arg; 439 struct pcic_event *pe; 440 int s; 441 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 442 443 while (h->shutdown == 0) { 444 s = splhigh(); 445 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 446 splx(s); 447 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 448 continue; 449 } else { 450 splx(s); 451 /* sleep .25s to be enqueued chatterling interrupts */ 452 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, "pcicss", hz/4); 453 } 454 s = splhigh(); 455 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 456 splx(s); 457 458 switch (pe->pe_type) { 459 case PCIC_EVENT_INSERTION: 460 s = splhigh(); 461 while (1) { 462 struct pcic_event *pe1, *pe2; 463 464 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 465 break; 466 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 467 break; 468 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 469 break; 470 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 471 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, pe_q); 472 free(pe1, M_TEMP); 473 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, pe_q); 474 free(pe2, M_TEMP); 475 } 476 } 477 splx(s); 478 479 DPRINTF(("%s: insertion event\n", h->ph_parent->dv_xname)); 480 pcic_attach_card(h); 481 break; 482 483 case PCIC_EVENT_REMOVAL: 484 s = splhigh(); 485 while (1) { 486 struct pcic_event *pe1, *pe2; 487 488 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 489 break; 490 if (pe1->pe_type != PCIC_EVENT_INSERTION) 491 break; 492 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 493 break; 494 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 495 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, pe_q); 496 free(pe1, M_TEMP); 497 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, pe_q); 498 free(pe2, M_TEMP); 499 } 500 } 501 splx(s); 502 503 DPRINTF(("%s: removal event\n", h->ph_parent->dv_xname)); 504 pcic_detach_card(h, DETACH_FORCE); 505 break; 506 507 default: 508 panic("pcic_event_thread: unknown event %d", 509 pe->pe_type); 510 } 511 free(pe, M_TEMP); 512 } 513 514 h->event_thread = NULL; 515 516 /* In case parent is waiting for us to exit. */ 517 wakeup(sc); 518 519 kthread_exit(0); 520 } 521 522 void 523 pcic_init_socket(h) 524 struct pcic_handle *h; 525 { 526 int reg; 527 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 528 529 /* 530 * queue creation of a kernel thread to handle insert/removal events. 531 */ 532 #ifdef DIAGNOSTIC 533 if (h->event_thread != NULL) 534 panic("pcic_attach_socket: event thread"); 535 #endif 536 kthread_create(pcic_create_event_thread, h); 537 538 /* set up the card to interrupt on card detect */ 539 540 pcic_write(h, PCIC_CSC_INTR, (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 541 PCIC_CSC_INTR_CD_ENABLE); 542 pcic_write(h, PCIC_INTR, 0); 543 pcic_read(h, PCIC_CSC); 544 545 /* 546 * Set up a powerhook to ensure it continues to interrupt on 547 * card detect even after suspend. 548 * (this works around a bug seen in suspend-to-disk on the 549 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 550 */ 551 powerhook_establish(pcic_power, h); 552 553 /* unsleep the cirrus controller */ 554 555 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 556 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 557 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 558 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 559 DPRINTF(("%s: socket %02x was suspended\n", 560 h->ph_parent->dv_xname, h->sock)); 561 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 562 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 563 } 564 } 565 /* if there's a card there, then attach it. */ 566 567 reg = pcic_read(h, PCIC_IF_STATUS); 568 569 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 570 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 571 pcic_attach_card(h); 572 h->laststate = PCIC_LASTSTATE_PRESENT; 573 } else { 574 h->laststate = PCIC_LASTSTATE_EMPTY; 575 } 576 } 577 578 int 579 pcic_submatch(parent, cf, aux) 580 struct device *parent; 581 struct cfdata *cf; 582 void *aux; 583 { 584 585 struct pcmciabus_attach_args *paa = aux; 586 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 587 588 switch (h->sock) { 589 case C0SA: 590 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 591 PCMCIABUSCF_CONTROLLER_DEFAULT && 592 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 593 return 0; 594 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 595 PCMCIABUSCF_SOCKET_DEFAULT && 596 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 597 return 0; 598 599 break; 600 case C0SB: 601 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 602 PCMCIABUSCF_CONTROLLER_DEFAULT && 603 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 604 return 0; 605 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 606 PCMCIABUSCF_SOCKET_DEFAULT && 607 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 608 return 0; 609 610 break; 611 case C1SA: 612 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 613 PCMCIABUSCF_CONTROLLER_DEFAULT && 614 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 615 return 0; 616 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 617 PCMCIABUSCF_SOCKET_DEFAULT && 618 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 619 return 0; 620 621 break; 622 case C1SB: 623 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 624 PCMCIABUSCF_CONTROLLER_DEFAULT && 625 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 626 return 0; 627 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 628 PCMCIABUSCF_SOCKET_DEFAULT && 629 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 630 return 0; 631 632 break; 633 default: 634 panic("unknown pcic socket"); 635 } 636 637 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 638 } 639 640 int 641 pcic_print(arg, pnp) 642 void *arg; 643 const char *pnp; 644 { 645 struct pcmciabus_attach_args *paa = arg; 646 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 647 648 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 649 if (pnp) 650 printf("pcmcia at %s", pnp); 651 652 switch (h->sock) { 653 case C0SA: 654 printf(" controller 0 socket 0"); 655 break; 656 case C0SB: 657 printf(" controller 0 socket 1"); 658 break; 659 case C1SA: 660 printf(" controller 1 socket 0"); 661 break; 662 case C1SB: 663 printf(" controller 1 socket 1"); 664 break; 665 default: 666 panic("unknown pcic socket"); 667 } 668 669 return (UNCONF); 670 } 671 672 int 673 pcic_intr(arg) 674 void *arg; 675 { 676 struct pcic_softc *sc = arg; 677 int i, ret = 0; 678 679 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 680 681 for (i = 0; i < PCIC_NSLOTS; i++) 682 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 683 ret += pcic_intr_socket(&sc->handle[i]); 684 685 return (ret ? 1 : 0); 686 } 687 688 int 689 pcic_intr_socket(h) 690 struct pcic_handle *h; 691 { 692 int cscreg; 693 694 cscreg = pcic_read(h, PCIC_CSC); 695 696 cscreg &= (PCIC_CSC_GPI | 697 PCIC_CSC_CD | 698 PCIC_CSC_READY | 699 PCIC_CSC_BATTWARN | 700 PCIC_CSC_BATTDEAD); 701 702 if (cscreg & PCIC_CSC_GPI) { 703 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 704 } 705 if (cscreg & PCIC_CSC_CD) { 706 int statreg; 707 708 statreg = pcic_read(h, PCIC_IF_STATUS); 709 710 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 711 statreg)); 712 713 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 714 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 715 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 716 DPRINTF(("%s: enqueing INSERTION event\n", 717 h->ph_parent->dv_xname)); 718 pcic_queue_event(h, PCIC_EVENT_INSERTION); 719 } 720 h->laststate = PCIC_LASTSTATE_PRESENT; 721 } else { 722 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 723 /* Deactivate the card now. */ 724 DPRINTF(("%s: deactivating card\n", 725 h->ph_parent->dv_xname)); 726 pcic_deactivate_card(h); 727 728 DPRINTF(("%s: enqueing REMOVAL event\n", 729 h->ph_parent->dv_xname)); 730 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 731 } 732 h->laststate = ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) 733 ? PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 734 } 735 } 736 if (cscreg & PCIC_CSC_READY) { 737 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 738 /* shouldn't happen */ 739 } 740 if (cscreg & PCIC_CSC_BATTWARN) { 741 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, h->sock)); 742 } 743 if (cscreg & PCIC_CSC_BATTDEAD) { 744 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, h->sock)); 745 } 746 return (cscreg ? 1 : 0); 747 } 748 749 void 750 pcic_queue_event(h, event) 751 struct pcic_handle *h; 752 int event; 753 { 754 struct pcic_event *pe; 755 int s; 756 757 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 758 if (pe == NULL) 759 panic("pcic_queue_event: can't allocate event"); 760 761 pe->pe_type = event; 762 s = splhigh(); 763 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 764 splx(s); 765 wakeup(&h->events); 766 } 767 768 void 769 pcic_attach_card(h) 770 struct pcic_handle *h; 771 { 772 773 if (!(h->flags & PCIC_FLAG_CARDP)) { 774 /* call the MI attach function */ 775 pcmcia_card_attach(h->pcmcia); 776 777 h->flags |= PCIC_FLAG_CARDP; 778 } else { 779 DPRINTF(("pcic_attach_card: already attached")); 780 } 781 } 782 783 void 784 pcic_detach_card(h, flags) 785 struct pcic_handle *h; 786 int flags; /* DETACH_* */ 787 { 788 789 if (h->flags & PCIC_FLAG_CARDP) { 790 h->flags &= ~PCIC_FLAG_CARDP; 791 792 /* call the MI detach function */ 793 pcmcia_card_detach(h->pcmcia, flags); 794 } else { 795 DPRINTF(("pcic_detach_card: already detached")); 796 } 797 } 798 799 void 800 pcic_deactivate_card(h) 801 struct pcic_handle *h; 802 { 803 804 /* call the MI deactivate function */ 805 pcmcia_card_deactivate(h->pcmcia); 806 807 /* power down the socket */ 808 pcic_write(h, PCIC_PWRCTL, 0); 809 810 /* reset the socket */ 811 pcic_write(h, PCIC_INTR, 0); 812 } 813 814 int 815 pcic_chip_mem_alloc(pch, size, pcmhp) 816 pcmcia_chipset_handle_t pch; 817 bus_size_t size; 818 struct pcmcia_mem_handle *pcmhp; 819 { 820 struct pcic_handle *h = (struct pcic_handle *) pch; 821 bus_space_handle_t memh; 822 bus_addr_t addr; 823 bus_size_t sizepg; 824 int i, mask, mhandle; 825 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 826 827 /* out of sc->memh, allocate as many pages as necessary */ 828 829 /* convert size to PCIC pages */ 830 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 831 if (sizepg > PCIC_MAX_MEM_PAGES) 832 return (1); 833 834 mask = (1 << sizepg) - 1; 835 836 addr = 0; /* XXX gcc -Wuninitialized */ 837 mhandle = 0; /* XXX gcc -Wuninitialized */ 838 839 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 840 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 841 if (bus_space_subregion(sc->memt, sc->memh, 842 i * PCIC_MEM_PAGESIZE, 843 sizepg * PCIC_MEM_PAGESIZE, &memh)) 844 return (1); 845 mhandle = mask << i; 846 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 847 sc->subregionmask &= ~(mhandle); 848 pcmhp->memt = sc->memt; 849 pcmhp->memh = memh; 850 pcmhp->addr = addr; 851 pcmhp->size = size; 852 pcmhp->mhandle = mhandle; 853 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 854 return (0); 855 } 856 } 857 858 return (1); 859 } 860 861 void 862 pcic_chip_mem_free(pch, pcmhp) 863 pcmcia_chipset_handle_t pch; 864 struct pcmcia_mem_handle *pcmhp; 865 { 866 struct pcic_handle *h = (struct pcic_handle *) pch; 867 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 868 869 sc->subregionmask |= pcmhp->mhandle; 870 } 871 872 static struct mem_map_index_st { 873 int sysmem_start_lsb; 874 int sysmem_start_msb; 875 int sysmem_stop_lsb; 876 int sysmem_stop_msb; 877 int cardmem_lsb; 878 int cardmem_msb; 879 int memenable; 880 } mem_map_index[] = { 881 { 882 PCIC_SYSMEM_ADDR0_START_LSB, 883 PCIC_SYSMEM_ADDR0_START_MSB, 884 PCIC_SYSMEM_ADDR0_STOP_LSB, 885 PCIC_SYSMEM_ADDR0_STOP_MSB, 886 PCIC_CARDMEM_ADDR0_LSB, 887 PCIC_CARDMEM_ADDR0_MSB, 888 PCIC_ADDRWIN_ENABLE_MEM0, 889 }, 890 { 891 PCIC_SYSMEM_ADDR1_START_LSB, 892 PCIC_SYSMEM_ADDR1_START_MSB, 893 PCIC_SYSMEM_ADDR1_STOP_LSB, 894 PCIC_SYSMEM_ADDR1_STOP_MSB, 895 PCIC_CARDMEM_ADDR1_LSB, 896 PCIC_CARDMEM_ADDR1_MSB, 897 PCIC_ADDRWIN_ENABLE_MEM1, 898 }, 899 { 900 PCIC_SYSMEM_ADDR2_START_LSB, 901 PCIC_SYSMEM_ADDR2_START_MSB, 902 PCIC_SYSMEM_ADDR2_STOP_LSB, 903 PCIC_SYSMEM_ADDR2_STOP_MSB, 904 PCIC_CARDMEM_ADDR2_LSB, 905 PCIC_CARDMEM_ADDR2_MSB, 906 PCIC_ADDRWIN_ENABLE_MEM2, 907 }, 908 { 909 PCIC_SYSMEM_ADDR3_START_LSB, 910 PCIC_SYSMEM_ADDR3_START_MSB, 911 PCIC_SYSMEM_ADDR3_STOP_LSB, 912 PCIC_SYSMEM_ADDR3_STOP_MSB, 913 PCIC_CARDMEM_ADDR3_LSB, 914 PCIC_CARDMEM_ADDR3_MSB, 915 PCIC_ADDRWIN_ENABLE_MEM3, 916 }, 917 { 918 PCIC_SYSMEM_ADDR4_START_LSB, 919 PCIC_SYSMEM_ADDR4_START_MSB, 920 PCIC_SYSMEM_ADDR4_STOP_LSB, 921 PCIC_SYSMEM_ADDR4_STOP_MSB, 922 PCIC_CARDMEM_ADDR4_LSB, 923 PCIC_CARDMEM_ADDR4_MSB, 924 PCIC_ADDRWIN_ENABLE_MEM4, 925 }, 926 }; 927 928 void 929 pcic_chip_do_mem_map(h, win) 930 struct pcic_handle *h; 931 int win; 932 { 933 int reg; 934 935 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 936 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 937 pcic_write(h, mem_map_index[win].sysmem_start_msb, 938 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 939 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 940 941 #if 0 942 /* XXX do I want 16 bit all the time? */ 943 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 944 #endif 945 946 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 947 ((h->mem[win].addr + h->mem[win].size) >> 948 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 949 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 950 (((h->mem[win].addr + h->mem[win].size) >> 951 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 952 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 953 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 954 955 pcic_write(h, mem_map_index[win].cardmem_lsb, 956 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 957 pcic_write(h, mem_map_index[win].cardmem_msb, 958 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 959 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 960 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 961 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 962 963 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 964 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 965 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 966 967 delay(100); 968 969 #ifdef PCICDEBUG 970 { 971 int r1, r2, r3, r4, r5, r6; 972 973 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 974 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 975 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 976 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 977 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 978 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 979 980 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 981 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 982 } 983 #endif 984 } 985 986 int 987 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 988 pcmcia_chipset_handle_t pch; 989 int kind; 990 bus_addr_t card_addr; 991 bus_size_t size; 992 struct pcmcia_mem_handle *pcmhp; 993 bus_addr_t *offsetp; 994 int *windowp; 995 { 996 struct pcic_handle *h = (struct pcic_handle *) pch; 997 bus_addr_t busaddr; 998 long card_offset; 999 int i, win; 1000 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1001 1002 win = -1; 1003 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1004 i++) { 1005 if ((h->memalloc & (1 << i)) == 0) { 1006 win = i; 1007 h->memalloc |= (1 << i); 1008 break; 1009 } 1010 } 1011 1012 if (win == -1) 1013 return (1); 1014 1015 *windowp = win; 1016 1017 /* XXX this is pretty gross */ 1018 1019 if (sc->memt != pcmhp->memt) 1020 panic("pcic_chip_mem_map memt is bogus"); 1021 1022 busaddr = pcmhp->addr; 1023 1024 /* 1025 * compute the address offset to the pcmcia address space for the 1026 * pcic. this is intentionally signed. The masks and shifts below 1027 * will cause TRT to happen in the pcic registers. Deal with making 1028 * sure the address is aligned, and return the alignment offset. 1029 */ 1030 1031 *offsetp = card_addr % PCIC_MEM_ALIGN; 1032 card_addr -= *offsetp; 1033 1034 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1035 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1036 (u_long) card_addr)); 1037 1038 /* 1039 * include the offset in the size, and decrement size by one, since 1040 * the hw wants start/stop 1041 */ 1042 size += *offsetp - 1; 1043 1044 card_offset = (((long) card_addr) - ((long) busaddr)); 1045 1046 h->mem[win].addr = busaddr; 1047 h->mem[win].size = size; 1048 h->mem[win].offset = card_offset; 1049 h->mem[win].kind = kind; 1050 1051 pcic_chip_do_mem_map(h, win); 1052 1053 return (0); 1054 } 1055 1056 void 1057 pcic_chip_mem_unmap(pch, window) 1058 pcmcia_chipset_handle_t pch; 1059 int window; 1060 { 1061 struct pcic_handle *h = (struct pcic_handle *) pch; 1062 int reg; 1063 1064 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1065 panic("pcic_chip_mem_unmap: window out of range"); 1066 1067 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1068 reg &= ~mem_map_index[window].memenable; 1069 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1070 1071 h->memalloc &= ~(1 << window); 1072 } 1073 1074 int 1075 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1076 pcmcia_chipset_handle_t pch; 1077 bus_addr_t start; 1078 bus_size_t size; 1079 bus_size_t align; 1080 struct pcmcia_io_handle *pcihp; 1081 { 1082 struct pcic_handle *h = (struct pcic_handle *) pch; 1083 bus_space_tag_t iot; 1084 bus_space_handle_t ioh; 1085 bus_addr_t ioaddr; 1086 int flags = 0; 1087 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1088 1089 /* 1090 * Allocate some arbitrary I/O space. 1091 */ 1092 1093 iot = sc->iot; 1094 1095 if (start) { 1096 ioaddr = start; 1097 if (bus_space_map(iot, start, size, 0, &ioh)) 1098 return (1); 1099 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1100 (u_long) ioaddr, (u_long) size)); 1101 } else { 1102 flags |= PCMCIA_IO_ALLOCATED; 1103 if (bus_space_alloc(iot, sc->iobase, 1104 sc->iobase + sc->iosize, size, align, 0, 0, 1105 &ioaddr, &ioh)) 1106 return (1); 1107 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1108 (u_long) ioaddr, (u_long) size)); 1109 } 1110 1111 pcihp->iot = iot; 1112 pcihp->ioh = ioh; 1113 pcihp->addr = ioaddr; 1114 pcihp->size = size; 1115 pcihp->flags = flags; 1116 1117 return (0); 1118 } 1119 1120 void 1121 pcic_chip_io_free(pch, pcihp) 1122 pcmcia_chipset_handle_t pch; 1123 struct pcmcia_io_handle *pcihp; 1124 { 1125 bus_space_tag_t iot = pcihp->iot; 1126 bus_space_handle_t ioh = pcihp->ioh; 1127 bus_size_t size = pcihp->size; 1128 1129 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1130 bus_space_free(iot, ioh, size); 1131 else 1132 bus_space_unmap(iot, ioh, size); 1133 } 1134 1135 1136 static struct io_map_index_st { 1137 int start_lsb; 1138 int start_msb; 1139 int stop_lsb; 1140 int stop_msb; 1141 int ioenable; 1142 int ioctlmask; 1143 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1144 } io_map_index[] = { 1145 { 1146 PCIC_IOADDR0_START_LSB, 1147 PCIC_IOADDR0_START_MSB, 1148 PCIC_IOADDR0_STOP_LSB, 1149 PCIC_IOADDR0_STOP_MSB, 1150 PCIC_ADDRWIN_ENABLE_IO0, 1151 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1152 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1153 { 1154 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1155 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1156 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1157 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1158 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1159 }, 1160 }, 1161 { 1162 PCIC_IOADDR1_START_LSB, 1163 PCIC_IOADDR1_START_MSB, 1164 PCIC_IOADDR1_STOP_LSB, 1165 PCIC_IOADDR1_STOP_MSB, 1166 PCIC_ADDRWIN_ENABLE_IO1, 1167 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1168 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1169 { 1170 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1171 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1172 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1173 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1174 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1175 }, 1176 }, 1177 }; 1178 1179 void 1180 pcic_chip_do_io_map(h, win) 1181 struct pcic_handle *h; 1182 int win; 1183 { 1184 int reg; 1185 1186 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1187 win, (long) h->io[win].addr, (long) h->io[win].size, 1188 h->io[win].width * 8)); 1189 1190 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1191 pcic_write(h, io_map_index[win].start_msb, 1192 (h->io[win].addr >> 8) & 0xff); 1193 1194 pcic_write(h, io_map_index[win].stop_lsb, 1195 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1196 pcic_write(h, io_map_index[win].stop_msb, 1197 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1198 1199 reg = pcic_read(h, PCIC_IOCTL); 1200 reg &= ~io_map_index[win].ioctlmask; 1201 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1202 pcic_write(h, PCIC_IOCTL, reg); 1203 1204 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1205 reg |= io_map_index[win].ioenable; 1206 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1207 } 1208 1209 int 1210 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1211 pcmcia_chipset_handle_t pch; 1212 int width; 1213 bus_addr_t offset; 1214 bus_size_t size; 1215 struct pcmcia_io_handle *pcihp; 1216 int *windowp; 1217 { 1218 struct pcic_handle *h = (struct pcic_handle *) pch; 1219 bus_addr_t ioaddr = pcihp->addr + offset; 1220 int i, win; 1221 #ifdef PCICDEBUG 1222 static char *width_names[] = { "auto", "io8", "io16" }; 1223 #endif 1224 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1225 1226 /* XXX Sanity check offset/size. */ 1227 1228 win = -1; 1229 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1230 if ((h->ioalloc & (1 << i)) == 0) { 1231 win = i; 1232 h->ioalloc |= (1 << i); 1233 break; 1234 } 1235 } 1236 1237 if (win == -1) 1238 return (1); 1239 1240 *windowp = win; 1241 1242 /* XXX this is pretty gross */ 1243 1244 if (sc->iot != pcihp->iot) 1245 panic("pcic_chip_io_map iot is bogus"); 1246 1247 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1248 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1249 1250 /* XXX wtf is this doing here? */ 1251 1252 printf(" port 0x%lx", (u_long) ioaddr); 1253 if (size > 1) 1254 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1255 1256 h->io[win].addr = ioaddr; 1257 h->io[win].size = size; 1258 h->io[win].width = width; 1259 1260 pcic_chip_do_io_map(h, win); 1261 1262 return (0); 1263 } 1264 1265 void 1266 pcic_chip_io_unmap(pch, window) 1267 pcmcia_chipset_handle_t pch; 1268 int window; 1269 { 1270 struct pcic_handle *h = (struct pcic_handle *) pch; 1271 int reg; 1272 1273 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1274 panic("pcic_chip_io_unmap: window out of range"); 1275 1276 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1277 reg &= ~io_map_index[window].ioenable; 1278 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1279 1280 h->ioalloc &= ~(1 << window); 1281 } 1282 1283 static void 1284 pcic_wait_ready(h) 1285 struct pcic_handle *h; 1286 { 1287 int i; 1288 1289 for (i = 0; i < 10000; i++) { 1290 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1291 return; 1292 delay(500); 1293 #ifdef PCICDEBUG 1294 if (pcic_debug) { 1295 if ((i>5000) && (i%100 == 99)) 1296 printf("."); 1297 } 1298 #endif 1299 } 1300 1301 #ifdef DIAGNOSTIC 1302 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1303 pcic_read(h, PCIC_IF_STATUS)); 1304 #endif 1305 } 1306 1307 void 1308 pcic_chip_socket_enable(pch) 1309 pcmcia_chipset_handle_t pch; 1310 { 1311 struct pcic_handle *h = (struct pcic_handle *) pch; 1312 int cardtype, reg, win; 1313 1314 /* this bit is mostly stolen from pcic_attach_card */ 1315 1316 /* power down the socket to reset it, clear the card reset pin */ 1317 1318 pcic_write(h, PCIC_PWRCTL, 0); 1319 1320 /* 1321 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1322 * we are changing Vcc (Toff). 1323 */ 1324 delay((300 + 100) * 1000); 1325 1326 #ifdef VADEM_POWER_HACK 1327 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1328 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1329 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1330 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1331 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1332 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1333 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1334 #endif 1335 1336 /* power up the socket */ 1337 1338 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1339 | PCIC_PWRCTL_PWR_ENABLE); 1340 1341 /* 1342 * wait 100ms until power raise (Tpr) and 20ms to become 1343 * stable (Tsu(Vcc)). 1344 * 1345 * some machines require some more time to be settled 1346 * (300ms is added here). 1347 */ 1348 delay((100 + 20 + 300) * 1000); 1349 1350 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1351 | PCIC_PWRCTL_PWR_ENABLE); 1352 pcic_write(h, PCIC_INTR, 0); 1353 1354 /* 1355 * hold RESET at least 10us. 1356 */ 1357 delay(10); 1358 1359 /* clear the reset flag */ 1360 1361 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1362 1363 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1364 1365 delay(20000); 1366 1367 /* wait for the chip to finish initializing */ 1368 1369 #ifdef DIAGNOSTIC 1370 reg = pcic_read(h, PCIC_IF_STATUS); 1371 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1372 printf("pcic_chip_socket_enable: status %x", reg); 1373 } 1374 #endif 1375 1376 pcic_wait_ready(h); 1377 1378 /* zero out the address windows */ 1379 1380 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1381 1382 /* set the card type */ 1383 1384 cardtype = pcmcia_card_gettype(h->pcmcia); 1385 1386 reg = pcic_read(h, PCIC_INTR); 1387 reg &= ~(PCIC_INTR_CARDTYPE_MASK | PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1388 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1389 PCIC_INTR_CARDTYPE_IO : 1390 PCIC_INTR_CARDTYPE_MEM); 1391 reg |= h->ih_irq; 1392 pcic_write(h, PCIC_INTR, reg); 1393 1394 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1395 h->ph_parent->dv_xname, h->sock, 1396 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1397 1398 /* reinstall all the memory and io mappings */ 1399 1400 for (win = 0; win < PCIC_MEM_WINS; win++) 1401 if (h->memalloc & (1 << win)) 1402 pcic_chip_do_mem_map(h, win); 1403 1404 for (win = 0; win < PCIC_IO_WINS; win++) 1405 if (h->ioalloc & (1 << win)) 1406 pcic_chip_do_io_map(h, win); 1407 } 1408 1409 void 1410 pcic_chip_socket_disable(pch) 1411 pcmcia_chipset_handle_t pch; 1412 { 1413 struct pcic_handle *h = (struct pcic_handle *) pch; 1414 1415 DPRINTF(("pcic_chip_socket_disable\n")); 1416 1417 /* power down the socket */ 1418 1419 pcic_write(h, PCIC_PWRCTL, 0); 1420 1421 /* 1422 * wait 300ms until power fails (Tpf). 1423 */ 1424 delay(300 * 1000); 1425 } 1426 1427 static u_int8_t 1428 st_pcic_read(h, idx) 1429 struct pcic_handle *h; 1430 int idx; 1431 { 1432 if (idx != -1) 1433 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1434 h->sock + idx); 1435 1436 return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA); 1437 } 1438 1439 static void 1440 st_pcic_write(h, idx, data) 1441 struct pcic_handle *h; 1442 int idx; 1443 u_int8_t data; 1444 { 1445 if (idx != -1) 1446 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1447 h->sock + idx); 1448 1449 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1450 } 1451
Indexes created Mon Sep 29 03:10:08 GMT 2025