i82365.c revision 1.28
1 /* $NetBSD: i82365.c,v 1.28 2000/01/13 09:00:30 joda Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <vm/vm.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/pcmcia/pcmciareg.h> 49 #include <dev/pcmcia/pcmciavar.h> 50 51 #include <dev/ic/i82365reg.h> 52 #include <dev/ic/i82365var.h> 53 54 #include "locators.h" 55 56 #ifdef PCICDEBUG 57 int pcic_debug = 0; 58 #define DPRINTF(arg) if (pcic_debug) printf arg; 59 #else 60 #define DPRINTF(arg) 61 #endif 62 63 #define PCIC_VENDOR_UNKNOWN 0 64 #define PCIC_VENDOR_I82365SLR0 1 65 #define PCIC_VENDOR_I82365SLR1 2 66 #define PCIC_VENDOR_CIRRUS_PD6710 3 67 #define PCIC_VENDOR_CIRRUS_PD672X 4 68 69 /* 70 * Individual drivers will allocate their own memory and io regions. Memory 71 * regions must be a multiple of 4k, aligned on a 4k boundary. 72 */ 73 74 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 75 76 void pcic_attach_socket __P((struct pcic_handle *)); 77 void pcic_init_socket __P((struct pcic_handle *)); 78 79 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 80 int pcic_print __P((void *arg, const char *pnp)); 81 int pcic_intr_socket __P((struct pcic_handle *)); 82 83 void pcic_attach_card __P((struct pcic_handle *)); 84 void pcic_detach_card __P((struct pcic_handle *, int)); 85 void pcic_deactivate_card __P((struct pcic_handle *)); 86 87 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 88 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 89 90 void pcic_create_event_thread __P((void *)); 91 void pcic_event_thread __P((void *)); 92 93 void pcic_queue_event __P((struct pcic_handle *, int)); 94 void pcic_power __P((int, void *)); 95 96 static void pcic_wait_ready __P((struct pcic_handle *)); 97 98 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 99 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 100 101 int 102 pcic_ident_ok(ident) 103 int ident; 104 { 105 /* this is very empirical and heuristic */ 106 107 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 108 return (0); 109 110 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 111 #ifdef DIAGNOSTIC 112 printf("pcic: does not support memory and I/O cards, " 113 "ignored (ident=%0x)\n", ident); 114 #endif 115 return (0); 116 } 117 return (1); 118 } 119 120 int 121 pcic_vendor(h) 122 struct pcic_handle *h; 123 { 124 int reg; 125 126 /* 127 * the chip_id of the cirrus toggles between 11 and 00 after a write. 128 * weird. 129 */ 130 131 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 132 reg = pcic_read(h, -1); 133 134 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 135 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 136 reg = pcic_read(h, -1); 137 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 138 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 139 return (PCIC_VENDOR_CIRRUS_PD672X); 140 else 141 return (PCIC_VENDOR_CIRRUS_PD6710); 142 } 143 } 144 145 reg = pcic_read(h, PCIC_IDENT); 146 147 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 148 return (PCIC_VENDOR_I82365SLR0); 149 else 150 return (PCIC_VENDOR_I82365SLR1); 151 152 return (PCIC_VENDOR_UNKNOWN); 153 } 154 155 char * 156 pcic_vendor_to_string(vendor) 157 int vendor; 158 { 159 switch (vendor) { 160 case PCIC_VENDOR_I82365SLR0: 161 return ("Intel 82365SL Revision 0"); 162 case PCIC_VENDOR_I82365SLR1: 163 return ("Intel 82365SL Revision 1"); 164 case PCIC_VENDOR_CIRRUS_PD6710: 165 return ("Cirrus PD6710"); 166 case PCIC_VENDOR_CIRRUS_PD672X: 167 return ("Cirrus PD672X"); 168 } 169 170 return ("Unknown controller"); 171 } 172 173 void 174 pcic_attach(sc) 175 struct pcic_softc *sc; 176 { 177 int vendor, count, i, reg; 178 179 /* now check for each controller/socket */ 180 181 /* 182 * this could be done with a loop, but it would violate the 183 * abstraction 184 */ 185 186 count = 0; 187 188 DPRINTF(("pcic ident regs:")); 189 190 sc->handle[0].ph_parent = (struct device *)sc; 191 sc->handle[0].sock = C0SA; 192 /* initialise pcic_read and pcic_write functions */ 193 sc->handle[0].ph_read = st_pcic_read; 194 sc->handle[0].ph_write = st_pcic_write; 195 sc->handle[0].ph_bus_t = sc->iot; 196 sc->handle[0].ph_bus_h = sc->ioh; 197 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 198 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 199 count++; 200 } else { 201 sc->handle[0].flags = 0; 202 } 203 sc->handle[0].laststate = PCIC_LASTSTATE_EMPTY; 204 205 DPRINTF((" 0x%02x", reg)); 206 207 sc->handle[1].ph_parent = (struct device *)sc; 208 sc->handle[1].sock = C0SB; 209 /* initialise pcic_read and pcic_write functions */ 210 sc->handle[1].ph_read = st_pcic_read; 211 sc->handle[1].ph_write = st_pcic_write; 212 sc->handle[1].ph_bus_t = sc->iot; 213 sc->handle[1].ph_bus_h = sc->ioh; 214 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 215 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 216 count++; 217 } else { 218 sc->handle[1].flags = 0; 219 } 220 sc->handle[1].laststate = PCIC_LASTSTATE_EMPTY; 221 222 DPRINTF((" 0x%02x", reg)); 223 224 /* 225 * The CL-PD6729 has only one controller and always returns 0 226 * if you try to read from the second one. Maybe pcic_ident_ok 227 * shouldn't accept 0? 228 */ 229 sc->handle[2].ph_parent = (struct device *)sc; 230 sc->handle[2].sock = C1SA; 231 /* initialise pcic_read and pcic_write functions */ 232 sc->handle[2].ph_read = st_pcic_read; 233 sc->handle[2].ph_write = st_pcic_write; 234 sc->handle[2].ph_bus_t = sc->iot; 235 sc->handle[2].ph_bus_h = sc->ioh; 236 if (pcic_vendor(&sc->handle[0]) != PCIC_VENDOR_CIRRUS_PD672X || 237 pcic_read(&sc->handle[2], PCIC_IDENT) != 0) { 238 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], 239 PCIC_IDENT))) { 240 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 241 count++; 242 } else { 243 sc->handle[2].flags = 0; 244 } 245 sc->handle[2].laststate = PCIC_LASTSTATE_EMPTY; 246 247 DPRINTF((" 0x%02x", reg)); 248 249 sc->handle[3].ph_parent = (struct device *)sc; 250 sc->handle[3].sock = C1SB; 251 /* initialise pcic_read and pcic_write functions */ 252 sc->handle[3].ph_read = st_pcic_read; 253 sc->handle[3].ph_write = st_pcic_write; 254 sc->handle[3].ph_bus_t = sc->iot; 255 sc->handle[3].ph_bus_h = sc->ioh; 256 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], 257 PCIC_IDENT))) { 258 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 259 count++; 260 } else { 261 sc->handle[3].flags = 0; 262 } 263 sc->handle[3].laststate = PCIC_LASTSTATE_EMPTY; 264 265 DPRINTF((" 0x%02x\n", reg)); 266 } else { 267 sc->handle[2].flags = 0; 268 sc->handle[3].flags = 0; 269 } 270 271 if (count == 0) 272 panic("pcic_attach: attach found no sockets"); 273 274 /* establish the interrupt */ 275 276 /* XXX block interrupts? */ 277 278 for (i = 0; i < PCIC_NSLOTS; i++) { 279 /* 280 * this should work, but w/o it, setting tty flags hangs at 281 * boot time. 282 */ 283 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 284 { 285 SIMPLEQ_INIT(&sc->handle[i].events); 286 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 287 pcic_read(&sc->handle[i], PCIC_CSC); 288 } 289 } 290 291 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 292 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 293 vendor = pcic_vendor(&sc->handle[0]); 294 295 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 296 pcic_vendor_to_string(vendor)); 297 298 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 299 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 300 printf("sockets A and B\n"); 301 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 302 printf("socket A only\n"); 303 else 304 printf("socket B only\n"); 305 306 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 307 sc->handle[0].vendor = vendor; 308 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 309 sc->handle[1].vendor = vendor; 310 } 311 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 312 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 313 vendor = pcic_vendor(&sc->handle[2]); 314 315 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 316 pcic_vendor_to_string(vendor)); 317 318 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 319 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 320 printf("sockets A and B\n"); 321 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 322 printf("socket A only\n"); 323 else 324 printf("socket B only\n"); 325 326 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 327 sc->handle[2].vendor = vendor; 328 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 329 sc->handle[3].vendor = vendor; 330 } 331 } 332 333 void 334 pcic_attach_sockets(sc) 335 struct pcic_softc *sc; 336 { 337 int i; 338 339 for (i = 0; i < PCIC_NSLOTS; i++) 340 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 341 pcic_attach_socket(&sc->handle[i]); 342 } 343 344 void 345 pcic_power (why, arg) 346 int why; 347 void *arg; 348 { 349 struct pcic_handle *h = (struct pcic_handle *)arg; 350 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 351 352 if (h->flags & PCIC_FLAG_SOCKETP) { 353 if ((why == PWR_RESUME) && 354 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 355 #ifdef PCICDEBUG 356 char bitbuf[64]; 357 #endif 358 pcic_write(h, PCIC_CSC_INTR, 359 (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 360 PCIC_CSC_INTR_CD_ENABLE); 361 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 362 sc->dev.dv_xname, 363 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 364 PCIC_CSC_INTR_FORMAT, 365 bitbuf, sizeof(bitbuf)))); 366 } 367 } 368 } 369 370 371 void 372 pcic_attach_socket(h) 373 struct pcic_handle *h; 374 { 375 struct pcmciabus_attach_args paa; 376 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 377 378 /* initialize the rest of the handle */ 379 380 h->shutdown = 0; 381 h->memalloc = 0; 382 h->ioalloc = 0; 383 h->ih_irq = 0; 384 385 /* now, config one pcmcia device per socket */ 386 387 paa.paa_busname = "pcmcia"; 388 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 389 paa.pch = (pcmcia_chipset_handle_t) h; 390 paa.iobase = sc->iobase; 391 paa.iosize = sc->iosize; 392 393 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, 394 pcic_submatch); 395 396 /* if there's actually a pcmcia device attached, initialize the slot */ 397 398 if (h->pcmcia) 399 pcic_init_socket(h); 400 } 401 402 void 403 pcic_create_event_thread(arg) 404 void *arg; 405 { 406 struct pcic_handle *h = arg; 407 const char *cs; 408 409 switch (h->sock) { 410 case C0SA: 411 cs = "0,0"; 412 break; 413 case C0SB: 414 cs = "0,1"; 415 break; 416 case C1SA: 417 cs = "1,0"; 418 break; 419 case C1SB: 420 cs = "1,1"; 421 break; 422 default: 423 panic("pcic_create_event_thread: unknown pcic socket"); 424 } 425 426 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 427 "%s,%s", h->ph_parent->dv_xname, cs)) { 428 printf("%s: unable to create event thread for sock 0x%02x\n", 429 h->ph_parent->dv_xname, h->sock); 430 panic("pcic_create_event_thread"); 431 } 432 } 433 434 void 435 pcic_event_thread(arg) 436 void *arg; 437 { 438 struct pcic_handle *h = arg; 439 struct pcic_event *pe; 440 int s; 441 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 442 443 while (h->shutdown == 0) { 444 s = splhigh(); 445 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 446 splx(s); 447 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 448 continue; 449 } else { 450 splx(s); 451 /* sleep .25s to be enqueued chatterling interrupts */ 452 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, "pcicss", hz/4); 453 } 454 s = splhigh(); 455 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 456 splx(s); 457 458 switch (pe->pe_type) { 459 case PCIC_EVENT_INSERTION: 460 s = splhigh(); 461 while (1) { 462 struct pcic_event *pe1, *pe2; 463 464 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 465 break; 466 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 467 break; 468 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 469 break; 470 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 471 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, pe_q); 472 free(pe1, M_TEMP); 473 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, pe_q); 474 free(pe2, M_TEMP); 475 } 476 } 477 splx(s); 478 479 DPRINTF(("%s: insertion event\n", h->ph_parent->dv_xname)); 480 pcic_attach_card(h); 481 break; 482 483 case PCIC_EVENT_REMOVAL: 484 s = splhigh(); 485 while (1) { 486 struct pcic_event *pe1, *pe2; 487 488 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 489 break; 490 if (pe1->pe_type != PCIC_EVENT_INSERTION) 491 break; 492 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 493 break; 494 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 495 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, pe_q); 496 free(pe1, M_TEMP); 497 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, pe_q); 498 free(pe2, M_TEMP); 499 } 500 } 501 splx(s); 502 503 DPRINTF(("%s: removal event\n", h->ph_parent->dv_xname)); 504 pcic_detach_card(h, DETACH_FORCE); 505 break; 506 507 default: 508 panic("pcic_event_thread: unknown event %d", 509 pe->pe_type); 510 } 511 free(pe, M_TEMP); 512 } 513 514 h->event_thread = NULL; 515 516 /* In case parent is waiting for us to exit. */ 517 wakeup(sc); 518 519 kthread_exit(0); 520 } 521 522 void 523 pcic_init_socket(h) 524 struct pcic_handle *h; 525 { 526 int reg; 527 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 528 529 /* 530 * queue creation of a kernel thread to handle insert/removal events. 531 */ 532 #ifdef DIAGNOSTIC 533 if (h->event_thread != NULL) 534 panic("pcic_attach_socket: event thread"); 535 #endif 536 kthread_create(pcic_create_event_thread, h); 537 538 /* set up the card to interrupt on card detect */ 539 540 pcic_write(h, PCIC_CSC_INTR, (sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 541 PCIC_CSC_INTR_CD_ENABLE); 542 pcic_write(h, PCIC_INTR, 0); 543 pcic_read(h, PCIC_CSC); 544 545 /* 546 * Set up a powerhook to ensure it continues to interrupt on 547 * card detect even after suspend. 548 * (this works around a bug seen in suspend-to-disk on the 549 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 550 */ 551 powerhook_establish(pcic_power, h); 552 553 /* unsleep the cirrus controller */ 554 555 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 556 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 557 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 558 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 559 DPRINTF(("%s: socket %02x was suspended\n", 560 h->ph_parent->dv_xname, h->sock)); 561 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 562 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 563 } 564 } 565 /* if there's a card there, then attach it. */ 566 567 reg = pcic_read(h, PCIC_IF_STATUS); 568 569 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 570 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 571 pcic_attach_card(h); 572 h->laststate = PCIC_LASTSTATE_PRESENT; 573 } else { 574 h->laststate = PCIC_LASTSTATE_EMPTY; 575 } 576 } 577 578 int 579 pcic_submatch(parent, cf, aux) 580 struct device *parent; 581 struct cfdata *cf; 582 void *aux; 583 { 584 585 struct pcmciabus_attach_args *paa = aux; 586 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 587 588 switch (h->sock) { 589 case C0SA: 590 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 591 PCMCIABUSCF_CONTROLLER_DEFAULT && 592 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 593 return 0; 594 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 595 PCMCIABUSCF_SOCKET_DEFAULT && 596 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 597 return 0; 598 599 break; 600 case C0SB: 601 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 602 PCMCIABUSCF_CONTROLLER_DEFAULT && 603 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 604 return 0; 605 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 606 PCMCIABUSCF_SOCKET_DEFAULT && 607 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 608 return 0; 609 610 break; 611 case C1SA: 612 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 613 PCMCIABUSCF_CONTROLLER_DEFAULT && 614 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 615 return 0; 616 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 617 PCMCIABUSCF_SOCKET_DEFAULT && 618 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 619 return 0; 620 621 break; 622 case C1SB: 623 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 624 PCMCIABUSCF_CONTROLLER_DEFAULT && 625 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 626 return 0; 627 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 628 PCMCIABUSCF_SOCKET_DEFAULT && 629 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 630 return 0; 631 632 break; 633 default: 634 panic("unknown pcic socket"); 635 } 636 637 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 638 } 639 640 int 641 pcic_print(arg, pnp) 642 void *arg; 643 const char *pnp; 644 { 645 struct pcmciabus_attach_args *paa = arg; 646 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 647 648 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 649 if (pnp) 650 printf("pcmcia at %s", pnp); 651 652 switch (h->sock) { 653 case C0SA: 654 printf(" controller 0 socket 0"); 655 break; 656 case C0SB: 657 printf(" controller 0 socket 1"); 658 break; 659 case C1SA: 660 printf(" controller 1 socket 0"); 661 break; 662 case C1SB: 663 printf(" controller 1 socket 1"); 664 break; 665 default: 666 panic("unknown pcic socket"); 667 } 668 669 return (UNCONF); 670 } 671 672 int 673 pcic_intr(arg) 674 void *arg; 675 { 676 struct pcic_softc *sc = arg; 677 int i, ret = 0; 678 679 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 680 681 for (i = 0; i < PCIC_NSLOTS; i++) 682 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 683 ret += pcic_intr_socket(&sc->handle[i]); 684 685 return (ret ? 1 : 0); 686 } 687 688 int 689 pcic_intr_socket(h) 690 struct pcic_handle *h; 691 { 692 int cscreg; 693 694 cscreg = pcic_read(h, PCIC_CSC); 695 696 cscreg &= (PCIC_CSC_GPI | 697 PCIC_CSC_CD | 698 PCIC_CSC_READY | 699 PCIC_CSC_BATTWARN | 700 PCIC_CSC_BATTDEAD); 701 702 if (cscreg & PCIC_CSC_GPI) { 703 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 704 } 705 if (cscreg & PCIC_CSC_CD) { 706 int statreg; 707 708 statreg = pcic_read(h, PCIC_IF_STATUS); 709 710 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 711 statreg)); 712 713 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 714 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 715 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 716 DPRINTF(("%s: enqueing INSERTION event\n", 717 h->ph_parent->dv_xname)); 718 pcic_queue_event(h, PCIC_EVENT_INSERTION); 719 } 720 h->laststate = PCIC_LASTSTATE_PRESENT; 721 } else { 722 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 723 /* Deactivate the card now. */ 724 DPRINTF(("%s: deactivating card\n", 725 h->ph_parent->dv_xname)); 726 pcic_deactivate_card(h); 727 728 DPRINTF(("%s: enqueing REMOVAL event\n", 729 h->ph_parent->dv_xname)); 730 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 731 } 732 h->laststate = ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) 733 ? PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 734 } 735 } 736 if (cscreg & PCIC_CSC_READY) { 737 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 738 /* shouldn't happen */ 739 } 740 if (cscreg & PCIC_CSC_BATTWARN) { 741 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, h->sock)); 742 } 743 if (cscreg & PCIC_CSC_BATTDEAD) { 744 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, h->sock)); 745 } 746 return (cscreg ? 1 : 0); 747 } 748 749 void 750 pcic_queue_event(h, event) 751 struct pcic_handle *h; 752 int event; 753 { 754 struct pcic_event *pe; 755 int s; 756 757 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 758 if (pe == NULL) 759 panic("pcic_queue_event: can't allocate event"); 760 761 pe->pe_type = event; 762 s = splhigh(); 763 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 764 splx(s); 765 wakeup(&h->events); 766 } 767 768 void 769 pcic_attach_card(h) 770 struct pcic_handle *h; 771 { 772 773 if (!(h->flags & PCIC_FLAG_CARDP)) { 774 /* call the MI attach function */ 775 pcmcia_card_attach(h->pcmcia); 776 777 h->flags |= PCIC_FLAG_CARDP; 778 } else { 779 DPRINTF(("pcic_attach_card: already attached")); 780 } 781 } 782 783 void 784 pcic_detach_card(h, flags) 785 struct pcic_handle *h; 786 int flags; /* DETACH_* */ 787 { 788 789 if (h->flags & PCIC_FLAG_CARDP) { 790 h->flags &= ~PCIC_FLAG_CARDP; 791 792 /* call the MI detach function */ 793 pcmcia_card_detach(h->pcmcia, flags); 794 } else { 795 DPRINTF(("pcic_detach_card: already detached")); 796 } 797 } 798 799 void 800 pcic_deactivate_card(h) 801 struct pcic_handle *h; 802 { 803 804 /* call the MI deactivate function */ 805 pcmcia_card_deactivate(h->pcmcia); 806 807 /* power down the socket */ 808 pcic_write(h, PCIC_PWRCTL, 0); 809 810 /* reset the socket */ 811 pcic_write(h, PCIC_INTR, 0); 812 } 813 814 int 815 pcic_chip_mem_alloc(pch, size, pcmhp) 816 pcmcia_chipset_handle_t pch; 817 bus_size_t size; 818 struct pcmcia_mem_handle *pcmhp; 819 { 820 struct pcic_handle *h = (struct pcic_handle *) pch; 821 bus_space_handle_t memh; 822 bus_addr_t addr; 823 bus_size_t sizepg; 824 int i, mask, mhandle; 825 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 826 827 /* out of sc->memh, allocate as many pages as necessary */ 828 829 /* convert size to PCIC pages */ 830 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 831 if (sizepg > PCIC_MAX_MEM_PAGES) 832 return (1); 833 834 mask = (1 << sizepg) - 1; 835 836 addr = 0; /* XXX gcc -Wuninitialized */ 837 mhandle = 0; /* XXX gcc -Wuninitialized */ 838 839 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 840 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 841 if (bus_space_subregion(sc->memt, sc->memh, 842 i * PCIC_MEM_PAGESIZE, 843 sizepg * PCIC_MEM_PAGESIZE, &memh)) 844 return (1); 845 mhandle = mask << i; 846 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 847 sc->subregionmask &= ~(mhandle); 848 pcmhp->memt = sc->memt; 849 pcmhp->memh = memh; 850 pcmhp->addr = addr; 851 pcmhp->size = size; 852 pcmhp->mhandle = mhandle; 853 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 854 return (0); 855 } 856 } 857 858 return (1); 859 } 860 861 void 862 pcic_chip_mem_free(pch, pcmhp) 863 pcmcia_chipset_handle_t pch; 864 struct pcmcia_mem_handle *pcmhp; 865 { 866 struct pcic_handle *h = (struct pcic_handle *) pch; 867 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 868 869 sc->subregionmask |= pcmhp->mhandle; 870 } 871 872 static struct mem_map_index_st { 873 int sysmem_start_lsb; 874 int sysmem_start_msb; 875 int sysmem_stop_lsb; 876 int sysmem_stop_msb; 877 int cardmem_lsb; 878 int cardmem_msb; 879 int memenable; 880 } mem_map_index[] = { 881 { 882 PCIC_SYSMEM_ADDR0_START_LSB, 883 PCIC_SYSMEM_ADDR0_START_MSB, 884 PCIC_SYSMEM_ADDR0_STOP_LSB, 885 PCIC_SYSMEM_ADDR0_STOP_MSB, 886 PCIC_CARDMEM_ADDR0_LSB, 887 PCIC_CARDMEM_ADDR0_MSB, 888 PCIC_ADDRWIN_ENABLE_MEM0, 889 }, 890 { 891 PCIC_SYSMEM_ADDR1_START_LSB, 892 PCIC_SYSMEM_ADDR1_START_MSB, 893 PCIC_SYSMEM_ADDR1_STOP_LSB, 894 PCIC_SYSMEM_ADDR1_STOP_MSB, 895 PCIC_CARDMEM_ADDR1_LSB, 896 PCIC_CARDMEM_ADDR1_MSB, 897 PCIC_ADDRWIN_ENABLE_MEM1, 898 }, 899 { 900 PCIC_SYSMEM_ADDR2_START_LSB, 901 PCIC_SYSMEM_ADDR2_START_MSB, 902 PCIC_SYSMEM_ADDR2_STOP_LSB, 903 PCIC_SYSMEM_ADDR2_STOP_MSB, 904 PCIC_CARDMEM_ADDR2_LSB, 905 PCIC_CARDMEM_ADDR2_MSB, 906 PCIC_ADDRWIN_ENABLE_MEM2, 907 }, 908 { 909 PCIC_SYSMEM_ADDR3_START_LSB, 910 PCIC_SYSMEM_ADDR3_START_MSB, 911 PCIC_SYSMEM_ADDR3_STOP_LSB, 912 PCIC_SYSMEM_ADDR3_STOP_MSB, 913 PCIC_CARDMEM_ADDR3_LSB, 914 PCIC_CARDMEM_ADDR3_MSB, 915 PCIC_ADDRWIN_ENABLE_MEM3, 916 }, 917 { 918 PCIC_SYSMEM_ADDR4_START_LSB, 919 PCIC_SYSMEM_ADDR4_START_MSB, 920 PCIC_SYSMEM_ADDR4_STOP_LSB, 921 PCIC_SYSMEM_ADDR4_STOP_MSB, 922 PCIC_CARDMEM_ADDR4_LSB, 923 PCIC_CARDMEM_ADDR4_MSB, 924 PCIC_ADDRWIN_ENABLE_MEM4, 925 }, 926 }; 927 928 void 929 pcic_chip_do_mem_map(h, win) 930 struct pcic_handle *h; 931 int win; 932 { 933 int reg; 934 935 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 936 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 937 938 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 939 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 940 pcic_write(h, mem_map_index[win].sysmem_start_msb, 941 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 942 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 943 944 #if 0 945 /* XXX do I want 16 bit all the time? */ 946 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 947 #endif 948 949 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 950 ((h->mem[win].addr + h->mem[win].size) >> 951 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 952 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 953 (((h->mem[win].addr + h->mem[win].size) >> 954 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 955 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 956 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 957 958 pcic_write(h, mem_map_index[win].cardmem_lsb, 959 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 960 pcic_write(h, mem_map_index[win].cardmem_msb, 961 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 962 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 963 ((kind == PCMCIA_MEM_ATTR) ? 964 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 965 966 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 967 reg |= (mem_map_index[win].memenable | (mem8 ? 0 : PCIC_ADDRWIN_ENABLE_MEMCS16)); 968 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 969 970 delay(100); 971 972 #ifdef PCICDEBUG 973 { 974 int r1, r2, r3, r4, r5, r6; 975 976 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 977 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 978 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 979 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 980 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 981 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 982 983 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 984 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 985 } 986 #endif 987 } 988 989 int 990 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 991 pcmcia_chipset_handle_t pch; 992 int kind; 993 bus_addr_t card_addr; 994 bus_size_t size; 995 struct pcmcia_mem_handle *pcmhp; 996 bus_addr_t *offsetp; 997 int *windowp; 998 { 999 struct pcic_handle *h = (struct pcic_handle *) pch; 1000 bus_addr_t busaddr; 1001 long card_offset; 1002 int i, win; 1003 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1004 1005 win = -1; 1006 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1007 i++) { 1008 if ((h->memalloc & (1 << i)) == 0) { 1009 win = i; 1010 h->memalloc |= (1 << i); 1011 break; 1012 } 1013 } 1014 1015 if (win == -1) 1016 return (1); 1017 1018 *windowp = win; 1019 1020 /* XXX this is pretty gross */ 1021 1022 if (sc->memt != pcmhp->memt) 1023 panic("pcic_chip_mem_map memt is bogus"); 1024 1025 busaddr = pcmhp->addr; 1026 1027 /* 1028 * compute the address offset to the pcmcia address space for the 1029 * pcic. this is intentionally signed. The masks and shifts below 1030 * will cause TRT to happen in the pcic registers. Deal with making 1031 * sure the address is aligned, and return the alignment offset. 1032 */ 1033 1034 *offsetp = card_addr % PCIC_MEM_ALIGN; 1035 card_addr -= *offsetp; 1036 1037 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1038 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1039 (u_long) card_addr)); 1040 1041 /* 1042 * include the offset in the size, and decrement size by one, since 1043 * the hw wants start/stop 1044 */ 1045 size += *offsetp - 1; 1046 1047 card_offset = (((long) card_addr) - ((long) busaddr)); 1048 1049 h->mem[win].addr = busaddr; 1050 h->mem[win].size = size; 1051 h->mem[win].offset = card_offset; 1052 h->mem[win].kind = kind; 1053 1054 pcic_chip_do_mem_map(h, win); 1055 1056 return (0); 1057 } 1058 1059 void 1060 pcic_chip_mem_unmap(pch, window) 1061 pcmcia_chipset_handle_t pch; 1062 int window; 1063 { 1064 struct pcic_handle *h = (struct pcic_handle *) pch; 1065 int reg; 1066 1067 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1068 panic("pcic_chip_mem_unmap: window out of range"); 1069 1070 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1071 reg &= ~mem_map_index[window].memenable; 1072 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1073 1074 h->memalloc &= ~(1 << window); 1075 } 1076 1077 int 1078 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1079 pcmcia_chipset_handle_t pch; 1080 bus_addr_t start; 1081 bus_size_t size; 1082 bus_size_t align; 1083 struct pcmcia_io_handle *pcihp; 1084 { 1085 struct pcic_handle *h = (struct pcic_handle *) pch; 1086 bus_space_tag_t iot; 1087 bus_space_handle_t ioh; 1088 bus_addr_t ioaddr; 1089 int flags = 0; 1090 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1091 1092 /* 1093 * Allocate some arbitrary I/O space. 1094 */ 1095 1096 iot = sc->iot; 1097 1098 if (start) { 1099 ioaddr = start; 1100 if (bus_space_map(iot, start, size, 0, &ioh)) 1101 return (1); 1102 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1103 (u_long) ioaddr, (u_long) size)); 1104 } else { 1105 flags |= PCMCIA_IO_ALLOCATED; 1106 if (bus_space_alloc(iot, sc->iobase, 1107 sc->iobase + sc->iosize, size, align, 0, 0, 1108 &ioaddr, &ioh)) 1109 return (1); 1110 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1111 (u_long) ioaddr, (u_long) size)); 1112 } 1113 1114 pcihp->iot = iot; 1115 pcihp->ioh = ioh; 1116 pcihp->addr = ioaddr; 1117 pcihp->size = size; 1118 pcihp->flags = flags; 1119 1120 return (0); 1121 } 1122 1123 void 1124 pcic_chip_io_free(pch, pcihp) 1125 pcmcia_chipset_handle_t pch; 1126 struct pcmcia_io_handle *pcihp; 1127 { 1128 bus_space_tag_t iot = pcihp->iot; 1129 bus_space_handle_t ioh = pcihp->ioh; 1130 bus_size_t size = pcihp->size; 1131 1132 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1133 bus_space_free(iot, ioh, size); 1134 else 1135 bus_space_unmap(iot, ioh, size); 1136 } 1137 1138 1139 static struct io_map_index_st { 1140 int start_lsb; 1141 int start_msb; 1142 int stop_lsb; 1143 int stop_msb; 1144 int ioenable; 1145 int ioctlmask; 1146 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1147 } io_map_index[] = { 1148 { 1149 PCIC_IOADDR0_START_LSB, 1150 PCIC_IOADDR0_START_MSB, 1151 PCIC_IOADDR0_STOP_LSB, 1152 PCIC_IOADDR0_STOP_MSB, 1153 PCIC_ADDRWIN_ENABLE_IO0, 1154 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1155 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1156 { 1157 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1158 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1159 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1160 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1161 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1162 }, 1163 }, 1164 { 1165 PCIC_IOADDR1_START_LSB, 1166 PCIC_IOADDR1_START_MSB, 1167 PCIC_IOADDR1_STOP_LSB, 1168 PCIC_IOADDR1_STOP_MSB, 1169 PCIC_ADDRWIN_ENABLE_IO1, 1170 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1171 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1172 { 1173 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1174 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1175 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1176 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1177 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1178 }, 1179 }, 1180 }; 1181 1182 void 1183 pcic_chip_do_io_map(h, win) 1184 struct pcic_handle *h; 1185 int win; 1186 { 1187 int reg; 1188 1189 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1190 win, (long) h->io[win].addr, (long) h->io[win].size, 1191 h->io[win].width * 8)); 1192 1193 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1194 pcic_write(h, io_map_index[win].start_msb, 1195 (h->io[win].addr >> 8) & 0xff); 1196 1197 pcic_write(h, io_map_index[win].stop_lsb, 1198 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1199 pcic_write(h, io_map_index[win].stop_msb, 1200 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1201 1202 reg = pcic_read(h, PCIC_IOCTL); 1203 reg &= ~io_map_index[win].ioctlmask; 1204 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1205 pcic_write(h, PCIC_IOCTL, reg); 1206 1207 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1208 reg |= io_map_index[win].ioenable; 1209 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1210 } 1211 1212 int 1213 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1214 pcmcia_chipset_handle_t pch; 1215 int width; 1216 bus_addr_t offset; 1217 bus_size_t size; 1218 struct pcmcia_io_handle *pcihp; 1219 int *windowp; 1220 { 1221 struct pcic_handle *h = (struct pcic_handle *) pch; 1222 bus_addr_t ioaddr = pcihp->addr + offset; 1223 int i, win; 1224 #ifdef PCICDEBUG 1225 static char *width_names[] = { "auto", "io8", "io16" }; 1226 #endif 1227 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 1228 1229 /* XXX Sanity check offset/size. */ 1230 1231 win = -1; 1232 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1233 if ((h->ioalloc & (1 << i)) == 0) { 1234 win = i; 1235 h->ioalloc |= (1 << i); 1236 break; 1237 } 1238 } 1239 1240 if (win == -1) 1241 return (1); 1242 1243 *windowp = win; 1244 1245 /* XXX this is pretty gross */ 1246 1247 if (sc->iot != pcihp->iot) 1248 panic("pcic_chip_io_map iot is bogus"); 1249 1250 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1251 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1252 1253 /* XXX wtf is this doing here? */ 1254 1255 printf(" port 0x%lx", (u_long) ioaddr); 1256 if (size > 1) 1257 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1258 1259 h->io[win].addr = ioaddr; 1260 h->io[win].size = size; 1261 h->io[win].width = width; 1262 1263 pcic_chip_do_io_map(h, win); 1264 1265 return (0); 1266 } 1267 1268 void 1269 pcic_chip_io_unmap(pch, window) 1270 pcmcia_chipset_handle_t pch; 1271 int window; 1272 { 1273 struct pcic_handle *h = (struct pcic_handle *) pch; 1274 int reg; 1275 1276 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1277 panic("pcic_chip_io_unmap: window out of range"); 1278 1279 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1280 reg &= ~io_map_index[window].ioenable; 1281 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1282 1283 h->ioalloc &= ~(1 << window); 1284 } 1285 1286 static void 1287 pcic_wait_ready(h) 1288 struct pcic_handle *h; 1289 { 1290 int i; 1291 1292 for (i = 0; i < 10000; i++) { 1293 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1294 return; 1295 delay(500); 1296 #ifdef PCICDEBUG 1297 if (pcic_debug) { 1298 if ((i>5000) && (i%100 == 99)) 1299 printf("."); 1300 } 1301 #endif 1302 } 1303 1304 #ifdef DIAGNOSTIC 1305 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1306 pcic_read(h, PCIC_IF_STATUS)); 1307 #endif 1308 } 1309 1310 void 1311 pcic_chip_socket_enable(pch) 1312 pcmcia_chipset_handle_t pch; 1313 { 1314 struct pcic_handle *h = (struct pcic_handle *) pch; 1315 int cardtype, reg, win; 1316 1317 /* this bit is mostly stolen from pcic_attach_card */ 1318 1319 /* power down the socket to reset it, clear the card reset pin */ 1320 1321 pcic_write(h, PCIC_PWRCTL, 0); 1322 1323 /* 1324 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1325 * we are changing Vcc (Toff). 1326 */ 1327 delay((300 + 100) * 1000); 1328 1329 #ifdef VADEM_POWER_HACK 1330 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1331 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1332 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1333 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1334 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1335 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1336 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1337 #endif 1338 1339 /* power up the socket */ 1340 1341 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1342 | PCIC_PWRCTL_PWR_ENABLE); 1343 1344 /* 1345 * wait 100ms until power raise (Tpr) and 20ms to become 1346 * stable (Tsu(Vcc)). 1347 * 1348 * some machines require some more time to be settled 1349 * (300ms is added here). 1350 */ 1351 delay((100 + 20 + 300) * 1000); 1352 1353 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1354 | PCIC_PWRCTL_PWR_ENABLE); 1355 pcic_write(h, PCIC_INTR, 0); 1356 1357 /* 1358 * hold RESET at least 10us. 1359 */ 1360 delay(10); 1361 1362 /* clear the reset flag */ 1363 1364 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1365 1366 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1367 1368 delay(20000); 1369 1370 /* wait for the chip to finish initializing */ 1371 1372 #ifdef DIAGNOSTIC 1373 reg = pcic_read(h, PCIC_IF_STATUS); 1374 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1375 printf("pcic_chip_socket_enable: status %x", reg); 1376 } 1377 #endif 1378 1379 pcic_wait_ready(h); 1380 1381 /* zero out the address windows */ 1382 1383 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1384 1385 /* set the card type */ 1386 1387 cardtype = pcmcia_card_gettype(h->pcmcia); 1388 1389 reg = pcic_read(h, PCIC_INTR); 1390 reg &= ~(PCIC_INTR_CARDTYPE_MASK | PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1391 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1392 PCIC_INTR_CARDTYPE_IO : 1393 PCIC_INTR_CARDTYPE_MEM); 1394 reg |= h->ih_irq; 1395 pcic_write(h, PCIC_INTR, reg); 1396 1397 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1398 h->ph_parent->dv_xname, h->sock, 1399 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1400 1401 /* reinstall all the memory and io mappings */ 1402 1403 for (win = 0; win < PCIC_MEM_WINS; win++) 1404 if (h->memalloc & (1 << win)) 1405 pcic_chip_do_mem_map(h, win); 1406 1407 for (win = 0; win < PCIC_IO_WINS; win++) 1408 if (h->ioalloc & (1 << win)) 1409 pcic_chip_do_io_map(h, win); 1410 } 1411 1412 void 1413 pcic_chip_socket_disable(pch) 1414 pcmcia_chipset_handle_t pch; 1415 { 1416 struct pcic_handle *h = (struct pcic_handle *) pch; 1417 1418 DPRINTF(("pcic_chip_socket_disable\n")); 1419 1420 /* power down the socket */ 1421 1422 pcic_write(h, PCIC_PWRCTL, 0); 1423 1424 /* 1425 * wait 300ms until power fails (Tpf). 1426 */ 1427 delay(300 * 1000); 1428 } 1429 1430 static u_int8_t 1431 st_pcic_read(h, idx) 1432 struct pcic_handle *h; 1433 int idx; 1434 { 1435 if (idx != -1) 1436 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1437 h->sock + idx); 1438 1439 return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA); 1440 } 1441 1442 static void 1443 st_pcic_write(h, idx, data) 1444 struct pcic_handle *h; 1445 int idx; 1446 u_int8_t data; 1447 { 1448 if (idx != -1) 1449 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1450 h->sock + idx); 1451 1452 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1453 } 1454
Indexes created Mon Sep 29 21:09:56 GMT 2025