i82365.c revision 1.3
1 /* $NetBSD: i82365.c,v 1.3 1997/10/17 07:59:39 enami Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 41 #include <vm/vm.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/i82365reg.h> 50 #include <dev/ic/i82365var.h> 51 52 #ifdef PCICDEBUG 53 int pcic_debug = 0; 54 #define DPRINTF(arg) if (pcic_debug) printf arg; 55 #else 56 #define DPRINTF(arg) 57 #endif 58 59 #define PCIC_VENDOR_UNKNOWN 0 60 #define PCIC_VENDOR_I82365SLR0 1 61 #define PCIC_VENDOR_I82365SLR1 2 62 #define PCIC_VENDOR_CIRRUS_PD6710 3 63 #define PCIC_VENDOR_CIRRUS_PD672X 4 64 65 /* 66 * Individual drivers will allocate their own memory and io regions. Memory 67 * regions must be a multiple of 4k, aligned on a 4k boundary. 68 */ 69 70 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 71 72 void pcic_attach_socket __P((struct pcic_handle *)); 73 void pcic_init_socket __P((struct pcic_handle *)); 74 75 #ifdef __BROKEN_INDIRECT_CONFIG 76 int pcic_submatch __P((struct device *, void *, void *)); 77 #else 78 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 79 #endif 80 int pcic_print __P((void *arg, const char *pnp)); 81 int pcic_intr_socket __P((struct pcic_handle *)); 82 83 void pcic_attach_card __P((struct pcic_handle *)); 84 void pcic_detach_card __P((struct pcic_handle *)); 85 86 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 87 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 88 89 struct cfdriver pcic_cd = { 90 NULL, "pcic", DV_DULL 91 }; 92 93 int 94 pcic_ident_ok(ident) 95 int ident; 96 { 97 /* this is very empirical and heuristic */ 98 99 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 100 return (0); 101 102 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 103 #ifdef DIAGNOSTIC 104 printf("pcic: does not support memory and I/O cards, " 105 "ignored (ident=%0x)\n", ident); 106 #endif 107 return (0); 108 } 109 return (1); 110 } 111 112 int 113 pcic_vendor(h) 114 struct pcic_handle *h; 115 { 116 int reg; 117 118 /* 119 * the chip_id of the cirrus toggles between 11 and 00 after a write. 120 * weird. 121 */ 122 123 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 124 reg = pcic_read(h, -1); 125 126 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 127 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 128 reg = pcic_read(h, -1); 129 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 130 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 131 return (PCIC_VENDOR_CIRRUS_PD672X); 132 else 133 return (PCIC_VENDOR_CIRRUS_PD6710); 134 } 135 } 136 /* XXX how do I identify the GD6729? */ 137 138 reg = pcic_read(h, PCIC_IDENT); 139 140 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 141 return (PCIC_VENDOR_I82365SLR0); 142 else 143 return (PCIC_VENDOR_I82365SLR1); 144 145 return (PCIC_VENDOR_UNKNOWN); 146 } 147 148 char * 149 pcic_vendor_to_string(vendor) 150 int vendor; 151 { 152 switch (vendor) { 153 case PCIC_VENDOR_I82365SLR0: 154 return ("Intel 82365SL Revision 0"); 155 case PCIC_VENDOR_I82365SLR1: 156 return ("Intel 82365SL Revision 1"); 157 case PCIC_VENDOR_CIRRUS_PD6710: 158 return ("Cirrus PD6710"); 159 case PCIC_VENDOR_CIRRUS_PD672X: 160 return ("Cirrus PD672X"); 161 } 162 163 return ("Unknown controller"); 164 } 165 166 void 167 pcic_attach(sc) 168 struct pcic_softc *sc; 169 { 170 int vendor, count, i, reg; 171 172 /* now check for each controller/socket */ 173 174 /* 175 * this could be done with a loop, but it would violate the 176 * abstraction 177 */ 178 179 count = 0; 180 181 DPRINTF(("pcic ident regs:")); 182 183 sc->handle[0].sc = sc; 184 sc->handle[0].sock = C0SA; 185 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 186 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 187 count++; 188 } else { 189 sc->handle[0].flags = 0; 190 } 191 192 DPRINTF((" 0x%02x", reg)); 193 194 sc->handle[1].sc = sc; 195 sc->handle[1].sock = C0SB; 196 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 197 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 198 count++; 199 } else { 200 sc->handle[1].flags = 0; 201 } 202 203 DPRINTF((" 0x%02x", reg)); 204 205 sc->handle[2].sc = sc; 206 sc->handle[2].sock = C1SA; 207 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], PCIC_IDENT))) { 208 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 209 count++; 210 } else { 211 sc->handle[2].flags = 0; 212 } 213 214 DPRINTF((" 0x%02x", reg)); 215 216 sc->handle[3].sc = sc; 217 sc->handle[3].sock = C1SB; 218 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], PCIC_IDENT))) { 219 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 220 count++; 221 } else { 222 sc->handle[3].flags = 0; 223 } 224 225 DPRINTF((" 0x%02x\n", reg)); 226 227 if (count == 0) 228 panic("pcic_attach: attach found no sockets"); 229 230 /* establish the interrupt */ 231 232 /* XXX block interrupts? */ 233 234 for (i = 0; i < PCIC_NSLOTS; i++) { 235 #if 0 236 /* 237 * this should work, but w/o it, setting tty flags hangs at 238 * boot time. 239 */ 240 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 241 #endif 242 { 243 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 244 pcic_read(&sc->handle[i], PCIC_CSC); 245 } 246 } 247 248 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 249 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 250 vendor = pcic_vendor(&sc->handle[0]); 251 252 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 253 pcic_vendor_to_string(vendor)); 254 255 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 256 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 257 printf("sockets A and B\n"); 258 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 259 printf("socket A only\n"); 260 else 261 printf("socket B only\n"); 262 263 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 264 sc->handle[0].vendor = vendor; 265 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 266 sc->handle[1].vendor = vendor; 267 } 268 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 269 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 270 vendor = pcic_vendor(&sc->handle[2]); 271 272 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 273 pcic_vendor_to_string(vendor)); 274 275 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 276 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 277 printf("sockets A and B\n"); 278 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 279 printf("socket A only\n"); 280 else 281 printf("socket B only\n"); 282 283 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 284 sc->handle[2].vendor = vendor; 285 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 286 sc->handle[3].vendor = vendor; 287 } 288 } 289 290 void 291 pcic_attach_sockets(sc) 292 struct pcic_softc *sc; 293 { 294 int i; 295 296 for (i = 0; i < PCIC_NSLOTS; i++) 297 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 298 pcic_attach_socket(&sc->handle[i]); 299 } 300 301 void 302 pcic_attach_socket(h) 303 struct pcic_handle *h; 304 { 305 struct pcmciabus_attach_args paa; 306 307 /* initialize the rest of the handle */ 308 309 h->memalloc = 0; 310 h->ioalloc = 0; 311 h->ih_irq = 0; 312 313 /* now, config one pcmcia device per socket */ 314 315 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 316 paa.pch = (pcmcia_chipset_handle_t) h; 317 paa.iobase = h->sc->iobase; 318 paa.iosize = h->sc->iosize; 319 320 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 321 pcic_submatch); 322 323 /* if there's actually a pcmcia device attached, initialize the slot */ 324 325 if (h->pcmcia) 326 pcic_init_socket(h); 327 } 328 329 void 330 pcic_init_socket(h) 331 struct pcic_handle *h; 332 { 333 int reg; 334 335 /* set up the card to interrupt on card detect */ 336 337 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 338 PCIC_CSC_INTR_CD_ENABLE); 339 pcic_write(h, PCIC_INTR, 0); 340 pcic_read(h, PCIC_CSC); 341 342 /* unsleep the cirrus controller */ 343 344 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 345 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 346 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 347 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 348 DPRINTF(("%s: socket %02x was suspended\n", 349 h->sc->dev.dv_xname, h->sock)); 350 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 351 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 352 } 353 } 354 /* if there's a card there, then attach it. */ 355 356 reg = pcic_read(h, PCIC_IF_STATUS); 357 358 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 359 PCIC_IF_STATUS_CARDDETECT_PRESENT) 360 pcic_attach_card(h); 361 } 362 363 int 364 #ifdef __BROKEN_INDIRECT_CONFIG 365 pcic_submatch(parent, match, aux) 366 #else 367 pcic_submatch(parent, cf, aux) 368 #endif 369 struct device *parent; 370 #ifdef __BROKEN_INDIRECT_CONFIG 371 void *match; 372 #else 373 struct cfdata *cf; 374 #endif 375 void *aux; 376 { 377 #ifdef __BROKEN_INDIRECT_CONFIG 378 struct cfdata *cf = match; 379 #endif 380 381 struct pcmciabus_attach_args *paa = aux; 382 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 383 384 switch (h->sock) { 385 case C0SA: 386 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 0) 387 return 0; 388 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 0) 389 return 0; 390 391 break; 392 case C0SB: 393 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 0) 394 return 0; 395 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 1) 396 return 0; 397 398 break; 399 case C1SA: 400 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 1) 401 return 0; 402 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 0) 403 return 0; 404 405 break; 406 case C1SB: 407 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != 1) 408 return 0; 409 if (cf->cf_loc[1] != -1 && cf->cf_loc[1] != 1) 410 return 0; 411 412 break; 413 default: 414 panic("unknown pcic socket"); 415 } 416 417 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 418 } 419 420 int 421 pcic_print(arg, pnp) 422 void *arg; 423 const char *pnp; 424 { 425 struct pcmciabus_attach_args *paa = arg; 426 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 427 428 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 429 if (pnp) 430 printf("pcmcia at %s", pnp); 431 432 switch (h->sock) { 433 case C0SA: 434 printf(" controller 0 socket 0"); 435 break; 436 case C0SB: 437 printf(" controller 0 socket 1"); 438 break; 439 case C1SA: 440 printf(" controller 1 socket 0"); 441 break; 442 case C1SB: 443 printf(" controller 1 socket 1"); 444 break; 445 default: 446 panic("unknown pcic socket"); 447 } 448 449 return (UNCONF); 450 } 451 452 int 453 pcic_intr(arg) 454 void *arg; 455 { 456 struct pcic_softc *sc = arg; 457 int i, ret = 0; 458 459 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 460 461 for (i = 0; i < PCIC_NSLOTS; i++) 462 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 463 ret += pcic_intr_socket(&sc->handle[i]); 464 465 return (ret ? 1 : 0); 466 } 467 468 int 469 pcic_intr_socket(h) 470 struct pcic_handle *h; 471 { 472 int cscreg; 473 474 cscreg = pcic_read(h, PCIC_CSC); 475 476 cscreg &= (PCIC_CSC_GPI | 477 PCIC_CSC_CD | 478 PCIC_CSC_READY | 479 PCIC_CSC_BATTWARN | 480 PCIC_CSC_BATTDEAD); 481 482 if (cscreg & PCIC_CSC_GPI) { 483 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 484 } 485 if (cscreg & PCIC_CSC_CD) { 486 int statreg; 487 488 statreg = pcic_read(h, PCIC_IF_STATUS); 489 490 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 491 statreg)); 492 493 /* 494 * XXX This should probably schedule something to happen 495 * after the interrupt handler completes 496 */ 497 498 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 499 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 500 if (!(h->flags & PCIC_FLAG_CARDP)) 501 pcic_attach_card(h); 502 } else { 503 if (h->flags & PCIC_FLAG_CARDP) 504 pcic_detach_card(h); 505 } 506 } 507 if (cscreg & PCIC_CSC_READY) { 508 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 509 /* shouldn't happen */ 510 } 511 if (cscreg & PCIC_CSC_BATTWARN) { 512 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 513 } 514 if (cscreg & PCIC_CSC_BATTDEAD) { 515 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 516 } 517 return (cscreg ? 1 : 0); 518 } 519 520 void 521 pcic_attach_card(h) 522 struct pcic_handle *h; 523 { 524 if (h->flags & PCIC_FLAG_CARDP) 525 panic("pcic_attach_card: already attached"); 526 527 /* call the MI attach function */ 528 529 pcmcia_card_attach(h->pcmcia); 530 531 h->flags |= PCIC_FLAG_CARDP; 532 } 533 534 void 535 pcic_detach_card(h) 536 struct pcic_handle *h; 537 { 538 if (!(h->flags & PCIC_FLAG_CARDP)) 539 panic("pcic_attach_card: already detached"); 540 541 h->flags &= ~PCIC_FLAG_CARDP; 542 543 /* call the MI attach function */ 544 545 pcmcia_card_detach(h->pcmcia); 546 547 /* disable card detect resume and configuration reset */ 548 549 /* power down the socket */ 550 551 pcic_write(h, PCIC_PWRCTL, 0); 552 553 /* reset the card */ 554 555 pcic_write(h, PCIC_INTR, 0); 556 } 557 558 int 559 pcic_chip_mem_alloc(pch, size, pcmhp) 560 pcmcia_chipset_handle_t pch; 561 bus_size_t size; 562 struct pcmcia_mem_handle *pcmhp; 563 { 564 struct pcic_handle *h = (struct pcic_handle *) pch; 565 bus_space_handle_t memh; 566 bus_addr_t addr; 567 bus_size_t sizepg; 568 int i, mask, mhandle; 569 570 /* out of sc->memh, allocate as many pages as necessary */ 571 572 /* convert size to PCIC pages */ 573 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 574 575 mask = (1 << sizepg) - 1; 576 577 addr = 0; /* XXX gcc -Wuninitialized */ 578 mhandle = 0; /* XXX gcc -Wuninitialized */ 579 580 for (i = 0; i < (PCIC_MEM_PAGES + 1 - sizepg); i++) { 581 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 582 if (bus_space_subregion(h->sc->memt, h->sc->memh, 583 i * PCIC_MEM_PAGESIZE, 584 sizepg * PCIC_MEM_PAGESIZE, &memh)) 585 return (1); 586 mhandle = mask << i; 587 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 588 h->sc->subregionmask &= ~(mhandle); 589 break; 590 } 591 } 592 593 if (i == (PCIC_MEM_PAGES + 1 - size)) 594 return (1); 595 596 DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 597 (u_long) size)); 598 599 pcmhp->memt = h->sc->memt; 600 pcmhp->memh = memh; 601 pcmhp->addr = addr; 602 pcmhp->size = size; 603 pcmhp->mhandle = mhandle; 604 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 605 606 return (0); 607 } 608 609 void 610 pcic_chip_mem_free(pch, pcmhp) 611 pcmcia_chipset_handle_t pch; 612 struct pcmcia_mem_handle *pcmhp; 613 { 614 struct pcic_handle *h = (struct pcic_handle *) pch; 615 616 h->sc->subregionmask |= pcmhp->mhandle; 617 } 618 619 static struct mem_map_index_st { 620 int sysmem_start_lsb; 621 int sysmem_start_msb; 622 int sysmem_stop_lsb; 623 int sysmem_stop_msb; 624 int cardmem_lsb; 625 int cardmem_msb; 626 int memenable; 627 } mem_map_index[] = { 628 { 629 PCIC_SYSMEM_ADDR0_START_LSB, 630 PCIC_SYSMEM_ADDR0_START_MSB, 631 PCIC_SYSMEM_ADDR0_STOP_LSB, 632 PCIC_SYSMEM_ADDR0_STOP_MSB, 633 PCIC_CARDMEM_ADDR0_LSB, 634 PCIC_CARDMEM_ADDR0_MSB, 635 PCIC_ADDRWIN_ENABLE_MEM0, 636 }, 637 { 638 PCIC_SYSMEM_ADDR1_START_LSB, 639 PCIC_SYSMEM_ADDR1_START_MSB, 640 PCIC_SYSMEM_ADDR1_STOP_LSB, 641 PCIC_SYSMEM_ADDR1_STOP_MSB, 642 PCIC_CARDMEM_ADDR1_LSB, 643 PCIC_CARDMEM_ADDR1_MSB, 644 PCIC_ADDRWIN_ENABLE_MEM1, 645 }, 646 { 647 PCIC_SYSMEM_ADDR2_START_LSB, 648 PCIC_SYSMEM_ADDR2_START_MSB, 649 PCIC_SYSMEM_ADDR2_STOP_LSB, 650 PCIC_SYSMEM_ADDR2_STOP_MSB, 651 PCIC_CARDMEM_ADDR2_LSB, 652 PCIC_CARDMEM_ADDR2_MSB, 653 PCIC_ADDRWIN_ENABLE_MEM2, 654 }, 655 { 656 PCIC_SYSMEM_ADDR3_START_LSB, 657 PCIC_SYSMEM_ADDR3_START_MSB, 658 PCIC_SYSMEM_ADDR3_STOP_LSB, 659 PCIC_SYSMEM_ADDR3_STOP_MSB, 660 PCIC_CARDMEM_ADDR3_LSB, 661 PCIC_CARDMEM_ADDR3_MSB, 662 PCIC_ADDRWIN_ENABLE_MEM3, 663 }, 664 { 665 PCIC_SYSMEM_ADDR4_START_LSB, 666 PCIC_SYSMEM_ADDR4_START_MSB, 667 PCIC_SYSMEM_ADDR4_STOP_LSB, 668 PCIC_SYSMEM_ADDR4_STOP_MSB, 669 PCIC_CARDMEM_ADDR4_LSB, 670 PCIC_CARDMEM_ADDR4_MSB, 671 PCIC_ADDRWIN_ENABLE_MEM4, 672 }, 673 }; 674 675 void 676 pcic_chip_do_mem_map(h, win) 677 struct pcic_handle *h; 678 int win; 679 { 680 int reg; 681 682 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 683 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 684 pcic_write(h, mem_map_index[win].sysmem_start_msb, 685 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 686 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 687 688 #if 0 689 /* XXX do I want 16 bit all the time? */ 690 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 691 #endif 692 693 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 694 ((h->mem[win].addr + h->mem[win].size) >> 695 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 696 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 697 (((h->mem[win].addr + h->mem[win].size) >> 698 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 699 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 700 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 701 702 pcic_write(h, mem_map_index[win].cardmem_lsb, 703 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 704 pcic_write(h, mem_map_index[win].cardmem_msb, 705 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 706 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 707 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 708 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 709 710 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 711 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 712 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 713 714 #ifdef PCICDEBUG 715 { 716 int r1, r2, r3, r4, r5, r6; 717 718 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 719 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 720 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 721 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 722 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 723 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 724 725 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 726 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 727 } 728 #endif 729 } 730 731 int 732 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 733 pcmcia_chipset_handle_t pch; 734 int kind; 735 bus_addr_t card_addr; 736 bus_size_t size; 737 struct pcmcia_mem_handle *pcmhp; 738 bus_addr_t *offsetp; 739 int *windowp; 740 { 741 struct pcic_handle *h = (struct pcic_handle *) pch; 742 bus_addr_t busaddr; 743 long card_offset; 744 int i, win; 745 746 win = -1; 747 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 748 i++) { 749 if ((h->memalloc & (1 << i)) == 0) { 750 win = i; 751 h->memalloc |= (1 << i); 752 break; 753 } 754 } 755 756 if (win == -1) 757 return (1); 758 759 *windowp = win; 760 761 /* XXX this is pretty gross */ 762 763 if (h->sc->memt != pcmhp->memt) 764 panic("pcic_chip_mem_map memt is bogus"); 765 766 busaddr = pcmhp->addr; 767 768 /* 769 * compute the address offset to the pcmcia address space for the 770 * pcic. this is intentionally signed. The masks and shifts below 771 * will cause TRT to happen in the pcic registers. Deal with making 772 * sure the address is aligned, and return the alignment offset. 773 */ 774 775 *offsetp = card_addr % PCIC_MEM_ALIGN; 776 card_addr -= *offsetp; 777 778 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 779 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 780 (u_long) card_addr)); 781 782 /* 783 * include the offset in the size, and decrement size by one, since 784 * the hw wants start/stop 785 */ 786 size += *offsetp - 1; 787 788 card_offset = (((long) card_addr) - ((long) busaddr)); 789 790 h->mem[win].addr = busaddr; 791 h->mem[win].size = size; 792 h->mem[win].offset = card_offset; 793 h->mem[win].kind = kind; 794 795 pcic_chip_do_mem_map(h, win); 796 797 return (0); 798 } 799 800 void 801 pcic_chip_mem_unmap(pch, window) 802 pcmcia_chipset_handle_t pch; 803 int window; 804 { 805 struct pcic_handle *h = (struct pcic_handle *) pch; 806 int reg; 807 808 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 809 panic("pcic_chip_mem_unmap: window out of range"); 810 811 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 812 reg &= ~mem_map_index[window].memenable; 813 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 814 815 h->memalloc &= ~(1 << window); 816 } 817 818 int 819 pcic_chip_io_alloc(pch, start, size, align, pcihp) 820 pcmcia_chipset_handle_t pch; 821 bus_addr_t start; 822 bus_size_t size; 823 bus_size_t align; 824 struct pcmcia_io_handle *pcihp; 825 { 826 struct pcic_handle *h = (struct pcic_handle *) pch; 827 bus_space_tag_t iot; 828 bus_space_handle_t ioh; 829 bus_addr_t ioaddr; 830 int flags = 0; 831 832 /* 833 * Allocate some arbitrary I/O space. 834 */ 835 836 iot = h->sc->iot; 837 838 if (start) { 839 ioaddr = start; 840 if (bus_space_map(iot, start, size, 0, &ioh)) 841 return (1); 842 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 843 (u_long) ioaddr, (u_long) size)); 844 } else { 845 flags |= PCMCIA_IO_ALLOCATED; 846 if (bus_space_alloc(iot, h->sc->iobase, 847 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 848 &ioaddr, &ioh)) 849 return (1); 850 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 851 (u_long) ioaddr, (u_long) size)); 852 } 853 854 pcihp->iot = iot; 855 pcihp->ioh = ioh; 856 pcihp->addr = ioaddr; 857 pcihp->size = size; 858 pcihp->flags = flags; 859 860 return (0); 861 } 862 863 void 864 pcic_chip_io_free(pch, pcihp) 865 pcmcia_chipset_handle_t pch; 866 struct pcmcia_io_handle *pcihp; 867 { 868 bus_space_tag_t iot = pcihp->iot; 869 bus_space_handle_t ioh = pcihp->ioh; 870 bus_size_t size = pcihp->size; 871 872 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 873 bus_space_free(iot, ioh, size); 874 else 875 bus_space_unmap(iot, ioh, size); 876 } 877 878 879 static struct io_map_index_st { 880 int start_lsb; 881 int start_msb; 882 int stop_lsb; 883 int stop_msb; 884 int ioenable; 885 int ioctlmask; 886 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 887 } io_map_index[] = { 888 { 889 PCIC_IOADDR0_START_LSB, 890 PCIC_IOADDR0_START_MSB, 891 PCIC_IOADDR0_STOP_LSB, 892 PCIC_IOADDR0_STOP_MSB, 893 PCIC_ADDRWIN_ENABLE_IO0, 894 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 895 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 896 { 897 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 898 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 899 | PCIC_IOCTL_IO0_DATASIZE_8BIT, 900 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 901 | PCIC_IOCTL_IO0_DATASIZE_16BIT, 902 }, 903 }, 904 { 905 PCIC_IOADDR1_START_LSB, 906 PCIC_IOADDR1_START_MSB, 907 PCIC_IOADDR1_STOP_LSB, 908 PCIC_IOADDR1_STOP_MSB, 909 PCIC_ADDRWIN_ENABLE_IO1, 910 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 911 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 912 { 913 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 914 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 915 PCIC_IOCTL_IO1_DATASIZE_8BIT, 916 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 917 PCIC_IOCTL_IO1_DATASIZE_16BIT, 918 }, 919 }, 920 }; 921 922 void 923 pcic_chip_do_io_map(h, win) 924 struct pcic_handle *h; 925 int win; 926 { 927 int reg; 928 929 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 930 win, (long) h->io[win].addr, (long) h->io[win].size, 931 h->io[win].width * 8)); 932 933 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 934 pcic_write(h, io_map_index[win].start_msb, 935 (h->io[win].addr >> 8) & 0xff); 936 937 pcic_write(h, io_map_index[win].stop_lsb, 938 (h->io[win].addr + h->io[win].size - 1) & 0xff); 939 pcic_write(h, io_map_index[win].stop_msb, 940 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 941 942 reg = pcic_read(h, PCIC_IOCTL); 943 reg &= ~io_map_index[win].ioctlmask; 944 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 945 pcic_write(h, PCIC_IOCTL, reg); 946 947 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 948 reg |= io_map_index[win].ioenable; 949 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 950 } 951 952 int 953 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 954 pcmcia_chipset_handle_t pch; 955 int width; 956 bus_addr_t offset; 957 bus_size_t size; 958 struct pcmcia_io_handle *pcihp; 959 int *windowp; 960 { 961 struct pcic_handle *h = (struct pcic_handle *) pch; 962 bus_addr_t ioaddr = pcihp->addr + offset; 963 static char *width_names[] = { "auto", "io8", "io16" }; 964 int i, win; 965 966 /* XXX Sanity check offset/size. */ 967 968 win = -1; 969 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 970 if ((h->ioalloc & (1 << i)) == 0) { 971 win = i; 972 h->ioalloc |= (1 << i); 973 break; 974 } 975 } 976 977 if (win == -1) 978 return (1); 979 980 *windowp = win; 981 982 /* XXX this is pretty gross */ 983 984 if (h->sc->iot != pcihp->iot) 985 panic("pcic_chip_io_map iot is bogus"); 986 987 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 988 win, width_names[width], (u_long) ioaddr, (u_long) size)); 989 990 /* XXX wtf is this doing here? */ 991 992 printf(" port 0x%lx", (u_long) ioaddr); 993 if (size > 1) 994 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 995 996 h->io[win].addr = ioaddr; 997 h->io[win].size = size; 998 h->io[win].width = width; 999 1000 pcic_chip_do_io_map(h, win); 1001 1002 return (0); 1003 } 1004 1005 void 1006 pcic_chip_io_unmap(pch, window) 1007 pcmcia_chipset_handle_t pch; 1008 int window; 1009 { 1010 struct pcic_handle *h = (struct pcic_handle *) pch; 1011 int reg; 1012 1013 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1014 panic("pcic_chip_io_unmap: window out of range"); 1015 1016 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1017 reg &= ~io_map_index[window].ioenable; 1018 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1019 1020 h->ioalloc &= ~(1 << window); 1021 } 1022 1023 void 1024 pcic_chip_socket_enable(pch) 1025 pcmcia_chipset_handle_t pch; 1026 { 1027 struct pcic_handle *h = (struct pcic_handle *) pch; 1028 int cardtype, reg, win; 1029 1030 /* this bit is mostly stolen from pcic_attach_card */ 1031 1032 /* power down the socket to reset it, clear the card reset pin */ 1033 1034 pcic_write(h, PCIC_PWRCTL, 0); 1035 1036 /* power up the socket */ 1037 1038 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_PWR_ENABLE); 1039 delay(10000); 1040 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_OE); 1041 1042 /* clear the reset flag */ 1043 1044 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1045 1046 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1047 1048 delay(20000); 1049 1050 /* wait for the chip to finish initializing */ 1051 1052 pcic_wait_ready(h); 1053 1054 /* zero out the address windows */ 1055 1056 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1057 1058 /* set the card type */ 1059 1060 cardtype = pcmcia_card_gettype(h->pcmcia); 1061 1062 reg = pcic_read(h, PCIC_INTR); 1063 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1064 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1065 PCIC_INTR_CARDTYPE_IO : 1066 PCIC_INTR_CARDTYPE_MEM); 1067 reg |= h->ih_irq; 1068 pcic_write(h, PCIC_INTR, reg); 1069 1070 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1071 h->sc->dev.dv_xname, h->sock, 1072 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1073 1074 /* reinstall all the memory and io mappings */ 1075 1076 for (win = 0; win < PCIC_MEM_WINS; win++) 1077 if (h->memalloc & (1 << win)) 1078 pcic_chip_do_mem_map(h, win); 1079 1080 for (win = 0; win < PCIC_IO_WINS; win++) 1081 if (h->ioalloc & (1 << win)) 1082 pcic_chip_do_io_map(h, win); 1083 } 1084 1085 void 1086 pcic_chip_socket_disable(pch) 1087 pcmcia_chipset_handle_t pch; 1088 { 1089 struct pcic_handle *h = (struct pcic_handle *) pch; 1090 1091 DPRINTF(("pcic_chip_socket_disable\n")); 1092 1093 /* power down the socket */ 1094 1095 pcic_write(h, PCIC_PWRCTL, 0); 1096 } 1097
Indexes created Fri Sep 26 20:09:58 GMT 2025