i82365.c revision 1.35
1 /* $NetBSD: i82365.c,v 1.35 2000/02/02 10:19:51 enami Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 7 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Marc Horowitz. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/kthread.h> 43 44 #include <vm/vm.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 52 #include <dev/ic/i82365reg.h> 53 #include <dev/ic/i82365var.h> 54 55 #include "locators.h" 56 57 #ifdef PCICDEBUG 58 int pcic_debug = 0; 59 #define DPRINTF(arg) if (pcic_debug) printf arg; 60 #else 61 #define DPRINTF(arg) 62 #endif 63 64 /* 65 * Individual drivers will allocate their own memory and io regions. Memory 66 * regions must be a multiple of 4k, aligned on a 4k boundary. 67 */ 68 69 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 70 71 void pcic_attach_socket __P((struct pcic_handle *)); 72 void pcic_attach_socket_finish __P((struct pcic_handle *)); 73 74 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 75 int pcic_print __P((void *arg, const char *pnp)); 76 int pcic_intr_socket __P((struct pcic_handle *)); 77 void pcic_poll_intr __P((void *)); 78 79 void pcic_attach_card __P((struct pcic_handle *)); 80 void pcic_detach_card __P((struct pcic_handle *, int)); 81 void pcic_deactivate_card __P((struct pcic_handle *)); 82 83 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 84 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 85 86 void pcic_create_event_thread __P((void *)); 87 void pcic_event_thread __P((void *)); 88 89 void pcic_queue_event __P((struct pcic_handle *, int)); 90 void pcic_power __P((int, void *)); 91 92 static void pcic_wait_ready __P((struct pcic_handle *)); 93 static void pcic_delay __P((struct pcic_handle *, int, const char *)); 94 95 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 96 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 97 98 #if !defined(PCIC_DELAY_SLEEP) 99 #if defined(__hpcmips__) 100 #define PCIC_DELAY_SLEEP 0 101 #else 102 #define PCIC_DELAY_SLEEP 1 103 #endif 104 #endif 105 int pcic_delay_sleep = PCIC_DELAY_SLEEP; 106 107 int 108 pcic_ident_ok(ident) 109 int ident; 110 { 111 /* this is very empirical and heuristic */ 112 113 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 114 return (0); 115 116 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 117 #ifdef DIAGNOSTIC 118 printf("pcic: does not support memory and I/O cards, " 119 "ignored (ident=%0x)\n", ident); 120 #endif 121 return (0); 122 } 123 return (1); 124 } 125 126 int 127 pcic_vendor(h) 128 struct pcic_handle *h; 129 { 130 int reg; 131 132 /* 133 * the chip_id of the cirrus toggles between 11 and 00 after a write. 134 * weird. 135 */ 136 137 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 138 reg = pcic_read(h, -1); 139 140 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 141 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 142 reg = pcic_read(h, -1); 143 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 144 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 145 return (PCIC_VENDOR_CIRRUS_PD672X); 146 else 147 return (PCIC_VENDOR_CIRRUS_PD6710); 148 } 149 } 150 151 reg = pcic_read(h, PCIC_IDENT); 152 153 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 154 return (PCIC_VENDOR_I82365SLR0); 155 else 156 return (PCIC_VENDOR_I82365SLR1); 157 158 return (PCIC_VENDOR_UNKNOWN); 159 } 160 161 char * 162 pcic_vendor_to_string(vendor) 163 int vendor; 164 { 165 switch (vendor) { 166 case PCIC_VENDOR_I82365SLR0: 167 return ("Intel 82365SL Revision 0"); 168 case PCIC_VENDOR_I82365SLR1: 169 return ("Intel 82365SL Revision 1"); 170 case PCIC_VENDOR_CIRRUS_PD6710: 171 return ("Cirrus PD6710"); 172 case PCIC_VENDOR_CIRRUS_PD672X: 173 return ("Cirrus PD672X"); 174 } 175 176 return ("Unknown controller"); 177 } 178 179 void 180 pcic_attach(sc) 181 struct pcic_softc *sc; 182 { 183 int count, i, reg, chip, socket, intr; 184 185 DPRINTF(("pcic ident regs:")); 186 187 /* find and configure for the available sockets */ 188 count = 0; 189 for (i = 0; i < PCIC_NSLOTS; i++) { 190 chip = i / 2; 191 socket = i % 2; 192 sc->handle[i].ph_parent = (struct device *)sc; 193 sc->handle[i].chip = chip; 194 sc->handle[i].sock = chip * PCIC_CHIP_OFFSET + 195 socket * PCIC_SOCKET_OFFSET; 196 /* initialize pcic_read and pcic_write functions */ 197 sc->handle[i].ph_read = st_pcic_read; 198 sc->handle[i].ph_write = st_pcic_write; 199 sc->handle[i].ph_bus_t = sc->iot; 200 sc->handle[i].ph_bus_h = sc->ioh; 201 /* need to read vendor -- for cirrus to report no xtra chip */ 202 if (socket == 0) 203 sc->handle[i].vendor = sc->handle[i + 1].vendor = 204 pcic_vendor(&sc->handle[i]); 205 reg = pcic_read(&sc->handle[i], PCIC_IDENT); 206 if (!pcic_ident_ok(reg)) { 207 sc->handle[i].flags = 0; 208 } else { 209 sc->handle[i].flags = PCIC_FLAG_SOCKETP; 210 count++; 211 } 212 sc->handle[i].laststate = PCIC_LASTSTATE_EMPTY; 213 DPRINTF(("ident reg 0x%02x\n", reg)); 214 } 215 if (count == 0) 216 panic("pcic_attach: attach found no sockets"); 217 218 for (i = 0; i < PCIC_NSLOTS; i++) { 219 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 220 SIMPLEQ_INIT(&sc->handle[i].events); 221 222 /* disable interrupts -- for now */ 223 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 224 intr = pcic_read(&sc->handle[i], PCIC_INTR); 225 DPRINTF(("intr was 0x%02x\n", intr)); 226 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | 227 PCIC_INTR_IRQ_MASK); 228 pcic_write(&sc->handle[i], PCIC_INTR, intr); 229 pcic_read(&sc->handle[i], PCIC_CSC); 230 } 231 } 232 233 /* print detected info */ 234 for (i = 0; i < PCIC_NSLOTS; i += 2) { 235 chip = i / 2; 236 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 237 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 238 continue; 239 240 printf("%s: controller %d (%s) has ", sc->dev.dv_xname, chip, 241 pcic_vendor_to_string(sc->handle[i].vendor)); 242 243 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) && 244 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP)) 245 printf("sockets A and B\n"); 246 else if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 247 printf("socket A only\n"); 248 else 249 printf("socket B only\n"); 250 } 251 } 252 253 /* 254 * attach the sockets before we know what interrupts we have 255 */ 256 void 257 pcic_attach_sockets(sc) 258 struct pcic_softc *sc; 259 { 260 int i; 261 262 for (i = 0; i < PCIC_NSLOTS; i++) 263 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 264 pcic_attach_socket(&sc->handle[i]); 265 } 266 267 void 268 pcic_power (why, arg) 269 int why; 270 void *arg; 271 { 272 struct pcic_handle *h = (struct pcic_handle *)arg; 273 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 274 int reg; 275 276 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 277 278 if (h->flags & PCIC_FLAG_SOCKETP) { 279 if ((why == PWR_RESUME) && 280 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 281 #ifdef PCICDEBUG 282 char bitbuf[64]; 283 #endif 284 reg = PCIC_CSC_INTR_CD_ENABLE; 285 if (sc->irq != -1) 286 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 287 pcic_write(h, PCIC_CSC_INTR, reg); 288 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 289 sc->dev.dv_xname, 290 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 291 PCIC_CSC_INTR_FORMAT, 292 bitbuf, sizeof(bitbuf)))); 293 } 294 } 295 } 296 297 298 /* 299 * attach a socket -- we don't know about irqs yet 300 */ 301 void 302 pcic_attach_socket(h) 303 struct pcic_handle *h; 304 { 305 struct pcmciabus_attach_args paa; 306 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 307 308 /* initialize the rest of the handle */ 309 310 h->shutdown = 0; 311 h->memalloc = 0; 312 h->ioalloc = 0; 313 h->ih_irq = 0; 314 315 /* now, config one pcmcia device per socket */ 316 317 paa.paa_busname = "pcmcia"; 318 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 319 paa.pch = (pcmcia_chipset_handle_t) h; 320 paa.iobase = sc->iobase; 321 paa.iosize = sc->iosize; 322 323 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, pcic_submatch); 324 if (h->pcmcia == NULL) 325 return; 326 327 /* 328 * queue creation of a kernel thread to handle insert/removal events. 329 */ 330 #ifdef DIAGNOSTIC 331 if (h->event_thread != NULL) 332 panic("pcic_attach_socket: event thread"); 333 #endif 334 config_pending_incr(); 335 kthread_create(pcic_create_event_thread, h); 336 } 337 338 /* 339 * now finish attaching the sockets, we are ready to allocate 340 * interrupts 341 */ 342 void 343 pcic_attach_sockets_finish(sc) 344 struct pcic_softc *sc; 345 { 346 int i; 347 348 for (i = 0; i < PCIC_NSLOTS; i++) 349 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) && 350 sc->handle[i].pcmcia != NULL) 351 pcic_attach_socket_finish(&sc->handle[i]); 352 } 353 354 /* 355 * finishing attaching the socket. Interrupts may now be on 356 * if so expects the pcic interrupt to be blocked 357 */ 358 void 359 pcic_attach_socket_finish(h) 360 struct pcic_handle *h; 361 { 362 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 363 int reg; 364 365 DPRINTF(("%s: attach finish socket %d\n", h->ph_parent->dv_xname, 366 h - &sc->handle[0])); 367 /* 368 * Set up a powerhook to ensure it continues to interrupt on 369 * card detect even after suspend. 370 * (this works around a bug seen in suspend-to-disk on the 371 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 372 */ 373 powerhook_establish(pcic_power, h); 374 375 /* enable interrupts on card detect, poll for them if no irq avail */ 376 reg = PCIC_CSC_INTR_CD_ENABLE; 377 if (sc->irq == -1) 378 timeout(pcic_poll_intr, sc, hz / 2); 379 else 380 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 381 pcic_write(h, PCIC_CSC_INTR, reg); 382 383 /* steer above mgmt interrupt to configured place */ 384 reg = pcic_read(h, PCIC_INTR); 385 reg &= ~PCIC_INTR_ENABLE; 386 pcic_write(h, PCIC_INTR, reg); 387 388 /* clear possible card detect interrupt */ 389 pcic_read(h, PCIC_CSC); 390 391 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 392 h->vendor)); 393 394 /* unsleep the cirrus controller */ 395 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 396 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 397 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 398 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 399 DPRINTF(("%s: socket %02x was suspended\n", 400 h->ph_parent->dv_xname, h->sock)); 401 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 402 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 403 } 404 } 405 406 /* if there's a card there, then attach it. */ 407 reg = pcic_read(h, PCIC_IF_STATUS); 408 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 409 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 410 pcic_queue_event(h, PCIC_EVENT_INSERTION); 411 h->laststate = PCIC_LASTSTATE_PRESENT; 412 } else { 413 h->laststate = PCIC_LASTSTATE_EMPTY; 414 } 415 } 416 417 void 418 pcic_create_event_thread(arg) 419 void *arg; 420 { 421 struct pcic_handle *h = arg; 422 const char *cs; 423 424 switch (h->sock) { 425 case C0SA: 426 cs = "0,0"; 427 break; 428 case C0SB: 429 cs = "0,1"; 430 break; 431 case C1SA: 432 cs = "1,0"; 433 break; 434 case C1SB: 435 cs = "1,1"; 436 break; 437 default: 438 panic("pcic_create_event_thread: unknown pcic socket"); 439 } 440 441 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 442 "%s,%s", h->ph_parent->dv_xname, cs)) { 443 printf("%s: unable to create event thread for sock 0x%02x\n", 444 h->ph_parent->dv_xname, h->sock); 445 panic("pcic_create_event_thread"); 446 } 447 } 448 449 void 450 pcic_event_thread(arg) 451 void *arg; 452 { 453 struct pcic_handle *h = arg; 454 struct pcic_event *pe; 455 int s, first = 1; 456 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 457 458 while (h->shutdown == 0) { 459 s = splhigh(); 460 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 461 splx(s); 462 if (first) { 463 first = 0; 464 config_pending_decr(); 465 } 466 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 467 continue; 468 } else { 469 splx(s); 470 /* sleep .25s to be enqueued chatterling interrupts */ 471 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 472 "pcicss", hz/4); 473 } 474 s = splhigh(); 475 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 476 splx(s); 477 478 switch (pe->pe_type) { 479 case PCIC_EVENT_INSERTION: 480 s = splhigh(); 481 while (1) { 482 struct pcic_event *pe1, *pe2; 483 484 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 485 break; 486 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 487 break; 488 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 489 break; 490 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 491 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 492 pe_q); 493 free(pe1, M_TEMP); 494 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 495 pe_q); 496 free(pe2, M_TEMP); 497 } 498 } 499 splx(s); 500 501 DPRINTF(("%s: insertion event\n", 502 h->ph_parent->dv_xname)); 503 pcic_attach_card(h); 504 break; 505 506 case PCIC_EVENT_REMOVAL: 507 s = splhigh(); 508 while (1) { 509 struct pcic_event *pe1, *pe2; 510 511 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 512 break; 513 if (pe1->pe_type != PCIC_EVENT_INSERTION) 514 break; 515 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 516 break; 517 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 518 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 519 pe_q); 520 free(pe1, M_TEMP); 521 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 522 pe_q); 523 free(pe2, M_TEMP); 524 } 525 } 526 splx(s); 527 528 DPRINTF(("%s: removal event\n", 529 h->ph_parent->dv_xname)); 530 pcic_detach_card(h, DETACH_FORCE); 531 break; 532 533 default: 534 panic("pcic_event_thread: unknown event %d", 535 pe->pe_type); 536 } 537 free(pe, M_TEMP); 538 } 539 540 h->event_thread = NULL; 541 542 /* In case parent is waiting for us to exit. */ 543 wakeup(sc); 544 545 kthread_exit(0); 546 } 547 548 int 549 pcic_submatch(parent, cf, aux) 550 struct device *parent; 551 struct cfdata *cf; 552 void *aux; 553 { 554 555 struct pcmciabus_attach_args *paa = aux; 556 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 557 558 switch (h->sock) { 559 case C0SA: 560 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 561 PCMCIABUSCF_CONTROLLER_DEFAULT && 562 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 563 return 0; 564 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 565 PCMCIABUSCF_SOCKET_DEFAULT && 566 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 567 return 0; 568 569 break; 570 case C0SB: 571 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 572 PCMCIABUSCF_CONTROLLER_DEFAULT && 573 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 574 return 0; 575 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 576 PCMCIABUSCF_SOCKET_DEFAULT && 577 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 578 return 0; 579 580 break; 581 case C1SA: 582 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 583 PCMCIABUSCF_CONTROLLER_DEFAULT && 584 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 585 return 0; 586 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 587 PCMCIABUSCF_SOCKET_DEFAULT && 588 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 589 return 0; 590 591 break; 592 case C1SB: 593 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 594 PCMCIABUSCF_CONTROLLER_DEFAULT && 595 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 596 return 0; 597 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 598 PCMCIABUSCF_SOCKET_DEFAULT && 599 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 600 return 0; 601 602 break; 603 default: 604 panic("unknown pcic socket"); 605 } 606 607 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 608 } 609 610 int 611 pcic_print(arg, pnp) 612 void *arg; 613 const char *pnp; 614 { 615 struct pcmciabus_attach_args *paa = arg; 616 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 617 618 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 619 if (pnp) 620 printf("pcmcia at %s", pnp); 621 622 switch (h->sock) { 623 case C0SA: 624 printf(" controller 0 socket 0"); 625 break; 626 case C0SB: 627 printf(" controller 0 socket 1"); 628 break; 629 case C1SA: 630 printf(" controller 1 socket 0"); 631 break; 632 case C1SB: 633 printf(" controller 1 socket 1"); 634 break; 635 default: 636 panic("unknown pcic socket"); 637 } 638 639 return (UNCONF); 640 } 641 642 void 643 pcic_poll_intr(arg) 644 void *arg; 645 { 646 struct pcic_softc *sc; 647 int i, s; 648 649 s = spltty(); 650 sc = arg; 651 for (i = 0; i < PCIC_NSLOTS; i++) 652 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 653 (void)pcic_intr_socket(&sc->handle[i]); 654 timeout(pcic_poll_intr, sc, hz / 2); 655 splx(s); 656 } 657 658 int 659 pcic_intr(arg) 660 void *arg; 661 { 662 struct pcic_softc *sc = arg; 663 int i, ret = 0; 664 665 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 666 667 for (i = 0; i < PCIC_NSLOTS; i++) 668 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 669 ret += pcic_intr_socket(&sc->handle[i]); 670 671 return (ret ? 1 : 0); 672 } 673 674 int 675 pcic_intr_socket(h) 676 struct pcic_handle *h; 677 { 678 int cscreg; 679 680 cscreg = pcic_read(h, PCIC_CSC); 681 682 cscreg &= (PCIC_CSC_GPI | 683 PCIC_CSC_CD | 684 PCIC_CSC_READY | 685 PCIC_CSC_BATTWARN | 686 PCIC_CSC_BATTDEAD); 687 688 if (cscreg & PCIC_CSC_GPI) { 689 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 690 } 691 if (cscreg & PCIC_CSC_CD) { 692 int statreg; 693 694 statreg = pcic_read(h, PCIC_IF_STATUS); 695 696 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 697 statreg)); 698 699 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 700 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 701 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 702 DPRINTF(("%s: enqueing INSERTION event\n", 703 h->ph_parent->dv_xname)); 704 pcic_queue_event(h, PCIC_EVENT_INSERTION); 705 } 706 h->laststate = PCIC_LASTSTATE_PRESENT; 707 } else { 708 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 709 /* Deactivate the card now. */ 710 DPRINTF(("%s: deactivating card\n", 711 h->ph_parent->dv_xname)); 712 pcic_deactivate_card(h); 713 714 DPRINTF(("%s: enqueing REMOVAL event\n", 715 h->ph_parent->dv_xname)); 716 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 717 } 718 h->laststate = 719 ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) ? 720 PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 721 } 722 } 723 if (cscreg & PCIC_CSC_READY) { 724 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 725 /* shouldn't happen */ 726 } 727 if (cscreg & PCIC_CSC_BATTWARN) { 728 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 729 h->sock)); 730 } 731 if (cscreg & PCIC_CSC_BATTDEAD) { 732 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 733 h->sock)); 734 } 735 return (cscreg ? 1 : 0); 736 } 737 738 void 739 pcic_queue_event(h, event) 740 struct pcic_handle *h; 741 int event; 742 { 743 struct pcic_event *pe; 744 int s; 745 746 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 747 if (pe == NULL) 748 panic("pcic_queue_event: can't allocate event"); 749 750 pe->pe_type = event; 751 s = splhigh(); 752 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 753 splx(s); 754 wakeup(&h->events); 755 } 756 757 void 758 pcic_attach_card(h) 759 struct pcic_handle *h; 760 { 761 762 if (!(h->flags & PCIC_FLAG_CARDP)) { 763 /* call the MI attach function */ 764 pcmcia_card_attach(h->pcmcia); 765 766 h->flags |= PCIC_FLAG_CARDP; 767 } else { 768 DPRINTF(("pcic_attach_card: already attached")); 769 } 770 } 771 772 void 773 pcic_detach_card(h, flags) 774 struct pcic_handle *h; 775 int flags; /* DETACH_* */ 776 { 777 778 if (h->flags & PCIC_FLAG_CARDP) { 779 h->flags &= ~PCIC_FLAG_CARDP; 780 781 /* call the MI detach function */ 782 pcmcia_card_detach(h->pcmcia, flags); 783 } else { 784 DPRINTF(("pcic_detach_card: already detached")); 785 } 786 } 787 788 void 789 pcic_deactivate_card(h) 790 struct pcic_handle *h; 791 { 792 793 /* call the MI deactivate function */ 794 pcmcia_card_deactivate(h->pcmcia); 795 796 /* power down the socket */ 797 pcic_write(h, PCIC_PWRCTL, 0); 798 799 /* reset the socket */ 800 pcic_write(h, PCIC_INTR, 0); 801 } 802 803 int 804 pcic_chip_mem_alloc(pch, size, pcmhp) 805 pcmcia_chipset_handle_t pch; 806 bus_size_t size; 807 struct pcmcia_mem_handle *pcmhp; 808 { 809 struct pcic_handle *h = (struct pcic_handle *) pch; 810 bus_space_handle_t memh; 811 bus_addr_t addr; 812 bus_size_t sizepg; 813 int i, mask, mhandle; 814 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 815 816 /* out of sc->memh, allocate as many pages as necessary */ 817 818 /* convert size to PCIC pages */ 819 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 820 if (sizepg > PCIC_MAX_MEM_PAGES) 821 return (1); 822 823 mask = (1 << sizepg) - 1; 824 825 addr = 0; /* XXX gcc -Wuninitialized */ 826 mhandle = 0; /* XXX gcc -Wuninitialized */ 827 828 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 829 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 830 if (bus_space_subregion(sc->memt, sc->memh, 831 i * PCIC_MEM_PAGESIZE, 832 sizepg * PCIC_MEM_PAGESIZE, &memh)) 833 return (1); 834 mhandle = mask << i; 835 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 836 sc->subregionmask &= ~(mhandle); 837 pcmhp->memt = sc->memt; 838 pcmhp->memh = memh; 839 pcmhp->addr = addr; 840 pcmhp->size = size; 841 pcmhp->mhandle = mhandle; 842 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 843 return (0); 844 } 845 } 846 847 return (1); 848 } 849 850 void 851 pcic_chip_mem_free(pch, pcmhp) 852 pcmcia_chipset_handle_t pch; 853 struct pcmcia_mem_handle *pcmhp; 854 { 855 struct pcic_handle *h = (struct pcic_handle *) pch; 856 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 857 858 sc->subregionmask |= pcmhp->mhandle; 859 } 860 861 static struct mem_map_index_st { 862 int sysmem_start_lsb; 863 int sysmem_start_msb; 864 int sysmem_stop_lsb; 865 int sysmem_stop_msb; 866 int cardmem_lsb; 867 int cardmem_msb; 868 int memenable; 869 } mem_map_index[] = { 870 { 871 PCIC_SYSMEM_ADDR0_START_LSB, 872 PCIC_SYSMEM_ADDR0_START_MSB, 873 PCIC_SYSMEM_ADDR0_STOP_LSB, 874 PCIC_SYSMEM_ADDR0_STOP_MSB, 875 PCIC_CARDMEM_ADDR0_LSB, 876 PCIC_CARDMEM_ADDR0_MSB, 877 PCIC_ADDRWIN_ENABLE_MEM0, 878 }, 879 { 880 PCIC_SYSMEM_ADDR1_START_LSB, 881 PCIC_SYSMEM_ADDR1_START_MSB, 882 PCIC_SYSMEM_ADDR1_STOP_LSB, 883 PCIC_SYSMEM_ADDR1_STOP_MSB, 884 PCIC_CARDMEM_ADDR1_LSB, 885 PCIC_CARDMEM_ADDR1_MSB, 886 PCIC_ADDRWIN_ENABLE_MEM1, 887 }, 888 { 889 PCIC_SYSMEM_ADDR2_START_LSB, 890 PCIC_SYSMEM_ADDR2_START_MSB, 891 PCIC_SYSMEM_ADDR2_STOP_LSB, 892 PCIC_SYSMEM_ADDR2_STOP_MSB, 893 PCIC_CARDMEM_ADDR2_LSB, 894 PCIC_CARDMEM_ADDR2_MSB, 895 PCIC_ADDRWIN_ENABLE_MEM2, 896 }, 897 { 898 PCIC_SYSMEM_ADDR3_START_LSB, 899 PCIC_SYSMEM_ADDR3_START_MSB, 900 PCIC_SYSMEM_ADDR3_STOP_LSB, 901 PCIC_SYSMEM_ADDR3_STOP_MSB, 902 PCIC_CARDMEM_ADDR3_LSB, 903 PCIC_CARDMEM_ADDR3_MSB, 904 PCIC_ADDRWIN_ENABLE_MEM3, 905 }, 906 { 907 PCIC_SYSMEM_ADDR4_START_LSB, 908 PCIC_SYSMEM_ADDR4_START_MSB, 909 PCIC_SYSMEM_ADDR4_STOP_LSB, 910 PCIC_SYSMEM_ADDR4_STOP_MSB, 911 PCIC_CARDMEM_ADDR4_LSB, 912 PCIC_CARDMEM_ADDR4_MSB, 913 PCIC_ADDRWIN_ENABLE_MEM4, 914 }, 915 }; 916 917 void 918 pcic_chip_do_mem_map(h, win) 919 struct pcic_handle *h; 920 int win; 921 { 922 int reg; 923 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 924 int mem8 = 925 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 926 927 DPRINTF(("mem8 %d\n", mem8)); 928 /* mem8 = 1; */ 929 930 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 931 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 932 pcic_write(h, mem_map_index[win].sysmem_start_msb, 933 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 934 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 935 936 #if 0 937 /* XXX do I want 16 bit all the time? */ 938 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 939 #endif 940 941 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 942 ((h->mem[win].addr + h->mem[win].size) >> 943 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 944 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 945 (((h->mem[win].addr + h->mem[win].size) >> 946 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 947 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 948 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 949 950 pcic_write(h, mem_map_index[win].cardmem_lsb, 951 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 952 pcic_write(h, mem_map_index[win].cardmem_msb, 953 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 954 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 955 ((kind == PCMCIA_MEM_ATTR) ? 956 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 957 958 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 959 reg |= (mem_map_index[win].memenable | 960 (mem8 ? 0 : PCIC_ADDRWIN_ENABLE_MEMCS16)); 961 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 962 963 delay(100); 964 965 #ifdef PCICDEBUG 966 { 967 int r1, r2, r3, r4, r5, r6; 968 969 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 970 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 971 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 972 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 973 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 974 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 975 976 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 977 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 978 } 979 #endif 980 } 981 982 int 983 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 984 pcmcia_chipset_handle_t pch; 985 int kind; 986 bus_addr_t card_addr; 987 bus_size_t size; 988 struct pcmcia_mem_handle *pcmhp; 989 bus_addr_t *offsetp; 990 int *windowp; 991 { 992 struct pcic_handle *h = (struct pcic_handle *) pch; 993 bus_addr_t busaddr; 994 long card_offset; 995 int i, win; 996 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 997 998 win = -1; 999 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1000 i++) { 1001 if ((h->memalloc & (1 << i)) == 0) { 1002 win = i; 1003 h->memalloc |= (1 << i); 1004 break; 1005 } 1006 } 1007 1008 if (win == -1) 1009 return (1); 1010 1011 *windowp = win; 1012 1013 /* XXX this is pretty gross */ 1014 1015 if (sc->memt != pcmhp->memt) 1016 panic("pcic_chip_mem_map memt is bogus"); 1017 1018 busaddr = pcmhp->addr; 1019 1020 /* 1021 * compute the address offset to the pcmcia address space for the 1022 * pcic. this is intentionally signed. The masks and shifts below 1023 * will cause TRT to happen in the pcic registers. Deal with making 1024 * sure the address is aligned, and return the alignment offset. 1025 */ 1026 1027 *offsetp = card_addr % PCIC_MEM_ALIGN; 1028 card_addr -= *offsetp; 1029 1030 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1031 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1032 (u_long) card_addr)); 1033 1034 /* 1035 * include the offset in the size, and decrement size by one, since 1036 * the hw wants start/stop 1037 */ 1038 size += *offsetp - 1; 1039 1040 card_offset = (((long) card_addr) - ((long) busaddr)); 1041 1042 h->mem[win].addr = busaddr; 1043 h->mem[win].size = size; 1044 h->mem[win].offset = card_offset; 1045 h->mem[win].kind = kind; 1046 1047 pcic_chip_do_mem_map(h, win); 1048 1049 return (0); 1050 } 1051 1052 void 1053 pcic_chip_mem_unmap(pch, window) 1054 pcmcia_chipset_handle_t pch; 1055 int window; 1056 { 1057 struct pcic_handle *h = (struct pcic_handle *) pch; 1058 int reg; 1059 1060 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1061 panic("pcic_chip_mem_unmap: window out of range"); 1062 1063 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1064 reg &= ~mem_map_index[window].memenable; 1065 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1066 1067 h->memalloc &= ~(1 << window); 1068 } 1069 1070 int 1071 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1072 pcmcia_chipset_handle_t pch; 1073 bus_addr_t start; 1074 bus_size_t size; 1075 bus_size_t align; 1076 struct pcmcia_io_handle *pcihp; 1077 { 1078 struct pcic_handle *h = (struct pcic_handle *) pch; 1079 bus_space_tag_t iot; 1080 bus_space_handle_t ioh; 1081 bus_addr_t ioaddr; 1082 int flags = 0; 1083 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1084 1085 /* 1086 * Allocate some arbitrary I/O space. 1087 */ 1088 1089 iot = sc->iot; 1090 1091 if (start) { 1092 ioaddr = start; 1093 if (bus_space_map(iot, start, size, 0, &ioh)) 1094 return (1); 1095 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1096 (u_long) ioaddr, (u_long) size)); 1097 } else { 1098 flags |= PCMCIA_IO_ALLOCATED; 1099 if (bus_space_alloc(iot, sc->iobase, 1100 sc->iobase + sc->iosize, size, align, 0, 0, 1101 &ioaddr, &ioh)) 1102 return (1); 1103 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1104 (u_long) ioaddr, (u_long) size)); 1105 } 1106 1107 pcihp->iot = iot; 1108 pcihp->ioh = ioh; 1109 pcihp->addr = ioaddr; 1110 pcihp->size = size; 1111 pcihp->flags = flags; 1112 1113 return (0); 1114 } 1115 1116 void 1117 pcic_chip_io_free(pch, pcihp) 1118 pcmcia_chipset_handle_t pch; 1119 struct pcmcia_io_handle *pcihp; 1120 { 1121 bus_space_tag_t iot = pcihp->iot; 1122 bus_space_handle_t ioh = pcihp->ioh; 1123 bus_size_t size = pcihp->size; 1124 1125 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1126 bus_space_free(iot, ioh, size); 1127 else 1128 bus_space_unmap(iot, ioh, size); 1129 } 1130 1131 1132 static struct io_map_index_st { 1133 int start_lsb; 1134 int start_msb; 1135 int stop_lsb; 1136 int stop_msb; 1137 int ioenable; 1138 int ioctlmask; 1139 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1140 } io_map_index[] = { 1141 { 1142 PCIC_IOADDR0_START_LSB, 1143 PCIC_IOADDR0_START_MSB, 1144 PCIC_IOADDR0_STOP_LSB, 1145 PCIC_IOADDR0_STOP_MSB, 1146 PCIC_ADDRWIN_ENABLE_IO0, 1147 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1148 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1149 { 1150 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1151 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1152 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1153 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1154 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1155 }, 1156 }, 1157 { 1158 PCIC_IOADDR1_START_LSB, 1159 PCIC_IOADDR1_START_MSB, 1160 PCIC_IOADDR1_STOP_LSB, 1161 PCIC_IOADDR1_STOP_MSB, 1162 PCIC_ADDRWIN_ENABLE_IO1, 1163 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1164 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1165 { 1166 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1167 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1168 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1169 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1170 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1171 }, 1172 }, 1173 }; 1174 1175 void 1176 pcic_chip_do_io_map(h, win) 1177 struct pcic_handle *h; 1178 int win; 1179 { 1180 int reg; 1181 1182 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1183 win, (long) h->io[win].addr, (long) h->io[win].size, 1184 h->io[win].width * 8)); 1185 1186 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1187 pcic_write(h, io_map_index[win].start_msb, 1188 (h->io[win].addr >> 8) & 0xff); 1189 1190 pcic_write(h, io_map_index[win].stop_lsb, 1191 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1192 pcic_write(h, io_map_index[win].stop_msb, 1193 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1194 1195 reg = pcic_read(h, PCIC_IOCTL); 1196 reg &= ~io_map_index[win].ioctlmask; 1197 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1198 pcic_write(h, PCIC_IOCTL, reg); 1199 1200 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1201 reg |= io_map_index[win].ioenable; 1202 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1203 } 1204 1205 int 1206 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1207 pcmcia_chipset_handle_t pch; 1208 int width; 1209 bus_addr_t offset; 1210 bus_size_t size; 1211 struct pcmcia_io_handle *pcihp; 1212 int *windowp; 1213 { 1214 struct pcic_handle *h = (struct pcic_handle *) pch; 1215 bus_addr_t ioaddr = pcihp->addr + offset; 1216 int i, win; 1217 #ifdef PCICDEBUG 1218 static char *width_names[] = { "auto", "io8", "io16" }; 1219 #endif 1220 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1221 1222 /* XXX Sanity check offset/size. */ 1223 1224 win = -1; 1225 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1226 if ((h->ioalloc & (1 << i)) == 0) { 1227 win = i; 1228 h->ioalloc |= (1 << i); 1229 break; 1230 } 1231 } 1232 1233 if (win == -1) 1234 return (1); 1235 1236 *windowp = win; 1237 1238 /* XXX this is pretty gross */ 1239 1240 if (sc->iot != pcihp->iot) 1241 panic("pcic_chip_io_map iot is bogus"); 1242 1243 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1244 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1245 1246 /* XXX wtf is this doing here? */ 1247 1248 printf(" port 0x%lx", (u_long) ioaddr); 1249 if (size > 1) 1250 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1251 1252 h->io[win].addr = ioaddr; 1253 h->io[win].size = size; 1254 h->io[win].width = width; 1255 1256 pcic_chip_do_io_map(h, win); 1257 1258 return (0); 1259 } 1260 1261 void 1262 pcic_chip_io_unmap(pch, window) 1263 pcmcia_chipset_handle_t pch; 1264 int window; 1265 { 1266 struct pcic_handle *h = (struct pcic_handle *) pch; 1267 int reg; 1268 1269 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1270 panic("pcic_chip_io_unmap: window out of range"); 1271 1272 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1273 reg &= ~io_map_index[window].ioenable; 1274 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1275 1276 h->ioalloc &= ~(1 << window); 1277 } 1278 1279 static void 1280 pcic_wait_ready(h) 1281 struct pcic_handle *h; 1282 { 1283 int i; 1284 1285 /* wait an initial 10ms for quick cards */ 1286 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1287 return; 1288 pcic_delay(h, 10, "wait_ready initial"); 1289 for (i = 0; i < 50; i++) { 1290 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1291 return; 1292 /* wait .1s (100ms) each iteration now */ 1293 pcic_delay(h, 100, "wait_ready loop"); 1294 #ifdef PCICDEBUG 1295 if (pcic_debug) { 1296 if ((i > 20) && (i % 100 == 99)) 1297 printf("."); 1298 } 1299 #endif 1300 } 1301 1302 #ifdef DIAGNOSTIC 1303 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1304 pcic_read(h, PCIC_IF_STATUS)); 1305 #endif 1306 } 1307 1308 /* 1309 * Perform long (msec order) delay. 1310 */ 1311 static void 1312 pcic_delay(h, timo, ident) 1313 struct pcic_handle *h; 1314 int timo; /* in ms. must not be zero */ 1315 const char *ident; 1316 { 1317 1318 #ifdef DIAGNOSTIC 1319 if (timo <= 0) { 1320 printf("called with timeout %d\n", timo); 1321 panic("pcic_delay"); 1322 } 1323 if (curproc == NULL) { 1324 printf("called in interrupt context\n"); 1325 panic("pcic_delay"); 1326 } 1327 if (h->event_thread == NULL) { 1328 printf("no event thread\n"); 1329 panic("pcic_delay"); 1330 } 1331 #endif 1332 DPRINTF(("pcic_delay: %p, sleep %d ms\n", h->event_thread, timo)); 1333 if (pcic_delay_sleep) 1334 tsleep(pcic_delay, PWAIT, ident, 1335 roundup(timo * hz, 1000) / 1000); 1336 else 1337 delay(timo * 1000); 1338 } 1339 1340 void 1341 pcic_chip_socket_enable(pch) 1342 pcmcia_chipset_handle_t pch; 1343 { 1344 struct pcic_handle *h = (struct pcic_handle *) pch; 1345 int cardtype, win, intr; 1346 #if defined(DIAGNOSTIC) || defined(PCIC_DEBUG) 1347 int reg; 1348 #endif 1349 1350 /* disable interrupts and put in a known state for power down */ 1351 intr = 0; 1352 pcic_write(h, PCIC_INTR, intr); 1353 1354 /* power down the socket to reset it, clear the card reset pin */ 1355 pcic_write(h, PCIC_PWRCTL, 0); 1356 1357 /* 1358 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1359 * we are changing Vcc (Toff). 1360 */ 1361 pcic_delay(h, 300 + 100, "pccen0"); 1362 1363 #ifdef VADEM_POWER_HACK 1364 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1365 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1366 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1367 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1368 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1369 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1370 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1371 #endif 1372 1373 /* power up the socket */ 1374 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | 1375 PCIC_PWRCTL_PWR_ENABLE); 1376 1377 /* 1378 * wait 100ms until power raise (Tpr) and 20ms to become 1379 * stable (Tsu(Vcc)). 1380 * 1381 * some machines require some more time to be settled 1382 * (300ms is added here). 1383 */ 1384 pcic_delay(h, 100 + 20 + 300, "pccen1"); 1385 1386 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | 1387 PCIC_PWRCTL_OE | PCIC_PWRCTL_PWR_ENABLE); 1388 /* 1389 * hold RESET at least 10us. 1390 */ 1391 delay(10); 1392 delay(2*1000); /* XXX: TI1130 requires it. */ 1393 delay(20*1000); /* XXX: TI1130 requires it. */ 1394 1395 /* clear the reset flag */ 1396 intr |= PCIC_INTR_RESET; 1397 pcic_write(h, PCIC_INTR, intr); 1398 1399 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1400 1401 pcic_delay(h, 20, "pccen2"); 1402 1403 /* wait for the chip to finish initializing */ 1404 1405 #ifdef DIAGNOSTIC 1406 reg = pcic_read(h, PCIC_IF_STATUS); 1407 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1408 printf("pcic_chip_socket_enable: status %x", reg); 1409 } 1410 #endif 1411 1412 pcic_wait_ready(h); 1413 1414 /* zero out the address windows */ 1415 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1416 1417 /* set the card type and enable the interrupt */ 1418 cardtype = pcmcia_card_gettype(h->pcmcia); 1419 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1420 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 1421 pcic_write(h, PCIC_INTR, intr); 1422 1423 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1424 h->ph_parent->dv_xname, h->sock, 1425 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1426 1427 /* reinstall all the memory and io mappings */ 1428 1429 for (win = 0; win < PCIC_MEM_WINS; win++) 1430 if (h->memalloc & (1 << win)) 1431 pcic_chip_do_mem_map(h, win); 1432 1433 for (win = 0; win < PCIC_IO_WINS; win++) 1434 if (h->ioalloc & (1 << win)) 1435 pcic_chip_do_io_map(h, win); 1436 1437 /* finally enable the interrupt */ 1438 intr |= h->ih_irq; 1439 pcic_write(h, PCIC_INTR, intr); 1440 } 1441 1442 void 1443 pcic_chip_socket_disable(pch) 1444 pcmcia_chipset_handle_t pch; 1445 { 1446 struct pcic_handle *h = (struct pcic_handle *) pch; 1447 1448 DPRINTF(("pcic_chip_socket_disable\n")); 1449 1450 /* power down the socket */ 1451 pcic_write(h, PCIC_PWRCTL, 0); 1452 1453 #if 1 1454 /* 1455 * This constraint is kept in pcic_chip_socket_enable. 1456 * When we enable the same card slot, we first turn off the 1457 * power and wait enough time. So we don't need to wait here. 1458 * 1459 * wait 300ms until power fails (Tpf). 1460 */ 1461 pcic_delay(h, 300, "pcicdis"); 1462 #endif 1463 } 1464 1465 static u_int8_t 1466 st_pcic_read(h, idx) 1467 struct pcic_handle *h; 1468 int idx; 1469 { 1470 1471 if (idx != -1) 1472 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1473 h->sock + idx); 1474 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1475 } 1476 1477 static void 1478 st_pcic_write(h, idx, data) 1479 struct pcic_handle *h; 1480 int idx; 1481 u_int8_t data; 1482 { 1483 1484 if (idx != -1) 1485 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1486 h->sock + idx); 1487 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1488 } 1489
Indexes created Mon Sep 29 21:09:56 GMT 2025