i82365.c revision 1.40
1 /* $NetBSD: i82365.c,v 1.40 2000/02/03 09:00:39 enami Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 7 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Marc Horowitz. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/kthread.h> 43 44 #include <vm/vm.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 52 #include <dev/ic/i82365reg.h> 53 #include <dev/ic/i82365var.h> 54 55 #include "locators.h" 56 57 #ifdef PCICDEBUG 58 int pcic_debug = 0; 59 #define DPRINTF(arg) if (pcic_debug) printf arg; 60 #else 61 #define DPRINTF(arg) 62 #endif 63 64 /* 65 * Individual drivers will allocate their own memory and io regions. Memory 66 * regions must be a multiple of 4k, aligned on a 4k boundary. 67 */ 68 69 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 70 71 void pcic_attach_socket __P((struct pcic_handle *)); 72 void pcic_attach_socket_finish __P((struct pcic_handle *)); 73 74 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 75 int pcic_print __P((void *arg, const char *pnp)); 76 int pcic_intr_socket __P((struct pcic_handle *)); 77 void pcic_poll_intr __P((void *)); 78 79 void pcic_attach_card __P((struct pcic_handle *)); 80 void pcic_detach_card __P((struct pcic_handle *, int)); 81 void pcic_deactivate_card __P((struct pcic_handle *)); 82 83 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 84 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 85 86 void pcic_create_event_thread __P((void *)); 87 void pcic_event_thread __P((void *)); 88 89 void pcic_queue_event __P((struct pcic_handle *, int)); 90 void pcic_power __P((int, void *)); 91 92 static void pcic_wait_ready __P((struct pcic_handle *)); 93 static void pcic_delay __P((struct pcic_handle *, int, const char *)); 94 95 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 96 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 97 98 int 99 pcic_ident_ok(ident) 100 int ident; 101 { 102 /* this is very empirical and heuristic */ 103 104 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 105 return (0); 106 107 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 108 #ifdef DIAGNOSTIC 109 printf("pcic: does not support memory and I/O cards, " 110 "ignored (ident=%0x)\n", ident); 111 #endif 112 return (0); 113 } 114 return (1); 115 } 116 117 int 118 pcic_vendor(h) 119 struct pcic_handle *h; 120 { 121 int reg; 122 123 /* 124 * the chip_id of the cirrus toggles between 11 and 00 after a write. 125 * weird. 126 */ 127 128 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 129 reg = pcic_read(h, -1); 130 131 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 132 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 133 reg = pcic_read(h, -1); 134 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 135 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 136 return (PCIC_VENDOR_CIRRUS_PD672X); 137 else 138 return (PCIC_VENDOR_CIRRUS_PD6710); 139 } 140 } 141 142 reg = pcic_read(h, PCIC_IDENT); 143 144 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 145 return (PCIC_VENDOR_I82365SLR0); 146 else 147 return (PCIC_VENDOR_I82365SLR1); 148 149 return (PCIC_VENDOR_UNKNOWN); 150 } 151 152 char * 153 pcic_vendor_to_string(vendor) 154 int vendor; 155 { 156 switch (vendor) { 157 case PCIC_VENDOR_I82365SLR0: 158 return ("Intel 82365SL Revision 0"); 159 case PCIC_VENDOR_I82365SLR1: 160 return ("Intel 82365SL Revision 1"); 161 case PCIC_VENDOR_CIRRUS_PD6710: 162 return ("Cirrus PD6710"); 163 case PCIC_VENDOR_CIRRUS_PD672X: 164 return ("Cirrus PD672X"); 165 } 166 167 return ("Unknown controller"); 168 } 169 170 void 171 pcic_attach(sc) 172 struct pcic_softc *sc; 173 { 174 int count, i, reg, chip, socket, intr; 175 176 DPRINTF(("pcic ident regs:")); 177 178 /* find and configure for the available sockets */ 179 count = 0; 180 for (i = 0; i < PCIC_NSLOTS; i++) { 181 chip = i / 2; 182 socket = i % 2; 183 sc->handle[i].ph_parent = (struct device *)sc; 184 sc->handle[i].chip = chip; 185 sc->handle[i].sock = chip * PCIC_CHIP_OFFSET + 186 socket * PCIC_SOCKET_OFFSET; 187 /* initialize pcic_read and pcic_write functions */ 188 sc->handle[i].ph_read = st_pcic_read; 189 sc->handle[i].ph_write = st_pcic_write; 190 sc->handle[i].ph_bus_t = sc->iot; 191 sc->handle[i].ph_bus_h = sc->ioh; 192 /* need to read vendor -- for cirrus to report no xtra chip */ 193 if (socket == 0) 194 sc->handle[i].vendor = sc->handle[i + 1].vendor = 195 pcic_vendor(&sc->handle[i]); 196 reg = pcic_read(&sc->handle[i], PCIC_IDENT); 197 if (!pcic_ident_ok(reg)) { 198 sc->handle[i].flags = 0; 199 } else { 200 sc->handle[i].flags = PCIC_FLAG_SOCKETP; 201 count++; 202 } 203 sc->handle[i].laststate = PCIC_LASTSTATE_EMPTY; 204 DPRINTF(("ident reg 0x%02x\n", reg)); 205 } 206 if (count == 0) 207 panic("pcic_attach: attach found no sockets"); 208 209 for (i = 0; i < PCIC_NSLOTS; i++) { 210 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 211 SIMPLEQ_INIT(&sc->handle[i].events); 212 213 /* disable interrupts -- for now */ 214 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 215 intr = pcic_read(&sc->handle[i], PCIC_INTR); 216 DPRINTF(("intr was 0x%02x\n", intr)); 217 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | 218 PCIC_INTR_IRQ_MASK); 219 pcic_write(&sc->handle[i], PCIC_INTR, intr); 220 pcic_read(&sc->handle[i], PCIC_CSC); 221 } 222 } 223 224 /* print detected info */ 225 for (i = 0; i < PCIC_NSLOTS; i += 2) { 226 chip = i / 2; 227 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 228 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 229 continue; 230 231 printf("%s: controller %d (%s) has ", sc->dev.dv_xname, chip, 232 pcic_vendor_to_string(sc->handle[i].vendor)); 233 234 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) && 235 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP)) 236 printf("sockets A and B\n"); 237 else if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 238 printf("socket A only\n"); 239 else 240 printf("socket B only\n"); 241 } 242 } 243 244 /* 245 * attach the sockets before we know what interrupts we have 246 */ 247 void 248 pcic_attach_sockets(sc) 249 struct pcic_softc *sc; 250 { 251 int i; 252 253 for (i = 0; i < PCIC_NSLOTS; i++) 254 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 255 pcic_attach_socket(&sc->handle[i]); 256 } 257 258 void 259 pcic_power (why, arg) 260 int why; 261 void *arg; 262 { 263 struct pcic_handle *h = (struct pcic_handle *)arg; 264 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 265 int reg; 266 267 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 268 269 if (h->flags & PCIC_FLAG_SOCKETP) { 270 if ((why == PWR_RESUME) && 271 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 272 #ifdef PCICDEBUG 273 char bitbuf[64]; 274 #endif 275 reg = PCIC_CSC_INTR_CD_ENABLE; 276 if (sc->irq != -1) 277 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 278 pcic_write(h, PCIC_CSC_INTR, reg); 279 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 280 sc->dev.dv_xname, 281 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 282 PCIC_CSC_INTR_FORMAT, 283 bitbuf, sizeof(bitbuf)))); 284 } 285 } 286 } 287 288 289 /* 290 * attach a socket -- we don't know about irqs yet 291 */ 292 void 293 pcic_attach_socket(h) 294 struct pcic_handle *h; 295 { 296 struct pcmciabus_attach_args paa; 297 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 298 299 /* initialize the rest of the handle */ 300 301 h->shutdown = 0; 302 h->memalloc = 0; 303 h->ioalloc = 0; 304 h->ih_irq = 0; 305 306 /* now, config one pcmcia device per socket */ 307 308 paa.paa_busname = "pcmcia"; 309 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 310 paa.pch = (pcmcia_chipset_handle_t) h; 311 paa.iobase = sc->iobase; 312 paa.iosize = sc->iosize; 313 314 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, pcic_submatch); 315 if (h->pcmcia == NULL) 316 return; 317 318 /* 319 * queue creation of a kernel thread to handle insert/removal events. 320 */ 321 #ifdef DIAGNOSTIC 322 if (h->event_thread != NULL) 323 panic("pcic_attach_socket: event thread"); 324 #endif 325 config_pending_incr(); 326 kthread_create(pcic_create_event_thread, h); 327 } 328 329 /* 330 * now finish attaching the sockets, we are ready to allocate 331 * interrupts 332 */ 333 void 334 pcic_attach_sockets_finish(sc) 335 struct pcic_softc *sc; 336 { 337 int i; 338 339 for (i = 0; i < PCIC_NSLOTS; i++) 340 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) && 341 sc->handle[i].pcmcia != NULL) 342 pcic_attach_socket_finish(&sc->handle[i]); 343 } 344 345 /* 346 * finishing attaching the socket. Interrupts may now be on 347 * if so expects the pcic interrupt to be blocked 348 */ 349 void 350 pcic_attach_socket_finish(h) 351 struct pcic_handle *h; 352 { 353 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 354 int reg; 355 356 DPRINTF(("%s: attach finish socket %d\n", h->ph_parent->dv_xname, 357 h - &sc->handle[0])); 358 /* 359 * Set up a powerhook to ensure it continues to interrupt on 360 * card detect even after suspend. 361 * (this works around a bug seen in suspend-to-disk on the 362 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 363 */ 364 powerhook_establish(pcic_power, h); 365 366 /* enable interrupts on card detect, poll for them if no irq avail */ 367 reg = PCIC_CSC_INTR_CD_ENABLE; 368 if (sc->irq == -1) 369 timeout(pcic_poll_intr, sc, hz / 2); 370 else 371 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 372 pcic_write(h, PCIC_CSC_INTR, reg); 373 374 /* steer above mgmt interrupt to configured place */ 375 reg = pcic_read(h, PCIC_INTR); 376 reg &= ~PCIC_INTR_ENABLE; 377 pcic_write(h, PCIC_INTR, reg); 378 379 /* clear possible card detect interrupt */ 380 pcic_read(h, PCIC_CSC); 381 382 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 383 h->vendor)); 384 385 /* unsleep the cirrus controller */ 386 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 387 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 388 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 389 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 390 DPRINTF(("%s: socket %02x was suspended\n", 391 h->ph_parent->dv_xname, h->sock)); 392 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 393 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 394 } 395 } 396 397 /* if there's a card there, then attach it. */ 398 reg = pcic_read(h, PCIC_IF_STATUS); 399 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 400 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 401 pcic_queue_event(h, PCIC_EVENT_INSERTION); 402 h->laststate = PCIC_LASTSTATE_PRESENT; 403 } else { 404 h->laststate = PCIC_LASTSTATE_EMPTY; 405 } 406 } 407 408 void 409 pcic_create_event_thread(arg) 410 void *arg; 411 { 412 struct pcic_handle *h = arg; 413 const char *cs; 414 415 switch (h->sock) { 416 case C0SA: 417 cs = "0,0"; 418 break; 419 case C0SB: 420 cs = "0,1"; 421 break; 422 case C1SA: 423 cs = "1,0"; 424 break; 425 case C1SB: 426 cs = "1,1"; 427 break; 428 default: 429 panic("pcic_create_event_thread: unknown pcic socket"); 430 } 431 432 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 433 "%s,%s", h->ph_parent->dv_xname, cs)) { 434 printf("%s: unable to create event thread for sock 0x%02x\n", 435 h->ph_parent->dv_xname, h->sock); 436 panic("pcic_create_event_thread"); 437 } 438 } 439 440 void 441 pcic_event_thread(arg) 442 void *arg; 443 { 444 struct pcic_handle *h = arg; 445 struct pcic_event *pe; 446 int s, first = 1; 447 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 448 449 while (h->shutdown == 0) { 450 s = splhigh(); 451 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 452 splx(s); 453 if (first) { 454 first = 0; 455 config_pending_decr(); 456 } 457 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 458 continue; 459 } else { 460 splx(s); 461 /* sleep .25s to be enqueued chatterling interrupts */ 462 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 463 "pcicss", hz/4); 464 } 465 s = splhigh(); 466 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 467 splx(s); 468 469 switch (pe->pe_type) { 470 case PCIC_EVENT_INSERTION: 471 s = splhigh(); 472 while (1) { 473 struct pcic_event *pe1, *pe2; 474 475 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 476 break; 477 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 478 break; 479 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 480 break; 481 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 482 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 483 pe_q); 484 free(pe1, M_TEMP); 485 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 486 pe_q); 487 free(pe2, M_TEMP); 488 } 489 } 490 splx(s); 491 492 DPRINTF(("%s: insertion event\n", 493 h->ph_parent->dv_xname)); 494 pcic_attach_card(h); 495 break; 496 497 case PCIC_EVENT_REMOVAL: 498 s = splhigh(); 499 while (1) { 500 struct pcic_event *pe1, *pe2; 501 502 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 503 break; 504 if (pe1->pe_type != PCIC_EVENT_INSERTION) 505 break; 506 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 507 break; 508 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 509 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 510 pe_q); 511 free(pe1, M_TEMP); 512 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 513 pe_q); 514 free(pe2, M_TEMP); 515 } 516 } 517 splx(s); 518 519 DPRINTF(("%s: removal event\n", 520 h->ph_parent->dv_xname)); 521 pcic_detach_card(h, DETACH_FORCE); 522 break; 523 524 default: 525 panic("pcic_event_thread: unknown event %d", 526 pe->pe_type); 527 } 528 free(pe, M_TEMP); 529 } 530 531 h->event_thread = NULL; 532 533 /* In case parent is waiting for us to exit. */ 534 wakeup(sc); 535 536 kthread_exit(0); 537 } 538 539 int 540 pcic_submatch(parent, cf, aux) 541 struct device *parent; 542 struct cfdata *cf; 543 void *aux; 544 { 545 546 struct pcmciabus_attach_args *paa = aux; 547 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 548 549 switch (h->sock) { 550 case C0SA: 551 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 552 PCMCIABUSCF_CONTROLLER_DEFAULT && 553 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 554 return 0; 555 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 556 PCMCIABUSCF_SOCKET_DEFAULT && 557 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 558 return 0; 559 560 break; 561 case C0SB: 562 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 563 PCMCIABUSCF_CONTROLLER_DEFAULT && 564 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 565 return 0; 566 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 567 PCMCIABUSCF_SOCKET_DEFAULT && 568 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 569 return 0; 570 571 break; 572 case C1SA: 573 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 574 PCMCIABUSCF_CONTROLLER_DEFAULT && 575 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 576 return 0; 577 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 578 PCMCIABUSCF_SOCKET_DEFAULT && 579 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 580 return 0; 581 582 break; 583 case C1SB: 584 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 585 PCMCIABUSCF_CONTROLLER_DEFAULT && 586 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 587 return 0; 588 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 589 PCMCIABUSCF_SOCKET_DEFAULT && 590 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 591 return 0; 592 593 break; 594 default: 595 panic("unknown pcic socket"); 596 } 597 598 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 599 } 600 601 int 602 pcic_print(arg, pnp) 603 void *arg; 604 const char *pnp; 605 { 606 struct pcmciabus_attach_args *paa = arg; 607 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 608 609 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 610 if (pnp) 611 printf("pcmcia at %s", pnp); 612 613 switch (h->sock) { 614 case C0SA: 615 printf(" controller 0 socket 0"); 616 break; 617 case C0SB: 618 printf(" controller 0 socket 1"); 619 break; 620 case C1SA: 621 printf(" controller 1 socket 0"); 622 break; 623 case C1SB: 624 printf(" controller 1 socket 1"); 625 break; 626 default: 627 panic("unknown pcic socket"); 628 } 629 630 return (UNCONF); 631 } 632 633 void 634 pcic_poll_intr(arg) 635 void *arg; 636 { 637 struct pcic_softc *sc; 638 int i, s; 639 640 s = spltty(); 641 sc = arg; 642 for (i = 0; i < PCIC_NSLOTS; i++) 643 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 644 (void)pcic_intr_socket(&sc->handle[i]); 645 timeout(pcic_poll_intr, sc, hz / 2); 646 splx(s); 647 } 648 649 int 650 pcic_intr(arg) 651 void *arg; 652 { 653 struct pcic_softc *sc = arg; 654 int i, ret = 0; 655 656 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 657 658 for (i = 0; i < PCIC_NSLOTS; i++) 659 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 660 ret += pcic_intr_socket(&sc->handle[i]); 661 662 return (ret ? 1 : 0); 663 } 664 665 int 666 pcic_intr_socket(h) 667 struct pcic_handle *h; 668 { 669 int cscreg; 670 671 cscreg = pcic_read(h, PCIC_CSC); 672 673 cscreg &= (PCIC_CSC_GPI | 674 PCIC_CSC_CD | 675 PCIC_CSC_READY | 676 PCIC_CSC_BATTWARN | 677 PCIC_CSC_BATTDEAD); 678 679 if (cscreg & PCIC_CSC_GPI) { 680 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 681 } 682 if (cscreg & PCIC_CSC_CD) { 683 int statreg; 684 685 statreg = pcic_read(h, PCIC_IF_STATUS); 686 687 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 688 statreg)); 689 690 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 691 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 692 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 693 DPRINTF(("%s: enqueing INSERTION event\n", 694 h->ph_parent->dv_xname)); 695 pcic_queue_event(h, PCIC_EVENT_INSERTION); 696 } 697 h->laststate = PCIC_LASTSTATE_PRESENT; 698 } else { 699 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 700 /* Deactivate the card now. */ 701 DPRINTF(("%s: deactivating card\n", 702 h->ph_parent->dv_xname)); 703 pcic_deactivate_card(h); 704 705 DPRINTF(("%s: enqueing REMOVAL event\n", 706 h->ph_parent->dv_xname)); 707 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 708 } 709 h->laststate = 710 ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) ? 711 PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 712 } 713 } 714 if (cscreg & PCIC_CSC_READY) { 715 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 716 /* shouldn't happen */ 717 } 718 if (cscreg & PCIC_CSC_BATTWARN) { 719 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 720 h->sock)); 721 } 722 if (cscreg & PCIC_CSC_BATTDEAD) { 723 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 724 h->sock)); 725 } 726 return (cscreg ? 1 : 0); 727 } 728 729 void 730 pcic_queue_event(h, event) 731 struct pcic_handle *h; 732 int event; 733 { 734 struct pcic_event *pe; 735 int s; 736 737 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 738 if (pe == NULL) 739 panic("pcic_queue_event: can't allocate event"); 740 741 pe->pe_type = event; 742 s = splhigh(); 743 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 744 splx(s); 745 wakeup(&h->events); 746 } 747 748 void 749 pcic_attach_card(h) 750 struct pcic_handle *h; 751 { 752 753 if (!(h->flags & PCIC_FLAG_CARDP)) { 754 /* call the MI attach function */ 755 pcmcia_card_attach(h->pcmcia); 756 757 h->flags |= PCIC_FLAG_CARDP; 758 } else { 759 DPRINTF(("pcic_attach_card: already attached")); 760 } 761 } 762 763 void 764 pcic_detach_card(h, flags) 765 struct pcic_handle *h; 766 int flags; /* DETACH_* */ 767 { 768 769 if (h->flags & PCIC_FLAG_CARDP) { 770 h->flags &= ~PCIC_FLAG_CARDP; 771 772 /* call the MI detach function */ 773 pcmcia_card_detach(h->pcmcia, flags); 774 } else { 775 DPRINTF(("pcic_detach_card: already detached")); 776 } 777 } 778 779 void 780 pcic_deactivate_card(h) 781 struct pcic_handle *h; 782 { 783 784 /* call the MI deactivate function */ 785 pcmcia_card_deactivate(h->pcmcia); 786 787 /* power down the socket */ 788 pcic_write(h, PCIC_PWRCTL, 0); 789 790 /* reset the socket */ 791 pcic_write(h, PCIC_INTR, 0); 792 } 793 794 int 795 pcic_chip_mem_alloc(pch, size, pcmhp) 796 pcmcia_chipset_handle_t pch; 797 bus_size_t size; 798 struct pcmcia_mem_handle *pcmhp; 799 { 800 struct pcic_handle *h = (struct pcic_handle *) pch; 801 bus_space_handle_t memh; 802 bus_addr_t addr; 803 bus_size_t sizepg; 804 int i, mask, mhandle; 805 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 806 807 /* out of sc->memh, allocate as many pages as necessary */ 808 809 /* convert size to PCIC pages */ 810 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 811 if (sizepg > PCIC_MAX_MEM_PAGES) 812 return (1); 813 814 mask = (1 << sizepg) - 1; 815 816 addr = 0; /* XXX gcc -Wuninitialized */ 817 mhandle = 0; /* XXX gcc -Wuninitialized */ 818 819 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 820 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 821 if (bus_space_subregion(sc->memt, sc->memh, 822 i * PCIC_MEM_PAGESIZE, 823 sizepg * PCIC_MEM_PAGESIZE, &memh)) 824 return (1); 825 mhandle = mask << i; 826 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 827 sc->subregionmask &= ~(mhandle); 828 pcmhp->memt = sc->memt; 829 pcmhp->memh = memh; 830 pcmhp->addr = addr; 831 pcmhp->size = size; 832 pcmhp->mhandle = mhandle; 833 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 834 return (0); 835 } 836 } 837 838 return (1); 839 } 840 841 void 842 pcic_chip_mem_free(pch, pcmhp) 843 pcmcia_chipset_handle_t pch; 844 struct pcmcia_mem_handle *pcmhp; 845 { 846 struct pcic_handle *h = (struct pcic_handle *) pch; 847 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 848 849 sc->subregionmask |= pcmhp->mhandle; 850 } 851 852 static struct mem_map_index_st { 853 int sysmem_start_lsb; 854 int sysmem_start_msb; 855 int sysmem_stop_lsb; 856 int sysmem_stop_msb; 857 int cardmem_lsb; 858 int cardmem_msb; 859 int memenable; 860 } mem_map_index[] = { 861 { 862 PCIC_SYSMEM_ADDR0_START_LSB, 863 PCIC_SYSMEM_ADDR0_START_MSB, 864 PCIC_SYSMEM_ADDR0_STOP_LSB, 865 PCIC_SYSMEM_ADDR0_STOP_MSB, 866 PCIC_CARDMEM_ADDR0_LSB, 867 PCIC_CARDMEM_ADDR0_MSB, 868 PCIC_ADDRWIN_ENABLE_MEM0, 869 }, 870 { 871 PCIC_SYSMEM_ADDR1_START_LSB, 872 PCIC_SYSMEM_ADDR1_START_MSB, 873 PCIC_SYSMEM_ADDR1_STOP_LSB, 874 PCIC_SYSMEM_ADDR1_STOP_MSB, 875 PCIC_CARDMEM_ADDR1_LSB, 876 PCIC_CARDMEM_ADDR1_MSB, 877 PCIC_ADDRWIN_ENABLE_MEM1, 878 }, 879 { 880 PCIC_SYSMEM_ADDR2_START_LSB, 881 PCIC_SYSMEM_ADDR2_START_MSB, 882 PCIC_SYSMEM_ADDR2_STOP_LSB, 883 PCIC_SYSMEM_ADDR2_STOP_MSB, 884 PCIC_CARDMEM_ADDR2_LSB, 885 PCIC_CARDMEM_ADDR2_MSB, 886 PCIC_ADDRWIN_ENABLE_MEM2, 887 }, 888 { 889 PCIC_SYSMEM_ADDR3_START_LSB, 890 PCIC_SYSMEM_ADDR3_START_MSB, 891 PCIC_SYSMEM_ADDR3_STOP_LSB, 892 PCIC_SYSMEM_ADDR3_STOP_MSB, 893 PCIC_CARDMEM_ADDR3_LSB, 894 PCIC_CARDMEM_ADDR3_MSB, 895 PCIC_ADDRWIN_ENABLE_MEM3, 896 }, 897 { 898 PCIC_SYSMEM_ADDR4_START_LSB, 899 PCIC_SYSMEM_ADDR4_START_MSB, 900 PCIC_SYSMEM_ADDR4_STOP_LSB, 901 PCIC_SYSMEM_ADDR4_STOP_MSB, 902 PCIC_CARDMEM_ADDR4_LSB, 903 PCIC_CARDMEM_ADDR4_MSB, 904 PCIC_ADDRWIN_ENABLE_MEM4, 905 }, 906 }; 907 908 void 909 pcic_chip_do_mem_map(h, win) 910 struct pcic_handle *h; 911 int win; 912 { 913 int reg; 914 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 915 int mem8 = 916 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 917 918 DPRINTF(("mem8 %d\n", mem8)); 919 /* mem8 = 1; */ 920 921 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 922 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 923 pcic_write(h, mem_map_index[win].sysmem_start_msb, 924 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 925 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 926 927 #if 0 928 /* XXX do I want 16 bit all the time? */ 929 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 930 #endif 931 932 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 933 ((h->mem[win].addr + h->mem[win].size) >> 934 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 935 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 936 (((h->mem[win].addr + h->mem[win].size) >> 937 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 938 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 939 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 940 941 pcic_write(h, mem_map_index[win].cardmem_lsb, 942 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 943 pcic_write(h, mem_map_index[win].cardmem_msb, 944 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 945 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 946 ((kind == PCMCIA_MEM_ATTR) ? 947 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 948 949 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 950 reg |= (mem_map_index[win].memenable | 951 (mem8 ? 0 : PCIC_ADDRWIN_ENABLE_MEMCS16)); 952 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 953 954 delay(100); 955 956 #ifdef PCICDEBUG 957 { 958 int r1, r2, r3, r4, r5, r6; 959 960 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 961 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 962 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 963 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 964 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 965 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 966 967 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 968 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 969 } 970 #endif 971 } 972 973 int 974 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 975 pcmcia_chipset_handle_t pch; 976 int kind; 977 bus_addr_t card_addr; 978 bus_size_t size; 979 struct pcmcia_mem_handle *pcmhp; 980 bus_addr_t *offsetp; 981 int *windowp; 982 { 983 struct pcic_handle *h = (struct pcic_handle *) pch; 984 bus_addr_t busaddr; 985 long card_offset; 986 int i, win; 987 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 988 989 win = -1; 990 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 991 i++) { 992 if ((h->memalloc & (1 << i)) == 0) { 993 win = i; 994 h->memalloc |= (1 << i); 995 break; 996 } 997 } 998 999 if (win == -1) 1000 return (1); 1001 1002 *windowp = win; 1003 1004 /* XXX this is pretty gross */ 1005 1006 if (sc->memt != pcmhp->memt) 1007 panic("pcic_chip_mem_map memt is bogus"); 1008 1009 busaddr = pcmhp->addr; 1010 1011 /* 1012 * compute the address offset to the pcmcia address space for the 1013 * pcic. this is intentionally signed. The masks and shifts below 1014 * will cause TRT to happen in the pcic registers. Deal with making 1015 * sure the address is aligned, and return the alignment offset. 1016 */ 1017 1018 *offsetp = card_addr % PCIC_MEM_ALIGN; 1019 card_addr -= *offsetp; 1020 1021 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1022 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1023 (u_long) card_addr)); 1024 1025 /* 1026 * include the offset in the size, and decrement size by one, since 1027 * the hw wants start/stop 1028 */ 1029 size += *offsetp - 1; 1030 1031 card_offset = (((long) card_addr) - ((long) busaddr)); 1032 1033 h->mem[win].addr = busaddr; 1034 h->mem[win].size = size; 1035 h->mem[win].offset = card_offset; 1036 h->mem[win].kind = kind; 1037 1038 pcic_chip_do_mem_map(h, win); 1039 1040 return (0); 1041 } 1042 1043 void 1044 pcic_chip_mem_unmap(pch, window) 1045 pcmcia_chipset_handle_t pch; 1046 int window; 1047 { 1048 struct pcic_handle *h = (struct pcic_handle *) pch; 1049 int reg; 1050 1051 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1052 panic("pcic_chip_mem_unmap: window out of range"); 1053 1054 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1055 reg &= ~mem_map_index[window].memenable; 1056 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1057 1058 h->memalloc &= ~(1 << window); 1059 } 1060 1061 int 1062 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1063 pcmcia_chipset_handle_t pch; 1064 bus_addr_t start; 1065 bus_size_t size; 1066 bus_size_t align; 1067 struct pcmcia_io_handle *pcihp; 1068 { 1069 struct pcic_handle *h = (struct pcic_handle *) pch; 1070 bus_space_tag_t iot; 1071 bus_space_handle_t ioh; 1072 bus_addr_t ioaddr; 1073 int flags = 0; 1074 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1075 1076 /* 1077 * Allocate some arbitrary I/O space. 1078 */ 1079 1080 iot = sc->iot; 1081 1082 if (start) { 1083 ioaddr = start; 1084 if (bus_space_map(iot, start, size, 0, &ioh)) 1085 return (1); 1086 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1087 (u_long) ioaddr, (u_long) size)); 1088 } else { 1089 flags |= PCMCIA_IO_ALLOCATED; 1090 if (bus_space_alloc(iot, sc->iobase, 1091 sc->iobase + sc->iosize, size, align, 0, 0, 1092 &ioaddr, &ioh)) 1093 return (1); 1094 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1095 (u_long) ioaddr, (u_long) size)); 1096 } 1097 1098 pcihp->iot = iot; 1099 pcihp->ioh = ioh; 1100 pcihp->addr = ioaddr; 1101 pcihp->size = size; 1102 pcihp->flags = flags; 1103 1104 return (0); 1105 } 1106 1107 void 1108 pcic_chip_io_free(pch, pcihp) 1109 pcmcia_chipset_handle_t pch; 1110 struct pcmcia_io_handle *pcihp; 1111 { 1112 bus_space_tag_t iot = pcihp->iot; 1113 bus_space_handle_t ioh = pcihp->ioh; 1114 bus_size_t size = pcihp->size; 1115 1116 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1117 bus_space_free(iot, ioh, size); 1118 else 1119 bus_space_unmap(iot, ioh, size); 1120 } 1121 1122 1123 static struct io_map_index_st { 1124 int start_lsb; 1125 int start_msb; 1126 int stop_lsb; 1127 int stop_msb; 1128 int ioenable; 1129 int ioctlmask; 1130 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1131 } io_map_index[] = { 1132 { 1133 PCIC_IOADDR0_START_LSB, 1134 PCIC_IOADDR0_START_MSB, 1135 PCIC_IOADDR0_STOP_LSB, 1136 PCIC_IOADDR0_STOP_MSB, 1137 PCIC_ADDRWIN_ENABLE_IO0, 1138 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1139 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1140 { 1141 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1142 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1143 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1144 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1145 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1146 }, 1147 }, 1148 { 1149 PCIC_IOADDR1_START_LSB, 1150 PCIC_IOADDR1_START_MSB, 1151 PCIC_IOADDR1_STOP_LSB, 1152 PCIC_IOADDR1_STOP_MSB, 1153 PCIC_ADDRWIN_ENABLE_IO1, 1154 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1155 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1156 { 1157 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1158 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1159 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1160 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1161 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1162 }, 1163 }, 1164 }; 1165 1166 void 1167 pcic_chip_do_io_map(h, win) 1168 struct pcic_handle *h; 1169 int win; 1170 { 1171 int reg; 1172 1173 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1174 win, (long) h->io[win].addr, (long) h->io[win].size, 1175 h->io[win].width * 8)); 1176 1177 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1178 pcic_write(h, io_map_index[win].start_msb, 1179 (h->io[win].addr >> 8) & 0xff); 1180 1181 pcic_write(h, io_map_index[win].stop_lsb, 1182 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1183 pcic_write(h, io_map_index[win].stop_msb, 1184 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1185 1186 reg = pcic_read(h, PCIC_IOCTL); 1187 reg &= ~io_map_index[win].ioctlmask; 1188 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1189 pcic_write(h, PCIC_IOCTL, reg); 1190 1191 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1192 reg |= io_map_index[win].ioenable; 1193 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1194 } 1195 1196 int 1197 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1198 pcmcia_chipset_handle_t pch; 1199 int width; 1200 bus_addr_t offset; 1201 bus_size_t size; 1202 struct pcmcia_io_handle *pcihp; 1203 int *windowp; 1204 { 1205 struct pcic_handle *h = (struct pcic_handle *) pch; 1206 bus_addr_t ioaddr = pcihp->addr + offset; 1207 int i, win; 1208 #ifdef PCICDEBUG 1209 static char *width_names[] = { "auto", "io8", "io16" }; 1210 #endif 1211 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1212 1213 /* XXX Sanity check offset/size. */ 1214 1215 win = -1; 1216 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1217 if ((h->ioalloc & (1 << i)) == 0) { 1218 win = i; 1219 h->ioalloc |= (1 << i); 1220 break; 1221 } 1222 } 1223 1224 if (win == -1) 1225 return (1); 1226 1227 *windowp = win; 1228 1229 /* XXX this is pretty gross */ 1230 1231 if (sc->iot != pcihp->iot) 1232 panic("pcic_chip_io_map iot is bogus"); 1233 1234 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1235 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1236 1237 /* XXX wtf is this doing here? */ 1238 1239 printf(" port 0x%lx", (u_long) ioaddr); 1240 if (size > 1) 1241 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1242 1243 h->io[win].addr = ioaddr; 1244 h->io[win].size = size; 1245 h->io[win].width = width; 1246 1247 pcic_chip_do_io_map(h, win); 1248 1249 return (0); 1250 } 1251 1252 void 1253 pcic_chip_io_unmap(pch, window) 1254 pcmcia_chipset_handle_t pch; 1255 int window; 1256 { 1257 struct pcic_handle *h = (struct pcic_handle *) pch; 1258 int reg; 1259 1260 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1261 panic("pcic_chip_io_unmap: window out of range"); 1262 1263 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1264 reg &= ~io_map_index[window].ioenable; 1265 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1266 1267 h->ioalloc &= ~(1 << window); 1268 } 1269 1270 static void 1271 pcic_wait_ready(h) 1272 struct pcic_handle *h; 1273 { 1274 int i; 1275 1276 /* wait an initial 10ms for quick cards */ 1277 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1278 return; 1279 pcic_delay(h, 10, "pccwr0"); 1280 for (i = 0; i < 50; i++) { 1281 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1282 return; 1283 /* wait .1s (100ms) each iteration now */ 1284 pcic_delay(h, 100, "pccwr1"); 1285 #ifdef PCICDEBUG 1286 if (pcic_debug) { 1287 if ((i > 20) && (i % 100 == 99)) 1288 printf("."); 1289 } 1290 #endif 1291 } 1292 1293 #ifdef DIAGNOSTIC 1294 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1295 pcic_read(h, PCIC_IF_STATUS)); 1296 #endif 1297 } 1298 1299 /* 1300 * Perform long (msec order) delay. 1301 */ 1302 static void 1303 pcic_delay(h, timo, wmesg) 1304 struct pcic_handle *h; 1305 int timo; /* in ms. must not be zero */ 1306 const char *wmesg; 1307 { 1308 1309 #ifdef DIAGNOSTIC 1310 if (timo <= 0) { 1311 printf("called with timeout %d\n", timo); 1312 panic("pcic_delay"); 1313 } 1314 if (curproc == NULL) { 1315 printf("called in interrupt context\n"); 1316 panic("pcic_delay"); 1317 } 1318 if (h->event_thread == NULL) { 1319 printf("no event thread\n"); 1320 panic("pcic_delay"); 1321 } 1322 #endif 1323 DPRINTF(("pcic_delay: %p, sleep %d ms\n", h->event_thread, timo)); 1324 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1325 } 1326 1327 void 1328 pcic_chip_socket_enable(pch) 1329 pcmcia_chipset_handle_t pch; 1330 { 1331 struct pcic_handle *h = (struct pcic_handle *) pch; 1332 int cardtype, win, intr, pwr; 1333 #if defined(DIAGNOSTIC) || defined(PCICDEBUG) 1334 int reg; 1335 #endif 1336 1337 /* disable interrupts */ 1338 intr = pcic_read(h, PCIC_INTR); 1339 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1340 pcic_write(h, PCIC_INTR, intr); 1341 1342 /* power down the socket to reset it, clear the card reset pin */ 1343 pwr = 0; 1344 pcic_write(h, PCIC_PWRCTL, pwr); 1345 1346 /* 1347 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1348 * we are changing Vcc (Toff). 1349 */ 1350 pcic_delay(h, 300 + 100, "pccen0"); 1351 1352 #ifdef VADEM_POWER_HACK 1353 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1354 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1355 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1356 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1357 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1358 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1359 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1360 #endif 1361 /* power up the socket */ 1362 pwr |= PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_PWR_ENABLE; 1363 pcic_write(h, PCIC_PWRCTL, pwr); 1364 1365 /* 1366 * wait 100ms until power raise (Tpr) and 20ms to become 1367 * stable (Tsu(Vcc)). 1368 * 1369 * some machines require some more time to be settled 1370 * (300ms is added here). 1371 */ 1372 pcic_delay(h, 100 + 20 + 300, "pccen1"); 1373 pwr |= PCIC_PWRCTL_OE; 1374 pcic_write(h, PCIC_PWRCTL, pwr); 1375 1376 /* now make sure we have reset# active */ 1377 intr &= ~PCIC_INTR_RESET; 1378 pcic_write(h, PCIC_INTR, intr); 1379 1380 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | 1381 PCIC_PWRCTL_OE | PCIC_PWRCTL_PWR_ENABLE); 1382 /* 1383 * hold RESET at least 10us, this is a min allow for slop in 1384 * delay routine. 1385 */ 1386 delay(20); 1387 1388 /* clear the reset flag */ 1389 intr |= PCIC_INTR_RESET; 1390 pcic_write(h, PCIC_INTR, intr); 1391 1392 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1393 pcic_delay(h, 20, "pccen2"); 1394 1395 #ifdef DIAGNOSTIC 1396 reg = pcic_read(h, PCIC_IF_STATUS); 1397 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1398 printf("pcic_chip_socket_enable: status %x", reg); 1399 } 1400 #endif 1401 /* wait for the chip to finish initializing */ 1402 pcic_wait_ready(h); 1403 1404 /* zero out the address windows */ 1405 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1406 1407 /* set the card type and enable the interrupt */ 1408 cardtype = pcmcia_card_gettype(h->pcmcia); 1409 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1410 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 1411 pcic_write(h, PCIC_INTR, intr); 1412 1413 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1414 h->ph_parent->dv_xname, h->sock, 1415 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1416 1417 /* reinstall all the memory and io mappings */ 1418 for (win = 0; win < PCIC_MEM_WINS; win++) 1419 if (h->memalloc & (1 << win)) 1420 pcic_chip_do_mem_map(h, win); 1421 for (win = 0; win < PCIC_IO_WINS; win++) 1422 if (h->ioalloc & (1 << win)) 1423 pcic_chip_do_io_map(h, win); 1424 1425 /* finally enable the interrupt */ 1426 intr |= h->ih_irq; 1427 pcic_write(h, PCIC_INTR, intr); 1428 } 1429 1430 void 1431 pcic_chip_socket_disable(pch) 1432 pcmcia_chipset_handle_t pch; 1433 { 1434 struct pcic_handle *h = (struct pcic_handle *) pch; 1435 int intr; 1436 1437 DPRINTF(("pcic_chip_socket_disable\n")); 1438 1439 /* disable interrupts */ 1440 intr = pcic_read(h, PCIC_INTR); 1441 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1442 pcic_write(h, PCIC_INTR, intr); 1443 1444 /* power down the socket */ 1445 pcic_write(h, PCIC_PWRCTL, 0); 1446 } 1447 1448 static u_int8_t 1449 st_pcic_read(h, idx) 1450 struct pcic_handle *h; 1451 int idx; 1452 { 1453 1454 if (idx != -1) 1455 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1456 h->sock + idx); 1457 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1458 } 1459 1460 static void 1461 st_pcic_write(h, idx, data) 1462 struct pcic_handle *h; 1463 int idx; 1464 u_int8_t data; 1465 { 1466 1467 if (idx != -1) 1468 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1469 h->sock + idx); 1470 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1471 } 1472
Indexes created Mon Sep 29 03:10:08 GMT 2025