i82365.c revision 1.50
1 /* $NetBSD: i82365.c,v 1.50 2000/02/25 04:24:37 mycroft Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 7 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Marc Horowitz. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/kthread.h> 43 44 #include <vm/vm.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 52 #include <dev/ic/i82365reg.h> 53 #include <dev/ic/i82365var.h> 54 55 #include "locators.h" 56 57 #ifdef PCICDEBUG 58 int pcic_debug = 0; 59 #define DPRINTF(arg) if (pcic_debug) printf arg; 60 #else 61 #define DPRINTF(arg) 62 #endif 63 64 /* 65 * Individual drivers will allocate their own memory and io regions. Memory 66 * regions must be a multiple of 4k, aligned on a 4k boundary. 67 */ 68 69 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 70 71 void pcic_attach_socket __P((struct pcic_handle *)); 72 void pcic_attach_socket_finish __P((struct pcic_handle *)); 73 74 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 75 int pcic_print __P((void *arg, const char *pnp)); 76 int pcic_intr_socket __P((struct pcic_handle *)); 77 void pcic_poll_intr __P((void *)); 78 79 void pcic_attach_card __P((struct pcic_handle *)); 80 void pcic_detach_card __P((struct pcic_handle *, int)); 81 void pcic_deactivate_card __P((struct pcic_handle *)); 82 83 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 84 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 85 86 void pcic_create_event_thread __P((void *)); 87 void pcic_event_thread __P((void *)); 88 89 void pcic_queue_event __P((struct pcic_handle *, int)); 90 void pcic_power __P((int, void *)); 91 92 static void pcic_wait_ready __P((struct pcic_handle *)); 93 static void pcic_delay __P((struct pcic_handle *, int, const char *)); 94 95 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 96 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 97 98 int 99 pcic_ident_ok(ident) 100 int ident; 101 { 102 /* this is very empirical and heuristic */ 103 104 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 105 return (0); 106 107 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 108 #ifdef DIAGNOSTIC 109 printf("pcic: does not support memory and I/O cards, " 110 "ignored (ident=%0x)\n", ident); 111 #endif 112 return (0); 113 } 114 return (1); 115 } 116 117 int 118 pcic_vendor(h) 119 struct pcic_handle *h; 120 { 121 int reg; 122 123 /* 124 * the chip_id of the cirrus toggles between 11 and 00 after a write. 125 * weird. 126 */ 127 128 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 129 reg = pcic_read(h, -1); 130 131 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 132 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 133 reg = pcic_read(h, -1); 134 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 135 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 136 return (PCIC_VENDOR_CIRRUS_PD672X); 137 else 138 return (PCIC_VENDOR_CIRRUS_PD6710); 139 } 140 } 141 142 reg = pcic_read(h, PCIC_IDENT); 143 144 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 145 return (PCIC_VENDOR_I82365SLR0); 146 else 147 return (PCIC_VENDOR_I82365SLR1); 148 149 return (PCIC_VENDOR_UNKNOWN); 150 } 151 152 char * 153 pcic_vendor_to_string(vendor) 154 int vendor; 155 { 156 switch (vendor) { 157 case PCIC_VENDOR_I82365SLR0: 158 return ("Intel 82365SL Revision 0"); 159 case PCIC_VENDOR_I82365SLR1: 160 return ("Intel 82365SL Revision 1"); 161 case PCIC_VENDOR_CIRRUS_PD6710: 162 return ("Cirrus PD6710"); 163 case PCIC_VENDOR_CIRRUS_PD672X: 164 return ("Cirrus PD672X"); 165 } 166 167 return ("Unknown controller"); 168 } 169 170 void 171 pcic_attach(sc) 172 struct pcic_softc *sc; 173 { 174 int count, i, reg, chip, socket, intr; 175 176 DPRINTF(("pcic ident regs:")); 177 178 /* find and configure for the available sockets */ 179 count = 0; 180 for (i = 0; i < PCIC_NSLOTS; i++) { 181 chip = i / 2; 182 socket = i % 2; 183 sc->handle[i].ph_parent = (struct device *)sc; 184 sc->handle[i].chip = chip; 185 sc->handle[i].sock = chip * PCIC_CHIP_OFFSET + 186 socket * PCIC_SOCKET_OFFSET; 187 /* initialize pcic_read and pcic_write functions */ 188 sc->handle[i].ph_read = st_pcic_read; 189 sc->handle[i].ph_write = st_pcic_write; 190 sc->handle[i].ph_bus_t = sc->iot; 191 sc->handle[i].ph_bus_h = sc->ioh; 192 /* need to read vendor -- for cirrus to report no xtra chip */ 193 if (socket == 0) 194 sc->handle[i].vendor = sc->handle[i + 1].vendor = 195 pcic_vendor(&sc->handle[i]); 196 reg = pcic_read(&sc->handle[i], PCIC_IDENT); 197 if (!pcic_ident_ok(reg)) { 198 sc->handle[i].flags = 0; 199 } else { 200 sc->handle[i].flags = PCIC_FLAG_SOCKETP; 201 count++; 202 } 203 sc->handle[i].laststate = PCIC_LASTSTATE_EMPTY; 204 DPRINTF(("ident reg 0x%02x\n", reg)); 205 } 206 if (count == 0) 207 panic("pcic_attach: attach found no sockets"); 208 209 for (i = 0; i < PCIC_NSLOTS; i++) { 210 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 211 SIMPLEQ_INIT(&sc->handle[i].events); 212 213 /* disable interrupts -- for now */ 214 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 215 intr = pcic_read(&sc->handle[i], PCIC_INTR); 216 DPRINTF(("intr was 0x%02x\n", intr)); 217 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | 218 PCIC_INTR_IRQ_MASK); 219 pcic_write(&sc->handle[i], PCIC_INTR, intr); 220 pcic_read(&sc->handle[i], PCIC_CSC); 221 } 222 } 223 224 /* print detected info */ 225 for (i = 0; i < PCIC_NSLOTS; i += 2) { 226 chip = i / 2; 227 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 228 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 229 continue; 230 231 printf("%s: controller %d (%s) has ", sc->dev.dv_xname, chip, 232 pcic_vendor_to_string(sc->handle[i].vendor)); 233 234 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) && 235 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP)) 236 printf("sockets A and B\n"); 237 else if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 238 printf("socket A only\n"); 239 else 240 printf("socket B only\n"); 241 } 242 } 243 244 /* 245 * attach the sockets before we know what interrupts we have 246 */ 247 void 248 pcic_attach_sockets(sc) 249 struct pcic_softc *sc; 250 { 251 int i; 252 253 for (i = 0; i < PCIC_NSLOTS; i++) 254 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 255 pcic_attach_socket(&sc->handle[i]); 256 } 257 258 void 259 pcic_power(why, arg) 260 int why; 261 void *arg; 262 { 263 struct pcic_handle *h = (struct pcic_handle *)arg; 264 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 265 int reg; 266 267 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 268 269 if (h->flags & PCIC_FLAG_SOCKETP) { 270 if ((why == PWR_RESUME) && 271 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 272 #ifdef PCICDEBUG 273 char bitbuf[64]; 274 #endif 275 reg = PCIC_CSC_INTR_CD_ENABLE; 276 if (sc->irq != -1) 277 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 278 pcic_write(h, PCIC_CSC_INTR, reg); 279 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 280 sc->dev.dv_xname, 281 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 282 PCIC_CSC_INTR_FORMAT, 283 bitbuf, sizeof(bitbuf)))); 284 } 285 286 /* 287 * check for card insertion or removal during suspend period. 288 * XXX: the code can't cope with card swap (remove then insert). 289 * how can we detect such situation? 290 */ 291 if (why == PWR_RESUME) 292 (void)pcic_intr_socket(h); 293 } 294 } 295 296 297 /* 298 * attach a socket -- we don't know about irqs yet 299 */ 300 void 301 pcic_attach_socket(h) 302 struct pcic_handle *h; 303 { 304 struct pcmciabus_attach_args paa; 305 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 306 307 /* initialize the rest of the handle */ 308 309 h->shutdown = 0; 310 h->memalloc = 0; 311 h->ioalloc = 0; 312 h->ih_irq = 0; 313 314 /* now, config one pcmcia device per socket */ 315 316 paa.paa_busname = "pcmcia"; 317 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 318 paa.pch = (pcmcia_chipset_handle_t) h; 319 paa.iobase = sc->iobase; 320 paa.iosize = sc->iosize; 321 322 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, pcic_submatch); 323 if (h->pcmcia == NULL) { 324 h->flags &= ~PCIC_FLAG_SOCKETP; 325 return; 326 } 327 328 /* 329 * queue creation of a kernel thread to handle insert/removal events. 330 */ 331 #ifdef DIAGNOSTIC 332 if (h->event_thread != NULL) 333 panic("pcic_attach_socket: event thread"); 334 #endif 335 config_pending_incr(); 336 kthread_create(pcic_create_event_thread, h); 337 } 338 339 /* 340 * now finish attaching the sockets, we are ready to allocate 341 * interrupts 342 */ 343 void 344 pcic_attach_sockets_finish(sc) 345 struct pcic_softc *sc; 346 { 347 int i; 348 349 for (i = 0; i < PCIC_NSLOTS; i++) 350 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) && 351 sc->handle[i].pcmcia != NULL) 352 pcic_attach_socket_finish(&sc->handle[i]); 353 } 354 355 /* 356 * finishing attaching the socket. Interrupts may now be on 357 * if so expects the pcic interrupt to be blocked 358 */ 359 void 360 pcic_attach_socket_finish(h) 361 struct pcic_handle *h; 362 { 363 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 364 int reg; 365 366 DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 367 (long) (h - &sc->handle[0]))); 368 /* 369 * Set up a powerhook to ensure it continues to interrupt on 370 * card detect even after suspend. 371 * (this works around a bug seen in suspend-to-disk on the 372 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 373 */ 374 powerhook_establish(pcic_power, h); 375 376 /* enable interrupts on card detect, poll for them if no irq avail */ 377 reg = PCIC_CSC_INTR_CD_ENABLE; 378 if (sc->irq == -1) 379 timeout(pcic_poll_intr, sc, hz / 2); 380 else 381 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 382 pcic_write(h, PCIC_CSC_INTR, reg); 383 384 /* steer above mgmt interrupt to configured place */ 385 reg = pcic_read(h, PCIC_INTR); 386 reg &= ~PCIC_INTR_ENABLE; 387 pcic_write(h, PCIC_INTR, reg); 388 389 /* clear possible card detect interrupt */ 390 pcic_read(h, PCIC_CSC); 391 392 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 393 h->vendor)); 394 395 /* unsleep the cirrus controller */ 396 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 397 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 398 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 399 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 400 DPRINTF(("%s: socket %02x was suspended\n", 401 h->ph_parent->dv_xname, h->sock)); 402 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 403 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 404 } 405 } 406 407 /* if there's a card there, then attach it. */ 408 reg = pcic_read(h, PCIC_IF_STATUS); 409 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 410 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 411 pcic_queue_event(h, PCIC_EVENT_INSERTION); 412 h->laststate = PCIC_LASTSTATE_PRESENT; 413 } else { 414 h->laststate = PCIC_LASTSTATE_EMPTY; 415 } 416 } 417 418 void 419 pcic_create_event_thread(arg) 420 void *arg; 421 { 422 struct pcic_handle *h = arg; 423 const char *cs; 424 425 switch (h->sock) { 426 case C0SA: 427 cs = "0,0"; 428 break; 429 case C0SB: 430 cs = "0,1"; 431 break; 432 case C1SA: 433 cs = "1,0"; 434 break; 435 case C1SB: 436 cs = "1,1"; 437 break; 438 default: 439 panic("pcic_create_event_thread: unknown pcic socket"); 440 } 441 442 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 443 "%s,%s", h->ph_parent->dv_xname, cs)) { 444 printf("%s: unable to create event thread for sock 0x%02x\n", 445 h->ph_parent->dv_xname, h->sock); 446 panic("pcic_create_event_thread"); 447 } 448 } 449 450 void 451 pcic_event_thread(arg) 452 void *arg; 453 { 454 struct pcic_handle *h = arg; 455 struct pcic_event *pe; 456 int s, first = 1; 457 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 458 459 while (h->shutdown == 0) { 460 s = splhigh(); 461 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 462 splx(s); 463 if (first) { 464 first = 0; 465 config_pending_decr(); 466 } 467 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 468 continue; 469 } else { 470 splx(s); 471 /* sleep .25s to be enqueued chatterling interrupts */ 472 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 473 "pcicss", hz/4); 474 } 475 s = splhigh(); 476 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 477 splx(s); 478 479 switch (pe->pe_type) { 480 case PCIC_EVENT_INSERTION: 481 s = splhigh(); 482 while (1) { 483 struct pcic_event *pe1, *pe2; 484 485 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 486 break; 487 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 488 break; 489 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 490 break; 491 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 492 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 493 pe_q); 494 free(pe1, M_TEMP); 495 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 496 pe_q); 497 free(pe2, M_TEMP); 498 } 499 } 500 splx(s); 501 502 DPRINTF(("%s: insertion event\n", 503 h->ph_parent->dv_xname)); 504 pcic_attach_card(h); 505 break; 506 507 case PCIC_EVENT_REMOVAL: 508 s = splhigh(); 509 while (1) { 510 struct pcic_event *pe1, *pe2; 511 512 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 513 break; 514 if (pe1->pe_type != PCIC_EVENT_INSERTION) 515 break; 516 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 517 break; 518 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 519 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 520 pe_q); 521 free(pe1, M_TEMP); 522 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 523 pe_q); 524 free(pe2, M_TEMP); 525 } 526 } 527 splx(s); 528 529 DPRINTF(("%s: removal event\n", 530 h->ph_parent->dv_xname)); 531 pcic_detach_card(h, DETACH_FORCE); 532 break; 533 534 default: 535 panic("pcic_event_thread: unknown event %d", 536 pe->pe_type); 537 } 538 free(pe, M_TEMP); 539 } 540 541 h->event_thread = NULL; 542 543 /* In case parent is waiting for us to exit. */ 544 wakeup(sc); 545 546 kthread_exit(0); 547 } 548 549 int 550 pcic_submatch(parent, cf, aux) 551 struct device *parent; 552 struct cfdata *cf; 553 void *aux; 554 { 555 556 struct pcmciabus_attach_args *paa = aux; 557 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 558 559 switch (h->sock) { 560 case C0SA: 561 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 562 PCMCIABUSCF_CONTROLLER_DEFAULT && 563 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 564 return 0; 565 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 566 PCMCIABUSCF_SOCKET_DEFAULT && 567 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 568 return 0; 569 570 break; 571 case C0SB: 572 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 573 PCMCIABUSCF_CONTROLLER_DEFAULT && 574 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 575 return 0; 576 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 577 PCMCIABUSCF_SOCKET_DEFAULT && 578 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 579 return 0; 580 581 break; 582 case C1SA: 583 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 584 PCMCIABUSCF_CONTROLLER_DEFAULT && 585 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 586 return 0; 587 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 588 PCMCIABUSCF_SOCKET_DEFAULT && 589 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 590 return 0; 591 592 break; 593 case C1SB: 594 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 595 PCMCIABUSCF_CONTROLLER_DEFAULT && 596 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 597 return 0; 598 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 599 PCMCIABUSCF_SOCKET_DEFAULT && 600 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 601 return 0; 602 603 break; 604 default: 605 panic("unknown pcic socket"); 606 } 607 608 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 609 } 610 611 int 612 pcic_print(arg, pnp) 613 void *arg; 614 const char *pnp; 615 { 616 struct pcmciabus_attach_args *paa = arg; 617 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 618 619 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 620 if (pnp) 621 printf("pcmcia at %s", pnp); 622 623 switch (h->sock) { 624 case C0SA: 625 printf(" controller 0 socket 0"); 626 break; 627 case C0SB: 628 printf(" controller 0 socket 1"); 629 break; 630 case C1SA: 631 printf(" controller 1 socket 0"); 632 break; 633 case C1SB: 634 printf(" controller 1 socket 1"); 635 break; 636 default: 637 panic("unknown pcic socket"); 638 } 639 640 return (UNCONF); 641 } 642 643 void 644 pcic_poll_intr(arg) 645 void *arg; 646 { 647 struct pcic_softc *sc; 648 int i, s; 649 650 s = spltty(); 651 sc = arg; 652 for (i = 0; i < PCIC_NSLOTS; i++) 653 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 654 (void)pcic_intr_socket(&sc->handle[i]); 655 timeout(pcic_poll_intr, sc, hz / 2); 656 splx(s); 657 } 658 659 int 660 pcic_intr(arg) 661 void *arg; 662 { 663 struct pcic_softc *sc = arg; 664 int i, ret = 0; 665 666 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 667 668 for (i = 0; i < PCIC_NSLOTS; i++) 669 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 670 ret += pcic_intr_socket(&sc->handle[i]); 671 672 return (ret ? 1 : 0); 673 } 674 675 int 676 pcic_intr_socket(h) 677 struct pcic_handle *h; 678 { 679 int cscreg; 680 681 cscreg = pcic_read(h, PCIC_CSC); 682 683 cscreg &= (PCIC_CSC_GPI | 684 PCIC_CSC_CD | 685 PCIC_CSC_READY | 686 PCIC_CSC_BATTWARN | 687 PCIC_CSC_BATTDEAD); 688 689 if (cscreg & PCIC_CSC_GPI) { 690 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 691 } 692 if (cscreg & PCIC_CSC_CD) { 693 int statreg; 694 695 statreg = pcic_read(h, PCIC_IF_STATUS); 696 697 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 698 statreg)); 699 700 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 701 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 702 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 703 DPRINTF(("%s: enqueing INSERTION event\n", 704 h->ph_parent->dv_xname)); 705 pcic_queue_event(h, PCIC_EVENT_INSERTION); 706 } 707 h->laststate = PCIC_LASTSTATE_PRESENT; 708 } else { 709 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 710 /* Deactivate the card now. */ 711 DPRINTF(("%s: deactivating card\n", 712 h->ph_parent->dv_xname)); 713 pcic_deactivate_card(h); 714 715 DPRINTF(("%s: enqueing REMOVAL event\n", 716 h->ph_parent->dv_xname)); 717 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 718 } 719 h->laststate = 720 ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) ? 721 PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 722 } 723 } 724 if (cscreg & PCIC_CSC_READY) { 725 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 726 /* shouldn't happen */ 727 } 728 if (cscreg & PCIC_CSC_BATTWARN) { 729 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 730 h->sock)); 731 } 732 if (cscreg & PCIC_CSC_BATTDEAD) { 733 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 734 h->sock)); 735 } 736 return (cscreg ? 1 : 0); 737 } 738 739 void 740 pcic_queue_event(h, event) 741 struct pcic_handle *h; 742 int event; 743 { 744 struct pcic_event *pe; 745 int s; 746 747 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 748 if (pe == NULL) 749 panic("pcic_queue_event: can't allocate event"); 750 751 pe->pe_type = event; 752 s = splhigh(); 753 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 754 splx(s); 755 wakeup(&h->events); 756 } 757 758 void 759 pcic_attach_card(h) 760 struct pcic_handle *h; 761 { 762 763 if (!(h->flags & PCIC_FLAG_CARDP)) { 764 /* call the MI attach function */ 765 pcmcia_card_attach(h->pcmcia); 766 767 h->flags |= PCIC_FLAG_CARDP; 768 } else { 769 DPRINTF(("pcic_attach_card: already attached")); 770 } 771 } 772 773 void 774 pcic_detach_card(h, flags) 775 struct pcic_handle *h; 776 int flags; /* DETACH_* */ 777 { 778 779 if (h->flags & PCIC_FLAG_CARDP) { 780 h->flags &= ~PCIC_FLAG_CARDP; 781 782 /* call the MI detach function */ 783 pcmcia_card_detach(h->pcmcia, flags); 784 } else { 785 DPRINTF(("pcic_detach_card: already detached")); 786 } 787 } 788 789 void 790 pcic_deactivate_card(h) 791 struct pcic_handle *h; 792 { 793 794 /* call the MI deactivate function */ 795 pcmcia_card_deactivate(h->pcmcia); 796 797 /* power down the socket */ 798 pcic_write(h, PCIC_PWRCTL, 0); 799 800 /* reset the socket */ 801 pcic_write(h, PCIC_INTR, 0); 802 } 803 804 int 805 pcic_chip_mem_alloc(pch, size, pcmhp) 806 pcmcia_chipset_handle_t pch; 807 bus_size_t size; 808 struct pcmcia_mem_handle *pcmhp; 809 { 810 struct pcic_handle *h = (struct pcic_handle *) pch; 811 bus_space_handle_t memh; 812 bus_addr_t addr; 813 bus_size_t sizepg; 814 int i, mask, mhandle; 815 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 816 817 /* out of sc->memh, allocate as many pages as necessary */ 818 819 /* convert size to PCIC pages */ 820 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 821 if (sizepg > PCIC_MAX_MEM_PAGES) 822 return (1); 823 824 mask = (1 << sizepg) - 1; 825 826 addr = 0; /* XXX gcc -Wuninitialized */ 827 mhandle = 0; /* XXX gcc -Wuninitialized */ 828 829 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 830 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 831 if (bus_space_subregion(sc->memt, sc->memh, 832 i * PCIC_MEM_PAGESIZE, 833 sizepg * PCIC_MEM_PAGESIZE, &memh)) 834 return (1); 835 mhandle = mask << i; 836 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 837 sc->subregionmask &= ~(mhandle); 838 pcmhp->memt = sc->memt; 839 pcmhp->memh = memh; 840 pcmhp->addr = addr; 841 pcmhp->size = size; 842 pcmhp->mhandle = mhandle; 843 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 844 return (0); 845 } 846 } 847 848 return (1); 849 } 850 851 void 852 pcic_chip_mem_free(pch, pcmhp) 853 pcmcia_chipset_handle_t pch; 854 struct pcmcia_mem_handle *pcmhp; 855 { 856 struct pcic_handle *h = (struct pcic_handle *) pch; 857 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 858 859 sc->subregionmask |= pcmhp->mhandle; 860 } 861 862 static struct mem_map_index_st { 863 int sysmem_start_lsb; 864 int sysmem_start_msb; 865 int sysmem_stop_lsb; 866 int sysmem_stop_msb; 867 int cardmem_lsb; 868 int cardmem_msb; 869 int memenable; 870 } mem_map_index[] = { 871 { 872 PCIC_SYSMEM_ADDR0_START_LSB, 873 PCIC_SYSMEM_ADDR0_START_MSB, 874 PCIC_SYSMEM_ADDR0_STOP_LSB, 875 PCIC_SYSMEM_ADDR0_STOP_MSB, 876 PCIC_CARDMEM_ADDR0_LSB, 877 PCIC_CARDMEM_ADDR0_MSB, 878 PCIC_ADDRWIN_ENABLE_MEM0, 879 }, 880 { 881 PCIC_SYSMEM_ADDR1_START_LSB, 882 PCIC_SYSMEM_ADDR1_START_MSB, 883 PCIC_SYSMEM_ADDR1_STOP_LSB, 884 PCIC_SYSMEM_ADDR1_STOP_MSB, 885 PCIC_CARDMEM_ADDR1_LSB, 886 PCIC_CARDMEM_ADDR1_MSB, 887 PCIC_ADDRWIN_ENABLE_MEM1, 888 }, 889 { 890 PCIC_SYSMEM_ADDR2_START_LSB, 891 PCIC_SYSMEM_ADDR2_START_MSB, 892 PCIC_SYSMEM_ADDR2_STOP_LSB, 893 PCIC_SYSMEM_ADDR2_STOP_MSB, 894 PCIC_CARDMEM_ADDR2_LSB, 895 PCIC_CARDMEM_ADDR2_MSB, 896 PCIC_ADDRWIN_ENABLE_MEM2, 897 }, 898 { 899 PCIC_SYSMEM_ADDR3_START_LSB, 900 PCIC_SYSMEM_ADDR3_START_MSB, 901 PCIC_SYSMEM_ADDR3_STOP_LSB, 902 PCIC_SYSMEM_ADDR3_STOP_MSB, 903 PCIC_CARDMEM_ADDR3_LSB, 904 PCIC_CARDMEM_ADDR3_MSB, 905 PCIC_ADDRWIN_ENABLE_MEM3, 906 }, 907 { 908 PCIC_SYSMEM_ADDR4_START_LSB, 909 PCIC_SYSMEM_ADDR4_START_MSB, 910 PCIC_SYSMEM_ADDR4_STOP_LSB, 911 PCIC_SYSMEM_ADDR4_STOP_MSB, 912 PCIC_CARDMEM_ADDR4_LSB, 913 PCIC_CARDMEM_ADDR4_MSB, 914 PCIC_ADDRWIN_ENABLE_MEM4, 915 }, 916 }; 917 918 void 919 pcic_chip_do_mem_map(h, win) 920 struct pcic_handle *h; 921 int win; 922 { 923 int reg; 924 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 925 int mem8 = 926 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 927 || (kind == PCMCIA_MEM_ATTR); 928 929 DPRINTF(("mem8 %d\n", mem8)); 930 /* mem8 = 1; */ 931 932 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 933 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 934 pcic_write(h, mem_map_index[win].sysmem_start_msb, 935 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 936 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 937 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 938 939 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 940 ((h->mem[win].addr + h->mem[win].size) >> 941 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 942 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 943 (((h->mem[win].addr + h->mem[win].size) >> 944 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 945 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 946 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 947 948 pcic_write(h, mem_map_index[win].cardmem_lsb, 949 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 950 pcic_write(h, mem_map_index[win].cardmem_msb, 951 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 952 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 953 ((kind == PCMCIA_MEM_ATTR) ? 954 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 955 956 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 957 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 958 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 959 960 delay(100); 961 962 #ifdef PCICDEBUG 963 { 964 int r1, r2, r3, r4, r5, r6; 965 966 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 967 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 968 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 969 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 970 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 971 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 972 973 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 974 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 975 } 976 #endif 977 } 978 979 int 980 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 981 pcmcia_chipset_handle_t pch; 982 int kind; 983 bus_addr_t card_addr; 984 bus_size_t size; 985 struct pcmcia_mem_handle *pcmhp; 986 bus_addr_t *offsetp; 987 int *windowp; 988 { 989 struct pcic_handle *h = (struct pcic_handle *) pch; 990 bus_addr_t busaddr; 991 long card_offset; 992 int i, win; 993 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 994 995 win = -1; 996 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 997 i++) { 998 if ((h->memalloc & (1 << i)) == 0) { 999 win = i; 1000 h->memalloc |= (1 << i); 1001 break; 1002 } 1003 } 1004 1005 if (win == -1) 1006 return (1); 1007 1008 *windowp = win; 1009 1010 /* XXX this is pretty gross */ 1011 1012 if (sc->memt != pcmhp->memt) 1013 panic("pcic_chip_mem_map memt is bogus"); 1014 1015 busaddr = pcmhp->addr; 1016 1017 /* 1018 * compute the address offset to the pcmcia address space for the 1019 * pcic. this is intentionally signed. The masks and shifts below 1020 * will cause TRT to happen in the pcic registers. Deal with making 1021 * sure the address is aligned, and return the alignment offset. 1022 */ 1023 1024 *offsetp = card_addr % PCIC_MEM_ALIGN; 1025 card_addr -= *offsetp; 1026 1027 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1028 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1029 (u_long) card_addr)); 1030 1031 /* 1032 * include the offset in the size, and decrement size by one, since 1033 * the hw wants start/stop 1034 */ 1035 size += *offsetp - 1; 1036 1037 card_offset = (((long) card_addr) - ((long) busaddr)); 1038 1039 h->mem[win].addr = busaddr; 1040 h->mem[win].size = size; 1041 h->mem[win].offset = card_offset; 1042 h->mem[win].kind = kind; 1043 1044 pcic_chip_do_mem_map(h, win); 1045 1046 return (0); 1047 } 1048 1049 void 1050 pcic_chip_mem_unmap(pch, window) 1051 pcmcia_chipset_handle_t pch; 1052 int window; 1053 { 1054 struct pcic_handle *h = (struct pcic_handle *) pch; 1055 int reg; 1056 1057 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1058 panic("pcic_chip_mem_unmap: window out of range"); 1059 1060 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1061 reg &= ~mem_map_index[window].memenable; 1062 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1063 1064 h->memalloc &= ~(1 << window); 1065 } 1066 1067 int 1068 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1069 pcmcia_chipset_handle_t pch; 1070 bus_addr_t start; 1071 bus_size_t size; 1072 bus_size_t align; 1073 struct pcmcia_io_handle *pcihp; 1074 { 1075 struct pcic_handle *h = (struct pcic_handle *) pch; 1076 bus_space_tag_t iot; 1077 bus_space_handle_t ioh; 1078 bus_addr_t ioaddr; 1079 int flags = 0; 1080 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1081 1082 /* 1083 * Allocate some arbitrary I/O space. 1084 */ 1085 1086 iot = sc->iot; 1087 1088 if (start) { 1089 ioaddr = start; 1090 if (bus_space_map(iot, start, size, 0, &ioh)) 1091 return (1); 1092 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1093 (u_long) ioaddr, (u_long) size)); 1094 } else { 1095 flags |= PCMCIA_IO_ALLOCATED; 1096 if (bus_space_alloc(iot, sc->iobase, 1097 sc->iobase + sc->iosize, size, align, 0, 0, 1098 &ioaddr, &ioh)) 1099 return (1); 1100 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1101 (u_long) ioaddr, (u_long) size)); 1102 } 1103 1104 pcihp->iot = iot; 1105 pcihp->ioh = ioh; 1106 pcihp->addr = ioaddr; 1107 pcihp->size = size; 1108 pcihp->flags = flags; 1109 1110 return (0); 1111 } 1112 1113 void 1114 pcic_chip_io_free(pch, pcihp) 1115 pcmcia_chipset_handle_t pch; 1116 struct pcmcia_io_handle *pcihp; 1117 { 1118 bus_space_tag_t iot = pcihp->iot; 1119 bus_space_handle_t ioh = pcihp->ioh; 1120 bus_size_t size = pcihp->size; 1121 1122 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1123 bus_space_free(iot, ioh, size); 1124 else 1125 bus_space_unmap(iot, ioh, size); 1126 } 1127 1128 1129 static struct io_map_index_st { 1130 int start_lsb; 1131 int start_msb; 1132 int stop_lsb; 1133 int stop_msb; 1134 int ioenable; 1135 int ioctlmask; 1136 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1137 } io_map_index[] = { 1138 { 1139 PCIC_IOADDR0_START_LSB, 1140 PCIC_IOADDR0_START_MSB, 1141 PCIC_IOADDR0_STOP_LSB, 1142 PCIC_IOADDR0_STOP_MSB, 1143 PCIC_ADDRWIN_ENABLE_IO0, 1144 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1145 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1146 { 1147 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1148 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1149 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1150 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1151 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1152 }, 1153 }, 1154 { 1155 PCIC_IOADDR1_START_LSB, 1156 PCIC_IOADDR1_START_MSB, 1157 PCIC_IOADDR1_STOP_LSB, 1158 PCIC_IOADDR1_STOP_MSB, 1159 PCIC_ADDRWIN_ENABLE_IO1, 1160 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1161 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1162 { 1163 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1164 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1165 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1166 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1167 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1168 }, 1169 }, 1170 }; 1171 1172 void 1173 pcic_chip_do_io_map(h, win) 1174 struct pcic_handle *h; 1175 int win; 1176 { 1177 int reg; 1178 1179 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1180 win, (long) h->io[win].addr, (long) h->io[win].size, 1181 h->io[win].width * 8)); 1182 1183 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1184 pcic_write(h, io_map_index[win].start_msb, 1185 (h->io[win].addr >> 8) & 0xff); 1186 1187 pcic_write(h, io_map_index[win].stop_lsb, 1188 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1189 pcic_write(h, io_map_index[win].stop_msb, 1190 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1191 1192 reg = pcic_read(h, PCIC_IOCTL); 1193 reg &= ~io_map_index[win].ioctlmask; 1194 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1195 pcic_write(h, PCIC_IOCTL, reg); 1196 1197 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1198 reg |= io_map_index[win].ioenable; 1199 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1200 } 1201 1202 int 1203 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1204 pcmcia_chipset_handle_t pch; 1205 int width; 1206 bus_addr_t offset; 1207 bus_size_t size; 1208 struct pcmcia_io_handle *pcihp; 1209 int *windowp; 1210 { 1211 struct pcic_handle *h = (struct pcic_handle *) pch; 1212 bus_addr_t ioaddr = pcihp->addr + offset; 1213 int i, win; 1214 #ifdef PCICDEBUG 1215 static char *width_names[] = { "auto", "io8", "io16" }; 1216 #endif 1217 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1218 1219 /* XXX Sanity check offset/size. */ 1220 1221 win = -1; 1222 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1223 if ((h->ioalloc & (1 << i)) == 0) { 1224 win = i; 1225 h->ioalloc |= (1 << i); 1226 break; 1227 } 1228 } 1229 1230 if (win == -1) 1231 return (1); 1232 1233 *windowp = win; 1234 1235 /* XXX this is pretty gross */ 1236 1237 if (sc->iot != pcihp->iot) 1238 panic("pcic_chip_io_map iot is bogus"); 1239 1240 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1241 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1242 1243 /* XXX wtf is this doing here? */ 1244 1245 printf(" port 0x%lx", (u_long) ioaddr); 1246 if (size > 1) 1247 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1248 1249 h->io[win].addr = ioaddr; 1250 h->io[win].size = size; 1251 h->io[win].width = width; 1252 1253 pcic_chip_do_io_map(h, win); 1254 1255 return (0); 1256 } 1257 1258 void 1259 pcic_chip_io_unmap(pch, window) 1260 pcmcia_chipset_handle_t pch; 1261 int window; 1262 { 1263 struct pcic_handle *h = (struct pcic_handle *) pch; 1264 int reg; 1265 1266 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1267 panic("pcic_chip_io_unmap: window out of range"); 1268 1269 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1270 reg &= ~io_map_index[window].ioenable; 1271 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1272 1273 h->ioalloc &= ~(1 << window); 1274 } 1275 1276 static void 1277 pcic_wait_ready(h) 1278 struct pcic_handle *h; 1279 { 1280 int i; 1281 1282 /* wait an initial 10ms for quick cards */ 1283 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1284 return; 1285 pcic_delay(h, 10, "pccwr0"); 1286 for (i = 0; i < 50; i++) { 1287 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1288 return; 1289 /* wait .1s (100ms) each iteration now */ 1290 pcic_delay(h, 100, "pccwr1"); 1291 #ifdef PCICDEBUG 1292 if (pcic_debug) { 1293 if ((i > 20) && (i % 100 == 99)) 1294 printf("."); 1295 } 1296 #endif 1297 } 1298 1299 #ifdef DIAGNOSTIC 1300 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1301 pcic_read(h, PCIC_IF_STATUS)); 1302 #endif 1303 } 1304 1305 /* 1306 * Perform long (msec order) delay. 1307 */ 1308 static void 1309 pcic_delay(h, timo, wmesg) 1310 struct pcic_handle *h; 1311 int timo; /* in ms. must not be zero */ 1312 const char *wmesg; 1313 { 1314 1315 #ifdef DIAGNOSTIC 1316 if (timo <= 0) { 1317 printf("called with timeout %d\n", timo); 1318 panic("pcic_delay"); 1319 } 1320 if (curproc == NULL) { 1321 printf("called in interrupt context\n"); 1322 panic("pcic_delay"); 1323 } 1324 if (h->event_thread == NULL) { 1325 printf("no event thread\n"); 1326 panic("pcic_delay"); 1327 } 1328 #endif 1329 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1330 wmesg, h->event_thread, timo)); 1331 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1332 } 1333 1334 void 1335 pcic_chip_socket_enable(pch) 1336 pcmcia_chipset_handle_t pch; 1337 { 1338 struct pcic_handle *h = (struct pcic_handle *) pch; 1339 int cardtype, win, intr, pwr; 1340 #if defined(DIAGNOSTIC) || defined(PCICDEBUG) 1341 int reg; 1342 #endif 1343 1344 #ifdef DIAGNOSTIC 1345 if (h->flags & PCIC_FLAG_ENABLED) 1346 printf("pcic_chip_socket_enable: enabling twice"); 1347 #endif 1348 1349 /* disable interrupts */ 1350 intr = pcic_read(h, PCIC_INTR); 1351 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1352 pcic_write(h, PCIC_INTR, intr); 1353 1354 /* power down the socket to reset it, clear the card reset pin */ 1355 pwr = 0; 1356 pcic_write(h, PCIC_PWRCTL, pwr); 1357 1358 /* 1359 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1360 * we are changing Vcc (Toff). 1361 */ 1362 pcic_delay(h, 300 + 100, "pccen0"); 1363 1364 #ifdef VADEM_POWER_HACK 1365 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1366 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1367 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1368 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1369 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1370 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1371 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1372 #endif 1373 /* power up the socket */ 1374 pwr |= PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_PWR_ENABLE; 1375 pcic_write(h, PCIC_PWRCTL, pwr); 1376 1377 /* 1378 * wait 100ms until power raise (Tpr) and 20ms to become 1379 * stable (Tsu(Vcc)). 1380 * 1381 * some machines require some more time to be settled 1382 * (300ms is added here). 1383 */ 1384 pcic_delay(h, 100 + 20 + 300, "pccen1"); 1385 pwr |= PCIC_PWRCTL_OE; 1386 pcic_write(h, PCIC_PWRCTL, pwr); 1387 1388 /* now make sure we have reset# active */ 1389 intr &= ~PCIC_INTR_RESET; 1390 pcic_write(h, PCIC_INTR, intr); 1391 1392 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | 1393 PCIC_PWRCTL_OE | PCIC_PWRCTL_PWR_ENABLE); 1394 /* 1395 * hold RESET at least 10us, this is a min allow for slop in 1396 * delay routine. 1397 */ 1398 delay(20); 1399 #ifdef __hpcmips__ 1400 pcic_delay(h, 22, "pccen3"); /* XXX */ 1401 #endif 1402 1403 /* clear the reset flag */ 1404 intr |= PCIC_INTR_RESET; 1405 pcic_write(h, PCIC_INTR, intr); 1406 1407 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1408 pcic_delay(h, 20, "pccen2"); 1409 1410 #ifdef DIAGNOSTIC 1411 reg = pcic_read(h, PCIC_IF_STATUS); 1412 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1413 printf("pcic_chip_socket_enable: status %x", reg); 1414 } 1415 #endif 1416 /* wait for the chip to finish initializing */ 1417 pcic_wait_ready(h); 1418 1419 /* zero out the address windows */ 1420 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1421 1422 /* set the card type and enable the interrupt */ 1423 cardtype = pcmcia_card_gettype(h->pcmcia); 1424 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1425 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 1426 pcic_write(h, PCIC_INTR, intr); 1427 1428 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1429 h->ph_parent->dv_xname, h->sock, 1430 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1431 1432 /* reinstall all the memory and io mappings */ 1433 for (win = 0; win < PCIC_MEM_WINS; win++) 1434 if (h->memalloc & (1 << win)) 1435 pcic_chip_do_mem_map(h, win); 1436 for (win = 0; win < PCIC_IO_WINS; win++) 1437 if (h->ioalloc & (1 << win)) 1438 pcic_chip_do_io_map(h, win); 1439 1440 h->flags |= PCIC_FLAG_ENABLED; 1441 1442 /* finally enable the interrupt */ 1443 intr |= h->ih_irq; 1444 pcic_write(h, PCIC_INTR, intr); 1445 } 1446 1447 void 1448 pcic_chip_socket_disable(pch) 1449 pcmcia_chipset_handle_t pch; 1450 { 1451 struct pcic_handle *h = (struct pcic_handle *) pch; 1452 int intr; 1453 1454 DPRINTF(("pcic_chip_socket_disable\n")); 1455 1456 /* disable interrupts */ 1457 intr = pcic_read(h, PCIC_INTR); 1458 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1459 pcic_write(h, PCIC_INTR, intr); 1460 1461 /* power down the socket */ 1462 pcic_write(h, PCIC_PWRCTL, 0); 1463 1464 h->flags &= ~PCIC_FLAG_ENABLED; 1465 } 1466 1467 static u_int8_t 1468 st_pcic_read(h, idx) 1469 struct pcic_handle *h; 1470 int idx; 1471 { 1472 1473 if (idx != -1) 1474 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1475 h->sock + idx); 1476 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1477 } 1478 1479 static void 1480 st_pcic_write(h, idx, data) 1481 struct pcic_handle *h; 1482 int idx; 1483 u_int8_t data; 1484 { 1485 1486 if (idx != -1) 1487 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1488 h->sock + idx); 1489 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1490 } 1491
Indexes created Tue Sep 30 11:09:46 GMT 2025