i82365.c revision 1.51
1 /* $NetBSD: i82365.c,v 1.51 2000/02/25 05:26:17 mycroft Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 7 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Marc Horowitz. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/kthread.h> 43 44 #include <vm/vm.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 52 #include <dev/ic/i82365reg.h> 53 #include <dev/ic/i82365var.h> 54 55 #include "locators.h" 56 57 #ifdef PCICDEBUG 58 int pcic_debug = 0; 59 #define DPRINTF(arg) if (pcic_debug) printf arg; 60 #else 61 #define DPRINTF(arg) 62 #endif 63 64 /* 65 * Individual drivers will allocate their own memory and io regions. Memory 66 * regions must be a multiple of 4k, aligned on a 4k boundary. 67 */ 68 69 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 70 71 void pcic_attach_socket __P((struct pcic_handle *)); 72 void pcic_attach_socket_finish __P((struct pcic_handle *)); 73 74 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 75 int pcic_print __P((void *arg, const char *pnp)); 76 int pcic_intr_socket __P((struct pcic_handle *)); 77 void pcic_poll_intr __P((void *)); 78 79 void pcic_attach_card __P((struct pcic_handle *)); 80 void pcic_detach_card __P((struct pcic_handle *, int)); 81 void pcic_deactivate_card __P((struct pcic_handle *)); 82 83 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 84 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 85 86 void pcic_create_event_thread __P((void *)); 87 void pcic_event_thread __P((void *)); 88 89 void pcic_queue_event __P((struct pcic_handle *, int)); 90 void pcic_power __P((int, void *)); 91 92 static void pcic_wait_ready __P((struct pcic_handle *)); 93 static void pcic_delay __P((struct pcic_handle *, int, const char *)); 94 95 static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 96 static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 97 98 int 99 pcic_ident_ok(ident) 100 int ident; 101 { 102 /* this is very empirical and heuristic */ 103 104 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 105 return (0); 106 107 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 108 #ifdef DIAGNOSTIC 109 printf("pcic: does not support memory and I/O cards, " 110 "ignored (ident=%0x)\n", ident); 111 #endif 112 return (0); 113 } 114 return (1); 115 } 116 117 int 118 pcic_vendor(h) 119 struct pcic_handle *h; 120 { 121 int reg; 122 123 /* 124 * the chip_id of the cirrus toggles between 11 and 00 after a write. 125 * weird. 126 */ 127 128 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 129 reg = pcic_read(h, -1); 130 131 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 132 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 133 reg = pcic_read(h, -1); 134 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 135 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 136 return (PCIC_VENDOR_CIRRUS_PD672X); 137 else 138 return (PCIC_VENDOR_CIRRUS_PD6710); 139 } 140 } 141 142 reg = pcic_read(h, PCIC_IDENT); 143 144 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 145 return (PCIC_VENDOR_I82365SLR0); 146 else 147 return (PCIC_VENDOR_I82365SLR1); 148 149 return (PCIC_VENDOR_UNKNOWN); 150 } 151 152 char * 153 pcic_vendor_to_string(vendor) 154 int vendor; 155 { 156 switch (vendor) { 157 case PCIC_VENDOR_I82365SLR0: 158 return ("Intel 82365SL Revision 0"); 159 case PCIC_VENDOR_I82365SLR1: 160 return ("Intel 82365SL Revision 1"); 161 case PCIC_VENDOR_CIRRUS_PD6710: 162 return ("Cirrus PD6710"); 163 case PCIC_VENDOR_CIRRUS_PD672X: 164 return ("Cirrus PD672X"); 165 } 166 167 return ("Unknown controller"); 168 } 169 170 void 171 pcic_attach(sc) 172 struct pcic_softc *sc; 173 { 174 int count, i, reg, chip, socket, intr; 175 176 DPRINTF(("pcic ident regs:")); 177 178 /* find and configure for the available sockets */ 179 count = 0; 180 for (i = 0; i < PCIC_NSLOTS; i++) { 181 chip = i / 2; 182 socket = i % 2; 183 sc->handle[i].ph_parent = (struct device *)sc; 184 sc->handle[i].chip = chip; 185 sc->handle[i].sock = chip * PCIC_CHIP_OFFSET + 186 socket * PCIC_SOCKET_OFFSET; 187 /* initialize pcic_read and pcic_write functions */ 188 sc->handle[i].ph_read = st_pcic_read; 189 sc->handle[i].ph_write = st_pcic_write; 190 sc->handle[i].ph_bus_t = sc->iot; 191 sc->handle[i].ph_bus_h = sc->ioh; 192 /* need to read vendor -- for cirrus to report no xtra chip */ 193 if (socket == 0) 194 sc->handle[i].vendor = sc->handle[i + 1].vendor = 195 pcic_vendor(&sc->handle[i]); 196 reg = pcic_read(&sc->handle[i], PCIC_IDENT); 197 if (!pcic_ident_ok(reg)) { 198 sc->handle[i].flags = 0; 199 } else { 200 sc->handle[i].flags = PCIC_FLAG_SOCKETP; 201 count++; 202 } 203 sc->handle[i].laststate = PCIC_LASTSTATE_EMPTY; 204 DPRINTF(("ident reg 0x%02x\n", reg)); 205 } 206 if (count == 0) 207 panic("pcic_attach: attach found no sockets"); 208 209 for (i = 0; i < PCIC_NSLOTS; i++) { 210 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 211 SIMPLEQ_INIT(&sc->handle[i].events); 212 213 /* disable interrupts -- for now */ 214 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 215 intr = pcic_read(&sc->handle[i], PCIC_INTR); 216 DPRINTF(("intr was 0x%02x\n", intr)); 217 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | 218 PCIC_INTR_IRQ_MASK); 219 pcic_write(&sc->handle[i], PCIC_INTR, intr); 220 pcic_read(&sc->handle[i], PCIC_CSC); 221 } 222 } 223 224 /* print detected info */ 225 for (i = 0; i < PCIC_NSLOTS; i += 2) { 226 chip = i / 2; 227 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 228 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 229 continue; 230 231 printf("%s: controller %d (%s) has ", sc->dev.dv_xname, chip, 232 pcic_vendor_to_string(sc->handle[i].vendor)); 233 234 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) && 235 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP)) 236 printf("sockets A and B\n"); 237 else if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 238 printf("socket A only\n"); 239 else 240 printf("socket B only\n"); 241 } 242 } 243 244 /* 245 * attach the sockets before we know what interrupts we have 246 */ 247 void 248 pcic_attach_sockets(sc) 249 struct pcic_softc *sc; 250 { 251 int i; 252 253 for (i = 0; i < PCIC_NSLOTS; i++) 254 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 255 pcic_attach_socket(&sc->handle[i]); 256 } 257 258 void 259 pcic_power(why, arg) 260 int why; 261 void *arg; 262 { 263 struct pcic_handle *h = (struct pcic_handle *)arg; 264 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 265 int reg; 266 267 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 268 269 if (h->flags & PCIC_FLAG_SOCKETP) { 270 if ((why == PWR_RESUME) && 271 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 272 #ifdef PCICDEBUG 273 char bitbuf[64]; 274 #endif 275 reg = PCIC_CSC_INTR_CD_ENABLE; 276 if (sc->irq != -1) 277 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 278 pcic_write(h, PCIC_CSC_INTR, reg); 279 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 280 sc->dev.dv_xname, 281 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 282 PCIC_CSC_INTR_FORMAT, 283 bitbuf, sizeof(bitbuf)))); 284 } 285 286 /* 287 * check for card insertion or removal during suspend period. 288 * XXX: the code can't cope with card swap (remove then insert). 289 * how can we detect such situation? 290 */ 291 if (why == PWR_RESUME) 292 (void)pcic_intr_socket(h); 293 } 294 } 295 296 297 /* 298 * attach a socket -- we don't know about irqs yet 299 */ 300 void 301 pcic_attach_socket(h) 302 struct pcic_handle *h; 303 { 304 struct pcmciabus_attach_args paa; 305 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 306 307 /* initialize the rest of the handle */ 308 309 h->shutdown = 0; 310 h->memalloc = 0; 311 h->ioalloc = 0; 312 h->ih_irq = 0; 313 314 /* now, config one pcmcia device per socket */ 315 316 paa.paa_busname = "pcmcia"; 317 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 318 paa.pch = (pcmcia_chipset_handle_t) h; 319 paa.iobase = sc->iobase; 320 paa.iosize = sc->iosize; 321 322 h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, pcic_submatch); 323 if (h->pcmcia == NULL) { 324 h->flags &= ~PCIC_FLAG_SOCKETP; 325 return; 326 } 327 328 /* 329 * queue creation of a kernel thread to handle insert/removal events. 330 */ 331 #ifdef DIAGNOSTIC 332 if (h->event_thread != NULL) 333 panic("pcic_attach_socket: event thread"); 334 #endif 335 config_pending_incr(); 336 kthread_create(pcic_create_event_thread, h); 337 } 338 339 /* 340 * now finish attaching the sockets, we are ready to allocate 341 * interrupts 342 */ 343 void 344 pcic_attach_sockets_finish(sc) 345 struct pcic_softc *sc; 346 { 347 int i; 348 349 for (i = 0; i < PCIC_NSLOTS; i++) 350 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 351 pcic_attach_socket_finish(&sc->handle[i]); 352 } 353 354 /* 355 * finishing attaching the socket. Interrupts may now be on 356 * if so expects the pcic interrupt to be blocked 357 */ 358 void 359 pcic_attach_socket_finish(h) 360 struct pcic_handle *h; 361 { 362 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 363 int reg; 364 365 DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 366 (long) (h - &sc->handle[0]))); 367 368 /* zero out the address windows */ 369 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 370 371 /* 372 * Set up a powerhook to ensure it continues to interrupt on 373 * card detect even after suspend. 374 * (this works around a bug seen in suspend-to-disk on the 375 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 376 */ 377 powerhook_establish(pcic_power, h); 378 379 /* enable interrupts on card detect, poll for them if no irq avail */ 380 reg = PCIC_CSC_INTR_CD_ENABLE; 381 if (sc->irq == -1) 382 timeout(pcic_poll_intr, sc, hz / 2); 383 else 384 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 385 pcic_write(h, PCIC_CSC_INTR, reg); 386 387 /* steer above mgmt interrupt to configured place */ 388 reg = pcic_read(h, PCIC_INTR); 389 reg &= ~PCIC_INTR_ENABLE; 390 pcic_write(h, PCIC_INTR, reg); 391 392 /* clear possible card detect interrupt */ 393 pcic_read(h, PCIC_CSC); 394 395 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 396 h->vendor)); 397 398 /* unsleep the cirrus controller */ 399 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 400 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 401 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 402 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 403 DPRINTF(("%s: socket %02x was suspended\n", 404 h->ph_parent->dv_xname, h->sock)); 405 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 406 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 407 } 408 } 409 410 /* if there's a card there, then attach it. */ 411 reg = pcic_read(h, PCIC_IF_STATUS); 412 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 413 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 414 pcic_queue_event(h, PCIC_EVENT_INSERTION); 415 h->laststate = PCIC_LASTSTATE_PRESENT; 416 } else { 417 h->laststate = PCIC_LASTSTATE_EMPTY; 418 } 419 } 420 421 void 422 pcic_create_event_thread(arg) 423 void *arg; 424 { 425 struct pcic_handle *h = arg; 426 const char *cs; 427 428 switch (h->sock) { 429 case C0SA: 430 cs = "0,0"; 431 break; 432 case C0SB: 433 cs = "0,1"; 434 break; 435 case C1SA: 436 cs = "1,0"; 437 break; 438 case C1SB: 439 cs = "1,1"; 440 break; 441 default: 442 panic("pcic_create_event_thread: unknown pcic socket"); 443 } 444 445 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 446 "%s,%s", h->ph_parent->dv_xname, cs)) { 447 printf("%s: unable to create event thread for sock 0x%02x\n", 448 h->ph_parent->dv_xname, h->sock); 449 panic("pcic_create_event_thread"); 450 } 451 } 452 453 void 454 pcic_event_thread(arg) 455 void *arg; 456 { 457 struct pcic_handle *h = arg; 458 struct pcic_event *pe; 459 int s, first = 1; 460 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 461 462 while (h->shutdown == 0) { 463 s = splhigh(); 464 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 465 splx(s); 466 if (first) { 467 first = 0; 468 config_pending_decr(); 469 } 470 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 471 continue; 472 } else { 473 splx(s); 474 /* sleep .25s to be enqueued chatterling interrupts */ 475 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 476 "pcicss", hz/4); 477 } 478 s = splhigh(); 479 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 480 splx(s); 481 482 switch (pe->pe_type) { 483 case PCIC_EVENT_INSERTION: 484 s = splhigh(); 485 while (1) { 486 struct pcic_event *pe1, *pe2; 487 488 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 489 break; 490 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 491 break; 492 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 493 break; 494 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 495 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 496 pe_q); 497 free(pe1, M_TEMP); 498 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 499 pe_q); 500 free(pe2, M_TEMP); 501 } 502 } 503 splx(s); 504 505 DPRINTF(("%s: insertion event\n", 506 h->ph_parent->dv_xname)); 507 pcic_attach_card(h); 508 break; 509 510 case PCIC_EVENT_REMOVAL: 511 s = splhigh(); 512 while (1) { 513 struct pcic_event *pe1, *pe2; 514 515 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 516 break; 517 if (pe1->pe_type != PCIC_EVENT_INSERTION) 518 break; 519 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 520 break; 521 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 522 SIMPLEQ_REMOVE_HEAD(&h->events, pe1, 523 pe_q); 524 free(pe1, M_TEMP); 525 SIMPLEQ_REMOVE_HEAD(&h->events, pe2, 526 pe_q); 527 free(pe2, M_TEMP); 528 } 529 } 530 splx(s); 531 532 DPRINTF(("%s: removal event\n", 533 h->ph_parent->dv_xname)); 534 pcic_detach_card(h, DETACH_FORCE); 535 break; 536 537 default: 538 panic("pcic_event_thread: unknown event %d", 539 pe->pe_type); 540 } 541 free(pe, M_TEMP); 542 } 543 544 h->event_thread = NULL; 545 546 /* In case parent is waiting for us to exit. */ 547 wakeup(sc); 548 549 kthread_exit(0); 550 } 551 552 int 553 pcic_submatch(parent, cf, aux) 554 struct device *parent; 555 struct cfdata *cf; 556 void *aux; 557 { 558 559 struct pcmciabus_attach_args *paa = aux; 560 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 561 562 switch (h->sock) { 563 case C0SA: 564 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 565 PCMCIABUSCF_CONTROLLER_DEFAULT && 566 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 567 return 0; 568 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 569 PCMCIABUSCF_SOCKET_DEFAULT && 570 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 571 return 0; 572 573 break; 574 case C0SB: 575 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 576 PCMCIABUSCF_CONTROLLER_DEFAULT && 577 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 578 return 0; 579 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 580 PCMCIABUSCF_SOCKET_DEFAULT && 581 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 582 return 0; 583 584 break; 585 case C1SA: 586 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 587 PCMCIABUSCF_CONTROLLER_DEFAULT && 588 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 589 return 0; 590 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 591 PCMCIABUSCF_SOCKET_DEFAULT && 592 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 593 return 0; 594 595 break; 596 case C1SB: 597 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 598 PCMCIABUSCF_CONTROLLER_DEFAULT && 599 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 600 return 0; 601 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 602 PCMCIABUSCF_SOCKET_DEFAULT && 603 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 604 return 0; 605 606 break; 607 default: 608 panic("unknown pcic socket"); 609 } 610 611 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 612 } 613 614 int 615 pcic_print(arg, pnp) 616 void *arg; 617 const char *pnp; 618 { 619 struct pcmciabus_attach_args *paa = arg; 620 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 621 622 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 623 if (pnp) 624 printf("pcmcia at %s", pnp); 625 626 switch (h->sock) { 627 case C0SA: 628 printf(" controller 0 socket 0"); 629 break; 630 case C0SB: 631 printf(" controller 0 socket 1"); 632 break; 633 case C1SA: 634 printf(" controller 1 socket 0"); 635 break; 636 case C1SB: 637 printf(" controller 1 socket 1"); 638 break; 639 default: 640 panic("unknown pcic socket"); 641 } 642 643 return (UNCONF); 644 } 645 646 void 647 pcic_poll_intr(arg) 648 void *arg; 649 { 650 struct pcic_softc *sc; 651 int i, s; 652 653 s = spltty(); 654 sc = arg; 655 for (i = 0; i < PCIC_NSLOTS; i++) 656 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 657 (void)pcic_intr_socket(&sc->handle[i]); 658 timeout(pcic_poll_intr, sc, hz / 2); 659 splx(s); 660 } 661 662 int 663 pcic_intr(arg) 664 void *arg; 665 { 666 struct pcic_softc *sc = arg; 667 int i, ret = 0; 668 669 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 670 671 for (i = 0; i < PCIC_NSLOTS; i++) 672 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 673 ret += pcic_intr_socket(&sc->handle[i]); 674 675 return (ret ? 1 : 0); 676 } 677 678 int 679 pcic_intr_socket(h) 680 struct pcic_handle *h; 681 { 682 int cscreg; 683 684 cscreg = pcic_read(h, PCIC_CSC); 685 686 cscreg &= (PCIC_CSC_GPI | 687 PCIC_CSC_CD | 688 PCIC_CSC_READY | 689 PCIC_CSC_BATTWARN | 690 PCIC_CSC_BATTDEAD); 691 692 if (cscreg & PCIC_CSC_GPI) { 693 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 694 } 695 if (cscreg & PCIC_CSC_CD) { 696 int statreg; 697 698 statreg = pcic_read(h, PCIC_IF_STATUS); 699 700 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 701 statreg)); 702 703 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 704 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 705 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 706 DPRINTF(("%s: enqueing INSERTION event\n", 707 h->ph_parent->dv_xname)); 708 pcic_queue_event(h, PCIC_EVENT_INSERTION); 709 } 710 h->laststate = PCIC_LASTSTATE_PRESENT; 711 } else { 712 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 713 /* Deactivate the card now. */ 714 DPRINTF(("%s: deactivating card\n", 715 h->ph_parent->dv_xname)); 716 pcic_deactivate_card(h); 717 718 DPRINTF(("%s: enqueing REMOVAL event\n", 719 h->ph_parent->dv_xname)); 720 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 721 } 722 h->laststate = 723 ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 0) ? 724 PCIC_LASTSTATE_EMPTY : PCIC_LASTSTATE_HALF; 725 } 726 } 727 if (cscreg & PCIC_CSC_READY) { 728 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 729 /* shouldn't happen */ 730 } 731 if (cscreg & PCIC_CSC_BATTWARN) { 732 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 733 h->sock)); 734 } 735 if (cscreg & PCIC_CSC_BATTDEAD) { 736 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 737 h->sock)); 738 } 739 return (cscreg ? 1 : 0); 740 } 741 742 void 743 pcic_queue_event(h, event) 744 struct pcic_handle *h; 745 int event; 746 { 747 struct pcic_event *pe; 748 int s; 749 750 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 751 if (pe == NULL) 752 panic("pcic_queue_event: can't allocate event"); 753 754 pe->pe_type = event; 755 s = splhigh(); 756 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 757 splx(s); 758 wakeup(&h->events); 759 } 760 761 void 762 pcic_attach_card(h) 763 struct pcic_handle *h; 764 { 765 766 if (!(h->flags & PCIC_FLAG_CARDP)) { 767 /* call the MI attach function */ 768 pcmcia_card_attach(h->pcmcia); 769 770 h->flags |= PCIC_FLAG_CARDP; 771 } else { 772 DPRINTF(("pcic_attach_card: already attached")); 773 } 774 } 775 776 void 777 pcic_detach_card(h, flags) 778 struct pcic_handle *h; 779 int flags; /* DETACH_* */ 780 { 781 782 if (h->flags & PCIC_FLAG_CARDP) { 783 h->flags &= ~PCIC_FLAG_CARDP; 784 785 /* call the MI detach function */ 786 pcmcia_card_detach(h->pcmcia, flags); 787 } else { 788 DPRINTF(("pcic_detach_card: already detached")); 789 } 790 } 791 792 void 793 pcic_deactivate_card(h) 794 struct pcic_handle *h; 795 { 796 797 /* call the MI deactivate function */ 798 pcmcia_card_deactivate(h->pcmcia); 799 800 /* power down the socket */ 801 pcic_write(h, PCIC_PWRCTL, 0); 802 803 /* reset the socket */ 804 pcic_write(h, PCIC_INTR, 0); 805 } 806 807 int 808 pcic_chip_mem_alloc(pch, size, pcmhp) 809 pcmcia_chipset_handle_t pch; 810 bus_size_t size; 811 struct pcmcia_mem_handle *pcmhp; 812 { 813 struct pcic_handle *h = (struct pcic_handle *) pch; 814 bus_space_handle_t memh; 815 bus_addr_t addr; 816 bus_size_t sizepg; 817 int i, mask, mhandle; 818 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 819 820 /* out of sc->memh, allocate as many pages as necessary */ 821 822 /* convert size to PCIC pages */ 823 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 824 if (sizepg > PCIC_MAX_MEM_PAGES) 825 return (1); 826 827 mask = (1 << sizepg) - 1; 828 829 addr = 0; /* XXX gcc -Wuninitialized */ 830 mhandle = 0; /* XXX gcc -Wuninitialized */ 831 832 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 833 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 834 if (bus_space_subregion(sc->memt, sc->memh, 835 i * PCIC_MEM_PAGESIZE, 836 sizepg * PCIC_MEM_PAGESIZE, &memh)) 837 return (1); 838 mhandle = mask << i; 839 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 840 sc->subregionmask &= ~(mhandle); 841 pcmhp->memt = sc->memt; 842 pcmhp->memh = memh; 843 pcmhp->addr = addr; 844 pcmhp->size = size; 845 pcmhp->mhandle = mhandle; 846 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 847 return (0); 848 } 849 } 850 851 return (1); 852 } 853 854 void 855 pcic_chip_mem_free(pch, pcmhp) 856 pcmcia_chipset_handle_t pch; 857 struct pcmcia_mem_handle *pcmhp; 858 { 859 struct pcic_handle *h = (struct pcic_handle *) pch; 860 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 861 862 sc->subregionmask |= pcmhp->mhandle; 863 } 864 865 static struct mem_map_index_st { 866 int sysmem_start_lsb; 867 int sysmem_start_msb; 868 int sysmem_stop_lsb; 869 int sysmem_stop_msb; 870 int cardmem_lsb; 871 int cardmem_msb; 872 int memenable; 873 } mem_map_index[] = { 874 { 875 PCIC_SYSMEM_ADDR0_START_LSB, 876 PCIC_SYSMEM_ADDR0_START_MSB, 877 PCIC_SYSMEM_ADDR0_STOP_LSB, 878 PCIC_SYSMEM_ADDR0_STOP_MSB, 879 PCIC_CARDMEM_ADDR0_LSB, 880 PCIC_CARDMEM_ADDR0_MSB, 881 PCIC_ADDRWIN_ENABLE_MEM0, 882 }, 883 { 884 PCIC_SYSMEM_ADDR1_START_LSB, 885 PCIC_SYSMEM_ADDR1_START_MSB, 886 PCIC_SYSMEM_ADDR1_STOP_LSB, 887 PCIC_SYSMEM_ADDR1_STOP_MSB, 888 PCIC_CARDMEM_ADDR1_LSB, 889 PCIC_CARDMEM_ADDR1_MSB, 890 PCIC_ADDRWIN_ENABLE_MEM1, 891 }, 892 { 893 PCIC_SYSMEM_ADDR2_START_LSB, 894 PCIC_SYSMEM_ADDR2_START_MSB, 895 PCIC_SYSMEM_ADDR2_STOP_LSB, 896 PCIC_SYSMEM_ADDR2_STOP_MSB, 897 PCIC_CARDMEM_ADDR2_LSB, 898 PCIC_CARDMEM_ADDR2_MSB, 899 PCIC_ADDRWIN_ENABLE_MEM2, 900 }, 901 { 902 PCIC_SYSMEM_ADDR3_START_LSB, 903 PCIC_SYSMEM_ADDR3_START_MSB, 904 PCIC_SYSMEM_ADDR3_STOP_LSB, 905 PCIC_SYSMEM_ADDR3_STOP_MSB, 906 PCIC_CARDMEM_ADDR3_LSB, 907 PCIC_CARDMEM_ADDR3_MSB, 908 PCIC_ADDRWIN_ENABLE_MEM3, 909 }, 910 { 911 PCIC_SYSMEM_ADDR4_START_LSB, 912 PCIC_SYSMEM_ADDR4_START_MSB, 913 PCIC_SYSMEM_ADDR4_STOP_LSB, 914 PCIC_SYSMEM_ADDR4_STOP_MSB, 915 PCIC_CARDMEM_ADDR4_LSB, 916 PCIC_CARDMEM_ADDR4_MSB, 917 PCIC_ADDRWIN_ENABLE_MEM4, 918 }, 919 }; 920 921 void 922 pcic_chip_do_mem_map(h, win) 923 struct pcic_handle *h; 924 int win; 925 { 926 int reg; 927 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 928 int mem8 = 929 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 930 || (kind == PCMCIA_MEM_ATTR); 931 932 DPRINTF(("mem8 %d\n", mem8)); 933 /* mem8 = 1; */ 934 935 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 936 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 937 pcic_write(h, mem_map_index[win].sysmem_start_msb, 938 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 939 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 940 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 941 942 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 943 ((h->mem[win].addr + h->mem[win].size) >> 944 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 945 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 946 (((h->mem[win].addr + h->mem[win].size) >> 947 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 948 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 949 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 950 951 pcic_write(h, mem_map_index[win].cardmem_lsb, 952 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 953 pcic_write(h, mem_map_index[win].cardmem_msb, 954 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 955 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 956 ((kind == PCMCIA_MEM_ATTR) ? 957 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 958 959 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 960 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 961 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 962 963 delay(100); 964 965 #ifdef PCICDEBUG 966 { 967 int r1, r2, r3, r4, r5, r6; 968 969 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 970 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 971 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 972 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 973 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 974 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 975 976 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 977 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 978 } 979 #endif 980 } 981 982 int 983 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 984 pcmcia_chipset_handle_t pch; 985 int kind; 986 bus_addr_t card_addr; 987 bus_size_t size; 988 struct pcmcia_mem_handle *pcmhp; 989 bus_addr_t *offsetp; 990 int *windowp; 991 { 992 struct pcic_handle *h = (struct pcic_handle *) pch; 993 bus_addr_t busaddr; 994 long card_offset; 995 int i, win; 996 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 997 998 win = -1; 999 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1000 i++) { 1001 if ((h->memalloc & (1 << i)) == 0) { 1002 win = i; 1003 h->memalloc |= (1 << i); 1004 break; 1005 } 1006 } 1007 1008 if (win == -1) 1009 return (1); 1010 1011 *windowp = win; 1012 1013 /* XXX this is pretty gross */ 1014 1015 if (sc->memt != pcmhp->memt) 1016 panic("pcic_chip_mem_map memt is bogus"); 1017 1018 busaddr = pcmhp->addr; 1019 1020 /* 1021 * compute the address offset to the pcmcia address space for the 1022 * pcic. this is intentionally signed. The masks and shifts below 1023 * will cause TRT to happen in the pcic registers. Deal with making 1024 * sure the address is aligned, and return the alignment offset. 1025 */ 1026 1027 *offsetp = card_addr % PCIC_MEM_ALIGN; 1028 card_addr -= *offsetp; 1029 1030 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1031 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1032 (u_long) card_addr)); 1033 1034 /* 1035 * include the offset in the size, and decrement size by one, since 1036 * the hw wants start/stop 1037 */ 1038 size += *offsetp - 1; 1039 1040 card_offset = (((long) card_addr) - ((long) busaddr)); 1041 1042 h->mem[win].addr = busaddr; 1043 h->mem[win].size = size; 1044 h->mem[win].offset = card_offset; 1045 h->mem[win].kind = kind; 1046 1047 pcic_chip_do_mem_map(h, win); 1048 1049 return (0); 1050 } 1051 1052 void 1053 pcic_chip_mem_unmap(pch, window) 1054 pcmcia_chipset_handle_t pch; 1055 int window; 1056 { 1057 struct pcic_handle *h = (struct pcic_handle *) pch; 1058 int reg; 1059 1060 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1061 panic("pcic_chip_mem_unmap: window out of range"); 1062 1063 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1064 reg &= ~mem_map_index[window].memenable; 1065 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1066 1067 h->memalloc &= ~(1 << window); 1068 } 1069 1070 int 1071 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1072 pcmcia_chipset_handle_t pch; 1073 bus_addr_t start; 1074 bus_size_t size; 1075 bus_size_t align; 1076 struct pcmcia_io_handle *pcihp; 1077 { 1078 struct pcic_handle *h = (struct pcic_handle *) pch; 1079 bus_space_tag_t iot; 1080 bus_space_handle_t ioh; 1081 bus_addr_t ioaddr; 1082 int flags = 0; 1083 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1084 1085 /* 1086 * Allocate some arbitrary I/O space. 1087 */ 1088 1089 iot = sc->iot; 1090 1091 if (start) { 1092 ioaddr = start; 1093 if (bus_space_map(iot, start, size, 0, &ioh)) 1094 return (1); 1095 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1096 (u_long) ioaddr, (u_long) size)); 1097 } else { 1098 flags |= PCMCIA_IO_ALLOCATED; 1099 if (bus_space_alloc(iot, sc->iobase, 1100 sc->iobase + sc->iosize, size, align, 0, 0, 1101 &ioaddr, &ioh)) 1102 return (1); 1103 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1104 (u_long) ioaddr, (u_long) size)); 1105 } 1106 1107 pcihp->iot = iot; 1108 pcihp->ioh = ioh; 1109 pcihp->addr = ioaddr; 1110 pcihp->size = size; 1111 pcihp->flags = flags; 1112 1113 return (0); 1114 } 1115 1116 void 1117 pcic_chip_io_free(pch, pcihp) 1118 pcmcia_chipset_handle_t pch; 1119 struct pcmcia_io_handle *pcihp; 1120 { 1121 bus_space_tag_t iot = pcihp->iot; 1122 bus_space_handle_t ioh = pcihp->ioh; 1123 bus_size_t size = pcihp->size; 1124 1125 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1126 bus_space_free(iot, ioh, size); 1127 else 1128 bus_space_unmap(iot, ioh, size); 1129 } 1130 1131 1132 static struct io_map_index_st { 1133 int start_lsb; 1134 int start_msb; 1135 int stop_lsb; 1136 int stop_msb; 1137 int ioenable; 1138 int ioctlmask; 1139 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1140 } io_map_index[] = { 1141 { 1142 PCIC_IOADDR0_START_LSB, 1143 PCIC_IOADDR0_START_MSB, 1144 PCIC_IOADDR0_STOP_LSB, 1145 PCIC_IOADDR0_STOP_MSB, 1146 PCIC_ADDRWIN_ENABLE_IO0, 1147 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1148 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1149 { 1150 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1151 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1152 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1153 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1154 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1155 }, 1156 }, 1157 { 1158 PCIC_IOADDR1_START_LSB, 1159 PCIC_IOADDR1_START_MSB, 1160 PCIC_IOADDR1_STOP_LSB, 1161 PCIC_IOADDR1_STOP_MSB, 1162 PCIC_ADDRWIN_ENABLE_IO1, 1163 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1164 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1165 { 1166 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1167 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1168 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1169 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1170 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1171 }, 1172 }, 1173 }; 1174 1175 void 1176 pcic_chip_do_io_map(h, win) 1177 struct pcic_handle *h; 1178 int win; 1179 { 1180 int reg; 1181 1182 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1183 win, (long) h->io[win].addr, (long) h->io[win].size, 1184 h->io[win].width * 8)); 1185 1186 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1187 pcic_write(h, io_map_index[win].start_msb, 1188 (h->io[win].addr >> 8) & 0xff); 1189 1190 pcic_write(h, io_map_index[win].stop_lsb, 1191 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1192 pcic_write(h, io_map_index[win].stop_msb, 1193 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1194 1195 reg = pcic_read(h, PCIC_IOCTL); 1196 reg &= ~io_map_index[win].ioctlmask; 1197 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1198 pcic_write(h, PCIC_IOCTL, reg); 1199 1200 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1201 reg |= io_map_index[win].ioenable; 1202 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1203 } 1204 1205 int 1206 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1207 pcmcia_chipset_handle_t pch; 1208 int width; 1209 bus_addr_t offset; 1210 bus_size_t size; 1211 struct pcmcia_io_handle *pcihp; 1212 int *windowp; 1213 { 1214 struct pcic_handle *h = (struct pcic_handle *) pch; 1215 bus_addr_t ioaddr = pcihp->addr + offset; 1216 int i, win; 1217 #ifdef PCICDEBUG 1218 static char *width_names[] = { "auto", "io8", "io16" }; 1219 #endif 1220 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1221 1222 /* XXX Sanity check offset/size. */ 1223 1224 win = -1; 1225 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1226 if ((h->ioalloc & (1 << i)) == 0) { 1227 win = i; 1228 h->ioalloc |= (1 << i); 1229 break; 1230 } 1231 } 1232 1233 if (win == -1) 1234 return (1); 1235 1236 *windowp = win; 1237 1238 /* XXX this is pretty gross */ 1239 1240 if (sc->iot != pcihp->iot) 1241 panic("pcic_chip_io_map iot is bogus"); 1242 1243 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1244 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1245 1246 /* XXX wtf is this doing here? */ 1247 1248 printf(" port 0x%lx", (u_long) ioaddr); 1249 if (size > 1) 1250 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1251 1252 h->io[win].addr = ioaddr; 1253 h->io[win].size = size; 1254 h->io[win].width = width; 1255 1256 pcic_chip_do_io_map(h, win); 1257 1258 return (0); 1259 } 1260 1261 void 1262 pcic_chip_io_unmap(pch, window) 1263 pcmcia_chipset_handle_t pch; 1264 int window; 1265 { 1266 struct pcic_handle *h = (struct pcic_handle *) pch; 1267 int reg; 1268 1269 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1270 panic("pcic_chip_io_unmap: window out of range"); 1271 1272 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1273 reg &= ~io_map_index[window].ioenable; 1274 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1275 1276 h->ioalloc &= ~(1 << window); 1277 } 1278 1279 static void 1280 pcic_wait_ready(h) 1281 struct pcic_handle *h; 1282 { 1283 int i; 1284 1285 /* wait an initial 10ms for quick cards */ 1286 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1287 return; 1288 pcic_delay(h, 10, "pccwr0"); 1289 for (i = 0; i < 50; i++) { 1290 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1291 return; 1292 /* wait .1s (100ms) each iteration now */ 1293 pcic_delay(h, 100, "pccwr1"); 1294 #ifdef PCICDEBUG 1295 if (pcic_debug) { 1296 if ((i > 20) && (i % 100 == 99)) 1297 printf("."); 1298 } 1299 #endif 1300 } 1301 1302 #ifdef DIAGNOSTIC 1303 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1304 pcic_read(h, PCIC_IF_STATUS)); 1305 #endif 1306 } 1307 1308 /* 1309 * Perform long (msec order) delay. 1310 */ 1311 static void 1312 pcic_delay(h, timo, wmesg) 1313 struct pcic_handle *h; 1314 int timo; /* in ms. must not be zero */ 1315 const char *wmesg; 1316 { 1317 1318 #ifdef DIAGNOSTIC 1319 if (timo <= 0) { 1320 printf("called with timeout %d\n", timo); 1321 panic("pcic_delay"); 1322 } 1323 if (curproc == NULL) { 1324 printf("called in interrupt context\n"); 1325 panic("pcic_delay"); 1326 } 1327 if (h->event_thread == NULL) { 1328 printf("no event thread\n"); 1329 panic("pcic_delay"); 1330 } 1331 #endif 1332 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1333 wmesg, h->event_thread, timo)); 1334 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1335 } 1336 1337 void 1338 pcic_chip_socket_enable(pch) 1339 pcmcia_chipset_handle_t pch; 1340 { 1341 struct pcic_handle *h = (struct pcic_handle *) pch; 1342 int cardtype, win, intr, pwr; 1343 #if defined(DIAGNOSTIC) || defined(PCICDEBUG) 1344 int reg; 1345 #endif 1346 1347 #ifdef DIAGNOSTIC 1348 if (h->flags & PCIC_FLAG_ENABLED) 1349 printf("pcic_chip_socket_enable: enabling twice"); 1350 #endif 1351 1352 /* disable interrupts */ 1353 intr = pcic_read(h, PCIC_INTR); 1354 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1355 pcic_write(h, PCIC_INTR, intr); 1356 1357 /* power down the socket to reset it, clear the card reset pin */ 1358 pwr = 0; 1359 pcic_write(h, PCIC_PWRCTL, pwr); 1360 1361 /* 1362 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1363 * we are changing Vcc (Toff). 1364 */ 1365 pcic_delay(h, 300 + 100, "pccen0"); 1366 1367 #ifdef VADEM_POWER_HACK 1368 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1369 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1370 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1371 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1372 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1373 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1374 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1375 #endif 1376 /* power up the socket */ 1377 pwr |= PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_PWR_ENABLE; 1378 pcic_write(h, PCIC_PWRCTL, pwr); 1379 1380 /* 1381 * wait 100ms until power raise (Tpr) and 20ms to become 1382 * stable (Tsu(Vcc)). 1383 * 1384 * some machines require some more time to be settled 1385 * (300ms is added here). 1386 */ 1387 pcic_delay(h, 100 + 20 + 300, "pccen1"); 1388 pwr |= PCIC_PWRCTL_OE; 1389 pcic_write(h, PCIC_PWRCTL, pwr); 1390 1391 /* now make sure we have reset# active */ 1392 intr &= ~PCIC_INTR_RESET; 1393 pcic_write(h, PCIC_INTR, intr); 1394 1395 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | 1396 PCIC_PWRCTL_OE | PCIC_PWRCTL_PWR_ENABLE); 1397 /* 1398 * hold RESET at least 10us, this is a min allow for slop in 1399 * delay routine. 1400 */ 1401 delay(20); 1402 #ifdef __hpcmips__ 1403 pcic_delay(h, 22, "pccen3"); /* XXX */ 1404 #endif 1405 1406 /* clear the reset flag */ 1407 intr |= PCIC_INTR_RESET; 1408 pcic_write(h, PCIC_INTR, intr); 1409 1410 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1411 pcic_delay(h, 20, "pccen2"); 1412 1413 #ifdef DIAGNOSTIC 1414 reg = pcic_read(h, PCIC_IF_STATUS); 1415 if (!(reg & PCIC_IF_STATUS_POWERACTIVE)) { 1416 printf("pcic_chip_socket_enable: status %x", reg); 1417 } 1418 #endif 1419 /* wait for the chip to finish initializing */ 1420 pcic_wait_ready(h); 1421 1422 /* zero out the address windows */ 1423 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1424 1425 /* set the card type and enable the interrupt */ 1426 cardtype = pcmcia_card_gettype(h->pcmcia); 1427 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1428 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM); 1429 pcic_write(h, PCIC_INTR, intr); 1430 1431 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1432 h->ph_parent->dv_xname, h->sock, 1433 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1434 1435 /* reinstall all the memory and io mappings */ 1436 for (win = 0; win < PCIC_MEM_WINS; win++) 1437 if (h->memalloc & (1 << win)) 1438 pcic_chip_do_mem_map(h, win); 1439 for (win = 0; win < PCIC_IO_WINS; win++) 1440 if (h->ioalloc & (1 << win)) 1441 pcic_chip_do_io_map(h, win); 1442 1443 h->flags |= PCIC_FLAG_ENABLED; 1444 1445 /* finally enable the interrupt */ 1446 intr |= h->ih_irq; 1447 pcic_write(h, PCIC_INTR, intr); 1448 } 1449 1450 void 1451 pcic_chip_socket_disable(pch) 1452 pcmcia_chipset_handle_t pch; 1453 { 1454 struct pcic_handle *h = (struct pcic_handle *) pch; 1455 int intr; 1456 1457 DPRINTF(("pcic_chip_socket_disable\n")); 1458 1459 /* disable interrupts */ 1460 intr = pcic_read(h, PCIC_INTR); 1461 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 1462 pcic_write(h, PCIC_INTR, intr); 1463 1464 /* power down the socket */ 1465 pcic_write(h, PCIC_PWRCTL, 0); 1466 1467 h->flags &= ~PCIC_FLAG_ENABLED; 1468 } 1469 1470 static u_int8_t 1471 st_pcic_read(h, idx) 1472 struct pcic_handle *h; 1473 int idx; 1474 { 1475 1476 if (idx != -1) 1477 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1478 h->sock + idx); 1479 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1480 } 1481 1482 static void 1483 st_pcic_write(h, idx, data) 1484 struct pcic_handle *h; 1485 int idx; 1486 u_int8_t data; 1487 { 1488 1489 if (idx != -1) 1490 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1491 h->sock + idx); 1492 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1493 } 1494
Indexes created Mon Sep 29 18:09:42 GMT 2025