i82365.c revision 1.6
1 /* $NetBSD: i82365.c,v 1.6 1997/10/19 14:10:11 enami Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 41 #include <vm/vm.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/i82365reg.h> 50 #include <dev/ic/i82365var.h> 51 52 #include "locators.h" 53 54 #ifdef PCICDEBUG 55 int pcic_debug = 0; 56 #define DPRINTF(arg) if (pcic_debug) printf arg; 57 #else 58 #define DPRINTF(arg) 59 #endif 60 61 #define PCIC_VENDOR_UNKNOWN 0 62 #define PCIC_VENDOR_I82365SLR0 1 63 #define PCIC_VENDOR_I82365SLR1 2 64 #define PCIC_VENDOR_CIRRUS_PD6710 3 65 #define PCIC_VENDOR_CIRRUS_PD672X 4 66 67 /* 68 * Individual drivers will allocate their own memory and io regions. Memory 69 * regions must be a multiple of 4k, aligned on a 4k boundary. 70 */ 71 72 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 73 74 void pcic_attach_socket __P((struct pcic_handle *)); 75 void pcic_init_socket __P((struct pcic_handle *)); 76 77 #ifdef __BROKEN_INDIRECT_CONFIG 78 int pcic_submatch __P((struct device *, void *, void *)); 79 #else 80 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 81 #endif 82 int pcic_print __P((void *arg, const char *pnp)); 83 int pcic_intr_socket __P((struct pcic_handle *)); 84 85 void pcic_attach_card __P((struct pcic_handle *)); 86 void pcic_detach_card __P((struct pcic_handle *)); 87 88 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 89 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 90 91 struct cfdriver pcic_cd = { 92 NULL, "pcic", DV_DULL 93 }; 94 95 int 96 pcic_ident_ok(ident) 97 int ident; 98 { 99 /* this is very empirical and heuristic */ 100 101 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 102 return (0); 103 104 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 105 #ifdef DIAGNOSTIC 106 printf("pcic: does not support memory and I/O cards, " 107 "ignored (ident=%0x)\n", ident); 108 #endif 109 return (0); 110 } 111 return (1); 112 } 113 114 int 115 pcic_vendor(h) 116 struct pcic_handle *h; 117 { 118 int reg; 119 120 /* 121 * the chip_id of the cirrus toggles between 11 and 00 after a write. 122 * weird. 123 */ 124 125 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 126 reg = pcic_read(h, -1); 127 128 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 129 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 130 reg = pcic_read(h, -1); 131 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 132 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 133 return (PCIC_VENDOR_CIRRUS_PD672X); 134 else 135 return (PCIC_VENDOR_CIRRUS_PD6710); 136 } 137 } 138 /* XXX how do I identify the GD6729? */ 139 140 reg = pcic_read(h, PCIC_IDENT); 141 142 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 143 return (PCIC_VENDOR_I82365SLR0); 144 else 145 return (PCIC_VENDOR_I82365SLR1); 146 147 return (PCIC_VENDOR_UNKNOWN); 148 } 149 150 char * 151 pcic_vendor_to_string(vendor) 152 int vendor; 153 { 154 switch (vendor) { 155 case PCIC_VENDOR_I82365SLR0: 156 return ("Intel 82365SL Revision 0"); 157 case PCIC_VENDOR_I82365SLR1: 158 return ("Intel 82365SL Revision 1"); 159 case PCIC_VENDOR_CIRRUS_PD6710: 160 return ("Cirrus PD6710"); 161 case PCIC_VENDOR_CIRRUS_PD672X: 162 return ("Cirrus PD672X"); 163 } 164 165 return ("Unknown controller"); 166 } 167 168 void 169 pcic_attach(sc) 170 struct pcic_softc *sc; 171 { 172 int vendor, count, i, reg; 173 174 /* now check for each controller/socket */ 175 176 /* 177 * this could be done with a loop, but it would violate the 178 * abstraction 179 */ 180 181 count = 0; 182 183 DPRINTF(("pcic ident regs:")); 184 185 sc->handle[0].sc = sc; 186 sc->handle[0].sock = C0SA; 187 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 188 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 189 count++; 190 } else { 191 sc->handle[0].flags = 0; 192 } 193 194 DPRINTF((" 0x%02x", reg)); 195 196 sc->handle[1].sc = sc; 197 sc->handle[1].sock = C0SB; 198 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 199 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 200 count++; 201 } else { 202 sc->handle[1].flags = 0; 203 } 204 205 DPRINTF((" 0x%02x", reg)); 206 207 sc->handle[2].sc = sc; 208 sc->handle[2].sock = C1SA; 209 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], PCIC_IDENT))) { 210 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 211 count++; 212 } else { 213 sc->handle[2].flags = 0; 214 } 215 216 DPRINTF((" 0x%02x", reg)); 217 218 sc->handle[3].sc = sc; 219 sc->handle[3].sock = C1SB; 220 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], PCIC_IDENT))) { 221 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 222 count++; 223 } else { 224 sc->handle[3].flags = 0; 225 } 226 227 DPRINTF((" 0x%02x\n", reg)); 228 229 if (count == 0) 230 panic("pcic_attach: attach found no sockets"); 231 232 /* establish the interrupt */ 233 234 /* XXX block interrupts? */ 235 236 for (i = 0; i < PCIC_NSLOTS; i++) { 237 #if 0 238 /* 239 * this should work, but w/o it, setting tty flags hangs at 240 * boot time. 241 */ 242 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 243 #endif 244 { 245 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 246 pcic_read(&sc->handle[i], PCIC_CSC); 247 } 248 } 249 250 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 251 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 252 vendor = pcic_vendor(&sc->handle[0]); 253 254 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 255 pcic_vendor_to_string(vendor)); 256 257 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 258 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 259 printf("sockets A and B\n"); 260 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 261 printf("socket A only\n"); 262 else 263 printf("socket B only\n"); 264 265 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 266 sc->handle[0].vendor = vendor; 267 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 268 sc->handle[1].vendor = vendor; 269 } 270 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 271 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 272 vendor = pcic_vendor(&sc->handle[2]); 273 274 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 275 pcic_vendor_to_string(vendor)); 276 277 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 278 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 279 printf("sockets A and B\n"); 280 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 281 printf("socket A only\n"); 282 else 283 printf("socket B only\n"); 284 285 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 286 sc->handle[2].vendor = vendor; 287 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 288 sc->handle[3].vendor = vendor; 289 } 290 } 291 292 void 293 pcic_attach_sockets(sc) 294 struct pcic_softc *sc; 295 { 296 int i; 297 298 for (i = 0; i < PCIC_NSLOTS; i++) 299 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 300 pcic_attach_socket(&sc->handle[i]); 301 } 302 303 void 304 pcic_attach_socket(h) 305 struct pcic_handle *h; 306 { 307 struct pcmciabus_attach_args paa; 308 309 /* initialize the rest of the handle */ 310 311 h->memalloc = 0; 312 h->ioalloc = 0; 313 h->ih_irq = 0; 314 315 /* now, config one pcmcia device per socket */ 316 317 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 318 paa.pch = (pcmcia_chipset_handle_t) h; 319 paa.iobase = h->sc->iobase; 320 paa.iosize = h->sc->iosize; 321 322 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 323 pcic_submatch); 324 325 /* if there's actually a pcmcia device attached, initialize the slot */ 326 327 if (h->pcmcia) 328 pcic_init_socket(h); 329 } 330 331 void 332 pcic_init_socket(h) 333 struct pcic_handle *h; 334 { 335 int reg; 336 337 /* set up the card to interrupt on card detect */ 338 339 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 340 PCIC_CSC_INTR_CD_ENABLE); 341 pcic_write(h, PCIC_INTR, 0); 342 pcic_read(h, PCIC_CSC); 343 344 /* unsleep the cirrus controller */ 345 346 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 347 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 348 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 349 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 350 DPRINTF(("%s: socket %02x was suspended\n", 351 h->sc->dev.dv_xname, h->sock)); 352 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 353 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 354 } 355 } 356 /* if there's a card there, then attach it. */ 357 358 reg = pcic_read(h, PCIC_IF_STATUS); 359 360 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 361 PCIC_IF_STATUS_CARDDETECT_PRESENT) 362 pcic_attach_card(h); 363 } 364 365 int 366 #ifdef __BROKEN_INDIRECT_CONFIG 367 pcic_submatch(parent, match, aux) 368 #else 369 pcic_submatch(parent, cf, aux) 370 #endif 371 struct device *parent; 372 #ifdef __BROKEN_INDIRECT_CONFIG 373 void *match; 374 #else 375 struct cfdata *cf; 376 #endif 377 void *aux; 378 { 379 #ifdef __BROKEN_INDIRECT_CONFIG 380 struct cfdata *cf = match; 381 #endif 382 383 struct pcmciabus_attach_args *paa = aux; 384 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 385 386 switch (h->sock) { 387 case C0SA: 388 if (cf->cf_loc[PCICCF_CONTROLLER] != 389 PCICCF_CONTROLLER_DEFAULT && 390 cf->cf_loc[PCICCF_CONTROLLER] != 0) 391 return 0; 392 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 393 cf->cf_loc[PCICCF_SOCKET] != 0) 394 return 0; 395 396 break; 397 case C0SB: 398 if (cf->cf_loc[PCICCF_CONTROLLER] != 399 PCICCF_CONTROLLER_DEFAULT && 400 cf->cf_loc[PCICCF_CONTROLLER] != 0) 401 return 0; 402 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 403 cf->cf_loc[PCICCF_SOCKET] != 1) 404 return 0; 405 406 break; 407 case C1SA: 408 if (cf->cf_loc[PCICCF_CONTROLLER] != 409 PCICCF_CONTROLLER_DEFAULT && 410 cf->cf_loc[PCICCF_CONTROLLER] != 1) 411 return 0; 412 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 413 cf->cf_loc[PCICCF_SOCKET] != 0) 414 return 0; 415 416 break; 417 case C1SB: 418 if (cf->cf_loc[PCICCF_CONTROLLER] != 419 PCICCF_CONTROLLER_DEFAULT && 420 cf->cf_loc[PCICCF_CONTROLLER] != 1) 421 return 0; 422 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 423 cf->cf_loc[PCICCF_SOCKET] != 1) 424 return 0; 425 426 break; 427 default: 428 panic("unknown pcic socket"); 429 } 430 431 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 432 } 433 434 int 435 pcic_print(arg, pnp) 436 void *arg; 437 const char *pnp; 438 { 439 struct pcmciabus_attach_args *paa = arg; 440 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 441 442 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 443 if (pnp) 444 printf("pcmcia at %s", pnp); 445 446 switch (h->sock) { 447 case C0SA: 448 printf(" controller 0 socket 0"); 449 break; 450 case C0SB: 451 printf(" controller 0 socket 1"); 452 break; 453 case C1SA: 454 printf(" controller 1 socket 0"); 455 break; 456 case C1SB: 457 printf(" controller 1 socket 1"); 458 break; 459 default: 460 panic("unknown pcic socket"); 461 } 462 463 return (UNCONF); 464 } 465 466 int 467 pcic_intr(arg) 468 void *arg; 469 { 470 struct pcic_softc *sc = arg; 471 int i, ret = 0; 472 473 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 474 475 for (i = 0; i < PCIC_NSLOTS; i++) 476 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 477 ret += pcic_intr_socket(&sc->handle[i]); 478 479 return (ret ? 1 : 0); 480 } 481 482 int 483 pcic_intr_socket(h) 484 struct pcic_handle *h; 485 { 486 int cscreg; 487 488 cscreg = pcic_read(h, PCIC_CSC); 489 490 cscreg &= (PCIC_CSC_GPI | 491 PCIC_CSC_CD | 492 PCIC_CSC_READY | 493 PCIC_CSC_BATTWARN | 494 PCIC_CSC_BATTDEAD); 495 496 if (cscreg & PCIC_CSC_GPI) { 497 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 498 } 499 if (cscreg & PCIC_CSC_CD) { 500 int statreg; 501 502 statreg = pcic_read(h, PCIC_IF_STATUS); 503 504 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 505 statreg)); 506 507 /* 508 * XXX This should probably schedule something to happen 509 * after the interrupt handler completes 510 */ 511 512 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 513 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 514 if (!(h->flags & PCIC_FLAG_CARDP)) 515 pcic_attach_card(h); 516 } else { 517 if (h->flags & PCIC_FLAG_CARDP) 518 pcic_detach_card(h); 519 } 520 } 521 if (cscreg & PCIC_CSC_READY) { 522 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 523 /* shouldn't happen */ 524 } 525 if (cscreg & PCIC_CSC_BATTWARN) { 526 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 527 } 528 if (cscreg & PCIC_CSC_BATTDEAD) { 529 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 530 } 531 return (cscreg ? 1 : 0); 532 } 533 534 void 535 pcic_attach_card(h) 536 struct pcic_handle *h; 537 { 538 if (h->flags & PCIC_FLAG_CARDP) 539 panic("pcic_attach_card: already attached"); 540 541 /* call the MI attach function */ 542 543 pcmcia_card_attach(h->pcmcia); 544 545 h->flags |= PCIC_FLAG_CARDP; 546 } 547 548 void 549 pcic_detach_card(h) 550 struct pcic_handle *h; 551 { 552 if (!(h->flags & PCIC_FLAG_CARDP)) 553 panic("pcic_attach_card: already detached"); 554 555 h->flags &= ~PCIC_FLAG_CARDP; 556 557 /* call the MI attach function */ 558 559 pcmcia_card_detach(h->pcmcia); 560 561 /* disable card detect resume and configuration reset */ 562 563 /* power down the socket */ 564 565 pcic_write(h, PCIC_PWRCTL, 0); 566 567 /* reset the card */ 568 569 pcic_write(h, PCIC_INTR, 0); 570 } 571 572 int 573 pcic_chip_mem_alloc(pch, size, pcmhp) 574 pcmcia_chipset_handle_t pch; 575 bus_size_t size; 576 struct pcmcia_mem_handle *pcmhp; 577 { 578 struct pcic_handle *h = (struct pcic_handle *) pch; 579 bus_space_handle_t memh; 580 bus_addr_t addr; 581 bus_size_t sizepg; 582 int i, mask, mhandle; 583 584 /* out of sc->memh, allocate as many pages as necessary */ 585 586 /* convert size to PCIC pages */ 587 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 588 589 mask = (1 << sizepg) - 1; 590 591 addr = 0; /* XXX gcc -Wuninitialized */ 592 mhandle = 0; /* XXX gcc -Wuninitialized */ 593 594 for (i = 0; i < (PCIC_MEM_PAGES + 1 - sizepg); i++) { 595 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 596 if (bus_space_subregion(h->sc->memt, h->sc->memh, 597 i * PCIC_MEM_PAGESIZE, 598 sizepg * PCIC_MEM_PAGESIZE, &memh)) 599 return (1); 600 mhandle = mask << i; 601 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 602 h->sc->subregionmask &= ~(mhandle); 603 break; 604 } 605 } 606 607 if (i == (PCIC_MEM_PAGES + 1 - size)) 608 return (1); 609 610 DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 611 (u_long) size)); 612 613 pcmhp->memt = h->sc->memt; 614 pcmhp->memh = memh; 615 pcmhp->addr = addr; 616 pcmhp->size = size; 617 pcmhp->mhandle = mhandle; 618 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 619 620 return (0); 621 } 622 623 void 624 pcic_chip_mem_free(pch, pcmhp) 625 pcmcia_chipset_handle_t pch; 626 struct pcmcia_mem_handle *pcmhp; 627 { 628 struct pcic_handle *h = (struct pcic_handle *) pch; 629 630 h->sc->subregionmask |= pcmhp->mhandle; 631 } 632 633 static struct mem_map_index_st { 634 int sysmem_start_lsb; 635 int sysmem_start_msb; 636 int sysmem_stop_lsb; 637 int sysmem_stop_msb; 638 int cardmem_lsb; 639 int cardmem_msb; 640 int memenable; 641 } mem_map_index[] = { 642 { 643 PCIC_SYSMEM_ADDR0_START_LSB, 644 PCIC_SYSMEM_ADDR0_START_MSB, 645 PCIC_SYSMEM_ADDR0_STOP_LSB, 646 PCIC_SYSMEM_ADDR0_STOP_MSB, 647 PCIC_CARDMEM_ADDR0_LSB, 648 PCIC_CARDMEM_ADDR0_MSB, 649 PCIC_ADDRWIN_ENABLE_MEM0, 650 }, 651 { 652 PCIC_SYSMEM_ADDR1_START_LSB, 653 PCIC_SYSMEM_ADDR1_START_MSB, 654 PCIC_SYSMEM_ADDR1_STOP_LSB, 655 PCIC_SYSMEM_ADDR1_STOP_MSB, 656 PCIC_CARDMEM_ADDR1_LSB, 657 PCIC_CARDMEM_ADDR1_MSB, 658 PCIC_ADDRWIN_ENABLE_MEM1, 659 }, 660 { 661 PCIC_SYSMEM_ADDR2_START_LSB, 662 PCIC_SYSMEM_ADDR2_START_MSB, 663 PCIC_SYSMEM_ADDR2_STOP_LSB, 664 PCIC_SYSMEM_ADDR2_STOP_MSB, 665 PCIC_CARDMEM_ADDR2_LSB, 666 PCIC_CARDMEM_ADDR2_MSB, 667 PCIC_ADDRWIN_ENABLE_MEM2, 668 }, 669 { 670 PCIC_SYSMEM_ADDR3_START_LSB, 671 PCIC_SYSMEM_ADDR3_START_MSB, 672 PCIC_SYSMEM_ADDR3_STOP_LSB, 673 PCIC_SYSMEM_ADDR3_STOP_MSB, 674 PCIC_CARDMEM_ADDR3_LSB, 675 PCIC_CARDMEM_ADDR3_MSB, 676 PCIC_ADDRWIN_ENABLE_MEM3, 677 }, 678 { 679 PCIC_SYSMEM_ADDR4_START_LSB, 680 PCIC_SYSMEM_ADDR4_START_MSB, 681 PCIC_SYSMEM_ADDR4_STOP_LSB, 682 PCIC_SYSMEM_ADDR4_STOP_MSB, 683 PCIC_CARDMEM_ADDR4_LSB, 684 PCIC_CARDMEM_ADDR4_MSB, 685 PCIC_ADDRWIN_ENABLE_MEM4, 686 }, 687 }; 688 689 void 690 pcic_chip_do_mem_map(h, win) 691 struct pcic_handle *h; 692 int win; 693 { 694 int reg; 695 696 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 697 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 698 pcic_write(h, mem_map_index[win].sysmem_start_msb, 699 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 700 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 701 702 #if 0 703 /* XXX do I want 16 bit all the time? */ 704 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 705 #endif 706 707 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 708 ((h->mem[win].addr + h->mem[win].size) >> 709 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 710 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 711 (((h->mem[win].addr + h->mem[win].size) >> 712 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 713 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 714 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 715 716 pcic_write(h, mem_map_index[win].cardmem_lsb, 717 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 718 pcic_write(h, mem_map_index[win].cardmem_msb, 719 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 720 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 721 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 722 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 723 724 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 725 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 726 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 727 728 #ifdef PCICDEBUG 729 { 730 int r1, r2, r3, r4, r5, r6; 731 732 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 733 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 734 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 735 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 736 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 737 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 738 739 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 740 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 741 } 742 #endif 743 } 744 745 int 746 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 747 pcmcia_chipset_handle_t pch; 748 int kind; 749 bus_addr_t card_addr; 750 bus_size_t size; 751 struct pcmcia_mem_handle *pcmhp; 752 bus_addr_t *offsetp; 753 int *windowp; 754 { 755 struct pcic_handle *h = (struct pcic_handle *) pch; 756 bus_addr_t busaddr; 757 long card_offset; 758 int i, win; 759 760 win = -1; 761 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 762 i++) { 763 if ((h->memalloc & (1 << i)) == 0) { 764 win = i; 765 h->memalloc |= (1 << i); 766 break; 767 } 768 } 769 770 if (win == -1) 771 return (1); 772 773 *windowp = win; 774 775 /* XXX this is pretty gross */ 776 777 if (h->sc->memt != pcmhp->memt) 778 panic("pcic_chip_mem_map memt is bogus"); 779 780 busaddr = pcmhp->addr; 781 782 /* 783 * compute the address offset to the pcmcia address space for the 784 * pcic. this is intentionally signed. The masks and shifts below 785 * will cause TRT to happen in the pcic registers. Deal with making 786 * sure the address is aligned, and return the alignment offset. 787 */ 788 789 *offsetp = card_addr % PCIC_MEM_ALIGN; 790 card_addr -= *offsetp; 791 792 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 793 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 794 (u_long) card_addr)); 795 796 /* 797 * include the offset in the size, and decrement size by one, since 798 * the hw wants start/stop 799 */ 800 size += *offsetp - 1; 801 802 card_offset = (((long) card_addr) - ((long) busaddr)); 803 804 h->mem[win].addr = busaddr; 805 h->mem[win].size = size; 806 h->mem[win].offset = card_offset; 807 h->mem[win].kind = kind; 808 809 pcic_chip_do_mem_map(h, win); 810 811 return (0); 812 } 813 814 void 815 pcic_chip_mem_unmap(pch, window) 816 pcmcia_chipset_handle_t pch; 817 int window; 818 { 819 struct pcic_handle *h = (struct pcic_handle *) pch; 820 int reg; 821 822 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 823 panic("pcic_chip_mem_unmap: window out of range"); 824 825 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 826 reg &= ~mem_map_index[window].memenable; 827 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 828 829 h->memalloc &= ~(1 << window); 830 } 831 832 int 833 pcic_chip_io_alloc(pch, start, size, align, pcihp) 834 pcmcia_chipset_handle_t pch; 835 bus_addr_t start; 836 bus_size_t size; 837 bus_size_t align; 838 struct pcmcia_io_handle *pcihp; 839 { 840 struct pcic_handle *h = (struct pcic_handle *) pch; 841 bus_space_tag_t iot; 842 bus_space_handle_t ioh; 843 bus_addr_t ioaddr; 844 int flags = 0; 845 846 /* 847 * Allocate some arbitrary I/O space. 848 */ 849 850 iot = h->sc->iot; 851 852 if (start) { 853 ioaddr = start; 854 if (bus_space_map(iot, start, size, 0, &ioh)) 855 return (1); 856 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 857 (u_long) ioaddr, (u_long) size)); 858 } else { 859 flags |= PCMCIA_IO_ALLOCATED; 860 if (bus_space_alloc(iot, h->sc->iobase, 861 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 862 &ioaddr, &ioh)) 863 return (1); 864 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 865 (u_long) ioaddr, (u_long) size)); 866 } 867 868 pcihp->iot = iot; 869 pcihp->ioh = ioh; 870 pcihp->addr = ioaddr; 871 pcihp->size = size; 872 pcihp->flags = flags; 873 874 return (0); 875 } 876 877 void 878 pcic_chip_io_free(pch, pcihp) 879 pcmcia_chipset_handle_t pch; 880 struct pcmcia_io_handle *pcihp; 881 { 882 bus_space_tag_t iot = pcihp->iot; 883 bus_space_handle_t ioh = pcihp->ioh; 884 bus_size_t size = pcihp->size; 885 886 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 887 bus_space_free(iot, ioh, size); 888 else 889 bus_space_unmap(iot, ioh, size); 890 } 891 892 893 static struct io_map_index_st { 894 int start_lsb; 895 int start_msb; 896 int stop_lsb; 897 int stop_msb; 898 int ioenable; 899 int ioctlmask; 900 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 901 } io_map_index[] = { 902 { 903 PCIC_IOADDR0_START_LSB, 904 PCIC_IOADDR0_START_MSB, 905 PCIC_IOADDR0_STOP_LSB, 906 PCIC_IOADDR0_STOP_MSB, 907 PCIC_ADDRWIN_ENABLE_IO0, 908 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 909 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 910 { 911 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 912 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 913 PCIC_IOCTL_IO0_DATASIZE_8BIT, 914 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 915 PCIC_IOCTL_IO0_DATASIZE_16BIT, 916 }, 917 }, 918 { 919 PCIC_IOADDR1_START_LSB, 920 PCIC_IOADDR1_START_MSB, 921 PCIC_IOADDR1_STOP_LSB, 922 PCIC_IOADDR1_STOP_MSB, 923 PCIC_ADDRWIN_ENABLE_IO1, 924 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 925 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 926 { 927 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 928 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 929 PCIC_IOCTL_IO1_DATASIZE_8BIT, 930 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 931 PCIC_IOCTL_IO1_DATASIZE_16BIT, 932 }, 933 }, 934 }; 935 936 void 937 pcic_chip_do_io_map(h, win) 938 struct pcic_handle *h; 939 int win; 940 { 941 int reg; 942 943 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 944 win, (long) h->io[win].addr, (long) h->io[win].size, 945 h->io[win].width * 8)); 946 947 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 948 pcic_write(h, io_map_index[win].start_msb, 949 (h->io[win].addr >> 8) & 0xff); 950 951 pcic_write(h, io_map_index[win].stop_lsb, 952 (h->io[win].addr + h->io[win].size - 1) & 0xff); 953 pcic_write(h, io_map_index[win].stop_msb, 954 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 955 956 reg = pcic_read(h, PCIC_IOCTL); 957 reg &= ~io_map_index[win].ioctlmask; 958 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 959 pcic_write(h, PCIC_IOCTL, reg); 960 961 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 962 reg |= io_map_index[win].ioenable; 963 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 964 } 965 966 int 967 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 968 pcmcia_chipset_handle_t pch; 969 int width; 970 bus_addr_t offset; 971 bus_size_t size; 972 struct pcmcia_io_handle *pcihp; 973 int *windowp; 974 { 975 struct pcic_handle *h = (struct pcic_handle *) pch; 976 bus_addr_t ioaddr = pcihp->addr + offset; 977 int i, win; 978 #ifdef PCICDEBUG 979 static char *width_names[] = { "auto", "io8", "io16" }; 980 #endif 981 982 /* XXX Sanity check offset/size. */ 983 984 win = -1; 985 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 986 if ((h->ioalloc & (1 << i)) == 0) { 987 win = i; 988 h->ioalloc |= (1 << i); 989 break; 990 } 991 } 992 993 if (win == -1) 994 return (1); 995 996 *windowp = win; 997 998 /* XXX this is pretty gross */ 999 1000 if (h->sc->iot != pcihp->iot) 1001 panic("pcic_chip_io_map iot is bogus"); 1002 1003 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1004 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1005 1006 /* XXX wtf is this doing here? */ 1007 1008 printf(" port 0x%lx", (u_long) ioaddr); 1009 if (size > 1) 1010 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1011 1012 h->io[win].addr = ioaddr; 1013 h->io[win].size = size; 1014 h->io[win].width = width; 1015 1016 pcic_chip_do_io_map(h, win); 1017 1018 return (0); 1019 } 1020 1021 void 1022 pcic_chip_io_unmap(pch, window) 1023 pcmcia_chipset_handle_t pch; 1024 int window; 1025 { 1026 struct pcic_handle *h = (struct pcic_handle *) pch; 1027 int reg; 1028 1029 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1030 panic("pcic_chip_io_unmap: window out of range"); 1031 1032 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1033 reg &= ~io_map_index[window].ioenable; 1034 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1035 1036 h->ioalloc &= ~(1 << window); 1037 } 1038 1039 void 1040 pcic_chip_socket_enable(pch) 1041 pcmcia_chipset_handle_t pch; 1042 { 1043 struct pcic_handle *h = (struct pcic_handle *) pch; 1044 int cardtype, reg, win; 1045 1046 /* this bit is mostly stolen from pcic_attach_card */ 1047 1048 /* power down the socket to reset it, clear the card reset pin */ 1049 1050 pcic_write(h, PCIC_PWRCTL, 0); 1051 1052 /* power up the socket */ 1053 1054 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_PWR_ENABLE); 1055 delay(10000); 1056 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_OE); 1057 1058 /* clear the reset flag */ 1059 1060 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1061 1062 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1063 1064 delay(20000); 1065 1066 /* wait for the chip to finish initializing */ 1067 1068 pcic_wait_ready(h); 1069 1070 /* zero out the address windows */ 1071 1072 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1073 1074 /* set the card type */ 1075 1076 cardtype = pcmcia_card_gettype(h->pcmcia); 1077 1078 reg = pcic_read(h, PCIC_INTR); 1079 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1080 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1081 PCIC_INTR_CARDTYPE_IO : 1082 PCIC_INTR_CARDTYPE_MEM); 1083 reg |= h->ih_irq; 1084 pcic_write(h, PCIC_INTR, reg); 1085 1086 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1087 h->sc->dev.dv_xname, h->sock, 1088 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1089 1090 /* reinstall all the memory and io mappings */ 1091 1092 for (win = 0; win < PCIC_MEM_WINS; win++) 1093 if (h->memalloc & (1 << win)) 1094 pcic_chip_do_mem_map(h, win); 1095 1096 for (win = 0; win < PCIC_IO_WINS; win++) 1097 if (h->ioalloc & (1 << win)) 1098 pcic_chip_do_io_map(h, win); 1099 } 1100 1101 void 1102 pcic_chip_socket_disable(pch) 1103 pcmcia_chipset_handle_t pch; 1104 { 1105 struct pcic_handle *h = (struct pcic_handle *) pch; 1106 1107 DPRINTF(("pcic_chip_socket_disable\n")); 1108 1109 /* power down the socket */ 1110 1111 pcic_write(h, PCIC_PWRCTL, 0); 1112 } 1113
Indexes created Fri Sep 26 20:09:58 GMT 2025