i82365.c revision 1.92
1 /* $NetBSD: i82365.c,v 1.92 2005/08/25 22:33:19 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 */ 20 21 /* 22 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 23 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 3. All advertising materials mentioning features or use of this software 34 * must display the following acknowledgement: 35 * This product includes software developed by Marc Horowitz. 36 * 4. The name of the author may not be used to endorse or promote products 37 * derived from this software without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 44 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 48 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.92 2005/08/25 22:33:19 drochner Exp $"); 53 54 #define PCICDEBUG 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/extent.h> 60 #include <sys/kernel.h> 61 #include <sys/malloc.h> 62 #include <sys/kthread.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <dev/pcmcia/pcmciareg.h> 68 #include <dev/pcmcia/pcmciavar.h> 69 70 #include <dev/ic/i82365reg.h> 71 #include <dev/ic/i82365var.h> 72 73 #include "locators.h" 74 75 #ifdef PCICDEBUG 76 int pcic_debug = 0; 77 #define DPRINTF(arg) if (pcic_debug) printf arg; 78 #else 79 #define DPRINTF(arg) 80 #endif 81 82 /* 83 * Individual drivers will allocate their own memory and io regions. Memory 84 * regions must be a multiple of 4k, aligned on a 4k boundary. 85 */ 86 87 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 88 89 void pcic_attach_socket(struct pcic_handle *); 90 void pcic_attach_socket_finish(struct pcic_handle *); 91 92 int pcic_print (void *arg, const char *pnp); 93 int pcic_intr_socket(struct pcic_handle *); 94 void pcic_poll_intr(void *); 95 96 void pcic_attach_card(struct pcic_handle *); 97 void pcic_detach_card(struct pcic_handle *, int); 98 void pcic_deactivate_card(struct pcic_handle *); 99 100 void pcic_chip_do_mem_map(struct pcic_handle *, int); 101 void pcic_chip_do_io_map(struct pcic_handle *, int); 102 103 void pcic_create_event_thread(void *); 104 void pcic_event_thread(void *); 105 106 void pcic_queue_event(struct pcic_handle *, int); 107 void pcic_power(int, void *); 108 109 static int pcic_wait_ready(struct pcic_handle *); 110 static void pcic_delay(struct pcic_handle *, int, const char *); 111 112 static u_int8_t st_pcic_read(struct pcic_handle *, int); 113 static void st_pcic_write(struct pcic_handle *, int, u_int8_t); 114 115 int 116 pcic_ident_ok(ident) 117 int ident; 118 { 119 /* this is very empirical and heuristic */ 120 121 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 122 return (0); 123 124 if ((ident & PCIC_IDENT_REV_MASK) == 0) 125 return (0); 126 127 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 128 #ifdef DIAGNOSTIC 129 printf("pcic: does not support memory and I/O cards, " 130 "ignored (ident=%0x)\n", ident); 131 #endif 132 return (0); 133 } 134 135 return (1); 136 } 137 138 int 139 pcic_vendor(h) 140 struct pcic_handle *h; 141 { 142 int reg; 143 int vendor; 144 145 reg = pcic_read(h, PCIC_IDENT); 146 147 if ((reg & PCIC_IDENT_REV_MASK) == 0) 148 return (PCIC_VENDOR_NONE); 149 150 switch (reg) { 151 case 0x00: 152 case 0xff: 153 return (PCIC_VENDOR_NONE); 154 case PCIC_IDENT_ID_INTEL0: 155 vendor = PCIC_VENDOR_I82365SLR0; 156 break; 157 case PCIC_IDENT_ID_INTEL1: 158 vendor = PCIC_VENDOR_I82365SLR1; 159 break; 160 case PCIC_IDENT_ID_INTEL2: 161 vendor = PCIC_VENDOR_I82365SL_DF; 162 break; 163 case PCIC_IDENT_ID_IBM1: 164 case PCIC_IDENT_ID_IBM2: 165 vendor = PCIC_VENDOR_IBM; 166 break; 167 case PCIC_IDENT_ID_IBM3: 168 vendor = PCIC_VENDOR_IBM_KING; 169 break; 170 default: 171 vendor = PCIC_VENDOR_UNKNOWN; 172 break; 173 } 174 175 if (vendor == PCIC_VENDOR_I82365SLR0 || 176 vendor == PCIC_VENDOR_I82365SLR1) { 177 /* 178 * Check for Cirrus PD67xx. 179 * the chip_id of the cirrus toggles between 11 and 00 after a 180 * write. weird. 181 */ 182 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 183 reg = pcic_read(h, -1); 184 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 185 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 186 reg = pcic_read(h, -1); 187 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) 188 return (PCIC_VENDOR_CIRRUS_PD67XX); 189 } 190 191 /* 192 * check for Ricoh RF5C[23]96 193 */ 194 reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 195 switch (reg) { 196 case PCIC_RICOH_CHIP_ID_5C296: 197 return (PCIC_VENDOR_RICOH_5C296); 198 case PCIC_RICOH_CHIP_ID_5C396: 199 return (PCIC_VENDOR_RICOH_5C396); 200 } 201 } 202 203 return (vendor); 204 } 205 206 const char * 207 pcic_vendor_to_string(vendor) 208 int vendor; 209 { 210 switch (vendor) { 211 case PCIC_VENDOR_I82365SLR0: 212 return ("Intel 82365SL Revision 0"); 213 case PCIC_VENDOR_I82365SLR1: 214 return ("Intel 82365SL Revision 1"); 215 case PCIC_VENDOR_CIRRUS_PD67XX: 216 return ("Cirrus PD6710/2X"); 217 case PCIC_VENDOR_I82365SL_DF: 218 return ("Intel 82365SL-DF"); 219 case PCIC_VENDOR_RICOH_5C296: 220 return ("Ricoh RF5C296"); 221 case PCIC_VENDOR_RICOH_5C396: 222 return ("Ricoh RF5C396"); 223 case PCIC_VENDOR_IBM: 224 return ("IBM PCIC"); 225 case PCIC_VENDOR_IBM_KING: 226 return ("IBM KING"); 227 } 228 229 return ("Unknown controller"); 230 } 231 232 void 233 pcic_attach(sc) 234 struct pcic_softc *sc; 235 { 236 int i, reg, chip, socket; 237 struct pcic_handle *h; 238 239 DPRINTF(("pcic ident regs:")); 240 241 lockinit(&sc->sc_pcic_lock, PWAIT, "pciclk", 0, 0); 242 243 /* find and configure for the available sockets */ 244 for (i = 0; i < PCIC_NSLOTS; i++) { 245 h = &sc->handle[i]; 246 chip = i / 2; 247 socket = i % 2; 248 249 h->ph_parent = (struct device *)sc; 250 h->chip = chip; 251 h->socket = socket; 252 h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 253 h->laststate = PCIC_LASTSTATE_EMPTY; 254 /* initialize pcic_read and pcic_write functions */ 255 h->ph_read = st_pcic_read; 256 h->ph_write = st_pcic_write; 257 h->ph_bus_t = sc->iot; 258 h->ph_bus_h = sc->ioh; 259 h->flags = 0; 260 261 /* need to read vendor -- for cirrus to report no xtra chip */ 262 if (socket == 0) 263 h->vendor = (h+1)->vendor = pcic_vendor(h); 264 265 switch (h->vendor) { 266 case PCIC_VENDOR_NONE: 267 /* no chip */ 268 continue; 269 case PCIC_VENDOR_CIRRUS_PD67XX: 270 reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO); 271 if (socket == 0 || 272 (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)) 273 h->flags = PCIC_FLAG_SOCKETP; 274 break; 275 default: 276 /* 277 * During the socket probe, read the ident register 278 * twice. I don't understand why, but sometimes the 279 * clone chips in hpcmips boxes read all-0s the first 280 * time. -- mycroft 281 */ 282 reg = pcic_read(h, PCIC_IDENT); 283 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 284 reg = pcic_read(h, PCIC_IDENT); 285 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 286 if (pcic_ident_ok(reg)) 287 h->flags = PCIC_FLAG_SOCKETP; 288 break; 289 } 290 } 291 292 for (i = 0; i < PCIC_NSLOTS; i++) { 293 h = &sc->handle[i]; 294 295 if (h->flags & PCIC_FLAG_SOCKETP) { 296 SIMPLEQ_INIT(&h->events); 297 298 /* disable interrupts and leave socket in reset */ 299 pcic_write(h, PCIC_INTR, 0); 300 301 /* zero out the address windows */ 302 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 303 304 /* power down the socket */ 305 pcic_write(h, PCIC_PWRCTL, 0); 306 307 pcic_write(h, PCIC_CSC_INTR, 0); 308 (void) pcic_read(h, PCIC_CSC); 309 } 310 } 311 312 /* print detected info */ 313 for (i = 0; i < PCIC_NSLOTS; i += 2) { 314 h = &sc->handle[i]; 315 chip = i / 2; 316 317 if (h->vendor == PCIC_VENDOR_NONE) 318 continue; 319 320 aprint_normal("%s: controller %d (%s) has ", sc->dev.dv_xname, 321 chip, pcic_vendor_to_string(sc->handle[i].vendor)); 322 323 if ((h->flags & PCIC_FLAG_SOCKETP) && 324 ((h+1)->flags & PCIC_FLAG_SOCKETP)) 325 aprint_normal("sockets A and B\n"); 326 else if (h->flags & PCIC_FLAG_SOCKETP) 327 aprint_normal("socket A only\n"); 328 else if ((h+1)->flags & PCIC_FLAG_SOCKETP) 329 aprint_normal("socket B only\n"); 330 else 331 aprint_normal("no sockets\n"); 332 } 333 } 334 335 /* 336 * attach the sockets before we know what interrupts we have 337 */ 338 void 339 pcic_attach_sockets(sc) 340 struct pcic_softc *sc; 341 { 342 int i; 343 344 for (i = 0; i < PCIC_NSLOTS; i++) 345 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 346 pcic_attach_socket(&sc->handle[i]); 347 } 348 349 void 350 pcic_power(why, arg) 351 int why; 352 void *arg; 353 { 354 struct pcic_handle *h = (struct pcic_handle *)arg; 355 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 356 int reg; 357 358 DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 359 360 if (h->flags & PCIC_FLAG_SOCKETP) { 361 if ((why == PWR_RESUME) && 362 (pcic_read(h, PCIC_CSC_INTR) == 0)) { 363 #ifdef PCICDEBUG 364 char bitbuf[64]; 365 #endif 366 reg = PCIC_CSC_INTR_CD_ENABLE; 367 if (sc->irq != -1) 368 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 369 pcic_write(h, PCIC_CSC_INTR, reg); 370 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 371 sc->dev.dv_xname, 372 bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 373 PCIC_CSC_INTR_FORMAT, 374 bitbuf, sizeof(bitbuf)))); 375 } 376 377 /* 378 * check for card insertion or removal during suspend period. 379 * XXX: the code can't cope with card swap (remove then insert). 380 * how can we detect such situation? 381 */ 382 if (why == PWR_RESUME) 383 (void)pcic_intr_socket(h); 384 } 385 } 386 387 388 /* 389 * attach a socket -- we don't know about irqs yet 390 */ 391 void 392 pcic_attach_socket(h) 393 struct pcic_handle *h; 394 { 395 struct pcmciabus_attach_args paa; 396 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 397 int locs[PCMCIABUSCF_NLOCS]; 398 399 /* initialize the rest of the handle */ 400 401 h->shutdown = 0; 402 h->memalloc = 0; 403 h->ioalloc = 0; 404 h->ih_irq = 0; 405 406 /* now, config one pcmcia device per socket */ 407 408 paa.paa_busname = "pcmcia"; 409 paa.pct = (pcmcia_chipset_tag_t) sc->pct; 410 paa.pch = (pcmcia_chipset_handle_t) h; 411 paa.iobase = sc->iobase; 412 paa.iosize = sc->iosize; 413 414 locs[PCMCIABUSCF_CONTROLLER] = h->chip; 415 locs[PCMCIABUSCF_SOCKET] = h->socket; 416 417 h->pcmcia = config_found_sm_loc(&sc->dev, "pcmciabus", locs, &paa, 418 pcic_print, config_stdsubmatch); 419 if (h->pcmcia == NULL) { 420 h->flags &= ~PCIC_FLAG_SOCKETP; 421 return; 422 } 423 424 /* 425 * queue creation of a kernel thread to handle insert/removal events. 426 */ 427 #ifdef DIAGNOSTIC 428 if (h->event_thread != NULL) 429 panic("pcic_attach_socket: event thread"); 430 #endif 431 config_pending_incr(); 432 kthread_create(pcic_create_event_thread, h); 433 } 434 435 /* 436 * now finish attaching the sockets, we are ready to allocate 437 * interrupts 438 */ 439 void 440 pcic_attach_sockets_finish(sc) 441 struct pcic_softc *sc; 442 { 443 int i; 444 445 for (i = 0; i < PCIC_NSLOTS; i++) 446 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 447 pcic_attach_socket_finish(&sc->handle[i]); 448 } 449 450 /* 451 * finishing attaching the socket. Interrupts may now be on 452 * if so expects the pcic interrupt to be blocked 453 */ 454 void 455 pcic_attach_socket_finish(h) 456 struct pcic_handle *h; 457 { 458 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 459 int reg; 460 461 DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 462 (long) (h - &sc->handle[0]))); 463 464 /* 465 * Set up a powerhook to ensure it continues to interrupt on 466 * card detect even after suspend. 467 * (this works around a bug seen in suspend-to-disk on the 468 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 469 */ 470 powerhook_establish(pcic_power, h); 471 472 /* enable interrupts on card detect, poll for them if no irq avail */ 473 reg = PCIC_CSC_INTR_CD_ENABLE; 474 if (sc->irq == -1) { 475 if (sc->poll_established == 0) { 476 callout_init(&sc->poll_ch); 477 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 478 sc->poll_established = 1; 479 } 480 } else 481 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 482 pcic_write(h, PCIC_CSC_INTR, reg); 483 484 /* steer above mgmt interrupt to configured place */ 485 if (sc->irq == 0) 486 pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE); 487 488 /* clear possible card detect interrupt */ 489 (void) pcic_read(h, PCIC_CSC); 490 491 DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 492 h->vendor)); 493 494 /* unsleep the cirrus controller */ 495 if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) { 496 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 497 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 498 DPRINTF(("%s: socket %02x was suspended\n", 499 h->ph_parent->dv_xname, h->sock)); 500 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 501 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 502 } 503 } 504 505 /* if there's a card there, then attach it. */ 506 reg = pcic_read(h, PCIC_IF_STATUS); 507 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 508 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 509 pcic_queue_event(h, PCIC_EVENT_INSERTION); 510 h->laststate = PCIC_LASTSTATE_PRESENT; 511 } else { 512 h->laststate = PCIC_LASTSTATE_EMPTY; 513 } 514 } 515 516 void 517 pcic_create_event_thread(arg) 518 void *arg; 519 { 520 struct pcic_handle *h = arg; 521 char cs[4]; 522 523 snprintf(cs, sizeof(cs), "%d,%d", h->chip, h->socket); 524 525 if (kthread_create1(pcic_event_thread, h, &h->event_thread, 526 "%s,%s", h->ph_parent->dv_xname, cs)) { 527 printf("%s: unable to create event thread for sock 0x%02x\n", 528 h->ph_parent->dv_xname, h->sock); 529 panic("pcic_create_event_thread"); 530 } 531 } 532 533 void 534 pcic_event_thread(arg) 535 void *arg; 536 { 537 struct pcic_handle *h = arg; 538 struct pcic_event *pe; 539 int s, first = 1; 540 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 541 542 while (h->shutdown == 0) { 543 /* 544 * Serialize event processing on the PCIC. We may 545 * sleep while we hold this lock. 546 */ 547 (void) lockmgr(&sc->sc_pcic_lock, LK_EXCLUSIVE, NULL); 548 549 s = splhigh(); 550 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 551 splx(s); 552 if (first) { 553 first = 0; 554 config_pending_decr(); 555 } 556 /* 557 * No events to process; release the PCIC lock. 558 */ 559 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 560 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 561 continue; 562 } else { 563 splx(s); 564 /* sleep .25s to be enqueued chatterling interrupts */ 565 (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 566 "pcicss", hz/4); 567 } 568 s = splhigh(); 569 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 570 splx(s); 571 572 switch (pe->pe_type) { 573 case PCIC_EVENT_INSERTION: 574 s = splhigh(); 575 while (1) { 576 struct pcic_event *pe1, *pe2; 577 578 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 579 break; 580 if (pe1->pe_type != PCIC_EVENT_REMOVAL) 581 break; 582 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 583 break; 584 if (pe2->pe_type == PCIC_EVENT_INSERTION) { 585 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 586 free(pe1, M_TEMP); 587 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 588 free(pe2, M_TEMP); 589 } 590 } 591 splx(s); 592 593 DPRINTF(("%s: insertion event\n", 594 h->ph_parent->dv_xname)); 595 pcic_attach_card(h); 596 break; 597 598 case PCIC_EVENT_REMOVAL: 599 s = splhigh(); 600 while (1) { 601 struct pcic_event *pe1, *pe2; 602 603 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 604 break; 605 if (pe1->pe_type != PCIC_EVENT_INSERTION) 606 break; 607 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 608 break; 609 if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 610 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 611 free(pe1, M_TEMP); 612 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 613 free(pe2, M_TEMP); 614 } 615 } 616 splx(s); 617 618 DPRINTF(("%s: removal event\n", 619 h->ph_parent->dv_xname)); 620 pcic_detach_card(h, DETACH_FORCE); 621 break; 622 623 default: 624 panic("pcic_event_thread: unknown event %d", 625 pe->pe_type); 626 } 627 free(pe, M_TEMP); 628 629 (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 630 } 631 632 h->event_thread = NULL; 633 634 /* In case parent is waiting for us to exit. */ 635 wakeup(sc); 636 637 kthread_exit(0); 638 } 639 640 int 641 pcic_print(arg, pnp) 642 void *arg; 643 const char *pnp; 644 { 645 struct pcmciabus_attach_args *paa = arg; 646 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 647 648 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 649 if (pnp) 650 aprint_normal("pcmcia at %s", pnp); 651 652 aprint_normal(" controller %d socket %d", h->chip, h->socket); 653 654 return (UNCONF); 655 } 656 657 void 658 pcic_poll_intr(arg) 659 void *arg; 660 { 661 struct pcic_softc *sc; 662 int i, s; 663 664 s = spltty(); 665 sc = arg; 666 for (i = 0; i < PCIC_NSLOTS; i++) 667 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 668 (void)pcic_intr_socket(&sc->handle[i]); 669 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 670 splx(s); 671 } 672 673 int 674 pcic_intr(arg) 675 void *arg; 676 { 677 struct pcic_softc *sc = arg; 678 int i, ret = 0; 679 680 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 681 682 for (i = 0; i < PCIC_NSLOTS; i++) 683 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 684 ret += pcic_intr_socket(&sc->handle[i]); 685 686 return (ret ? 1 : 0); 687 } 688 689 int 690 pcic_intr_socket(h) 691 struct pcic_handle *h; 692 { 693 int cscreg; 694 695 cscreg = pcic_read(h, PCIC_CSC); 696 697 cscreg &= (PCIC_CSC_GPI | 698 PCIC_CSC_CD | 699 PCIC_CSC_READY | 700 PCIC_CSC_BATTWARN | 701 PCIC_CSC_BATTDEAD); 702 703 if (cscreg & PCIC_CSC_GPI) { 704 DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 705 } 706 if (cscreg & PCIC_CSC_CD) { 707 int statreg; 708 709 statreg = pcic_read(h, PCIC_IF_STATUS); 710 711 DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 712 statreg)); 713 714 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 715 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 716 if (h->laststate != PCIC_LASTSTATE_PRESENT) { 717 DPRINTF(("%s: enqueing INSERTION event\n", 718 h->ph_parent->dv_xname)); 719 pcic_queue_event(h, PCIC_EVENT_INSERTION); 720 } 721 h->laststate = PCIC_LASTSTATE_PRESENT; 722 } else { 723 if (h->laststate == PCIC_LASTSTATE_PRESENT) { 724 /* Deactivate the card now. */ 725 DPRINTF(("%s: deactivating card\n", 726 h->ph_parent->dv_xname)); 727 pcic_deactivate_card(h); 728 729 DPRINTF(("%s: enqueing REMOVAL event\n", 730 h->ph_parent->dv_xname)); 731 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 732 } 733 h->laststate = PCIC_LASTSTATE_EMPTY; 734 } 735 } 736 if (cscreg & PCIC_CSC_READY) { 737 DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 738 /* shouldn't happen */ 739 } 740 if (cscreg & PCIC_CSC_BATTWARN) { 741 DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 742 h->sock)); 743 } 744 if (cscreg & PCIC_CSC_BATTDEAD) { 745 DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 746 h->sock)); 747 } 748 return (cscreg ? 1 : 0); 749 } 750 751 void 752 pcic_queue_event(h, event) 753 struct pcic_handle *h; 754 int event; 755 { 756 struct pcic_event *pe; 757 int s; 758 759 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 760 if (pe == NULL) 761 panic("pcic_queue_event: can't allocate event"); 762 763 pe->pe_type = event; 764 s = splhigh(); 765 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 766 splx(s); 767 wakeup(&h->events); 768 } 769 770 void 771 pcic_attach_card(h) 772 struct pcic_handle *h; 773 { 774 775 if (!(h->flags & PCIC_FLAG_CARDP)) { 776 /* call the MI attach function */ 777 pcmcia_card_attach(h->pcmcia); 778 779 h->flags |= PCIC_FLAG_CARDP; 780 } else { 781 DPRINTF(("pcic_attach_card: already attached")); 782 } 783 } 784 785 void 786 pcic_detach_card(h, flags) 787 struct pcic_handle *h; 788 int flags; /* DETACH_* */ 789 { 790 791 if (h->flags & PCIC_FLAG_CARDP) { 792 h->flags &= ~PCIC_FLAG_CARDP; 793 794 /* call the MI detach function */ 795 pcmcia_card_detach(h->pcmcia, flags); 796 } else { 797 DPRINTF(("pcic_detach_card: already detached")); 798 } 799 } 800 801 void 802 pcic_deactivate_card(h) 803 struct pcic_handle *h; 804 { 805 int intr; 806 807 /* call the MI deactivate function */ 808 pcmcia_card_deactivate(h->pcmcia); 809 810 /* reset the socket */ 811 intr = pcic_read(h, PCIC_INTR); 812 intr &= PCIC_INTR_ENABLE; 813 pcic_write(h, PCIC_INTR, intr); 814 815 /* power down the socket */ 816 pcic_write(h, PCIC_PWRCTL, 0); 817 } 818 819 int 820 pcic_chip_mem_alloc(pch, size, pcmhp) 821 pcmcia_chipset_handle_t pch; 822 bus_size_t size; 823 struct pcmcia_mem_handle *pcmhp; 824 { 825 struct pcic_handle *h = (struct pcic_handle *) pch; 826 bus_space_handle_t memh; 827 bus_addr_t addr; 828 bus_size_t sizepg; 829 int i, mask, mhandle; 830 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 831 832 /* out of sc->memh, allocate as many pages as necessary */ 833 834 /* convert size to PCIC pages */ 835 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 836 if (sizepg > PCIC_MAX_MEM_PAGES) 837 return (1); 838 839 mask = (1 << sizepg) - 1; 840 841 addr = 0; /* XXX gcc -Wuninitialized */ 842 mhandle = 0; /* XXX gcc -Wuninitialized */ 843 844 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 845 if ((sc->subregionmask & (mask << i)) == (mask << i)) { 846 if (bus_space_subregion(sc->memt, sc->memh, 847 i * PCIC_MEM_PAGESIZE, 848 sizepg * PCIC_MEM_PAGESIZE, &memh)) 849 return (1); 850 mhandle = mask << i; 851 addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 852 sc->subregionmask &= ~(mhandle); 853 pcmhp->memt = sc->memt; 854 pcmhp->memh = memh; 855 pcmhp->addr = addr; 856 pcmhp->size = size; 857 pcmhp->mhandle = mhandle; 858 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 859 return (0); 860 } 861 } 862 863 return (1); 864 } 865 866 void 867 pcic_chip_mem_free(pch, pcmhp) 868 pcmcia_chipset_handle_t pch; 869 struct pcmcia_mem_handle *pcmhp; 870 { 871 struct pcic_handle *h = (struct pcic_handle *) pch; 872 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 873 874 sc->subregionmask |= pcmhp->mhandle; 875 } 876 877 static const struct mem_map_index_st { 878 int sysmem_start_lsb; 879 int sysmem_start_msb; 880 int sysmem_stop_lsb; 881 int sysmem_stop_msb; 882 int cardmem_lsb; 883 int cardmem_msb; 884 int memenable; 885 } mem_map_index[] = { 886 { 887 PCIC_SYSMEM_ADDR0_START_LSB, 888 PCIC_SYSMEM_ADDR0_START_MSB, 889 PCIC_SYSMEM_ADDR0_STOP_LSB, 890 PCIC_SYSMEM_ADDR0_STOP_MSB, 891 PCIC_CARDMEM_ADDR0_LSB, 892 PCIC_CARDMEM_ADDR0_MSB, 893 PCIC_ADDRWIN_ENABLE_MEM0, 894 }, 895 { 896 PCIC_SYSMEM_ADDR1_START_LSB, 897 PCIC_SYSMEM_ADDR1_START_MSB, 898 PCIC_SYSMEM_ADDR1_STOP_LSB, 899 PCIC_SYSMEM_ADDR1_STOP_MSB, 900 PCIC_CARDMEM_ADDR1_LSB, 901 PCIC_CARDMEM_ADDR1_MSB, 902 PCIC_ADDRWIN_ENABLE_MEM1, 903 }, 904 { 905 PCIC_SYSMEM_ADDR2_START_LSB, 906 PCIC_SYSMEM_ADDR2_START_MSB, 907 PCIC_SYSMEM_ADDR2_STOP_LSB, 908 PCIC_SYSMEM_ADDR2_STOP_MSB, 909 PCIC_CARDMEM_ADDR2_LSB, 910 PCIC_CARDMEM_ADDR2_MSB, 911 PCIC_ADDRWIN_ENABLE_MEM2, 912 }, 913 { 914 PCIC_SYSMEM_ADDR3_START_LSB, 915 PCIC_SYSMEM_ADDR3_START_MSB, 916 PCIC_SYSMEM_ADDR3_STOP_LSB, 917 PCIC_SYSMEM_ADDR3_STOP_MSB, 918 PCIC_CARDMEM_ADDR3_LSB, 919 PCIC_CARDMEM_ADDR3_MSB, 920 PCIC_ADDRWIN_ENABLE_MEM3, 921 }, 922 { 923 PCIC_SYSMEM_ADDR4_START_LSB, 924 PCIC_SYSMEM_ADDR4_START_MSB, 925 PCIC_SYSMEM_ADDR4_STOP_LSB, 926 PCIC_SYSMEM_ADDR4_STOP_MSB, 927 PCIC_CARDMEM_ADDR4_LSB, 928 PCIC_CARDMEM_ADDR4_MSB, 929 PCIC_ADDRWIN_ENABLE_MEM4, 930 }, 931 }; 932 933 void 934 pcic_chip_do_mem_map(h, win) 935 struct pcic_handle *h; 936 int win; 937 { 938 int reg; 939 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 940 int mem8 = 941 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 942 || (kind == PCMCIA_MEM_ATTR); 943 944 DPRINTF(("mem8 %d\n", mem8)); 945 /* mem8 = 1; */ 946 947 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 948 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 949 pcic_write(h, mem_map_index[win].sysmem_start_msb, 950 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 951 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 952 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 953 954 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 955 ((h->mem[win].addr + h->mem[win].size) >> 956 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 957 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 958 (((h->mem[win].addr + h->mem[win].size) >> 959 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 960 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 961 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 962 963 pcic_write(h, mem_map_index[win].cardmem_lsb, 964 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 965 pcic_write(h, mem_map_index[win].cardmem_msb, 966 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 967 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 968 ((kind == PCMCIA_MEM_ATTR) ? 969 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 970 971 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 972 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 973 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 974 975 delay(100); 976 977 #ifdef PCICDEBUG 978 { 979 int r1, r2, r3, r4, r5, r6; 980 981 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 982 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 983 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 984 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 985 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 986 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 987 988 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 989 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 990 } 991 #endif 992 } 993 994 int 995 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 996 pcmcia_chipset_handle_t pch; 997 int kind; 998 bus_addr_t card_addr; 999 bus_size_t size; 1000 struct pcmcia_mem_handle *pcmhp; 1001 bus_size_t *offsetp; 1002 int *windowp; 1003 { 1004 struct pcic_handle *h = (struct pcic_handle *) pch; 1005 bus_addr_t busaddr; 1006 long card_offset; 1007 int i, win; 1008 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1009 1010 win = -1; 1011 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1012 i++) { 1013 if ((h->memalloc & (1 << i)) == 0) { 1014 win = i; 1015 h->memalloc |= (1 << i); 1016 break; 1017 } 1018 } 1019 1020 if (win == -1) 1021 return (1); 1022 1023 *windowp = win; 1024 1025 /* XXX this is pretty gross */ 1026 1027 if (sc->memt != pcmhp->memt) 1028 panic("pcic_chip_mem_map memt is bogus"); 1029 1030 busaddr = pcmhp->addr; 1031 1032 /* 1033 * compute the address offset to the pcmcia address space for the 1034 * pcic. this is intentionally signed. The masks and shifts below 1035 * will cause TRT to happen in the pcic registers. Deal with making 1036 * sure the address is aligned, and return the alignment offset. 1037 */ 1038 1039 *offsetp = card_addr % PCIC_MEM_ALIGN; 1040 card_addr -= *offsetp; 1041 1042 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1043 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1044 (u_long) card_addr)); 1045 1046 /* 1047 * include the offset in the size, and decrement size by one, since 1048 * the hw wants start/stop 1049 */ 1050 size += *offsetp - 1; 1051 1052 card_offset = (((long) card_addr) - ((long) busaddr)); 1053 1054 h->mem[win].addr = busaddr; 1055 h->mem[win].size = size; 1056 h->mem[win].offset = card_offset; 1057 h->mem[win].kind = kind; 1058 1059 pcic_chip_do_mem_map(h, win); 1060 1061 return (0); 1062 } 1063 1064 void 1065 pcic_chip_mem_unmap(pch, window) 1066 pcmcia_chipset_handle_t pch; 1067 int window; 1068 { 1069 struct pcic_handle *h = (struct pcic_handle *) pch; 1070 int reg; 1071 1072 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1073 panic("pcic_chip_mem_unmap: window out of range"); 1074 1075 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1076 reg &= ~mem_map_index[window].memenable; 1077 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1078 1079 h->memalloc &= ~(1 << window); 1080 } 1081 1082 int 1083 pcic_chip_io_alloc(pch, start, size, align, pcihp) 1084 pcmcia_chipset_handle_t pch; 1085 bus_addr_t start; 1086 bus_size_t size; 1087 bus_size_t align; 1088 struct pcmcia_io_handle *pcihp; 1089 { 1090 struct pcic_handle *h = (struct pcic_handle *) pch; 1091 bus_space_tag_t iot; 1092 bus_space_handle_t ioh; 1093 bus_addr_t ioaddr; 1094 int flags = 0; 1095 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1096 1097 /* 1098 * Allocate some arbitrary I/O space. 1099 */ 1100 1101 iot = sc->iot; 1102 1103 if (start) { 1104 ioaddr = start; 1105 if (bus_space_map(iot, start, size, 0, &ioh)) 1106 return (1); 1107 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1108 (u_long) ioaddr, (u_long) size)); 1109 } else { 1110 flags |= PCMCIA_IO_ALLOCATED; 1111 if (bus_space_alloc(iot, sc->iobase, 1112 sc->iobase + sc->iosize, size, align, 0, 0, 1113 &ioaddr, &ioh)) 1114 return (1); 1115 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1116 (u_long) ioaddr, (u_long) size)); 1117 } 1118 1119 pcihp->iot = iot; 1120 pcihp->ioh = ioh; 1121 pcihp->addr = ioaddr; 1122 pcihp->size = size; 1123 pcihp->flags = flags; 1124 1125 return (0); 1126 } 1127 1128 void 1129 pcic_chip_io_free(pch, pcihp) 1130 pcmcia_chipset_handle_t pch; 1131 struct pcmcia_io_handle *pcihp; 1132 { 1133 bus_space_tag_t iot = pcihp->iot; 1134 bus_space_handle_t ioh = pcihp->ioh; 1135 bus_size_t size = pcihp->size; 1136 1137 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1138 bus_space_free(iot, ioh, size); 1139 else 1140 bus_space_unmap(iot, ioh, size); 1141 } 1142 1143 1144 static const struct io_map_index_st { 1145 int start_lsb; 1146 int start_msb; 1147 int stop_lsb; 1148 int stop_msb; 1149 int ioenable; 1150 int ioctlmask; 1151 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1152 } io_map_index[] = { 1153 { 1154 PCIC_IOADDR0_START_LSB, 1155 PCIC_IOADDR0_START_MSB, 1156 PCIC_IOADDR0_STOP_LSB, 1157 PCIC_IOADDR0_STOP_MSB, 1158 PCIC_ADDRWIN_ENABLE_IO0, 1159 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1160 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1161 { 1162 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1163 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1164 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1165 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1166 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1167 }, 1168 }, 1169 { 1170 PCIC_IOADDR1_START_LSB, 1171 PCIC_IOADDR1_START_MSB, 1172 PCIC_IOADDR1_STOP_LSB, 1173 PCIC_IOADDR1_STOP_MSB, 1174 PCIC_ADDRWIN_ENABLE_IO1, 1175 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1176 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1177 { 1178 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1179 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1180 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1181 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1182 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1183 }, 1184 }, 1185 }; 1186 1187 void 1188 pcic_chip_do_io_map(h, win) 1189 struct pcic_handle *h; 1190 int win; 1191 { 1192 int reg; 1193 1194 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1195 win, (long) h->io[win].addr, (long) h->io[win].size, 1196 h->io[win].width * 8)); 1197 1198 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1199 pcic_write(h, io_map_index[win].start_msb, 1200 (h->io[win].addr >> 8) & 0xff); 1201 1202 pcic_write(h, io_map_index[win].stop_lsb, 1203 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1204 pcic_write(h, io_map_index[win].stop_msb, 1205 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1206 1207 reg = pcic_read(h, PCIC_IOCTL); 1208 reg &= ~io_map_index[win].ioctlmask; 1209 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1210 pcic_write(h, PCIC_IOCTL, reg); 1211 1212 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1213 reg |= io_map_index[win].ioenable; 1214 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1215 } 1216 1217 int 1218 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1219 pcmcia_chipset_handle_t pch; 1220 int width; 1221 bus_addr_t offset; 1222 bus_size_t size; 1223 struct pcmcia_io_handle *pcihp; 1224 int *windowp; 1225 { 1226 struct pcic_handle *h = (struct pcic_handle *) pch; 1227 bus_addr_t ioaddr = pcihp->addr + offset; 1228 int i, win; 1229 #ifdef PCICDEBUG 1230 static const char *width_names[] = { "auto", "io8", "io16" }; 1231 #endif 1232 struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1233 1234 /* XXX Sanity check offset/size. */ 1235 1236 win = -1; 1237 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1238 if ((h->ioalloc & (1 << i)) == 0) { 1239 win = i; 1240 h->ioalloc |= (1 << i); 1241 break; 1242 } 1243 } 1244 1245 if (win == -1) 1246 return (1); 1247 1248 *windowp = win; 1249 1250 /* XXX this is pretty gross */ 1251 1252 if (sc->iot != pcihp->iot) 1253 panic("pcic_chip_io_map iot is bogus"); 1254 1255 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1256 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1257 1258 /* XXX wtf is this doing here? */ 1259 1260 printf("%s: port 0x%lx", sc->dev.dv_xname, (u_long) ioaddr); 1261 if (size > 1) 1262 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1263 printf("\n"); 1264 1265 h->io[win].addr = ioaddr; 1266 h->io[win].size = size; 1267 h->io[win].width = width; 1268 1269 pcic_chip_do_io_map(h, win); 1270 1271 return (0); 1272 } 1273 1274 void 1275 pcic_chip_io_unmap(pch, window) 1276 pcmcia_chipset_handle_t pch; 1277 int window; 1278 { 1279 struct pcic_handle *h = (struct pcic_handle *) pch; 1280 int reg; 1281 1282 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1283 panic("pcic_chip_io_unmap: window out of range"); 1284 1285 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1286 reg &= ~io_map_index[window].ioenable; 1287 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1288 1289 h->ioalloc &= ~(1 << window); 1290 } 1291 1292 static int 1293 pcic_wait_ready(h) 1294 struct pcic_handle *h; 1295 { 1296 u_int8_t stat; 1297 int i; 1298 1299 /* wait an initial 10ms for quick cards */ 1300 stat = pcic_read(h, PCIC_IF_STATUS); 1301 if (stat & PCIC_IF_STATUS_READY) 1302 return (0); 1303 pcic_delay(h, 10, "pccwr0"); 1304 for (i = 0; i < 50; i++) { 1305 stat = pcic_read(h, PCIC_IF_STATUS); 1306 if (stat & PCIC_IF_STATUS_READY) 1307 return (0); 1308 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 1309 PCIC_IF_STATUS_CARDDETECT_PRESENT) 1310 return (ENXIO); 1311 /* wait .1s (100ms) each iteration now */ 1312 pcic_delay(h, 100, "pccwr1"); 1313 } 1314 1315 printf("pcic_wait_ready: ready never happened, status=%02x\n", stat); 1316 return (EWOULDBLOCK); 1317 } 1318 1319 /* 1320 * Perform long (msec order) delay. 1321 */ 1322 static void 1323 pcic_delay(h, timo, wmesg) 1324 struct pcic_handle *h; 1325 int timo; /* in ms. must not be zero */ 1326 const char *wmesg; 1327 { 1328 1329 #ifdef DIAGNOSTIC 1330 if (timo <= 0) 1331 panic("pcic_delay: called with timeout %d", timo); 1332 if (!curlwp) 1333 panic("pcic_delay: called in interrupt context"); 1334 if (!h->event_thread) 1335 panic("pcic_delay: no event thread"); 1336 #endif 1337 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1338 wmesg, h->event_thread, timo)); 1339 tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1340 } 1341 1342 void 1343 pcic_chip_socket_enable(pch) 1344 pcmcia_chipset_handle_t pch; 1345 { 1346 struct pcic_handle *h = (struct pcic_handle *) pch; 1347 int win; 1348 u_int8_t power, intr; 1349 #ifdef DIAGNOSTIC 1350 int reg; 1351 #endif 1352 1353 #ifdef DIAGNOSTIC 1354 if (h->flags & PCIC_FLAG_ENABLED) 1355 printf("pcic_chip_socket_enable: enabling twice\n"); 1356 #endif 1357 1358 /* disable interrupts; assert RESET */ 1359 intr = pcic_read(h, PCIC_INTR); 1360 intr &= PCIC_INTR_ENABLE; 1361 pcic_write(h, PCIC_INTR, intr); 1362 1363 /* zero out the address windows */ 1364 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1365 1366 /* power off; assert output enable bit */ 1367 power = PCIC_PWRCTL_OE; 1368 pcic_write(h, PCIC_PWRCTL, power); 1369 1370 /* 1371 * power hack for RICOH RF5C[23]96 1372 */ 1373 switch( h->vendor ) { 1374 case PCIC_VENDOR_RICOH_5C296: 1375 case PCIC_VENDOR_RICOH_5C396: 1376 { 1377 int regtmp; 1378 regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1379 #ifdef RICOH_POWER_HACK 1380 regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT; 1381 #else 1382 regtmp &= ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V); 1383 #endif 1384 pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1385 } 1386 break; 1387 default: 1388 break; 1389 } 1390 1391 #ifdef VADEM_POWER_HACK 1392 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1393 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1394 printf("prcr = %02x\n", pcic_read(h, 0x02)); 1395 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1396 printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1397 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1398 printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1399 #endif 1400 1401 /* power up the socket */ 1402 power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1403 pcic_write(h, PCIC_PWRCTL, power); 1404 1405 /* 1406 * Table 4-18 and figure 4-6 of the PC Card specifiction say: 1407 * Vcc Rising Time (Tpr) = 100ms 1408 * RESET Width (Th (Hi-z RESET)) = 1ms 1409 * RESET Width (Tw (RESET)) = 10us 1410 * 1411 * some machines require some more time to be settled 1412 * (100ms is added here). 1413 */ 1414 pcic_delay(h, 200 + 1, "pccen1"); 1415 1416 /* negate RESET */ 1417 intr |= PCIC_INTR_RESET; 1418 pcic_write(h, PCIC_INTR, intr); 1419 1420 /* 1421 * RESET Setup Time (Tsu (RESET)) = 20ms 1422 */ 1423 pcic_delay(h, 20, "pccen2"); 1424 1425 #ifdef DIAGNOSTIC 1426 reg = pcic_read(h, PCIC_IF_STATUS); 1427 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 1428 printf("pcic_chip_socket_enable: no power, status=%x\n", reg); 1429 #endif 1430 1431 /* wait for the chip to finish initializing */ 1432 if (pcic_wait_ready(h)) { 1433 /* XXX return a failure status?? */ 1434 pcic_write(h, PCIC_PWRCTL, 0); 1435 return; 1436 } 1437 1438 /* reinstall all the memory and io mappings */ 1439 for (win = 0; win < PCIC_MEM_WINS; win++) 1440 if (h->memalloc & (1 << win)) 1441 pcic_chip_do_mem_map(h, win); 1442 for (win = 0; win < PCIC_IO_WINS; win++) 1443 if (h->ioalloc & (1 << win)) 1444 pcic_chip_do_io_map(h, win); 1445 1446 h->flags |= PCIC_FLAG_ENABLED; 1447 } 1448 1449 void 1450 pcic_chip_socket_disable(pch) 1451 pcmcia_chipset_handle_t pch; 1452 { 1453 struct pcic_handle *h = (struct pcic_handle *) pch; 1454 u_int8_t intr; 1455 1456 DPRINTF(("pcic_chip_socket_disable\n")); 1457 1458 /* disable interrupts; assert RESET */ 1459 intr = pcic_read(h, PCIC_INTR); 1460 intr &= PCIC_INTR_ENABLE; 1461 pcic_write(h, PCIC_INTR, intr); 1462 1463 /* zero out the address windows */ 1464 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1465 1466 /* disable socket: negate output enable bit and power off */ 1467 pcic_write(h, PCIC_PWRCTL, 0); 1468 1469 /* 1470 * Vcc Falling Time (Tpf) = 300ms 1471 */ 1472 pcic_delay(h, 300, "pccwr1"); 1473 1474 h->flags &= ~PCIC_FLAG_ENABLED; 1475 } 1476 1477 void 1478 pcic_chip_socket_settype(pch, type) 1479 pcmcia_chipset_handle_t pch; 1480 int type; 1481 { 1482 struct pcic_handle *h = (struct pcic_handle *) pch; 1483 int intr; 1484 1485 intr = pcic_read(h, PCIC_INTR); 1486 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 1487 if (type == PCMCIA_IFTYPE_IO) { 1488 intr |= PCIC_INTR_CARDTYPE_IO; 1489 intr |= h->ih_irq << PCIC_INTR_IRQ_SHIFT; 1490 } else 1491 intr |= PCIC_INTR_CARDTYPE_MEM; 1492 pcic_write(h, PCIC_INTR, intr); 1493 1494 DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n", 1495 h->ph_parent->dv_xname, h->sock, 1496 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 1497 } 1498 1499 static u_int8_t 1500 st_pcic_read(h, idx) 1501 struct pcic_handle *h; 1502 int idx; 1503 { 1504 1505 if (idx != -1) 1506 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1507 h->sock + idx); 1508 return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1509 } 1510 1511 static void 1512 st_pcic_write(h, idx, data) 1513 struct pcic_handle *h; 1514 int idx; 1515 u_int8_t data; 1516 { 1517 1518 if (idx != -1) 1519 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1520 h->sock + idx); 1521 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1522 } 1523
Indexes created Mon Sep 29 21:09:56 GMT 2025