i82365reg.h revision 1.6
1 /* $NetBSD: i82365reg.h,v 1.6 2000/02/28 07:33:08 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Marc Horowitz. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * All information is from the intel 82365sl PC Card Interface Controller 34 * (PCIC) data sheet, marked "preliminary". Order number 290423-002, January 35 * 1993. 36 */ 37 38 #define PCIC_IOSIZE 2 39 40 #define PCIC_REG_INDEX 0 41 #define PCIC_REG_DATA 1 42 43 /* 44 * The PCIC allows two chips to share the same address. In order not to run 45 * afoul of the netbsd device model, this driver will treat those chips as 46 * the same device. 47 */ 48 49 /* pcic can have 2 controllers offset by 0x80 and 2 sockets offset by 0x40 */ 50 #define PCIC_CHIP_OFFSET 0x80 51 #define PCIC_SOCKET_OFFSET 0x40 52 53 /* general setup registers */ 54 55 #define PCIC_IDENT 0x00 /* RO */ 56 #define PCIC_IDENT_IFTYPE_MASK 0xC0 57 #define PCIC_IDENT_IFTYPE_IO_ONLY 0x00 58 #define PCIC_IDENT_IFTYPE_MEM_ONLY 0x40 59 #define PCIC_IDENT_IFTYPE_MEM_AND_IO 0x80 60 #define PCIC_IDENT_IFTYPE_RESERVED 0xC0 61 #define PCIC_IDENT_ZERO 0x30 62 #define PCIC_IDENT_REV_MASK 0x0F 63 #define PCIC_IDENT_REV_I82365SLR0 0x02 64 #define PCIC_IDENT_REV_I82365SLR1 0x03 65 66 #define PCIC_IF_STATUS 0x01 /* RO */ 67 #define PCIC_IF_STATUS_GPI 0x80 /* General Purpose Input */ 68 #define PCIC_IF_STATUS_POWERACTIVE 0x40 69 #define PCIC_IF_STATUS_READY 0x20 /* really READY/!BUSY */ 70 #define PCIC_IF_STATUS_MEM_WP 0x10 71 #define PCIC_IF_STATUS_CARDDETECT_MASK 0x0C 72 #define PCIC_IF_STATUS_CARDDETECT_PRESENT 0x0C 73 #define PCIC_IF_STATUS_BATTERY_MASK 0x03 74 #define PCIC_IF_STATUS_BATTERY_DEAD1 0x00 75 #define PCIC_IF_STATUS_BATTERY_DEAD2 0x01 76 #define PCIC_IF_STATUS_BATTERY_WARNING 0x02 77 #define PCIC_IF_STATUS_BATTERY_GOOD 0x03 78 79 #define PCIC_PWRCTL 0x02 /* RW */ 80 #define PCIC_PWRCTL_OE 0x80 /* output enable */ 81 #define PCIC_PWRCTL_DISABLE_RESETDRV 0x40 82 #define PCIC_PWRCTL_AUTOSWITCH_ENABLE 0x20 83 #define PCIC_PWRCTL_PWR_ENABLE 0x10 84 #define PCIC_PWRCTL_VPP2_MASK 0x0C 85 #define PCIC_PWRCTL_VPP2_RESERVED 0x0C 86 #define PCIC_PWRCTL_VPP2_12V 0x08 87 #define PCIC_PWRCTL_VPP2_VCC 0x04 88 #define PCIC_PWRCTL_VPP2_OFF 0x00 89 #define PCIC_PWRCTL_VPP1_MASK 0x03 90 #define PCIC_PWRCTL_VPP1_RESERVED 0x03 91 #define PCIC_PWRCTL_VPP1_12V 0x02 92 #define PCIC_PWRCTL_VPP1_VCC 0x01 93 #define PCIC_PWRCTL_VPP1_OFF 0x00 94 95 #define PCIC_CSC 0x04 /* RW */ 96 #define PCIC_CSC_ZERO 0xE0 97 #define PCIC_CSC_GPI 0x10 98 #define PCIC_CSC_CD 0x08 /* Card Detect Change */ 99 #define PCIC_CSC_READY 0x04 100 #define PCIC_CSC_BATTWARN 0x02 101 #define PCIC_CSC_BATTDEAD 0x01 /* for memory cards */ 102 #define PCIC_CSC_RI 0x01 /* for i/o cards */ 103 104 #define PCIC_ADDRWIN_ENABLE 0x06 /* RW */ 105 #define PCIC_ADDRWIN_ENABLE_IO1 0x80 106 #define PCIC_ADDRWIN_ENABLE_IO0 0x40 107 #define PCIC_ADDRWIN_ENABLE_MEMCS16 0x20 /* rtfds if you care */ 108 #define PCIC_ADDRWIN_ENABLE_MEM4 0x10 109 #define PCIC_ADDRWIN_ENABLE_MEM3 0x08 110 #define PCIC_ADDRWIN_ENABLE_MEM2 0x04 111 #define PCIC_ADDRWIN_ENABLE_MEM1 0x02 112 #define PCIC_ADDRWIN_ENABLE_MEM0 0x01 113 114 /* this is _not_ available on cirrus chips */ 115 #define PCIC_CARD_DETECT 0x16 /* RW */ 116 #define PCIC_CARD_DETECT_RESERVED 0xC0 117 #define PCIC_CARD_DETECT_SW_INTR 0x20 118 #define PCIC_CARD_DETECT_RESUME_ENABLE 0x10 119 #define PCIC_CARD_DETECT_GPI_TRANSCTL 0x08 120 #define PCIC_CARD_DETECT_GPI_ENABLE 0x04 121 #define PCIC_CARD_DETECT_CFGRST_ENABLE 0x02 122 #define PCIC_CARD_DETECT_MEMDLY_INHIBIT 0x01 123 124 /* interrupt registers */ 125 126 #define PCIC_INTR 0x03 /* RW */ 127 #define PCIC_INTR_RI_ENABLE 0x80 128 #define PCIC_INTR_RESET 0x40 /* active low (zero) */ 129 #define PCIC_INTR_CARDTYPE_MASK 0x20 130 #define PCIC_INTR_CARDTYPE_IO 0x20 131 #define PCIC_INTR_CARDTYPE_MEM 0x00 132 #define PCIC_INTR_ENABLE 0x10 133 #define PCIC_INTR_IRQ_MASK 0x0F 134 #define PCIC_INTR_IRQ_SHIFT 0 135 #define PCIC_INTR_IRQ_NONE 0x00 136 #define PCIC_INTR_IRQ_RESERVED1 0x01 137 #define PCIC_INTR_IRQ_RESERVED2 0x02 138 #define PCIC_INTR_IRQ3 0x03 139 #define PCIC_INTR_IRQ4 0x04 140 #define PCIC_INTR_IRQ5 0x05 141 #define PCIC_INTR_IRQ_RESERVED6 0x06 142 #define PCIC_INTR_IRQ7 0x07 143 #define PCIC_INTR_IRQ_RESERVED8 0x08 144 #define PCIC_INTR_IRQ9 0x09 145 #define PCIC_INTR_IRQ10 0x0A 146 #define PCIC_INTR_IRQ11 0x0B 147 #define PCIC_INTR_IRQ12 0x0C 148 #define PCIC_INTR_IRQ_RESERVED13 0x0D 149 #define PCIC_INTR_IRQ14 0x0E 150 #define PCIC_INTR_IRQ15 0x0F 151 152 #define PCIC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */ 153 154 #define PCIC_CSC_INTR 0x05 /* RW */ 155 #define PCIC_CSC_INTR_IRQ_MASK 0xF0 156 #define PCIC_CSC_INTR_IRQ_SHIFT 4 157 #define PCIC_CSC_INTR_IRQ_NONE 0x00 158 #define PCIC_CSC_INTR_IRQ_RESERVED1 0x10 159 #define PCIC_CSC_INTR_IRQ_RESERVED2 0x20 160 #define PCIC_CSC_INTR_IRQ3 0x30 161 #define PCIC_CSC_INTR_IRQ4 0x40 162 #define PCIC_CSC_INTR_IRQ5 0x50 163 #define PCIC_CSC_INTR_IRQ_RESERVED6 0x60 164 #define PCIC_CSC_INTR_IRQ7 0x70 165 #define PCIC_CSC_INTR_IRQ_RESERVED8 0x80 166 #define PCIC_CSC_INTR_IRQ9 0x90 167 #define PCIC_CSC_INTR_IRQ10 0xA0 168 #define PCIC_CSC_INTR_IRQ11 0xB0 169 #define PCIC_CSC_INTR_IRQ12 0xC0 170 #define PCIC_CSC_INTR_IRQ_RESERVED13 0xD0 171 #define PCIC_CSC_INTR_IRQ14 0xE0 172 #define PCIC_CSC_INTR_IRQ15 0xF0 173 #define PCIC_CSC_INTR_CD_ENABLE 0x08 174 #define PCIC_CSC_INTR_READY_ENABLE 0x04 175 #define PCIC_CSC_INTR_BATTWARN_ENABLE 0x02 176 #define PCIC_CSC_INTR_BATTDEAD_ENABLE 0x01 /* for memory cards */ 177 #define PCIC_CSC_INTR_RI_ENABLE 0x01 /* for I/O cards */ 178 179 #define PCIC_CSC_INTR_FORMAT "\177\020" "f\4\4CSC_INTR_IRQ\0" \ 180 "b\0RI\0" \ 181 "b\1BATTWARN\0" \ 182 "b\2READY\0" \ 183 "b\3CD\0" 184 185 #define PCIC_CSC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */ 186 187 /* I/O registers */ 188 189 #define PCIC_IO_WINS 2 190 191 #define PCIC_IOCTL 0x07 /* RW */ 192 #define PCIC_IOCTL_IO1_WAITSTATE 0x80 193 #define PCIC_IOCTL_IO1_ZEROWAIT 0x40 194 #define PCIC_IOCTL_IO1_IOCS16SRC_MASK 0x20 195 #define PCIC_IOCTL_IO1_IOCS16SRC_CARD 0x20 196 #define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE 0x00 197 #define PCIC_IOCTL_IO1_DATASIZE_MASK 0x10 198 #define PCIC_IOCTL_IO1_DATASIZE_16BIT 0x10 199 #define PCIC_IOCTL_IO1_DATASIZE_8BIT 0x00 200 #define PCIC_IOCTL_IO0_WAITSTATE 0x08 201 #define PCIC_IOCTL_IO0_ZEROWAIT 0x04 202 #define PCIC_IOCTL_IO0_IOCS16SRC_MASK 0x02 203 #define PCIC_IOCTL_IO0_IOCS16SRC_CARD 0x02 204 #define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 0x00 205 #define PCIC_IOCTL_IO0_DATASIZE_MASK 0x01 206 #define PCIC_IOCTL_IO0_DATASIZE_16BIT 0x01 207 #define PCIC_IOCTL_IO0_DATASIZE_8BIT 0x00 208 209 #define PCIC_IOADDR0_START_LSB 0x08 210 #define PCIC_IOADDR0_START_MSB 0x09 211 #define PCIC_IOADDR0_STOP_LSB 0x0A 212 #define PCIC_IOADDR0_STOP_MSB 0x0B 213 #define PCIC_IOADDR1_START_LSB 0x0C 214 #define PCIC_IOADDR1_START_MSB 0x0D 215 #define PCIC_IOADDR1_STOP_LSB 0x0E 216 #define PCIC_IOADDR1_STOP_MSB 0x0F 217 218 /* memory registers */ 219 220 /* 221 * memory window addresses refer to bits A23-A12 of the ISA system memory 222 * address. This is a shift of 12 bits. The LSB contains A19-A12, and the 223 * MSB contains A23-A20, plus some other bits. 224 */ 225 226 #define PCIC_MEM_WINS 5 227 228 #define PCIC_MEM_SHIFT 12 229 #define PCIC_MEM_PAGESIZE (1<<PCIC_MEM_SHIFT) 230 231 #define PCIC_SYSMEM_ADDRX_SHIFT PCIC_MEM_SHIFT 232 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK 0x80 233 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80 234 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00 235 #define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40 236 #define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30 237 #define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F 238 239 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0 240 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00 241 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40 242 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80 243 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0 244 #define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F 245 246 /* 247 * The card side of a memory mapping consists of bits A19-A12 of the card 248 * memory address in the LSB, and A25-A20 plus some other bits in the MSB. 249 * Again, the shift is 12 bits. 250 */ 251 252 #define PCIC_CARDMEM_ADDRX_SHIFT PCIC_MEM_SHIFT 253 #define PCIC_CARDMEM_ADDRX_MSB_WP 0x80 254 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK 0x40 255 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR 0x40 256 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00 257 #define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F 258 259 #define PCIC_SYSMEM_ADDR0_START_LSB 0x10 260 #define PCIC_SYSMEM_ADDR0_START_MSB 0x11 261 #define PCIC_SYSMEM_ADDR0_STOP_LSB 0x12 262 #define PCIC_SYSMEM_ADDR0_STOP_MSB 0x13 263 264 #define PCIC_CARDMEM_ADDR0_LSB 0x14 265 #define PCIC_CARDMEM_ADDR0_MSB 0x15 266 267 /* #define PCIC_RESERVED 0x17 */ 268 269 #define PCIC_SYSMEM_ADDR1_START_LSB 0x18 270 #define PCIC_SYSMEM_ADDR1_START_MSB 0x19 271 #define PCIC_SYSMEM_ADDR1_STOP_LSB 0x1A 272 #define PCIC_SYSMEM_ADDR1_STOP_MSB 0x1B 273 274 #define PCIC_CARDMEM_ADDR1_LSB 0x1C 275 #define PCIC_CARDMEM_ADDR1_MSB 0x1D 276 277 #define PCIC_SYSMEM_ADDR2_START_LSB 0x20 278 #define PCIC_SYSMEM_ADDR2_START_MSB 0x21 279 #define PCIC_SYSMEM_ADDR2_STOP_LSB 0x22 280 #define PCIC_SYSMEM_ADDR2_STOP_MSB 0x23 281 282 #define PCIC_CARDMEM_ADDR2_LSB 0x24 283 #define PCIC_CARDMEM_ADDR2_MSB 0x25 284 285 /* #define PCIC_RESERVED 0x26 */ 286 /* #define PCIC_RESERVED 0x27 */ 287 288 #define PCIC_SYSMEM_ADDR3_START_LSB 0x28 289 #define PCIC_SYSMEM_ADDR3_START_MSB 0x29 290 #define PCIC_SYSMEM_ADDR3_STOP_LSB 0x2A 291 #define PCIC_SYSMEM_ADDR3_STOP_MSB 0x2B 292 293 #define PCIC_CARDMEM_ADDR3_LSB 0x2C 294 #define PCIC_CARDMEM_ADDR3_MSB 0x2D 295 296 /* #define PCIC_RESERVED 0x2E */ 297 /* #define PCIC_RESERVED 0x2F */ 298 299 #define PCIC_SYSMEM_ADDR4_START_LSB 0x30 300 #define PCIC_SYSMEM_ADDR4_START_MSB 0x31 301 #define PCIC_SYSMEM_ADDR4_STOP_LSB 0x32 302 #define PCIC_SYSMEM_ADDR4_STOP_MSB 0x33 303 304 #define PCIC_CARDMEM_ADDR4_LSB 0x34 305 #define PCIC_CARDMEM_ADDR4_MSB 0x35 306 307 /* #define PCIC_RESERVED 0x36 */ 308 /* #define PCIC_RESERVED 0x37 */ 309 /* #define PCIC_RESERVED 0x38 */ 310 /* #define PCIC_RESERVED 0x39 */ 311 /* #define PCIC_RESERVED 0x3A */ 312 /* #define PCIC_RESERVED 0x3B */ 313 /* #define PCIC_RESERVED 0x3C */ 314 /* #define PCIC_RESERVED 0x3D */ 315 /* #define PCIC_RESERVED 0x3E */ 316 /* #define PCIC_RESERVED 0x3F */ 317 318 /* vendor-specific registers */ 319 320 #define PCIC_INTEL_GLOBAL_CTL 0x1E /* RW */ 321 #define PCIC_INTEL_GLOBAL_CTL_RESERVED 0xF0 322 #define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08 323 #define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK 0x04 324 #define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02 325 #define PCIC_INTEL_GLOBAL_CTL_POWERDOWN 0x01 326 327 #define PCIC_CIRRUS_MISC_CTL_2 0x1E 328 #define PCIC_CIRRUS_MISC_CTL_2_SUSPEND 0x04 329 330 #define PCIC_CIRRUS_CHIP_INFO 0x1F 331 #define PCIC_CIRRUS_CHIP_INFO_CHIP_ID 0xC0 332 #define PCIC_CIRRUS_CHIP_INFO_SLOTS 0x20 333 #define PCIC_CIRRUS_CHIP_INFO_REV 0x1F 334 335 #define PCIC_CIRRUS_EXTENDED_INDEX 0x2E 336 #define PCIC_CIRRUS_EXTENDED_DATA 0x2F 337 #define PCIC_CIRRUS_EXT_CONTROL_1 0x03 338 #define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18 339
Indexes created Tue Sep 30 11:09:46 GMT 2025