i82365var.h revision 1.14
1 /* $NetBSD: i82365var.h,v 1.14 2000/02/26 17:24:44 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Marc Horowitz. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/device.h> 33 #include <sys/lock.h> 34 35 #include <dev/pcmcia/pcmciareg.h> 36 #include <dev/pcmcia/pcmciachip.h> 37 38 #include <dev/ic/i82365reg.h> 39 40 struct proc; 41 42 struct pcic_event { 43 SIMPLEQ_ENTRY(pcic_event) pe_q; 44 int pe_type; 45 }; 46 47 /* pe_type */ 48 #define PCIC_EVENT_INSERTION 0 49 #define PCIC_EVENT_REMOVAL 1 50 51 struct pcic_handle { 52 struct device *ph_parent; 53 bus_space_tag_t ph_bus_t; /* I/O or MEM? I don't mind */ 54 bus_space_handle_t ph_bus_h; 55 u_int8_t (*ph_read) __P((struct pcic_handle *, int)); 56 void (*ph_write) __P((struct pcic_handle *, int, u_int8_t)); 57 58 int vendor; /* vendor of chip */ 59 int chip; /* chip index 0 or 1 */ 60 int sock; 61 int flags; 62 int laststate; 63 int memalloc; 64 struct { 65 bus_addr_t addr; 66 bus_size_t size; 67 long offset; 68 int kind; 69 } mem[PCIC_MEM_WINS]; 70 int ioalloc; 71 struct { 72 bus_addr_t addr; 73 bus_size_t size; 74 int width; 75 } io[PCIC_IO_WINS]; 76 int ih_irq; 77 struct device *pcmcia; 78 79 int shutdown; 80 struct proc *event_thread; 81 SIMPLEQ_HEAD(, pcic_event) events; 82 }; 83 84 #define PCIC_FLAG_SOCKETP 0x0001 85 #define PCIC_FLAG_CARDP 0x0002 86 #define PCIC_FLAG_ENABLED 0x0004 87 88 #define PCIC_LASTSTATE_PRESENT 0x0002 89 #define PCIC_LASTSTATE_HALF 0x0001 90 #define PCIC_LASTSTATE_EMPTY 0x0000 91 92 #define C0SA 0 93 #define C0SB PCIC_SOCKET_OFFSET 94 #define C1SA PCIC_CHIP_OFFSET 95 #define C1SB PCIC_CHIP_OFFSET + PCIC_SOCKET_OFFSET 96 97 #define PCIC_VENDOR_UNKNOWN 0 98 #define PCIC_VENDOR_I82365SLR0 1 99 #define PCIC_VENDOR_I82365SLR1 2 100 #define PCIC_VENDOR_CIRRUS_PD6710 3 101 #define PCIC_VENDOR_CIRRUS_PD672X 4 102 103 /* 104 * This is sort of arbitrary. It merely needs to be "enough". It can be 105 * overridden in the conf file, anyway. 106 */ 107 108 #define PCIC_MEM_PAGES 4 109 #define PCIC_MEMSIZE PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE 110 111 #define PCIC_NSLOTS 4 112 113 struct pcic_softc { 114 struct device dev; 115 116 bus_space_tag_t memt; 117 bus_space_handle_t memh; 118 bus_space_tag_t iot; 119 bus_space_handle_t ioh; 120 121 pcmcia_chipset_tag_t pct; 122 123 struct lock sc_pcic_lock; 124 125 /* this needs to be large enough to hold PCIC_MEM_PAGES bits */ 126 int subregionmask; 127 #define PCIC_MAX_MEM_PAGES (8 * sizeof(int)) 128 129 /* used by memory window mapping functions */ 130 bus_addr_t membase; 131 132 /* 133 * used by io window mapping functions. These can actually overlap 134 * with another pcic, since the underlying extent mapper will deal 135 * with individual allocations. This is here to deal with the fact 136 * that different busses have different real widths (different pc 137 * hardware seems to use 10 or 12 bits for the I/O bus). 138 */ 139 bus_addr_t iobase; 140 bus_addr_t iosize; 141 142 int irq; 143 void *ih; 144 145 struct pcic_handle handle[PCIC_NSLOTS]; 146 147 /* for use by underlying chip code for discovering irqs */ 148 int intr_detect, intr_false; 149 int intr_mask[PCIC_NSLOTS / 2]; /* probed intterupts if possible */ 150 }; 151 152 153 int pcic_ident_ok __P((int)); 154 int pcic_vendor __P((struct pcic_handle *)); 155 char *pcic_vendor_to_string __P((int)); 156 157 void pcic_attach __P((struct pcic_softc *)); 158 void pcic_attach_sockets __P((struct pcic_softc *)); 159 void pcic_attach_sockets_finish __P((struct pcic_softc *)); 160 int pcic_intr __P((void *arg)); 161 162 /* 163 static inline int pcic_read __P((struct pcic_handle *, int)); 164 static inline void pcic_write __P((struct pcic_handle *, int, u_int8_t)); 165 */ 166 167 int pcic_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *)); 169 void pcic_chip_mem_free __P((pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *)); 171 int pcic_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 173 void pcic_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 174 175 int pcic_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 176 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 177 void pcic_chip_io_free __P((pcmcia_chipset_handle_t, 178 struct pcmcia_io_handle *)); 179 int pcic_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 180 bus_size_t, struct pcmcia_io_handle *, int *)); 181 void pcic_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 182 183 void pcic_chip_socket_enable __P((pcmcia_chipset_handle_t)); 184 void pcic_chip_socket_disable __P((pcmcia_chipset_handle_t)); 185 186 #if 0 187 188 static __inline int pcic_read __P((struct pcic_handle *, int)); 189 static __inline int 190 pcic_read(h, idx) 191 struct pcic_handle *h; 192 int idx; 193 { 194 if (idx != -1) 195 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 196 h->sock + idx); 197 return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA)); 198 } 199 200 static __inline void pcic_write __P((struct pcic_handle *, int, int)); 201 static __inline void 202 pcic_write(h, idx, data) 203 struct pcic_handle *h; 204 int idx; 205 int data; 206 { 207 if (idx != -1) 208 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 209 h->sock + idx); 210 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data)); 211 } 212 #else 213 #define pcic_read(h, idx) \ 214 (*(h)->ph_read)((h), (idx)) 215 216 #define pcic_write(h, idx, data) \ 217 (*(h)->ph_write)((h), (idx), (data)) 218 219 #endif 220
Indexes created Mon Sep 29 21:09:56 GMT 2025