i82365var.h revision 1.16
1 /* $NetBSD: i82365var.h,v 1.16 2001/12/15 13:23:21 soren Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Marc Horowitz. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/device.h> 33 #include <sys/callout.h> 34 #include <sys/lock.h> 35 36 #include <dev/pcmcia/pcmciareg.h> 37 #include <dev/pcmcia/pcmciachip.h> 38 39 #include <dev/ic/i82365reg.h> 40 41 struct proc; 42 43 struct pcic_event { 44 SIMPLEQ_ENTRY(pcic_event) pe_q; 45 int pe_type; 46 }; 47 48 /* pe_type */ 49 #define PCIC_EVENT_INSERTION 0 50 #define PCIC_EVENT_REMOVAL 1 51 52 struct pcic_handle { 53 struct device *ph_parent; 54 bus_space_tag_t ph_bus_t; /* I/O or MEM? I don't mind */ 55 bus_space_handle_t ph_bus_h; 56 u_int8_t (*ph_read) __P((struct pcic_handle *, int)); 57 void (*ph_write) __P((struct pcic_handle *, int, u_int8_t)); 58 59 int vendor; /* vendor of chip */ 60 int chip; /* chip index 0 or 1 */ 61 int sock; 62 int flags; 63 int laststate; 64 int memalloc; 65 struct { 66 bus_addr_t addr; 67 bus_size_t size; 68 long offset; 69 int kind; 70 } mem[PCIC_MEM_WINS]; 71 int ioalloc; 72 struct { 73 bus_addr_t addr; 74 bus_size_t size; 75 int width; 76 } io[PCIC_IO_WINS]; 77 int ih_irq; 78 struct device *pcmcia; 79 80 int shutdown; 81 struct proc *event_thread; 82 SIMPLEQ_HEAD(, pcic_event) events; 83 }; 84 85 #define PCIC_FLAG_SOCKETP 0x0001 86 #define PCIC_FLAG_CARDP 0x0002 87 #define PCIC_FLAG_ENABLED 0x0004 88 89 #define PCIC_LASTSTATE_PRESENT 0x0002 90 #define PCIC_LASTSTATE_HALF 0x0001 91 #define PCIC_LASTSTATE_EMPTY 0x0000 92 93 #define C0SA 0 94 #define C0SB PCIC_SOCKET_OFFSET 95 #define C1SA PCIC_CHIP_OFFSET 96 #define C1SB PCIC_CHIP_OFFSET + PCIC_SOCKET_OFFSET 97 98 #define PCIC_VENDOR_UNKNOWN 0 99 #define PCIC_VENDOR_I82365SLR0 1 100 #define PCIC_VENDOR_I82365SLR1 2 101 #define PCIC_VENDOR_CIRRUS_PD6710 3 102 #define PCIC_VENDOR_CIRRUS_PD672X 4 103 104 /* 105 * This is sort of arbitrary. It merely needs to be "enough". It can be 106 * overridden in the conf file, anyway. 107 */ 108 109 #define PCIC_MEM_PAGES 4 110 #define PCIC_MEMSIZE PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE 111 112 #define PCIC_NSLOTS 4 113 114 struct pcic_softc { 115 struct device dev; 116 117 bus_space_tag_t memt; 118 bus_space_handle_t memh; 119 bus_space_tag_t iot; 120 bus_space_handle_t ioh; 121 122 struct callout poll_ch; 123 int poll_established; 124 125 pcmcia_chipset_tag_t pct; 126 127 struct lock sc_pcic_lock; 128 129 /* this needs to be large enough to hold PCIC_MEM_PAGES bits */ 130 int subregionmask; 131 #define PCIC_MAX_MEM_PAGES (8 * sizeof(int)) 132 133 /* used by memory window mapping functions */ 134 bus_addr_t membase; 135 136 /* 137 * used by io window mapping functions. These can actually overlap 138 * with another pcic, since the underlying extent mapper will deal 139 * with individual allocations. This is here to deal with the fact 140 * that different busses have different real widths (different pc 141 * hardware seems to use 10 or 12 bits for the I/O bus). 142 */ 143 bus_addr_t iobase; 144 bus_addr_t iosize; 145 146 int irq; 147 void *ih; 148 149 struct pcic_handle handle[PCIC_NSLOTS]; 150 151 /* for use by underlying chip code for discovering irqs */ 152 int intr_detect, intr_false; 153 int intr_mask[PCIC_NSLOTS / 2]; /* probed intterupts if possible */ 154 }; 155 156 157 int pcic_ident_ok __P((int)); 158 int pcic_vendor __P((struct pcic_handle *)); 159 char *pcic_vendor_to_string __P((int)); 160 161 void pcic_attach __P((struct pcic_softc *)); 162 void pcic_attach_sockets __P((struct pcic_softc *)); 163 void pcic_attach_sockets_finish __P((struct pcic_softc *)); 164 int pcic_intr __P((void *arg)); 165 166 /* 167 static inline int pcic_read __P((struct pcic_handle *, int)); 168 static inline void pcic_write __P((struct pcic_handle *, int, u_int8_t)); 169 */ 170 171 int pcic_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 172 struct pcmcia_mem_handle *)); 173 void pcic_chip_mem_free __P((pcmcia_chipset_handle_t, 174 struct pcmcia_mem_handle *)); 175 int pcic_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 176 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *)); 177 void pcic_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 178 179 int pcic_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 180 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 181 void pcic_chip_io_free __P((pcmcia_chipset_handle_t, 182 struct pcmcia_io_handle *)); 183 int pcic_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 184 bus_size_t, struct pcmcia_io_handle *, int *)); 185 void pcic_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 186 187 void pcic_chip_socket_enable __P((pcmcia_chipset_handle_t)); 188 void pcic_chip_socket_disable __P((pcmcia_chipset_handle_t)); 189 190 #if 0 191 192 static __inline int pcic_read __P((struct pcic_handle *, int)); 193 static __inline int 194 pcic_read(h, idx) 195 struct pcic_handle *h; 196 int idx; 197 { 198 if (idx != -1) 199 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 200 h->sock + idx); 201 return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA)); 202 } 203 204 static __inline void pcic_write __P((struct pcic_handle *, int, int)); 205 static __inline void 206 pcic_write(h, idx, data) 207 struct pcic_handle *h; 208 int idx; 209 int data; 210 { 211 if (idx != -1) 212 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 213 h->sock + idx); 214 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data)); 215 } 216 #else 217 #define pcic_read(h, idx) \ 218 (*(h)->ph_read)((h), (idx)) 219 220 #define pcic_write(h, idx, data) \ 221 (*(h)->ph_write)((h), (idx), (data)) 222 223 #endif 224
Indexes created Tue Sep 30 20:09:53 GMT 2025