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i82365var.h revision 1.6 
      1 /*	$NetBSD: i82365var.h,v 1.6 1999/01/01 14:05:18 christos Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Marc Horowitz.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/device.h>
     33 
     34 #include <dev/pcmcia/pcmciareg.h>
     35 #include <dev/pcmcia/pcmciachip.h>
     36 
     37 #include <dev/ic/i82365reg.h>
     38 
     39 struct proc;
     40 
     41 struct pcic_event {
     42 	SIMPLEQ_ENTRY(pcic_event) pe_q;
     43 	int pe_type;
     44 };
     45 
     46 /* pe_type */
     47 #define	PCIC_EVENT_INSERTION	0
     48 #define	PCIC_EVENT_REMOVAL	1
     49 
     50 struct pcic_handle {
     51 	struct pcic_softc *sc;
     52 	int	vendor;
     53 	int	sock;
     54 	int	flags;
     55 	int	memalloc;
     56 	struct {
     57 		bus_addr_t	addr;
     58 		bus_size_t	size;
     59 		long		offset;
     60 		int		kind;
     61 	} mem[PCIC_MEM_WINS];
     62 	int	ioalloc;
     63 	struct {
     64 		bus_addr_t	addr;
     65 		bus_size_t	size;
     66 		int		width;
     67 	} io[PCIC_IO_WINS];
     68 	int	ih_irq;
     69 	struct device *pcmcia;
     70 
     71 	int shutdown;
     72 	struct proc *event_thread;
     73 	SIMPLEQ_HEAD(, pcic_event) events;
     74 };
     75 
     76 #define	PCIC_FLAG_SOCKETP	0x0001
     77 #define	PCIC_FLAG_CARDP		0x0002
     78 
     79 #define	C0SA PCIC_CHIP0_BASE+PCIC_SOCKETA_INDEX
     80 #define	C0SB PCIC_CHIP0_BASE+PCIC_SOCKETB_INDEX
     81 #define	C1SA PCIC_CHIP1_BASE+PCIC_SOCKETA_INDEX
     82 #define	C1SB PCIC_CHIP1_BASE+PCIC_SOCKETB_INDEX
     83 
     84 /*
     85  * This is sort of arbitrary.  It merely needs to be "enough". It can be
     86  * overridden in the conf file, anyway.
     87  */
     88 
     89 #define	PCIC_MEM_PAGES	4
     90 #define	PCIC_MEMSIZE	PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE
     91 
     92 #define	PCIC_NSLOTS	4
     93 
     94 struct pcic_softc {
     95 	struct device dev;
     96 
     97 	bus_space_tag_t memt;
     98 	bus_space_handle_t memh;
     99 	bus_space_tag_t iot;
    100 	bus_space_handle_t ioh;
    101 
    102 	/* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */
    103 	void *intr_est;
    104 
    105 	pcmcia_chipset_tag_t pct;
    106 
    107 	/* this needs to be large enough to hold PCIC_MEM_PAGES bits */
    108 	int	subregionmask;
    109 #define PCIC_MAX_MEM_PAGES	(8 * sizeof(int))
    110 
    111 	/* used by memory window mapping functions */
    112 	bus_addr_t membase;
    113 
    114 	/*
    115 	 * used by io window mapping functions.  These can actually overlap
    116 	 * with another pcic, since the underlying extent mapper will deal
    117 	 * with individual allocations.  This is here to deal with the fact
    118 	 * that different busses have different real widths (different pc
    119 	 * hardware seems to use 10 or 12 bits for the I/O bus).
    120 	 */
    121 	bus_addr_t iobase;
    122 	bus_addr_t iosize;
    123 
    124 	int	irq;
    125 	void	*ih;
    126 
    127 	struct pcic_handle handle[PCIC_NSLOTS];
    128 };
    129 
    130 
    131 int	pcic_ident_ok __P((int));
    132 int	pcic_vendor __P((struct pcic_handle *));
    133 char	*pcic_vendor_to_string __P((int));
    134 
    135 void	pcic_attach __P((struct pcic_softc *));
    136 void	pcic_attach_sockets __P((struct pcic_softc *));
    137 int	pcic_intr __P((void *arg));
    138 
    139 static inline int pcic_read __P((struct pcic_handle *, int));
    140 static inline void pcic_write __P((struct pcic_handle *, int, int));
    141 
    142 int	pcic_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t,
    143 	    struct pcmcia_mem_handle *));
    144 void	pcic_chip_mem_free __P((pcmcia_chipset_handle_t,
    145 	    struct pcmcia_mem_handle *));
    146 int	pcic_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
    147 	    bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *));
    148 void	pcic_chip_mem_unmap __P((pcmcia_chipset_handle_t, int));
    149 
    150 int	pcic_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t,
    151 	    bus_size_t, bus_size_t, struct pcmcia_io_handle *));
    152 void	pcic_chip_io_free __P((pcmcia_chipset_handle_t,
    153 	    struct pcmcia_io_handle *));
    154 int	pcic_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
    155 	    bus_size_t, struct pcmcia_io_handle *, int *));
    156 void	pcic_chip_io_unmap __P((pcmcia_chipset_handle_t, int));
    157 
    158 void	pcic_chip_socket_enable __P((pcmcia_chipset_handle_t));
    159 void	pcic_chip_socket_disable __P((pcmcia_chipset_handle_t));
    160 
    161 static __inline int pcic_read __P((struct pcic_handle *, int));
    162 static __inline int
    163 pcic_read(h, idx)
    164 	struct pcic_handle *h;
    165 	int idx;
    166 {
    167 	if (idx != -1)
    168 		bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
    169 		    h->sock + idx);
    170 	return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA));
    171 }
    172 
    173 static __inline void pcic_write __P((struct pcic_handle *, int, int));
    174 static __inline void
    175 pcic_write(h, idx, data)
    176 	struct pcic_handle *h;
    177 	int idx;
    178 	int data;
    179 {
    180 	if (idx != -1)
    181 		bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
    182 		    h->sock + idx);
    183 	bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data));
    184 }
    185