i82365var.h revision 1.8
1 /* $NetBSD: i82365var.h,v 1.8 1999/10/15 06:07:27 haya Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Marc Horowitz. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/device.h> 33 34 #include <dev/pcmcia/pcmciareg.h> 35 #include <dev/pcmcia/pcmciachip.h> 36 37 #include <dev/ic/i82365reg.h> 38 39 struct proc; 40 41 struct pcic_event { 42 SIMPLEQ_ENTRY(pcic_event) pe_q; 43 int pe_type; 44 }; 45 46 /* pe_type */ 47 #define PCIC_EVENT_INSERTION 0 48 #define PCIC_EVENT_REMOVAL 1 49 50 struct pcic_handle { 51 struct device *ph_parent; 52 bus_space_tag_t ph_bus_t; /* I/O or MEM? I don't mind */ 53 bus_space_handle_t ph_bus_h; 54 u_int8_t (* ph_read) __P((struct pcic_handle*, int)); 55 void (* ph_write) __P((struct pcic_handle *, int, u_int8_t)); 56 57 int vendor; 58 int sock; 59 int flags; 60 int laststate; 61 int memalloc; 62 struct { 63 bus_addr_t addr; 64 bus_size_t size; 65 long offset; 66 int kind; 67 } mem[PCIC_MEM_WINS]; 68 int ioalloc; 69 struct { 70 bus_addr_t addr; 71 bus_size_t size; 72 int width; 73 } io[PCIC_IO_WINS]; 74 int ih_irq; 75 struct device *pcmcia; 76 77 int shutdown; 78 struct proc *event_thread; 79 SIMPLEQ_HEAD(, pcic_event) events; 80 }; 81 82 #define PCIC_FLAG_SOCKETP 0x0001 83 #define PCIC_FLAG_CARDP 0x0002 84 85 #define PCIC_LASTSTATE_PRESENT 0x0002 86 #define PCIC_LASTSTATE_HALF 0x0001 87 #define PCIC_LASTSTATE_EMPTY 0x0000 88 89 #define C0SA PCIC_CHIP0_BASE+PCIC_SOCKETA_INDEX 90 #define C0SB PCIC_CHIP0_BASE+PCIC_SOCKETB_INDEX 91 #define C1SA PCIC_CHIP1_BASE+PCIC_SOCKETA_INDEX 92 #define C1SB PCIC_CHIP1_BASE+PCIC_SOCKETB_INDEX 93 94 /* 95 * This is sort of arbitrary. It merely needs to be "enough". It can be 96 * overridden in the conf file, anyway. 97 */ 98 99 #define PCIC_MEM_PAGES 4 100 #define PCIC_MEMSIZE PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE 101 102 #define PCIC_NSLOTS 4 103 104 struct pcic_softc { 105 struct device dev; 106 107 bus_space_tag_t memt; 108 bus_space_handle_t memh; 109 bus_space_tag_t iot; 110 bus_space_handle_t ioh; 111 112 /* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */ 113 void *intr_est; 114 115 pcmcia_chipset_tag_t pct; 116 117 /* this needs to be large enough to hold PCIC_MEM_PAGES bits */ 118 int subregionmask; 119 #define PCIC_MAX_MEM_PAGES (8 * sizeof(int)) 120 121 /* used by memory window mapping functions */ 122 bus_addr_t membase; 123 124 /* 125 * used by io window mapping functions. These can actually overlap 126 * with another pcic, since the underlying extent mapper will deal 127 * with individual allocations. This is here to deal with the fact 128 * that different busses have different real widths (different pc 129 * hardware seems to use 10 or 12 bits for the I/O bus). 130 */ 131 bus_addr_t iobase; 132 bus_addr_t iosize; 133 134 int irq; 135 void *ih; 136 137 struct pcic_handle handle[PCIC_NSLOTS]; 138 }; 139 140 141 int pcic_ident_ok __P((int)); 142 int pcic_vendor __P((struct pcic_handle *)); 143 char *pcic_vendor_to_string __P((int)); 144 145 void pcic_attach __P((struct pcic_softc *)); 146 void pcic_attach_sockets __P((struct pcic_softc *)); 147 int pcic_intr __P((void *arg)); 148 149 /* 150 static inline int pcic_read __P((struct pcic_handle *, int)); 151 static inline void pcic_write __P((struct pcic_handle *, int, u_int8_t)); 152 */ 153 154 int pcic_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 155 struct pcmcia_mem_handle *)); 156 void pcic_chip_mem_free __P((pcmcia_chipset_handle_t, 157 struct pcmcia_mem_handle *)); 158 int pcic_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 159 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 160 void pcic_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 161 162 int pcic_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 163 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 164 void pcic_chip_io_free __P((pcmcia_chipset_handle_t, 165 struct pcmcia_io_handle *)); 166 int pcic_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 167 bus_size_t, struct pcmcia_io_handle *, int *)); 168 void pcic_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 169 170 void pcic_chip_socket_enable __P((pcmcia_chipset_handle_t)); 171 void pcic_chip_socket_disable __P((pcmcia_chipset_handle_t)); 172 173 #if 0 174 175 static __inline int pcic_read __P((struct pcic_handle *, int)); 176 static __inline int 177 pcic_read(h, idx) 178 struct pcic_handle *h; 179 int idx; 180 { 181 if (idx != -1) 182 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 183 h->sock + idx); 184 return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA)); 185 } 186 187 static __inline void pcic_write __P((struct pcic_handle *, int, int)); 188 static __inline void 189 pcic_write(h, idx, data) 190 struct pcic_handle *h; 191 int idx; 192 int data; 193 { 194 if (idx != -1) 195 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 196 h->sock + idx); 197 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data)); 198 } 199 #else 200 #define pcic_read(h, idx) \ 201 (*(h)->ph_read)((h), (idx)) 202 203 #define pcic_write(h, idx, data) \ 204 (*(h)->ph_write)((h), (idx), (data)) 205 206 #endif 207
Indexes created Mon Sep 29 21:09:56 GMT 2025