i82365var.h revision 1.9
1 /* $NetBSD: i82365var.h,v 1.9 2000/02/01 22:39:51 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Marc Horowitz. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/device.h> 33 34 #include <dev/pcmcia/pcmciareg.h> 35 #include <dev/pcmcia/pcmciachip.h> 36 37 #include <dev/ic/i82365reg.h> 38 39 struct proc; 40 41 struct pcic_event { 42 SIMPLEQ_ENTRY(pcic_event) pe_q; 43 int pe_type; 44 }; 45 46 /* pe_type */ 47 #define PCIC_EVENT_INSERTION 0 48 #define PCIC_EVENT_REMOVAL 1 49 50 struct pcic_handle { 51 struct device *ph_parent; 52 bus_space_tag_t ph_bus_t; /* I/O or MEM? I don't mind */ 53 bus_space_handle_t ph_bus_h; 54 u_int8_t (* ph_read) __P((struct pcic_handle*, int)); 55 void (* ph_write) __P((struct pcic_handle *, int, u_int8_t)); 56 57 int vendor; /* vendor of chip */ 58 int chip; /* chip index 0 or 1 */ 59 int sock; 60 int flags; 61 int laststate; 62 int memalloc; 63 struct { 64 bus_addr_t addr; 65 bus_size_t size; 66 long offset; 67 int kind; 68 } mem[PCIC_MEM_WINS]; 69 int ioalloc; 70 struct { 71 bus_addr_t addr; 72 bus_size_t size; 73 int width; 74 } io[PCIC_IO_WINS]; 75 int ih_irq; 76 struct device *pcmcia; 77 78 int shutdown; 79 struct proc *event_thread; 80 SIMPLEQ_HEAD(, pcic_event) events; 81 }; 82 83 #define PCIC_FLAG_SOCKETP 0x0001 84 #define PCIC_FLAG_CARDP 0x0002 85 86 #define PCIC_LASTSTATE_PRESENT 0x0002 87 #define PCIC_LASTSTATE_HALF 0x0001 88 #define PCIC_LASTSTATE_EMPTY 0x0000 89 90 #define C0SA 0 91 #define C0SB PCIC_SOCKET_OFFSET 92 #define C1SA PCIC_CHIP_OFFSET 93 #define C1SB PCIC_CHIP_OFFSET + PCIC_SOCKET_OFFSET 94 95 #define PCIC_VENDOR_UNKNOWN 0 96 #define PCIC_VENDOR_I82365SLR0 1 97 #define PCIC_VENDOR_I82365SLR1 2 98 #define PCIC_VENDOR_CIRRUS_PD6710 3 99 #define PCIC_VENDOR_CIRRUS_PD672X 4 100 101 /* 102 * This is sort of arbitrary. It merely needs to be "enough". It can be 103 * overridden in the conf file, anyway. 104 */ 105 106 #define PCIC_MEM_PAGES 4 107 #define PCIC_MEMSIZE PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE 108 109 #define PCIC_NSLOTS 4 110 111 struct pcic_softc { 112 struct device dev; 113 114 bus_space_tag_t memt; 115 bus_space_handle_t memh; 116 bus_space_tag_t iot; 117 bus_space_handle_t ioh; 118 119 /* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */ 120 void *intr_est; 121 122 pcmcia_chipset_tag_t pct; 123 124 /* this needs to be large enough to hold PCIC_MEM_PAGES bits */ 125 int subregionmask; 126 #define PCIC_MAX_MEM_PAGES (8 * sizeof(int)) 127 128 /* used by memory window mapping functions */ 129 bus_addr_t membase; 130 131 /* 132 * used by io window mapping functions. These can actually overlap 133 * with another pcic, since the underlying extent mapper will deal 134 * with individual allocations. This is here to deal with the fact 135 * that different busses have different real widths (different pc 136 * hardware seems to use 10 or 12 bits for the I/O bus). 137 */ 138 bus_addr_t iobase; 139 bus_addr_t iosize; 140 141 int irq; 142 void *ih; 143 144 struct pcic_handle handle[PCIC_NSLOTS]; 145 146 /* for use by underlying chip code for discovering irqs */ 147 int intr_detect; 148 int intr_mask[PCIC_NSLOTS / 2]; /* probed intterupts if possible */ 149 }; 150 151 152 int pcic_ident_ok __P((int)); 153 int pcic_vendor __P((struct pcic_handle *)); 154 char *pcic_vendor_to_string __P((int)); 155 156 void pcic_attach __P((struct pcic_softc *)); 157 void pcic_attach_sockets __P((struct pcic_softc *)); 158 void pcic_attach_sockets_finish __P((struct pcic_softc *)); 159 int pcic_intr __P((void *arg)); 160 161 /* 162 static inline int pcic_read __P((struct pcic_handle *, int)); 163 static inline void pcic_write __P((struct pcic_handle *, int, u_int8_t)); 164 */ 165 166 int pcic_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 167 struct pcmcia_mem_handle *)); 168 void pcic_chip_mem_free __P((pcmcia_chipset_handle_t, 169 struct pcmcia_mem_handle *)); 170 int pcic_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 171 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *)); 172 void pcic_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 173 174 int pcic_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *)); 176 void pcic_chip_io_free __P((pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *)); 178 int pcic_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *)); 180 void pcic_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 181 182 void pcic_chip_socket_enable __P((pcmcia_chipset_handle_t)); 183 void pcic_chip_socket_disable __P((pcmcia_chipset_handle_t)); 184 185 #if 0 186 187 static __inline int pcic_read __P((struct pcic_handle *, int)); 188 static __inline int 189 pcic_read(h, idx) 190 struct pcic_handle *h; 191 int idx; 192 { 193 if (idx != -1) 194 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 195 h->sock + idx); 196 return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA)); 197 } 198 199 static __inline void pcic_write __P((struct pcic_handle *, int, int)); 200 static __inline void 201 pcic_write(h, idx, data) 202 struct pcic_handle *h; 203 int idx; 204 int data; 205 { 206 if (idx != -1) 207 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX, 208 h->sock + idx); 209 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data)); 210 } 211 #else 212 #define pcic_read(h, idx) \ 213 (*(h)->ph_read)((h), (idx)) 214 215 #define pcic_write(h, idx, data) \ 216 (*(h)->ph_write)((h), (idx), (data)) 217 218 #endif 219
Indexes created Mon Sep 29 13:09:55 GMT 2025