i82557.c revision 1.10
1 /* $NetBSD: i82557.c,v 1.10 1999/10/30 16:07:58 sommerfeld Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller. 71 */ 72 73 #include "opt_inet.h" 74 #include "opt_ns.h" 75 #include "bpfilter.h" 76 #include "rnd.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/ioctl.h> 85 #include <sys/errno.h> 86 #include <sys/device.h> 87 88 #include <vm/vm.h> /* for PAGE_SIZE */ 89 90 #if NRND > 0 91 #include <sys/rnd.h> 92 #endif 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/if_inarp.h> 106 #endif 107 108 #ifdef NS 109 #include <netns/ns.h> 110 #include <netns/ns_if.h> 111 #endif 112 113 #include <machine/bus.h> 114 #include <machine/intr.h> 115 116 #include <dev/mii/miivar.h> 117 118 #include <dev/ic/i82557reg.h> 119 #include <dev/ic/i82557var.h> 120 121 /* 122 * NOTE! On the Alpha, we have an alignment constraint. The 123 * card DMAs the packet immediately following the RFA. However, 124 * the first thing in the packet is a 14-byte Ethernet header. 125 * This means that the packet is misaligned. To compensate, 126 * we actually offset the RFA 2 bytes into the cluster. This 127 * alignes the packet after the Ethernet header at a 32-bit 128 * boundary. HOWEVER! This means that the RFA is misaligned! 129 */ 130 #define RFA_ALIGNMENT_FUDGE 2 131 132 /* 133 * Template for default configuration parameters. 134 * See struct fxp_cb_config for the bit definitions. 135 */ 136 u_int8_t fxp_cb_config_template[] = { 137 0x0, 0x0, /* cb_status */ 138 0x80, 0x2, /* cb_command */ 139 0xff, 0xff, 0xff, 0xff, /* link_addr */ 140 0x16, /* 0 */ 141 0x8, /* 1 */ 142 0x0, /* 2 */ 143 0x0, /* 3 */ 144 0x0, /* 4 */ 145 0x80, /* 5 */ 146 0xb2, /* 6 */ 147 0x3, /* 7 */ 148 0x1, /* 8 */ 149 0x0, /* 9 */ 150 0x26, /* 10 */ 151 0x0, /* 11 */ 152 0x60, /* 12 */ 153 0x0, /* 13 */ 154 0xf2, /* 14 */ 155 0x48, /* 15 */ 156 0x0, /* 16 */ 157 0x40, /* 17 */ 158 0xf3, /* 18 */ 159 0x0, /* 19 */ 160 0x3f, /* 20 */ 161 0x5 /* 21 */ 162 }; 163 164 void fxp_mii_initmedia __P((struct fxp_softc *)); 165 int fxp_mii_mediachange __P((struct ifnet *)); 166 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 167 168 void fxp_80c24_initmedia __P((struct fxp_softc *)); 169 int fxp_80c24_mediachange __P((struct ifnet *)); 170 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 inline void fxp_scb_wait __P((struct fxp_softc *)); 173 174 void fxp_start __P((struct ifnet *)); 175 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 176 int fxp_init __P((struct fxp_softc *)); 177 void fxp_rxdrain __P((struct fxp_softc *)); 178 void fxp_stop __P((struct fxp_softc *, int)); 179 void fxp_watchdog __P((struct ifnet *)); 180 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 181 int fxp_mdi_read __P((struct device *, int, int)); 182 void fxp_statchg __P((struct device *)); 183 void fxp_mdi_write __P((struct device *, int, int, int)); 184 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 185 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 186 void fxp_tick __P((void *)); 187 void fxp_mc_setup __P((struct fxp_softc *)); 188 189 void fxp_shutdown __P((void *)); 190 void fxp_power __P((int, void *)); 191 192 int fxp_copy_small = 0; 193 194 int fxp_enable __P((struct fxp_softc*)); 195 void fxp_disable __P((struct fxp_softc*)); 196 197 struct fxp_phytype { 198 int fp_phy; /* type of PHY, -1 for MII at the end. */ 199 void (*fp_init) __P((struct fxp_softc *)); 200 } fxp_phytype_table[] = { 201 { FXP_PHY_80C24, fxp_80c24_initmedia }, 202 { -1, fxp_mii_initmedia }, 203 }; 204 205 /* 206 * Set initial transmit threshold at 64 (512 bytes). This is 207 * increased by 64 (512 bytes) at a time, to maximum of 192 208 * (1536 bytes), if an underrun occurs. 209 */ 210 static int tx_threshold = 64; 211 212 /* 213 * Wait for the previous command to be accepted (but not necessarily 214 * completed). 215 */ 216 inline void 217 fxp_scb_wait(sc) 218 struct fxp_softc *sc; 219 { 220 int i = 10000; 221 222 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 223 delay(2); 224 if (i == 0) 225 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 226 } 227 228 /* 229 * Finish attaching an i82557 interface. Called by bus-specific front-end. 230 */ 231 void 232 fxp_attach(sc) 233 struct fxp_softc *sc; 234 { 235 u_int8_t enaddr[6]; 236 struct ifnet *ifp; 237 bus_dma_segment_t seg; 238 int rseg, i, error; 239 struct fxp_phytype *fp; 240 241 /* 242 * Allocate the control data structures, and create and load the 243 * DMA map for it. 244 */ 245 if ((error = bus_dmamem_alloc(sc->sc_dmat, 246 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 247 0)) != 0) { 248 printf("%s: unable to allocate control data, error = %d\n", 249 sc->sc_dev.dv_xname, error); 250 goto fail_0; 251 } 252 253 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 254 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 255 BUS_DMA_COHERENT)) != 0) { 256 printf("%s: unable to map control data, error = %d\n", 257 sc->sc_dev.dv_xname, error); 258 goto fail_1; 259 } 260 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 261 262 if ((error = bus_dmamap_create(sc->sc_dmat, 263 sizeof(struct fxp_control_data), 1, 264 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 265 printf("%s: unable to create control data DMA map, " 266 "error = %d\n", sc->sc_dev.dv_xname, error); 267 goto fail_2; 268 } 269 270 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 271 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 272 0)) != 0) { 273 printf("%s: can't load control data DMA map, error = %d\n", 274 sc->sc_dev.dv_xname, error); 275 goto fail_3; 276 } 277 278 /* 279 * Create the transmit buffer DMA maps. 280 */ 281 for (i = 0; i < FXP_NTXCB; i++) { 282 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 283 FXP_NTXSEG, MCLBYTES, 0, 0, 284 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 285 printf("%s: unable to create tx DMA map %d, " 286 "error = %d\n", sc->sc_dev.dv_xname, i, error); 287 goto fail_4; 288 } 289 } 290 291 /* 292 * Create the receive buffer DMA maps. 293 */ 294 for (i = 0; i < FXP_NRFABUFS; i++) { 295 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 296 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 297 printf("%s: unable to create rx DMA map %d, " 298 "error = %d\n", sc->sc_dev.dv_xname, i, error); 299 goto fail_5; 300 } 301 } 302 303 /* Initialize MAC address and media structures. */ 304 fxp_get_info(sc, enaddr); 305 306 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 307 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 308 309 ifp = &sc->sc_ethercom.ec_if; 310 311 /* 312 * Get info about our media interface, and initialize it. Note 313 * the table terminates itself with a phy of -1, indicating 314 * that we're using MII. 315 */ 316 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 317 if (fp->fp_phy == sc->phy_primary_device) 318 break; 319 (*fp->fp_init)(sc); 320 321 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 322 ifp->if_softc = sc; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_ioctl = fxp_ioctl; 325 ifp->if_start = fxp_start; 326 ifp->if_watchdog = fxp_watchdog; 327 328 /* 329 * Attach the interface. 330 */ 331 if_attach(ifp); 332 ether_ifattach(ifp, enaddr); 333 #if NBPFILTER > 0 334 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 335 sizeof(struct ether_header)); 336 #endif 337 #if NRND > 0 338 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 339 RND_TYPE_NET, 0); 340 #endif 341 342 /* 343 * Add shutdown hook so that DMA is disabled prior to reboot. Not 344 * doing do could allow DMA to corrupt kernel memory during the 345 * reboot before the driver initializes. 346 */ 347 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 348 if (sc->sc_sdhook == NULL) 349 printf("%s: WARNING: unable to establish shutdown hook\n", 350 sc->sc_dev.dv_xname); 351 /* 352 * Add suspend hook, for similar reasons.. 353 */ 354 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 355 if (sc->sc_powerhook == NULL) 356 printf("%s: WARNING: unable to establish power hook\n", 357 sc->sc_dev.dv_xname); 358 return; 359 360 /* 361 * Free any resources we've allocated during the failed attach 362 * attempt. Do this in reverse order and fall though. 363 */ 364 fail_5: 365 for (i = 0; i < FXP_NRFABUFS; i++) { 366 if (sc->sc_rxmaps[i] != NULL) 367 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 368 } 369 fail_4: 370 for (i = 0; i < FXP_NTXCB; i++) { 371 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 372 bus_dmamap_destroy(sc->sc_dmat, 373 FXP_DSTX(sc, i)->txs_dmamap); 374 } 375 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 376 fail_3: 377 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 378 fail_2: 379 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 380 sizeof(struct fxp_control_data)); 381 fail_1: 382 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 383 fail_0: 384 return; 385 } 386 387 void 388 fxp_mii_initmedia(sc) 389 struct fxp_softc *sc; 390 { 391 392 sc->sc_flags |= FXPF_MII; 393 394 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 395 sc->sc_mii.mii_readreg = fxp_mdi_read; 396 sc->sc_mii.mii_writereg = fxp_mdi_write; 397 sc->sc_mii.mii_statchg = fxp_statchg; 398 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 399 fxp_mii_mediastatus); 400 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff); 401 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 402 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 403 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 404 } else 405 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 406 } 407 408 void 409 fxp_80c24_initmedia(sc) 410 struct fxp_softc *sc; 411 { 412 413 /* 414 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 415 * doesn't have a programming interface of any sort. The 416 * media is sensed automatically based on how the link partner 417 * is configured. This is, in essence, manual configuration. 418 */ 419 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 420 sc->sc_dev.dv_xname); 421 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 422 fxp_80c24_mediastatus); 423 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 424 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 425 } 426 427 /* 428 * Device shutdown routine. Called at system shutdown after sync. The 429 * main purpose of this routine is to shut off receiver DMA so that 430 * kernel memory doesn't get clobbered during warmboot. 431 */ 432 void 433 fxp_shutdown(arg) 434 void *arg; 435 { 436 struct fxp_softc *sc = arg; 437 438 /* 439 * Since the system's going to halt shortly, don't bother 440 * freeing mbufs. 441 */ 442 fxp_stop(sc, 0); 443 } 444 /* 445 * Power handler routine. Called when the system is transitioning 446 * into/out of power save modes. As with fxp_shutdown, the main 447 * purpose of this routine is to shut off receiver DMA so it doesn't 448 * clobber kernel memory at the wrong time. 449 */ 450 void 451 fxp_power(why, arg) 452 int why; 453 void *arg; 454 { 455 struct fxp_softc *sc = arg; 456 struct ifnet *ifp; 457 int s; 458 459 s = splnet(); 460 if (why != PWR_RESUME) 461 fxp_stop(sc, 0); 462 else { 463 ifp = &sc->sc_ethercom.ec_if; 464 if (ifp->if_flags & IFF_UP) 465 fxp_init(sc); 466 } 467 splx(s); 468 } 469 470 /* 471 * Initialize the interface media. 472 */ 473 void 474 fxp_get_info(sc, enaddr) 475 struct fxp_softc *sc; 476 u_int8_t *enaddr; 477 { 478 u_int16_t data, myea[3]; 479 480 /* 481 * Reset to a stable state. 482 */ 483 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 484 DELAY(10); 485 486 /* 487 * Figure out EEPROM size. 488 * 489 * Cards can have either 64-word or 256-word EEPROMs, with 490 * addresses fed in using a bit-at-a-time protocol, MSB first. 491 * 492 * XXX this is probably not the best way to do this; the linux 493 * driver does a checksum of the eeprom, but there is 494 * (AFAIK) no on-line documentation on what this checksum 495 * should look like (you could just steal the code from 496 * linux, but that's cheating); for now we just use the fact 497 * that the upper two bits of word 10 should be 01 498 */ 499 for(sc->sc_eeprom_size = 6; 500 sc->sc_eeprom_size <= 8; 501 sc->sc_eeprom_size += 2) { 502 fxp_read_eeprom(sc, &data, 10, 1); 503 if((data & 0xc000) == 0x4000) 504 break; 505 } 506 if(sc->sc_eeprom_size > 8) 507 panic("%s: failed to get EEPROM size", sc->sc_dev.dv_xname); 508 #ifdef DEBUG 509 printf("%s: assuming %d word EEPROM\n", 510 sc->sc_dev.dv_xname, 511 1 << sc->sc_eeprom_size); 512 #endif 513 514 /* 515 * Get info about the primary PHY 516 */ 517 fxp_read_eeprom(sc, &data, 6, 1); 518 sc->phy_primary_addr = data & 0xff; 519 sc->phy_primary_device = (data >> 8) & 0x3f; 520 sc->phy_10Mbps_only = data >> 15; 521 522 /* 523 * Read MAC address. 524 */ 525 fxp_read_eeprom(sc, myea, 0, 3); 526 bcopy(myea, enaddr, ETHER_ADDR_LEN); 527 } 528 529 /* 530 * Read from the serial EEPROM. Basically, you manually shift in 531 * the read opcode (one bit at a time) and then shift in the address, 532 * and then you shift out the data (all of this one bit at a time). 533 * The word size is 16 bits, so you have to provide the address for 534 * every 16 bits of data. 535 */ 536 void 537 fxp_read_eeprom(sc, data, offset, words) 538 struct fxp_softc *sc; 539 u_int16_t *data; 540 int offset; 541 int words; 542 { 543 u_int16_t reg; 544 int i, x; 545 546 for (i = 0; i < words; i++) { 547 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 548 /* 549 * Shift in read opcode. 550 */ 551 for (x = 3; x > 0; x--) { 552 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 553 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 554 } else { 555 reg = FXP_EEPROM_EECS; 556 } 557 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 558 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 559 reg | FXP_EEPROM_EESK); 560 DELAY(1); 561 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 562 DELAY(1); 563 } 564 /* 565 * Shift in address. 566 */ 567 for (x = sc->sc_eeprom_size; x > 0; x--) { 568 if ((i + offset) & (1 << (x - 1))) { 569 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 570 } else { 571 reg = FXP_EEPROM_EECS; 572 } 573 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 574 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 575 reg | FXP_EEPROM_EESK); 576 DELAY(1); 577 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 578 DELAY(1); 579 } 580 reg = FXP_EEPROM_EECS; 581 data[i] = 0; 582 /* 583 * Shift out data. 584 */ 585 for (x = 16; x > 0; x--) { 586 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 587 reg | FXP_EEPROM_EESK); 588 DELAY(1); 589 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 590 FXP_EEPROM_EEDO) 591 data[i] |= (1 << (x - 1)); 592 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 593 DELAY(1); 594 } 595 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 596 DELAY(1); 597 } 598 } 599 600 /* 601 * Start packet transmission on the interface. 602 */ 603 void 604 fxp_start(ifp) 605 struct ifnet *ifp; 606 { 607 struct fxp_softc *sc = ifp->if_softc; 608 struct mbuf *m0, *m; 609 struct fxp_cb_tx *txd; 610 struct fxp_txsoft *txs; 611 struct fxp_tbdlist *tbd; 612 bus_dmamap_t dmamap; 613 int error, lasttx, nexttx, opending, seg; 614 615 /* 616 * If we want a re-init, bail out now. 617 */ 618 if (sc->sc_flags & FXPF_WANTINIT) { 619 ifp->if_flags |= IFF_OACTIVE; 620 return; 621 } 622 623 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 624 return; 625 626 /* 627 * Remember the previous txpending and the current lasttx. 628 */ 629 opending = sc->sc_txpending; 630 lasttx = sc->sc_txlast; 631 632 /* 633 * Loop through the send queue, setting up transmit descriptors 634 * until we drain the queue, or use up all available transmit 635 * descriptors. 636 */ 637 while (sc->sc_txpending < FXP_NTXCB) { 638 /* 639 * Grab a packet off the queue. 640 */ 641 IF_DEQUEUE(&ifp->if_snd, m0); 642 if (m0 == NULL) 643 break; 644 645 /* 646 * Get the next available transmit descriptor. 647 */ 648 nexttx = FXP_NEXTTX(sc->sc_txlast); 649 txd = FXP_CDTX(sc, nexttx); 650 tbd = FXP_CDTBD(sc, nexttx); 651 txs = FXP_DSTX(sc, nexttx); 652 dmamap = txs->txs_dmamap; 653 654 /* 655 * Load the DMA map. If this fails, the packet either 656 * didn't fit in the allotted number of frags, or we were 657 * short on resources. In this case, we'll copy and try 658 * again. 659 */ 660 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 661 BUS_DMA_NOWAIT) != 0) { 662 MGETHDR(m, M_DONTWAIT, MT_DATA); 663 if (m == NULL) { 664 printf("%s: unable to allocate Tx mbuf\n", 665 sc->sc_dev.dv_xname); 666 IF_PREPEND(&ifp->if_snd, m0); 667 break; 668 } 669 if (m0->m_pkthdr.len > MHLEN) { 670 MCLGET(m, M_DONTWAIT); 671 if ((m->m_flags & M_EXT) == 0) { 672 printf("%s: unable to allocate Tx " 673 "cluster\n", sc->sc_dev.dv_xname); 674 m_freem(m); 675 IF_PREPEND(&ifp->if_snd, m0); 676 break; 677 } 678 } 679 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 680 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 681 m_freem(m0); 682 m0 = m; 683 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 684 m0, BUS_DMA_NOWAIT); 685 if (error) { 686 printf("%s: unable to load Tx buffer, " 687 "error = %d\n", sc->sc_dev.dv_xname, error); 688 IF_PREPEND(&ifp->if_snd, m0); 689 break; 690 } 691 } 692 693 /* Initialize the fraglist. */ 694 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 695 tbd->tbd_d[seg].tb_addr = 696 dmamap->dm_segs[seg].ds_addr; 697 tbd->tbd_d[seg].tb_size = 698 dmamap->dm_segs[seg].ds_len; 699 } 700 701 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 702 703 /* Sync the DMA map. */ 704 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 705 BUS_DMASYNC_PREWRITE); 706 707 /* 708 * Store a pointer to the packet so we can free it later. 709 */ 710 txs->txs_mbuf = m0; 711 712 /* 713 * Initialize the transmit descriptor. 714 */ 715 txd->cb_status = 0; 716 txd->cb_command = 717 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF; 718 txd->tx_threshold = tx_threshold; 719 txd->tbd_number = dmamap->dm_nsegs; 720 721 FXP_CDTXSYNC(sc, nexttx, 722 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 723 724 /* Advance the tx pointer. */ 725 sc->sc_txpending++; 726 sc->sc_txlast = nexttx; 727 728 #if NBPFILTER > 0 729 /* 730 * Pass packet to bpf if there is a listener. 731 */ 732 if (ifp->if_bpf) 733 bpf_mtap(ifp->if_bpf, m0); 734 #endif 735 } 736 737 if (sc->sc_txpending == FXP_NTXCB) { 738 /* No more slots; notify upper layer. */ 739 ifp->if_flags |= IFF_OACTIVE; 740 } 741 742 if (sc->sc_txpending != opending) { 743 /* 744 * We enqueued packets. If the transmitter was idle, 745 * reset the txdirty pointer. 746 */ 747 if (opending == 0) 748 sc->sc_txdirty = FXP_NEXTTX(lasttx); 749 750 /* 751 * Cause the chip to interrupt and suspend command 752 * processing once the last packet we've enqueued 753 * has been transmitted. 754 */ 755 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 756 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S; 757 FXP_CDTXSYNC(sc, sc->sc_txlast, 758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 759 760 /* 761 * The entire packet chain is set up. Clear the suspend bit 762 * on the command prior to the first packet we set up. 763 */ 764 FXP_CDTXSYNC(sc, lasttx, 765 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 766 FXP_CDTX(sc, lasttx)->cb_command &= ~FXP_CB_COMMAND_S; 767 FXP_CDTXSYNC(sc, lasttx, 768 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 769 770 /* 771 * Issue a Resume command in case the chip was suspended. 772 */ 773 fxp_scb_wait(sc); 774 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 775 776 /* Set a watchdog timer in case the chip flakes out. */ 777 ifp->if_timer = 5; 778 } 779 } 780 781 /* 782 * Process interface interrupts. 783 */ 784 int 785 fxp_intr(arg) 786 void *arg; 787 { 788 struct fxp_softc *sc = arg; 789 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 790 struct fxp_cb_tx *txd; 791 struct fxp_txsoft *txs; 792 struct mbuf *m, *m0; 793 bus_dmamap_t rxmap; 794 struct fxp_rfa *rfa; 795 struct ether_header *eh; 796 int i, claimed = 0; 797 u_int16_t len; 798 u_int8_t statack; 799 800 /* 801 * If the interface isn't running, don't try to 802 * service the interrupt.. just ack it and bail. 803 */ 804 if ((ifp->if_flags & IFF_RUNNING) == 0) { 805 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 806 if (statack) { 807 claimed = 1; 808 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 809 } 810 return claimed; 811 } 812 813 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 814 claimed = 1; 815 816 /* 817 * First ACK all the interrupts in this pass. 818 */ 819 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 820 821 /* 822 * Process receiver interrupts. If a no-resource (RNR) 823 * condition exists, get whatever packets we can and 824 * re-start the receiver. 825 */ 826 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 827 rcvloop: 828 m = sc->sc_rxq.ifq_head; 829 rfa = FXP_MTORFA(m); 830 rxmap = M_GETCTX(m, bus_dmamap_t); 831 832 FXP_RFASYNC(sc, m, 833 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 834 835 if ((rfa->rfa_status & FXP_RFA_STATUS_C) == 0) { 836 /* 837 * We have processed all of the 838 * receive buffers. 839 */ 840 goto do_transmit; 841 } 842 843 IF_DEQUEUE(&sc->sc_rxq, m); 844 845 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 846 847 len = rfa->actual_size & (m->m_ext.ext_size - 1); 848 849 if (len < sizeof(struct ether_header)) { 850 /* 851 * Runt packet; drop it now. 852 */ 853 FXP_INIT_RFABUF(sc, m); 854 goto rcvloop; 855 } 856 857 /* 858 * If the packet is small enough to fit in a 859 * single header mbuf, allocate one and copy 860 * the data into it. This greatly reduces 861 * memory consumption when we receive lots 862 * of small packets. 863 * 864 * Otherwise, we add a new buffer to the receive 865 * chain. If this fails, we drop the packet and 866 * recycle the old buffer. 867 */ 868 if (fxp_copy_small != 0 && len <= MHLEN) { 869 MGETHDR(m0, M_DONTWAIT, MT_DATA); 870 if (m == NULL) 871 goto dropit; 872 memcpy(mtod(m0, caddr_t), 873 mtod(m, caddr_t), len); 874 FXP_INIT_RFABUF(sc, m); 875 m = m0; 876 } else { 877 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 878 dropit: 879 ifp->if_ierrors++; 880 FXP_INIT_RFABUF(sc, m); 881 goto rcvloop; 882 } 883 } 884 885 m->m_pkthdr.rcvif = ifp; 886 m->m_pkthdr.len = m->m_len = len; 887 eh = mtod(m, struct ether_header *); 888 889 #if NBPFILTER > 0 890 /* 891 * Pass this up to any BPF listeners, but only 892 * pass it up the stack it its for us. 893 */ 894 if (ifp->if_bpf) { 895 bpf_mtap(ifp->if_bpf, m); 896 897 if ((ifp->if_flags & IFF_PROMISC) != 0 && 898 (rfa->rfa_status & 899 FXP_RFA_STATUS_IAMATCH) != 0 && 900 (eh->ether_dhost[0] & 1) == 0) { 901 m_freem(m); 902 goto rcvloop; 903 } 904 } 905 #endif /* NBPFILTER > 0 */ 906 907 /* Pass it on. */ 908 (*ifp->if_input)(ifp, m); 909 goto rcvloop; 910 } 911 912 do_transmit: 913 if (statack & FXP_SCB_STATACK_RNR) { 914 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 915 fxp_scb_wait(sc); 916 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 917 rxmap->dm_segs[0].ds_addr + 918 RFA_ALIGNMENT_FUDGE); 919 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 920 FXP_SCB_COMMAND_RU_START); 921 } 922 923 /* 924 * Free any finished transmit mbuf chains. 925 */ 926 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 927 ifp->if_flags &= ~IFF_OACTIVE; 928 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 929 i = FXP_NEXTTX(i), sc->sc_txpending--) { 930 txd = FXP_CDTX(sc, i); 931 txs = FXP_DSTX(sc, i); 932 933 FXP_CDTXSYNC(sc, i, 934 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 935 936 if ((txd->cb_status & FXP_CB_STATUS_C) == 0) 937 break; 938 939 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 940 941 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 942 0, txs->txs_dmamap->dm_mapsize, 943 BUS_DMASYNC_POSTWRITE); 944 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 945 m_freem(txs->txs_mbuf); 946 txs->txs_mbuf = NULL; 947 } 948 949 /* Update the dirty transmit buffer pointer. */ 950 sc->sc_txdirty = i; 951 952 /* 953 * Cancel the watchdog timer if there are no pending 954 * transmissions. 955 */ 956 if (sc->sc_txpending == 0) { 957 ifp->if_timer = 0; 958 959 /* 960 * If we want a re-init, do that now. 961 */ 962 if (sc->sc_flags & FXPF_WANTINIT) 963 (void) fxp_init(sc); 964 } 965 966 /* 967 * Try to get more packets going. 968 */ 969 fxp_start(ifp); 970 } 971 } 972 973 #if NRND > 0 974 if (claimed) 975 rnd_add_uint32(&sc->rnd_source, statack); 976 #endif 977 return (claimed); 978 } 979 980 /* 981 * Update packet in/out/collision statistics. The i82557 doesn't 982 * allow you to access these counters without doing a fairly 983 * expensive DMA to get _all_ of the statistics it maintains, so 984 * we do this operation here only once per second. The statistics 985 * counters in the kernel are updated from the previous dump-stats 986 * DMA and then a new dump-stats DMA is started. The on-chip 987 * counters are zeroed when the DMA completes. If we can't start 988 * the DMA immediately, we don't wait - we just prepare to read 989 * them again next time. 990 */ 991 void 992 fxp_tick(arg) 993 void *arg; 994 { 995 struct fxp_softc *sc = arg; 996 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 997 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 998 int s; 999 1000 s = splnet(); 1001 1002 ifp->if_opackets += sp->tx_good; 1003 ifp->if_collisions += sp->tx_total_collisions; 1004 if (sp->rx_good) { 1005 ifp->if_ipackets += sp->rx_good; 1006 sc->sc_rxidle = 0; 1007 } else { 1008 sc->sc_rxidle++; 1009 } 1010 ifp->if_ierrors += 1011 sp->rx_crc_errors + 1012 sp->rx_alignment_errors + 1013 sp->rx_rnr_errors + 1014 sp->rx_overrun_errors; 1015 /* 1016 * If any transmit underruns occured, bump up the transmit 1017 * threshold by another 512 bytes (64 * 8). 1018 */ 1019 if (sp->tx_underruns) { 1020 ifp->if_oerrors += sp->tx_underruns; 1021 if (tx_threshold < 192) 1022 tx_threshold += 64; 1023 } 1024 1025 /* 1026 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1027 * then assume the receiver has locked up and attempt to clear 1028 * the condition by reprogramming the multicast filter (actually, 1029 * resetting the interface). This is a work-around for a bug in 1030 * the 82557 where the receiver locks up if it gets certain types 1031 * of garbage in the syncronization bits prior to the packet header. 1032 * This bug is supposed to only occur in 10Mbps mode, but has been 1033 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1034 * speed transition). 1035 */ 1036 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1037 (void) fxp_init(sc); 1038 splx(s); 1039 return; 1040 } 1041 /* 1042 * If there is no pending command, start another stats 1043 * dump. Otherwise punt for now. 1044 */ 1045 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1046 /* 1047 * Start another stats dump. 1048 */ 1049 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1050 FXP_SCB_COMMAND_CU_DUMPRESET); 1051 } else { 1052 /* 1053 * A previous command is still waiting to be accepted. 1054 * Just zero our copy of the stats and wait for the 1055 * next timer event to update them. 1056 */ 1057 sp->tx_good = 0; 1058 sp->tx_underruns = 0; 1059 sp->tx_total_collisions = 0; 1060 1061 sp->rx_good = 0; 1062 sp->rx_crc_errors = 0; 1063 sp->rx_alignment_errors = 0; 1064 sp->rx_rnr_errors = 0; 1065 sp->rx_overrun_errors = 0; 1066 } 1067 1068 if (sc->sc_flags & FXPF_MII) { 1069 /* Tick the MII clock. */ 1070 mii_tick(&sc->sc_mii); 1071 } 1072 1073 splx(s); 1074 1075 /* 1076 * Schedule another timeout one second from now. 1077 */ 1078 timeout(fxp_tick, sc, hz); 1079 } 1080 1081 /* 1082 * Drain the receive queue. 1083 */ 1084 void 1085 fxp_rxdrain(sc) 1086 struct fxp_softc *sc; 1087 { 1088 bus_dmamap_t rxmap; 1089 struct mbuf *m; 1090 1091 for (;;) { 1092 IF_DEQUEUE(&sc->sc_rxq, m); 1093 if (m == NULL) 1094 break; 1095 rxmap = M_GETCTX(m, bus_dmamap_t); 1096 bus_dmamap_unload(sc->sc_dmat, rxmap); 1097 FXP_RXMAP_PUT(sc, rxmap); 1098 m_freem(m); 1099 } 1100 } 1101 1102 /* 1103 * Stop the interface. Cancels the statistics updater and resets 1104 * the interface. 1105 */ 1106 void 1107 fxp_stop(sc, drain) 1108 struct fxp_softc *sc; 1109 int drain; 1110 { 1111 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1112 struct fxp_txsoft *txs; 1113 int i; 1114 1115 /* 1116 * Turn down interface (done early to avoid bad interactions 1117 * between panics, shutdown hooks, and the watchdog timer) 1118 */ 1119 ifp->if_timer = 0; 1120 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1121 1122 /* 1123 * Cancel stats updater. 1124 */ 1125 untimeout(fxp_tick, sc); 1126 1127 /* 1128 * Issue software reset 1129 */ 1130 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1131 DELAY(10); 1132 1133 /* 1134 * Release any xmit buffers. 1135 */ 1136 for (i = 0; i < FXP_NTXCB; i++) { 1137 txs = FXP_DSTX(sc, i); 1138 if (txs->txs_mbuf != NULL) { 1139 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1140 m_freem(txs->txs_mbuf); 1141 txs->txs_mbuf = NULL; 1142 } 1143 } 1144 sc->sc_txpending = 0; 1145 1146 if (drain) { 1147 /* 1148 * Release the receive buffers. 1149 */ 1150 fxp_rxdrain(sc); 1151 } 1152 1153 } 1154 1155 /* 1156 * Watchdog/transmission transmit timeout handler. Called when a 1157 * transmission is started on the interface, but no interrupt is 1158 * received before the timeout. This usually indicates that the 1159 * card has wedged for some reason. 1160 */ 1161 void 1162 fxp_watchdog(ifp) 1163 struct ifnet *ifp; 1164 { 1165 struct fxp_softc *sc = ifp->if_softc; 1166 1167 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1168 ifp->if_oerrors++; 1169 1170 (void) fxp_init(sc); 1171 } 1172 1173 /* 1174 * Initialize the interface. Must be called at splnet(). 1175 */ 1176 int 1177 fxp_init(sc) 1178 struct fxp_softc *sc; 1179 { 1180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1181 struct fxp_cb_config *cbp; 1182 struct fxp_cb_ias *cb_ias; 1183 struct fxp_cb_tx *txd; 1184 bus_dmamap_t rxmap; 1185 int i, prm, allm, error = 0; 1186 1187 /* 1188 * Cancel any pending I/O 1189 */ 1190 fxp_stop(sc, 0); 1191 1192 sc->sc_flags = 0; 1193 1194 /* 1195 * Initialize base of CBL and RFA memory. Loading with zero 1196 * sets it up for regular linear addressing. 1197 */ 1198 fxp_scb_wait(sc); 1199 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1200 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1201 1202 fxp_scb_wait(sc); 1203 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1204 1205 /* 1206 * Initialize the multicast filter. Do this now, since we might 1207 * have to setup the config block differently. 1208 */ 1209 fxp_mc_setup(sc); 1210 1211 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1212 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1213 1214 /* 1215 * Initialize base of dump-stats buffer. 1216 */ 1217 fxp_scb_wait(sc); 1218 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1219 sc->sc_cddma + FXP_CDSTATSOFF); 1220 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1221 1222 cbp = &sc->sc_control_data->fcd_configcb; 1223 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1224 1225 /* 1226 * This copy is kind of disgusting, but there are a bunch of must be 1227 * zero and must be one bits in this structure and this is the easiest 1228 * way to initialize them all to proper values. 1229 */ 1230 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1231 1232 cbp->cb_status = 0; 1233 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1234 cbp->link_addr = -1; /* (no) next command */ 1235 cbp->byte_count = 22; /* (22) bytes to config */ 1236 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1237 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1238 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1239 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1240 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1241 cbp->dma_bce = 0; /* (disable) dma max counters */ 1242 cbp->late_scb = 0; /* (don't) defer SCB update */ 1243 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1244 cbp->ci_int = 1; /* interrupt on CU idle */ 1245 cbp->save_bf = prm; /* save bad frames */ 1246 cbp->disc_short_rx = !prm; /* discard short packets */ 1247 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1248 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1249 cbp->nsai = 1; /* (don't) disable source addr insert */ 1250 cbp->preamble_length = 2; /* (7 byte) preamble */ 1251 cbp->loopback = 0; /* (don't) loopback */ 1252 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1253 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1254 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1255 cbp->promiscuous = prm; /* promiscuous mode */ 1256 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1257 cbp->crscdt = 0; /* (CRS only) */ 1258 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1259 cbp->padding = 1; /* (do) pad short tx packets */ 1260 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1261 cbp->force_fdx = 0; /* (don't) force full duplex */ 1262 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1263 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1264 cbp->mc_all = allm; /* accept all multicasts */ 1265 1266 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1267 1268 /* 1269 * Start the config command/DMA. 1270 */ 1271 fxp_scb_wait(sc); 1272 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1273 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1274 /* ...and wait for it to complete. */ 1275 do { 1276 FXP_CDCONFIGSYNC(sc, 1277 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1278 } while ((cbp->cb_status & FXP_CB_STATUS_C) == 0); 1279 1280 /* 1281 * Initialize the station address. 1282 */ 1283 cb_ias = &sc->sc_control_data->fcd_iascb; 1284 cb_ias->cb_status = 0; 1285 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1286 cb_ias->link_addr = -1; 1287 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1288 1289 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1290 1291 /* 1292 * Start the IAS (Individual Address Setup) command/DMA. 1293 */ 1294 fxp_scb_wait(sc); 1295 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1296 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1297 /* ...and wait for it to complete. */ 1298 do { 1299 FXP_CDIASSYNC(sc, 1300 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1301 } while ((cb_ias->cb_status & FXP_CB_STATUS_C) == 0); 1302 1303 /* 1304 * Initialize the transmit descriptor ring. txlast is initialized 1305 * to the end of the list so that it will wrap around to the first 1306 * descriptor when the first packet is transmitted. 1307 */ 1308 for (i = 0; i < FXP_NTXCB; i++) { 1309 txd = FXP_CDTX(sc, i); 1310 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1311 txd->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1312 txd->tbd_array_addr = FXP_CDTBDADDR(sc, i); 1313 txd->link_addr = FXP_CDTXADDR(sc, FXP_NEXTTX(i)); 1314 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1315 } 1316 sc->sc_txpending = 0; 1317 sc->sc_txdirty = 0; 1318 sc->sc_txlast = FXP_NTXCB - 1; 1319 1320 /* 1321 * Initialize the receive buffer list. 1322 */ 1323 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1324 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1325 rxmap = FXP_RXMAP_GET(sc); 1326 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1327 printf("%s: unable to allocate or map rx " 1328 "buffer %d, error = %d\n", 1329 sc->sc_dev.dv_xname, 1330 sc->sc_rxq.ifq_len, error); 1331 /* 1332 * XXX Should attempt to run with fewer receive 1333 * XXX buffers instead of just failing. 1334 */ 1335 FXP_RXMAP_PUT(sc, rxmap); 1336 fxp_rxdrain(sc); 1337 goto out; 1338 } 1339 } 1340 sc->sc_rxidle = 0; 1341 1342 /* 1343 * Give the transmit ring to the chip. We do this by pointing 1344 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1345 * issuing a start command. It will execute the NOP and then 1346 * suspend, pointing at the first descriptor. 1347 */ 1348 fxp_scb_wait(sc); 1349 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1350 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1351 1352 /* 1353 * Initialize receiver buffer area - RFA. 1354 */ 1355 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1356 fxp_scb_wait(sc); 1357 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1358 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1359 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1360 1361 if (sc->sc_flags & FXPF_MII) { 1362 /* 1363 * Set current media. 1364 */ 1365 mii_mediachg(&sc->sc_mii); 1366 } 1367 1368 /* 1369 * ...all done! 1370 */ 1371 ifp->if_flags |= IFF_RUNNING; 1372 ifp->if_flags &= ~IFF_OACTIVE; 1373 1374 /* 1375 * Start the one second timer. 1376 */ 1377 timeout(fxp_tick, sc, hz); 1378 1379 /* 1380 * Attempt to start output on the interface. 1381 */ 1382 fxp_start(ifp); 1383 1384 out: 1385 if (error) 1386 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1387 return (error); 1388 } 1389 1390 /* 1391 * Change media according to request. 1392 */ 1393 int 1394 fxp_mii_mediachange(ifp) 1395 struct ifnet *ifp; 1396 { 1397 struct fxp_softc *sc = ifp->if_softc; 1398 1399 if (ifp->if_flags & IFF_UP) 1400 mii_mediachg(&sc->sc_mii); 1401 return (0); 1402 } 1403 1404 /* 1405 * Notify the world which media we're using. 1406 */ 1407 void 1408 fxp_mii_mediastatus(ifp, ifmr) 1409 struct ifnet *ifp; 1410 struct ifmediareq *ifmr; 1411 { 1412 struct fxp_softc *sc = ifp->if_softc; 1413 1414 if(sc->sc_enabled == 0) { 1415 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1416 ifmr->ifm_status = 0; 1417 return; 1418 } 1419 1420 mii_pollstat(&sc->sc_mii); 1421 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1422 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1423 } 1424 1425 int 1426 fxp_80c24_mediachange(ifp) 1427 struct ifnet *ifp; 1428 { 1429 1430 /* Nothing to do here. */ 1431 return (0); 1432 } 1433 1434 void 1435 fxp_80c24_mediastatus(ifp, ifmr) 1436 struct ifnet *ifp; 1437 struct ifmediareq *ifmr; 1438 { 1439 struct fxp_softc *sc = ifp->if_softc; 1440 1441 /* 1442 * Media is currently-selected media. We cannot determine 1443 * the link status. 1444 */ 1445 ifmr->ifm_status = 0; 1446 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1447 } 1448 1449 /* 1450 * Add a buffer to the end of the RFA buffer list. 1451 * Return 0 if successful, error code on failure. 1452 * 1453 * The RFA struct is stuck at the beginning of mbuf cluster and the 1454 * data pointer is fixed up to point just past it. 1455 */ 1456 int 1457 fxp_add_rfabuf(sc, rxmap, unload) 1458 struct fxp_softc *sc; 1459 bus_dmamap_t rxmap; 1460 int unload; 1461 { 1462 struct mbuf *m; 1463 int error; 1464 1465 MGETHDR(m, M_DONTWAIT, MT_DATA); 1466 if (m == NULL) 1467 return (ENOBUFS); 1468 1469 MCLGET(m, M_DONTWAIT); 1470 if ((m->m_flags & M_EXT) == 0) { 1471 m_freem(m); 1472 return (ENOBUFS); 1473 } 1474 1475 if (unload) 1476 bus_dmamap_unload(sc->sc_dmat, rxmap); 1477 1478 M_SETCTX(m, rxmap); 1479 1480 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1481 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1482 if (error) { 1483 printf("%s: can't load rx DMA map %d, error = %d\n", 1484 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1485 panic("fxp_add_rfabuf"); /* XXX */ 1486 } 1487 1488 FXP_INIT_RFABUF(sc, m); 1489 1490 return (0); 1491 } 1492 1493 volatile int 1494 fxp_mdi_read(self, phy, reg) 1495 struct device *self; 1496 int phy; 1497 int reg; 1498 { 1499 struct fxp_softc *sc = (struct fxp_softc *)self; 1500 int count = 10000; 1501 int value; 1502 1503 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1504 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1505 1506 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1507 && count--) 1508 DELAY(10); 1509 1510 if (count <= 0) 1511 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1512 1513 return (value & 0xffff); 1514 } 1515 1516 void 1517 fxp_statchg(self) 1518 struct device *self; 1519 { 1520 1521 /* XXX Update ifp->if_baudrate */ 1522 } 1523 1524 void 1525 fxp_mdi_write(self, phy, reg, value) 1526 struct device *self; 1527 int phy; 1528 int reg; 1529 int value; 1530 { 1531 struct fxp_softc *sc = (struct fxp_softc *)self; 1532 int count = 10000; 1533 1534 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1535 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1536 (value & 0xffff)); 1537 1538 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1539 count--) 1540 DELAY(10); 1541 1542 if (count <= 0) 1543 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1544 } 1545 1546 int 1547 fxp_ioctl(ifp, command, data) 1548 struct ifnet *ifp; 1549 u_long command; 1550 caddr_t data; 1551 { 1552 struct fxp_softc *sc = ifp->if_softc; 1553 struct ifreq *ifr = (struct ifreq *)data; 1554 struct ifaddr *ifa = (struct ifaddr *)data; 1555 int s, error = 0; 1556 1557 s = splnet(); 1558 1559 switch (command) { 1560 case SIOCSIFADDR: 1561 if ((error = fxp_enable(sc)) != 0) 1562 break; 1563 ifp->if_flags |= IFF_UP; 1564 1565 switch (ifa->ifa_addr->sa_family) { 1566 #ifdef INET 1567 case AF_INET: 1568 if ((error = fxp_init(sc)) != 0) 1569 break; 1570 arp_ifinit(ifp, ifa); 1571 break; 1572 #endif /* INET */ 1573 #ifdef NS 1574 case AF_NS: 1575 { 1576 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1577 1578 if (ns_nullhost(*ina)) 1579 ina->x_host = *(union ns_host *) 1580 LLADDR(ifp->if_sadl); 1581 else 1582 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1583 ifp->if_addrlen); 1584 /* Set new address. */ 1585 error = fxp_init(sc); 1586 break; 1587 } 1588 #endif /* NS */ 1589 default: 1590 error = fxp_init(sc); 1591 break; 1592 } 1593 break; 1594 1595 case SIOCSIFMTU: 1596 if (ifr->ifr_mtu > ETHERMTU) 1597 error = EINVAL; 1598 else 1599 ifp->if_mtu = ifr->ifr_mtu; 1600 break; 1601 1602 case SIOCSIFFLAGS: 1603 if ((ifp->if_flags & IFF_UP) == 0 && 1604 (ifp->if_flags & IFF_RUNNING) != 0) { 1605 /* 1606 * If interface is marked down and it is running, then 1607 * stop it. 1608 */ 1609 fxp_stop(sc, 1); 1610 fxp_disable(sc); 1611 } else if ((ifp->if_flags & IFF_UP) != 0 && 1612 (ifp->if_flags & IFF_RUNNING) == 0) { 1613 /* 1614 * If interface is marked up and it is stopped, then 1615 * start it. 1616 */ 1617 if((error = fxp_enable(sc)) != 0) 1618 break; 1619 error = fxp_init(sc); 1620 } else if ((ifp->if_flags & IFF_UP) != 0) { 1621 /* 1622 * Reset the interface to pick up change in any other 1623 * flags that affect the hardware state. 1624 */ 1625 if((error = fxp_enable(sc)) != 0) 1626 break; 1627 error = fxp_init(sc); 1628 } 1629 break; 1630 1631 case SIOCADDMULTI: 1632 case SIOCDELMULTI: 1633 if(sc->sc_enabled == 0) { 1634 error = EIO; 1635 break; 1636 } 1637 error = (command == SIOCADDMULTI) ? 1638 ether_addmulti(ifr, &sc->sc_ethercom) : 1639 ether_delmulti(ifr, &sc->sc_ethercom); 1640 1641 if (error == ENETRESET) { 1642 /* 1643 * Multicast list has changed; set the hardware 1644 * filter accordingly. 1645 */ 1646 if (sc->sc_txpending) { 1647 sc->sc_flags |= FXPF_WANTINIT; 1648 error = 0; 1649 } else 1650 error = fxp_init(sc); 1651 } 1652 break; 1653 1654 case SIOCSIFMEDIA: 1655 case SIOCGIFMEDIA: 1656 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1657 break; 1658 1659 default: 1660 error = EINVAL; 1661 break; 1662 } 1663 1664 splx(s); 1665 return (error); 1666 } 1667 1668 /* 1669 * Program the multicast filter. 1670 * 1671 * This function must be called at splnet(). 1672 */ 1673 void 1674 fxp_mc_setup(sc) 1675 struct fxp_softc *sc; 1676 { 1677 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1678 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1679 struct ethercom *ec = &sc->sc_ethercom; 1680 struct ether_multi *enm; 1681 struct ether_multistep step; 1682 int nmcasts; 1683 1684 #ifdef DIAGNOSTIC 1685 if (sc->sc_txpending) 1686 panic("fxp_mc_setup: pending transmissions"); 1687 #endif 1688 1689 ifp->if_flags &= ~IFF_ALLMULTI; 1690 1691 /* 1692 * Initialize multicast setup descriptor. 1693 */ 1694 nmcasts = 0; 1695 ETHER_FIRST_MULTI(step, ec, enm); 1696 while (enm != NULL) { 1697 /* 1698 * Check for too many multicast addresses or if we're 1699 * listening to a range. Either way, we simply have 1700 * to accept all multicasts. 1701 */ 1702 if (nmcasts >= MAXMCADDR || 1703 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1704 ETHER_ADDR_LEN) != 0) { 1705 /* 1706 * Callers of this function must do the 1707 * right thing with this. If we're called 1708 * from outside fxp_init(), the caller must 1709 * detect if the state if IFF_ALLMULTI changes. 1710 * If it does, the caller must then call 1711 * fxp_init(), since allmulti is handled by 1712 * the config block. 1713 */ 1714 ifp->if_flags |= IFF_ALLMULTI; 1715 return; 1716 } 1717 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1718 ETHER_ADDR_LEN); 1719 nmcasts++; 1720 ETHER_NEXT_MULTI(step, enm); 1721 } 1722 1723 mcsp->cb_status = 0; 1724 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1725 mcsp->link_addr = FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast)); 1726 mcsp->mc_cnt = nmcasts * ETHER_ADDR_LEN; 1727 1728 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1729 1730 /* 1731 * Wait until the command unit is not active. This should never 1732 * happen since nothing is queued, but make sure anyway. 1733 */ 1734 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1735 FXP_SCB_CUS_ACTIVE) 1736 /* nothing */ ; 1737 1738 /* 1739 * Start the multicast setup command/DMA. 1740 */ 1741 fxp_scb_wait(sc); 1742 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1743 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1744 1745 /* ...and wait for it to complete. */ 1746 do { 1747 FXP_CDMCSSYNC(sc, 1748 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1749 } while ((mcsp->cb_status & FXP_CB_STATUS_C) == 0); 1750 } 1751 1752 int 1753 fxp_enable(sc) 1754 struct fxp_softc *sc; 1755 { 1756 1757 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1758 if ((*sc->sc_enable)(sc) != 0) { 1759 printf("%s: device enable failed\n", 1760 sc->sc_dev.dv_xname); 1761 return (EIO); 1762 } 1763 } 1764 1765 sc->sc_enabled = 1; 1766 1767 return 0; 1768 } 1769 1770 void 1771 fxp_disable(sc) 1772 struct fxp_softc *sc; 1773 { 1774 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1775 (*sc->sc_disable)(sc); 1776 sc->sc_enabled = 0; 1777 } 1778 } 1779
Indexes created Mon Sep 29 21:09:56 GMT 2025