i82557.c revision 1.104.2.1
1 /* $NetBSD: i82557.c,v 1.104.2.1 2008/02/18 21:05:41 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.104.2.1 2008/02/18 21:05:41 mjf Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, void *); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 void fxp_shutdown(void *); 210 void fxp_power(int, void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 log(LOG_WARNING, 248 "%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 249 } 250 251 /* 252 * Submit a command to the i82557. 253 */ 254 static inline void 255 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 256 { 257 258 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 259 } 260 261 /* 262 * Finish attaching an i82557 interface. Called by bus-specific front-end. 263 */ 264 void 265 fxp_attach(struct fxp_softc *sc) 266 { 267 u_int8_t enaddr[ETHER_ADDR_LEN]; 268 struct ifnet *ifp; 269 bus_dma_segment_t seg; 270 int rseg, i, error; 271 struct fxp_phytype *fp; 272 273 callout_init(&sc->sc_callout, 0); 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Enable use of extended RFDs and TCBs for 82550 285 * and later chips. Note: we need extended TXCB support 286 * too, but that's already enabled by the code above. 287 * Be careful to do this only on the right devices. 288 */ 289 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 290 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 291 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 292 } else { 293 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 294 } 295 296 sc->sc_rfa_size = 297 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 298 299 /* 300 * Allocate the control data structures, and create and load the 301 * DMA map for it. 302 */ 303 if ((error = bus_dmamem_alloc(sc->sc_dmat, 304 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 305 0)) != 0) { 306 aprint_error( 307 "%s: unable to allocate control data, error = %d\n", 308 sc->sc_dev.dv_xname, error); 309 goto fail_0; 310 } 311 312 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 313 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 314 BUS_DMA_COHERENT)) != 0) { 315 aprint_error("%s: unable to map control data, error = %d\n", 316 sc->sc_dev.dv_xname, error); 317 goto fail_1; 318 } 319 sc->sc_cdseg = seg; 320 sc->sc_cdnseg = rseg; 321 322 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 323 324 if ((error = bus_dmamap_create(sc->sc_dmat, 325 sizeof(struct fxp_control_data), 1, 326 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 327 aprint_error("%s: unable to create control data DMA map, " 328 "error = %d\n", sc->sc_dev.dv_xname, error); 329 goto fail_2; 330 } 331 332 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 333 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 334 0)) != 0) { 335 aprint_error( 336 "%s: can't load control data DMA map, error = %d\n", 337 sc->sc_dev.dv_xname, error); 338 goto fail_3; 339 } 340 341 /* 342 * Create the transmit buffer DMA maps. 343 */ 344 for (i = 0; i < FXP_NTXCB; i++) { 345 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 346 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 347 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 348 aprint_error("%s: unable to create tx DMA map %d, " 349 "error = %d\n", sc->sc_dev.dv_xname, i, error); 350 goto fail_4; 351 } 352 } 353 354 /* 355 * Create the receive buffer DMA maps. 356 */ 357 for (i = 0; i < FXP_NRFABUFS; i++) { 358 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 359 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 360 aprint_error("%s: unable to create rx DMA map %d, " 361 "error = %d\n", sc->sc_dev.dv_xname, i, error); 362 goto fail_5; 363 } 364 } 365 366 /* Initialize MAC address and media structures. */ 367 fxp_get_info(sc, enaddr); 368 369 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 370 ether_sprintf(enaddr)); 371 372 ifp = &sc->sc_ethercom.ec_if; 373 374 /* 375 * Get info about our media interface, and initialize it. Note 376 * the table terminates itself with a phy of -1, indicating 377 * that we're using MII. 378 */ 379 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 380 if (fp->fp_phy == sc->phy_primary_device) 381 break; 382 (*fp->fp_init)(sc); 383 384 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 385 ifp->if_softc = sc; 386 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 387 ifp->if_ioctl = fxp_ioctl; 388 ifp->if_start = fxp_start; 389 ifp->if_watchdog = fxp_watchdog; 390 ifp->if_init = fxp_init; 391 ifp->if_stop = fxp_stop; 392 IFQ_SET_READY(&ifp->if_snd); 393 394 if (sc->sc_flags & FXPF_IPCB) { 395 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 396 /* 397 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 398 * at least, on i82550 rev.12. 399 * specifically, it doesn't calculate ipv4 checksum correctly 400 * when sending 20 byte ipv4 header + 1 or 2 byte data. 401 * FreeBSD driver has related comments. 402 */ 403 ifp->if_capabilities = 404 IFCAP_CSUM_IPv4_Rx | 405 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 406 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 407 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 408 } 409 410 /* 411 * We can support 802.1Q VLAN-sized frames. 412 */ 413 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 414 415 /* 416 * Attach the interface. 417 */ 418 if_attach(ifp); 419 ether_ifattach(ifp, enaddr); 420 #if NRND > 0 421 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 422 RND_TYPE_NET, 0); 423 #endif 424 425 #ifdef FXP_EVENT_COUNTERS 426 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 427 NULL, sc->sc_dev.dv_xname, "txstall"); 428 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 429 NULL, sc->sc_dev.dv_xname, "txintr"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 431 NULL, sc->sc_dev.dv_xname, "rxintr"); 432 if (sc->sc_rev >= FXP_REV_82558_A4) { 433 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 434 NULL, sc->sc_dev.dv_xname, "txpause"); 435 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 436 NULL, sc->sc_dev.dv_xname, "rxpause"); 437 } 438 #endif /* FXP_EVENT_COUNTERS */ 439 440 /* 441 * Add shutdown hook so that DMA is disabled prior to reboot. Not 442 * doing do could allow DMA to corrupt kernel memory during the 443 * reboot before the driver initializes. 444 */ 445 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 446 if (sc->sc_sdhook == NULL) 447 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 448 sc->sc_dev.dv_xname); 449 /* 450 * Add suspend hook, for similar reasons.. 451 */ 452 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 453 fxp_power, sc); 454 if (sc->sc_powerhook == NULL) 455 aprint_error("%s: WARNING: unable to establish power hook\n", 456 sc->sc_dev.dv_xname); 457 458 /* The attach is successful. */ 459 sc->sc_flags |= FXPF_ATTACHED; 460 461 return; 462 463 /* 464 * Free any resources we've allocated during the failed attach 465 * attempt. Do this in reverse order and fall though. 466 */ 467 fail_5: 468 for (i = 0; i < FXP_NRFABUFS; i++) { 469 if (sc->sc_rxmaps[i] != NULL) 470 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 471 } 472 fail_4: 473 for (i = 0; i < FXP_NTXCB; i++) { 474 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 475 bus_dmamap_destroy(sc->sc_dmat, 476 FXP_DSTX(sc, i)->txs_dmamap); 477 } 478 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 479 fail_3: 480 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 481 fail_2: 482 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 483 sizeof(struct fxp_control_data)); 484 fail_1: 485 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 486 fail_0: 487 return; 488 } 489 490 void 491 fxp_mii_initmedia(struct fxp_softc *sc) 492 { 493 int flags; 494 495 sc->sc_flags |= FXPF_MII; 496 497 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 498 sc->sc_mii.mii_readreg = fxp_mdi_read; 499 sc->sc_mii.mii_writereg = fxp_mdi_write; 500 sc->sc_mii.mii_statchg = fxp_statchg; 501 502 sc->sc_ethercom.ec_mii = &sc->sc_mii; 503 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 504 fxp_mii_mediastatus); 505 506 flags = MIIF_NOISOLATE; 507 if (sc->sc_rev >= FXP_REV_82558_A4) 508 flags |= MIIF_DOPAUSE; 509 /* 510 * The i82557 wedges if all of its PHYs are isolated! 511 */ 512 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 513 MII_OFFSET_ANY, flags); 514 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 515 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 516 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 517 } else 518 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 519 } 520 521 void 522 fxp_80c24_initmedia(struct fxp_softc *sc) 523 { 524 525 /* 526 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 527 * doesn't have a programming interface of any sort. The 528 * media is sensed automatically based on how the link partner 529 * is configured. This is, in essence, manual configuration. 530 */ 531 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 532 sc->sc_dev.dv_xname); 533 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 534 fxp_80c24_mediastatus); 535 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 536 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 537 } 538 539 /* 540 * Device shutdown routine. Called at system shutdown after sync. The 541 * main purpose of this routine is to shut off receiver DMA so that 542 * kernel memory doesn't get clobbered during warmboot. 543 */ 544 void 545 fxp_shutdown(void *arg) 546 { 547 struct fxp_softc *sc = arg; 548 549 /* 550 * Since the system's going to halt shortly, don't bother 551 * freeing mbufs. 552 */ 553 fxp_stop(&sc->sc_ethercom.ec_if, 0); 554 } 555 /* 556 * Power handler routine. Called when the system is transitioning 557 * into/out of power save modes. As with fxp_shutdown, the main 558 * purpose of this routine is to shut off receiver DMA so it doesn't 559 * clobber kernel memory at the wrong time. 560 */ 561 void 562 fxp_power(int why, void *arg) 563 { 564 struct fxp_softc *sc = arg; 565 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 566 int s; 567 568 s = splnet(); 569 switch (why) { 570 case PWR_SUSPEND: 571 case PWR_STANDBY: 572 fxp_stop(ifp, 0); 573 break; 574 case PWR_RESUME: 575 if (ifp->if_flags & IFF_UP) 576 fxp_init(ifp); 577 break; 578 case PWR_SOFTSUSPEND: 579 case PWR_SOFTSTANDBY: 580 case PWR_SOFTRESUME: 581 break; 582 } 583 splx(s); 584 } 585 586 /* 587 * Initialize the interface media. 588 */ 589 void 590 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 591 { 592 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 593 594 /* 595 * Reset to a stable state. 596 */ 597 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 598 DELAY(100); 599 600 sc->sc_eeprom_size = 0; 601 fxp_autosize_eeprom(sc); 602 if (sc->sc_eeprom_size == 0) { 603 aprint_error("%s: failed to detect EEPROM size\n", 604 sc->sc_dev.dv_xname); 605 sc->sc_eeprom_size = 6; /* XXX panic here? */ 606 } 607 #ifdef DEBUG 608 aprint_debug("%s: detected %d word EEPROM\n", 609 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 610 #endif 611 612 /* 613 * Get info about the primary PHY 614 */ 615 fxp_read_eeprom(sc, &data, 6, 1); 616 sc->phy_primary_device = 617 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 618 619 /* 620 * Read MAC address. 621 */ 622 fxp_read_eeprom(sc, myea, 0, 3); 623 enaddr[0] = myea[0] & 0xff; 624 enaddr[1] = myea[0] >> 8; 625 enaddr[2] = myea[1] & 0xff; 626 enaddr[3] = myea[1] >> 8; 627 enaddr[4] = myea[2] & 0xff; 628 enaddr[5] = myea[2] >> 8; 629 630 /* 631 * Systems based on the ICH2/ICH2-M chip from Intel, as well 632 * as some i82559 designs, have a defect where the chip can 633 * cause a PCI protocol violation if it receives a CU_RESUME 634 * command when it is entering the IDLE state. 635 * 636 * The work-around is to disable Dynamic Standby Mode, so that 637 * the chip never deasserts #CLKRUN, and always remains in the 638 * active state. 639 * 640 * Unfortunately, the only way to disable Dynamic Standby is 641 * to frob an EEPROM setting and reboot (the EEPROM setting 642 * is only consulted when the PCI bus comes out of reset). 643 * 644 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 645 */ 646 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 647 fxp_read_eeprom(sc, &data, 10, 1); 648 if (data & 0x02) { /* STB enable */ 649 aprint_error("%s: WARNING: " 650 "Disabling dynamic standby mode in EEPROM " 651 "to work around a\n", 652 sc->sc_dev.dv_xname); 653 aprint_normal( 654 "%s: WARNING: hardware bug. You must reset " 655 "the system before using this\n", 656 sc->sc_dev.dv_xname); 657 aprint_normal("%s: WARNING: interface.\n", 658 sc->sc_dev.dv_xname); 659 data &= ~0x02; 660 fxp_write_eeprom(sc, &data, 10, 1); 661 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 662 sc->sc_dev.dv_xname, data); 663 fxp_eeprom_update_cksum(sc); 664 } 665 } 666 667 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 668 /* Due to false positives we make it conditional on setting link1 */ 669 fxp_read_eeprom(sc, &data, 3, 1); 670 if ((data & 0x03) != 0x03) { 671 aprint_verbose("%s: May need receiver lock-up workaround\n", 672 sc->sc_dev.dv_xname); 673 } 674 } 675 676 static void 677 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 678 { 679 uint16_t reg; 680 int x; 681 682 for (x = 1 << (len - 1); x != 0; x >>= 1) { 683 DELAY(40); 684 if (data & x) 685 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 686 else 687 reg = FXP_EEPROM_EECS; 688 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 689 DELAY(40); 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 691 reg | FXP_EEPROM_EESK); 692 DELAY(40); 693 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 694 } 695 DELAY(40); 696 } 697 698 /* 699 * Figure out EEPROM size. 700 * 701 * 559's can have either 64-word or 256-word EEPROMs, the 558 702 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 703 * talks about the existence of 16 to 256 word EEPROMs. 704 * 705 * The only known sizes are 64 and 256, where the 256 version is used 706 * by CardBus cards to store CIS information. 707 * 708 * The address is shifted in msb-to-lsb, and after the last 709 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 710 * after which follows the actual data. We try to detect this zero, by 711 * probing the data-out bit in the EEPROM control register just after 712 * having shifted in a bit. If the bit is zero, we assume we've 713 * shifted enough address bits. The data-out should be tri-state, 714 * before this, which should translate to a logical one. 715 * 716 * Other ways to do this would be to try to read a register with known 717 * contents with a varying number of address bits, but no such 718 * register seem to be available. The high bits of register 10 are 01 719 * on the 558 and 559, but apparently not on the 557. 720 * 721 * The Linux driver computes a checksum on the EEPROM data, but the 722 * value of this checksum is not very well documented. 723 */ 724 725 void 726 fxp_autosize_eeprom(struct fxp_softc *sc) 727 { 728 int x; 729 730 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 731 DELAY(40); 732 733 /* Shift in read opcode. */ 734 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 735 736 /* 737 * Shift in address, wait for the dummy zero following a correct 738 * address shift. 739 */ 740 for (x = 1; x <= 8; x++) { 741 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 742 DELAY(40); 743 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 744 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 745 DELAY(40); 746 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 747 FXP_EEPROM_EEDO) == 0) 748 break; 749 DELAY(40); 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 751 DELAY(40); 752 } 753 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 754 DELAY(40); 755 if (x != 6 && x != 8) { 756 #ifdef DEBUG 757 printf("%s: strange EEPROM size (%d)\n", 758 sc->sc_dev.dv_xname, 1 << x); 759 #endif 760 } else 761 sc->sc_eeprom_size = x; 762 } 763 764 /* 765 * Read from the serial EEPROM. Basically, you manually shift in 766 * the read opcode (one bit at a time) and then shift in the address, 767 * and then you shift out the data (all of this one bit at a time). 768 * The word size is 16 bits, so you have to provide the address for 769 * every 16 bits of data. 770 */ 771 void 772 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 773 { 774 u_int16_t reg; 775 int i, x; 776 777 for (i = 0; i < words; i++) { 778 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 779 780 /* Shift in read opcode. */ 781 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 782 783 /* Shift in address. */ 784 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 785 786 reg = FXP_EEPROM_EECS; 787 data[i] = 0; 788 789 /* Shift out data. */ 790 for (x = 16; x > 0; x--) { 791 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 792 reg | FXP_EEPROM_EESK); 793 DELAY(40); 794 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 795 FXP_EEPROM_EEDO) 796 data[i] |= (1 << (x - 1)); 797 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 798 DELAY(40); 799 } 800 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 801 DELAY(40); 802 } 803 } 804 805 /* 806 * Write data to the serial EEPROM. 807 */ 808 void 809 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 810 { 811 int i, j; 812 813 for (i = 0; i < words; i++) { 814 /* Erase/write enable. */ 815 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 816 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 817 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 818 sc->sc_eeprom_size); 819 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 820 DELAY(4); 821 822 /* Shift in write opcode, address, data. */ 823 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 824 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 825 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 826 fxp_eeprom_shiftin(sc, data[i], 16); 827 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 828 DELAY(4); 829 830 /* Wait for the EEPROM to finish up. */ 831 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 832 DELAY(4); 833 for (j = 0; j < 1000; j++) { 834 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 835 FXP_EEPROM_EEDO) 836 break; 837 DELAY(50); 838 } 839 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 840 DELAY(4); 841 842 /* Erase/write disable. */ 843 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 844 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 845 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 846 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 847 DELAY(4); 848 } 849 } 850 851 /* 852 * Update the checksum of the EEPROM. 853 */ 854 void 855 fxp_eeprom_update_cksum(struct fxp_softc *sc) 856 { 857 int i; 858 uint16_t data, cksum; 859 860 cksum = 0; 861 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 862 fxp_read_eeprom(sc, &data, i, 1); 863 cksum += data; 864 } 865 i = (1 << sc->sc_eeprom_size) - 1; 866 cksum = 0xbaba - cksum; 867 fxp_read_eeprom(sc, &data, i, 1); 868 fxp_write_eeprom(sc, &cksum, i, 1); 869 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 870 sc->sc_dev.dv_xname, i, data, cksum); 871 } 872 873 /* 874 * Start packet transmission on the interface. 875 */ 876 void 877 fxp_start(struct ifnet *ifp) 878 { 879 struct fxp_softc *sc = ifp->if_softc; 880 struct mbuf *m0, *m; 881 struct fxp_txdesc *txd; 882 struct fxp_txsoft *txs; 883 bus_dmamap_t dmamap; 884 int error, lasttx, nexttx, opending, seg; 885 886 /* 887 * If we want a re-init, bail out now. 888 */ 889 if (sc->sc_flags & FXPF_WANTINIT) { 890 ifp->if_flags |= IFF_OACTIVE; 891 return; 892 } 893 894 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 895 return; 896 897 /* 898 * Remember the previous txpending and the current lasttx. 899 */ 900 opending = sc->sc_txpending; 901 lasttx = sc->sc_txlast; 902 903 /* 904 * Loop through the send queue, setting up transmit descriptors 905 * until we drain the queue, or use up all available transmit 906 * descriptors. 907 */ 908 for (;;) { 909 struct fxp_tbd *tbdp; 910 int csum_flags; 911 912 /* 913 * Grab a packet off the queue. 914 */ 915 IFQ_POLL(&ifp->if_snd, m0); 916 if (m0 == NULL) 917 break; 918 m = NULL; 919 920 if (sc->sc_txpending == FXP_NTXCB) { 921 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 922 break; 923 } 924 925 /* 926 * Get the next available transmit descriptor. 927 */ 928 nexttx = FXP_NEXTTX(sc->sc_txlast); 929 txd = FXP_CDTX(sc, nexttx); 930 txs = FXP_DSTX(sc, nexttx); 931 dmamap = txs->txs_dmamap; 932 933 /* 934 * Load the DMA map. If this fails, the packet either 935 * didn't fit in the allotted number of frags, or we were 936 * short on resources. In this case, we'll copy and try 937 * again. 938 */ 939 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 940 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 941 MGETHDR(m, M_DONTWAIT, MT_DATA); 942 if (m == NULL) { 943 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 944 sc->sc_dev.dv_xname); 945 break; 946 } 947 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 948 if (m0->m_pkthdr.len > MHLEN) { 949 MCLGET(m, M_DONTWAIT); 950 if ((m->m_flags & M_EXT) == 0) { 951 log(LOG_ERR, 952 "%s: unable to allocate Tx " 953 "cluster\n", sc->sc_dev.dv_xname); 954 m_freem(m); 955 break; 956 } 957 } 958 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 959 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 960 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 961 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 962 if (error) { 963 log(LOG_ERR, "%s: unable to load Tx buffer, " 964 "error = %d\n", sc->sc_dev.dv_xname, error); 965 break; 966 } 967 } 968 969 IFQ_DEQUEUE(&ifp->if_snd, m0); 970 csum_flags = m0->m_pkthdr.csum_flags; 971 if (m != NULL) { 972 m_freem(m0); 973 m0 = m; 974 } 975 976 /* Initialize the fraglist. */ 977 tbdp = txd->txd_tbd; 978 if (sc->sc_flags & FXPF_IPCB) 979 tbdp++; 980 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 981 tbdp[seg].tb_addr = 982 htole32(dmamap->dm_segs[seg].ds_addr); 983 tbdp[seg].tb_size = 984 htole32(dmamap->dm_segs[seg].ds_len); 985 } 986 987 /* Sync the DMA map. */ 988 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 989 BUS_DMASYNC_PREWRITE); 990 991 /* 992 * Store a pointer to the packet so we can free it later. 993 */ 994 txs->txs_mbuf = m0; 995 996 /* 997 * Initialize the transmit descriptor. 998 */ 999 /* BIG_ENDIAN: no need to swap to store 0 */ 1000 txd->txd_txcb.cb_status = 0; 1001 txd->txd_txcb.cb_command = 1002 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 1003 txd->txd_txcb.tx_threshold = tx_threshold; 1004 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 1005 1006 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 1007 if (sc->sc_flags & FXPF_IPCB) { 1008 struct m_tag *vtag; 1009 struct fxp_ipcb *ipcb; 1010 /* 1011 * Deal with TCP/IP checksum offload. Note that 1012 * in order for TCP checksum offload to work, 1013 * the pseudo header checksum must have already 1014 * been computed and stored in the checksum field 1015 * in the TCP header. The stack should have 1016 * already done this for us. 1017 */ 1018 ipcb = &txd->txd_u.txdu_ipcb; 1019 memset(ipcb, 0, sizeof(*ipcb)); 1020 /* 1021 * always do hardware parsing. 1022 */ 1023 ipcb->ipcb_ip_activation_high = 1024 FXP_IPCB_HARDWAREPARSING_ENABLE; 1025 /* 1026 * ip checksum offloading. 1027 */ 1028 if (csum_flags & M_CSUM_IPv4) { 1029 ipcb->ipcb_ip_schedule |= 1030 FXP_IPCB_IP_CHECKSUM_ENABLE; 1031 } 1032 /* 1033 * TCP/UDP checksum offloading. 1034 */ 1035 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1036 ipcb->ipcb_ip_schedule |= 1037 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1038 } 1039 1040 /* 1041 * request VLAN tag insertion if needed. 1042 */ 1043 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 1044 if (vtag) { 1045 ipcb->ipcb_vlan_id = 1046 htobe16(*(u_int *)(vtag + 1)); 1047 ipcb->ipcb_ip_activation_high |= 1048 FXP_IPCB_INSERTVLAN_ENABLE; 1049 } 1050 } else { 1051 KASSERT((csum_flags & 1052 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1053 } 1054 1055 FXP_CDTXSYNC(sc, nexttx, 1056 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1057 1058 /* Advance the tx pointer. */ 1059 sc->sc_txpending++; 1060 sc->sc_txlast = nexttx; 1061 1062 #if NBPFILTER > 0 1063 /* 1064 * Pass packet to bpf if there is a listener. 1065 */ 1066 if (ifp->if_bpf) 1067 bpf_mtap(ifp->if_bpf, m0); 1068 #endif 1069 } 1070 1071 if (sc->sc_txpending == FXP_NTXCB) { 1072 /* No more slots; notify upper layer. */ 1073 ifp->if_flags |= IFF_OACTIVE; 1074 } 1075 1076 if (sc->sc_txpending != opending) { 1077 /* 1078 * We enqueued packets. If the transmitter was idle, 1079 * reset the txdirty pointer. 1080 */ 1081 if (opending == 0) 1082 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1083 1084 /* 1085 * Cause the chip to interrupt and suspend command 1086 * processing once the last packet we've enqueued 1087 * has been transmitted. 1088 */ 1089 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1090 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1091 FXP_CDTXSYNC(sc, sc->sc_txlast, 1092 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1093 1094 /* 1095 * The entire packet chain is set up. Clear the suspend bit 1096 * on the command prior to the first packet we set up. 1097 */ 1098 FXP_CDTXSYNC(sc, lasttx, 1099 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1100 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1101 htole16(~FXP_CB_COMMAND_S); 1102 FXP_CDTXSYNC(sc, lasttx, 1103 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1104 1105 /* 1106 * Issue a Resume command in case the chip was suspended. 1107 */ 1108 fxp_scb_wait(sc); 1109 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1110 1111 /* Set a watchdog timer in case the chip flakes out. */ 1112 ifp->if_timer = 5; 1113 } 1114 } 1115 1116 /* 1117 * Process interface interrupts. 1118 */ 1119 int 1120 fxp_intr(void *arg) 1121 { 1122 struct fxp_softc *sc = arg; 1123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1124 bus_dmamap_t rxmap; 1125 int claimed = 0; 1126 u_int8_t statack; 1127 1128 if (!device_is_active(&sc->sc_dev) || sc->sc_enabled == 0) 1129 return (0); 1130 /* 1131 * If the interface isn't running, don't try to 1132 * service the interrupt.. just ack it and bail. 1133 */ 1134 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1135 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1136 if (statack) { 1137 claimed = 1; 1138 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1139 } 1140 return (claimed); 1141 } 1142 1143 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1144 claimed = 1; 1145 1146 /* 1147 * First ACK all the interrupts in this pass. 1148 */ 1149 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1150 1151 /* 1152 * Process receiver interrupts. If a no-resource (RNR) 1153 * condition exists, get whatever packets we can and 1154 * re-start the receiver. 1155 */ 1156 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1157 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1158 fxp_rxintr(sc); 1159 } 1160 1161 if (statack & FXP_SCB_STATACK_RNR) { 1162 fxp_scb_wait(sc); 1163 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1164 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1165 fxp_scb_wait(sc); 1166 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1167 rxmap->dm_segs[0].ds_addr + 1168 RFA_ALIGNMENT_FUDGE); 1169 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1170 } 1171 1172 /* 1173 * Free any finished transmit mbuf chains. 1174 */ 1175 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1176 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1177 fxp_txintr(sc); 1178 1179 /* 1180 * Try to get more packets going. 1181 */ 1182 fxp_start(ifp); 1183 1184 if (sc->sc_txpending == 0) { 1185 /* 1186 * If we want a re-init, do that now. 1187 */ 1188 if (sc->sc_flags & FXPF_WANTINIT) 1189 (void) fxp_init(ifp); 1190 } 1191 } 1192 } 1193 1194 #if NRND > 0 1195 if (claimed) 1196 rnd_add_uint32(&sc->rnd_source, statack); 1197 #endif 1198 return (claimed); 1199 } 1200 1201 /* 1202 * Handle transmit completion interrupts. 1203 */ 1204 void 1205 fxp_txintr(struct fxp_softc *sc) 1206 { 1207 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1208 struct fxp_txdesc *txd; 1209 struct fxp_txsoft *txs; 1210 int i; 1211 u_int16_t txstat; 1212 1213 ifp->if_flags &= ~IFF_OACTIVE; 1214 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1215 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1216 txd = FXP_CDTX(sc, i); 1217 txs = FXP_DSTX(sc, i); 1218 1219 FXP_CDTXSYNC(sc, i, 1220 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1221 1222 txstat = le16toh(txd->txd_txcb.cb_status); 1223 1224 if ((txstat & FXP_CB_STATUS_C) == 0) 1225 break; 1226 1227 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1228 0, txs->txs_dmamap->dm_mapsize, 1229 BUS_DMASYNC_POSTWRITE); 1230 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1231 m_freem(txs->txs_mbuf); 1232 txs->txs_mbuf = NULL; 1233 } 1234 1235 /* Update the dirty transmit buffer pointer. */ 1236 sc->sc_txdirty = i; 1237 1238 /* 1239 * Cancel the watchdog timer if there are no pending 1240 * transmissions. 1241 */ 1242 if (sc->sc_txpending == 0) 1243 ifp->if_timer = 0; 1244 } 1245 1246 /* 1247 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1248 */ 1249 1250 int 1251 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1252 { 1253 u_int16_t rxparsestat; 1254 u_int16_t csum_stat; 1255 u_int32_t csum_data; 1256 int csum_flags; 1257 1258 /* 1259 * check VLAN tag stripping. 1260 */ 1261 1262 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1263 struct m_tag *vtag; 1264 1265 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1266 if (vtag == NULL) 1267 return ENOMEM; 1268 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1269 m_tag_prepend(m, vtag); 1270 } 1271 1272 /* 1273 * check H/W Checksumming. 1274 */ 1275 1276 csum_stat = le16toh(rfa->cksum_stat); 1277 rxparsestat = le16toh(rfa->rx_parse_stat); 1278 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1279 return 0; 1280 1281 csum_flags = 0; 1282 csum_data = 0; 1283 1284 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1285 csum_flags = M_CSUM_IPv4; 1286 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1287 csum_flags |= M_CSUM_IPv4_BAD; 1288 } 1289 1290 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1291 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1292 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1293 csum_flags |= M_CSUM_TCP_UDP_BAD; 1294 } 1295 1296 m->m_pkthdr.csum_flags = csum_flags; 1297 m->m_pkthdr.csum_data = csum_data; 1298 1299 return 0; 1300 } 1301 1302 /* 1303 * Handle receive interrupts. 1304 */ 1305 void 1306 fxp_rxintr(struct fxp_softc *sc) 1307 { 1308 struct ethercom *ec = &sc->sc_ethercom; 1309 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1310 struct mbuf *m, *m0; 1311 bus_dmamap_t rxmap; 1312 struct fxp_rfa *rfa; 1313 u_int16_t len, rxstat; 1314 1315 for (;;) { 1316 m = sc->sc_rxq.ifq_head; 1317 rfa = FXP_MTORFA(m); 1318 rxmap = M_GETCTX(m, bus_dmamap_t); 1319 1320 FXP_RFASYNC(sc, m, 1321 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1322 1323 rxstat = le16toh(rfa->rfa_status); 1324 1325 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1326 /* 1327 * We have processed all of the 1328 * receive buffers. 1329 */ 1330 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1331 return; 1332 } 1333 1334 IF_DEQUEUE(&sc->sc_rxq, m); 1335 1336 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1337 1338 len = le16toh(rfa->actual_size) & 1339 (m->m_ext.ext_size - 1); 1340 1341 if (len < sizeof(struct ether_header)) { 1342 /* 1343 * Runt packet; drop it now. 1344 */ 1345 FXP_INIT_RFABUF(sc, m); 1346 continue; 1347 } 1348 1349 /* 1350 * If support for 802.1Q VLAN sized frames is 1351 * enabled, we need to do some additional error 1352 * checking (as we are saving bad frames, in 1353 * order to receive the larger ones). 1354 */ 1355 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1356 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1357 FXP_RFA_STATUS_RNR| 1358 FXP_RFA_STATUS_ALIGN| 1359 FXP_RFA_STATUS_CRC)) != 0) { 1360 FXP_INIT_RFABUF(sc, m); 1361 continue; 1362 } 1363 1364 /* Do checksum checking. */ 1365 m->m_pkthdr.csum_flags = 0; 1366 if (sc->sc_flags & FXPF_EXT_RFA) 1367 if (fxp_rx_hwcksum(m, rfa)) 1368 goto dropit; 1369 1370 /* 1371 * If the packet is small enough to fit in a 1372 * single header mbuf, allocate one and copy 1373 * the data into it. This greatly reduces 1374 * memory consumption when we receive lots 1375 * of small packets. 1376 * 1377 * Otherwise, we add a new buffer to the receive 1378 * chain. If this fails, we drop the packet and 1379 * recycle the old buffer. 1380 */ 1381 if (fxp_copy_small != 0 && len <= MHLEN) { 1382 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1383 if (m0 == NULL) 1384 goto dropit; 1385 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1386 memcpy(mtod(m0, void *), 1387 mtod(m, void *), len); 1388 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1389 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1390 FXP_INIT_RFABUF(sc, m); 1391 m = m0; 1392 } else { 1393 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1394 dropit: 1395 ifp->if_ierrors++; 1396 FXP_INIT_RFABUF(sc, m); 1397 continue; 1398 } 1399 } 1400 1401 m->m_pkthdr.rcvif = ifp; 1402 m->m_pkthdr.len = m->m_len = len; 1403 1404 #if NBPFILTER > 0 1405 /* 1406 * Pass this up to any BPF listeners, but only 1407 * pass it up the stack if it's for us. 1408 */ 1409 if (ifp->if_bpf) 1410 bpf_mtap(ifp->if_bpf, m); 1411 #endif 1412 1413 /* Pass it on. */ 1414 (*ifp->if_input)(ifp, m); 1415 } 1416 } 1417 1418 /* 1419 * Update packet in/out/collision statistics. The i82557 doesn't 1420 * allow you to access these counters without doing a fairly 1421 * expensive DMA to get _all_ of the statistics it maintains, so 1422 * we do this operation here only once per second. The statistics 1423 * counters in the kernel are updated from the previous dump-stats 1424 * DMA and then a new dump-stats DMA is started. The on-chip 1425 * counters are zeroed when the DMA completes. If we can't start 1426 * the DMA immediately, we don't wait - we just prepare to read 1427 * them again next time. 1428 */ 1429 void 1430 fxp_tick(void *arg) 1431 { 1432 struct fxp_softc *sc = arg; 1433 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1434 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1435 int s; 1436 1437 if (!device_is_active(&sc->sc_dev)) 1438 return; 1439 1440 s = splnet(); 1441 1442 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1443 1444 ifp->if_opackets += le32toh(sp->tx_good); 1445 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1446 if (sp->rx_good) { 1447 ifp->if_ipackets += le32toh(sp->rx_good); 1448 sc->sc_rxidle = 0; 1449 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1450 sc->sc_rxidle++; 1451 } 1452 ifp->if_ierrors += 1453 le32toh(sp->rx_crc_errors) + 1454 le32toh(sp->rx_alignment_errors) + 1455 le32toh(sp->rx_rnr_errors) + 1456 le32toh(sp->rx_overrun_errors); 1457 /* 1458 * If any transmit underruns occurred, bump up the transmit 1459 * threshold by another 512 bytes (64 * 8). 1460 */ 1461 if (sp->tx_underruns) { 1462 ifp->if_oerrors += le32toh(sp->tx_underruns); 1463 if (tx_threshold < 192) 1464 tx_threshold += 64; 1465 } 1466 #ifdef FXP_EVENT_COUNTERS 1467 if (sc->sc_rev >= FXP_REV_82558_A4) { 1468 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1469 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1470 } 1471 #endif 1472 1473 /* 1474 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1475 * then assume the receiver has locked up and attempt to clear 1476 * the condition by reprogramming the multicast filter (actually, 1477 * resetting the interface). This is a work-around for a bug in 1478 * the 82557 where the receiver locks up if it gets certain types 1479 * of garbage in the synchronization bits prior to the packet header. 1480 * This bug is supposed to only occur in 10Mbps mode, but has been 1481 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1482 * speed transition). 1483 */ 1484 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1485 (void) fxp_init(ifp); 1486 splx(s); 1487 return; 1488 } 1489 /* 1490 * If there is no pending command, start another stats 1491 * dump. Otherwise punt for now. 1492 */ 1493 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1494 /* 1495 * Start another stats dump. 1496 */ 1497 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1498 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1499 } else { 1500 /* 1501 * A previous command is still waiting to be accepted. 1502 * Just zero our copy of the stats and wait for the 1503 * next timer event to update them. 1504 */ 1505 /* BIG_ENDIAN: no swap required to store 0 */ 1506 sp->tx_good = 0; 1507 sp->tx_underruns = 0; 1508 sp->tx_total_collisions = 0; 1509 1510 sp->rx_good = 0; 1511 sp->rx_crc_errors = 0; 1512 sp->rx_alignment_errors = 0; 1513 sp->rx_rnr_errors = 0; 1514 sp->rx_overrun_errors = 0; 1515 if (sc->sc_rev >= FXP_REV_82558_A4) { 1516 sp->tx_pauseframes = 0; 1517 sp->rx_pauseframes = 0; 1518 } 1519 } 1520 1521 if (sc->sc_flags & FXPF_MII) { 1522 /* Tick the MII clock. */ 1523 mii_tick(&sc->sc_mii); 1524 } 1525 1526 splx(s); 1527 1528 /* 1529 * Schedule another timeout one second from now. 1530 */ 1531 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1532 } 1533 1534 /* 1535 * Drain the receive queue. 1536 */ 1537 void 1538 fxp_rxdrain(struct fxp_softc *sc) 1539 { 1540 bus_dmamap_t rxmap; 1541 struct mbuf *m; 1542 1543 for (;;) { 1544 IF_DEQUEUE(&sc->sc_rxq, m); 1545 if (m == NULL) 1546 break; 1547 rxmap = M_GETCTX(m, bus_dmamap_t); 1548 bus_dmamap_unload(sc->sc_dmat, rxmap); 1549 FXP_RXMAP_PUT(sc, rxmap); 1550 m_freem(m); 1551 } 1552 } 1553 1554 /* 1555 * Stop the interface. Cancels the statistics updater and resets 1556 * the interface. 1557 */ 1558 void 1559 fxp_stop(struct ifnet *ifp, int disable) 1560 { 1561 struct fxp_softc *sc = ifp->if_softc; 1562 struct fxp_txsoft *txs; 1563 int i; 1564 1565 /* 1566 * Turn down interface (done early to avoid bad interactions 1567 * between panics, shutdown hooks, and the watchdog timer) 1568 */ 1569 ifp->if_timer = 0; 1570 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1571 1572 /* 1573 * Cancel stats updater. 1574 */ 1575 callout_stop(&sc->sc_callout); 1576 if (sc->sc_flags & FXPF_MII) { 1577 /* Down the MII. */ 1578 mii_down(&sc->sc_mii); 1579 } 1580 1581 /* 1582 * Issue software reset. This unloads any microcode that 1583 * might already be loaded. 1584 */ 1585 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1586 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1587 DELAY(50); 1588 1589 /* 1590 * Release any xmit buffers. 1591 */ 1592 for (i = 0; i < FXP_NTXCB; i++) { 1593 txs = FXP_DSTX(sc, i); 1594 if (txs->txs_mbuf != NULL) { 1595 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1596 m_freem(txs->txs_mbuf); 1597 txs->txs_mbuf = NULL; 1598 } 1599 } 1600 sc->sc_txpending = 0; 1601 1602 if (disable) { 1603 fxp_rxdrain(sc); 1604 fxp_disable(sc); 1605 } 1606 1607 } 1608 1609 /* 1610 * Watchdog/transmission transmit timeout handler. Called when a 1611 * transmission is started on the interface, but no interrupt is 1612 * received before the timeout. This usually indicates that the 1613 * card has wedged for some reason. 1614 */ 1615 void 1616 fxp_watchdog(struct ifnet *ifp) 1617 { 1618 struct fxp_softc *sc = ifp->if_softc; 1619 1620 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1621 ifp->if_oerrors++; 1622 1623 (void) fxp_init(ifp); 1624 } 1625 1626 /* 1627 * Initialize the interface. Must be called at splnet(). 1628 */ 1629 int 1630 fxp_init(struct ifnet *ifp) 1631 { 1632 struct fxp_softc *sc = ifp->if_softc; 1633 struct fxp_cb_config *cbp; 1634 struct fxp_cb_ias *cb_ias; 1635 struct fxp_txdesc *txd; 1636 bus_dmamap_t rxmap; 1637 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1638 1639 if ((error = fxp_enable(sc)) != 0) 1640 goto out; 1641 1642 /* 1643 * Cancel any pending I/O 1644 */ 1645 fxp_stop(ifp, 0); 1646 1647 /* 1648 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1649 * flag, and this prevents the MII from detaching resulting in 1650 * a panic. The flags field should perhaps be split in runtime 1651 * flags and more static information. For now, just clear the 1652 * only other flag set. 1653 */ 1654 1655 sc->sc_flags &= ~FXPF_WANTINIT; 1656 1657 /* 1658 * Initialize base of CBL and RFA memory. Loading with zero 1659 * sets it up for regular linear addressing. 1660 */ 1661 fxp_scb_wait(sc); 1662 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1663 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1664 1665 fxp_scb_wait(sc); 1666 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1667 1668 /* 1669 * Initialize the multicast filter. Do this now, since we might 1670 * have to setup the config block differently. 1671 */ 1672 fxp_mc_setup(sc); 1673 1674 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1675 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1676 1677 /* 1678 * In order to support receiving 802.1Q VLAN frames, we have to 1679 * enable "save bad frames", since they are 4 bytes larger than 1680 * the normal Ethernet maximum frame length. On i82558 and later, 1681 * we have a better mechanism for this. 1682 */ 1683 save_bf = 0; 1684 lrxen = 0; 1685 vlan_drop = 0; 1686 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1687 if (sc->sc_rev < FXP_REV_82558_A4) 1688 save_bf = 1; 1689 else 1690 lrxen = 1; 1691 if (sc->sc_rev >= FXP_REV_82550) 1692 vlan_drop = 1; 1693 } 1694 1695 /* 1696 * Initialize base of dump-stats buffer. 1697 */ 1698 fxp_scb_wait(sc); 1699 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1700 sc->sc_cddma + FXP_CDSTATSOFF); 1701 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1702 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1703 1704 cbp = &sc->sc_control_data->fcd_configcb; 1705 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1706 1707 /* 1708 * Load microcode for this controller. 1709 */ 1710 fxp_load_ucode(sc); 1711 1712 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1713 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1714 else 1715 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1716 1717 /* 1718 * This copy is kind of disgusting, but there are a bunch of must be 1719 * zero and must be one bits in this structure and this is the easiest 1720 * way to initialize them all to proper values. 1721 */ 1722 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1723 1724 /* BIG_ENDIAN: no need to swap to store 0 */ 1725 cbp->cb_status = 0; 1726 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1727 FXP_CB_COMMAND_EL); 1728 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1729 cbp->link_addr = 0xffffffff; /* (no) next command */ 1730 /* bytes in config block */ 1731 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1732 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1733 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1734 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1735 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1736 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1737 cbp->type_enable = 0; /* actually reserved */ 1738 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1739 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1740 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1741 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1742 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1743 cbp->late_scb = 0; /* (don't) defer SCB update */ 1744 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1745 cbp->ci_int = 1; /* interrupt on CU idle */ 1746 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1747 cbp->ext_stats_dis = 1; /* disable extended counters */ 1748 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1749 cbp->save_bf = save_bf;/* save bad frames */ 1750 cbp->disc_short_rx = !prm; /* discard short packets */ 1751 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1752 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1753 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1754 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1755 /* interface mode */ 1756 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1757 cbp->csma_dis = 0; /* (don't) disable link */ 1758 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1759 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1760 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1761 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1762 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1763 cbp->nsai = 1; /* (don't) disable source addr insert */ 1764 cbp->preamble_length = 2; /* (7 byte) preamble */ 1765 cbp->loopback = 0; /* (don't) loopback */ 1766 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1767 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1768 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1769 cbp->promiscuous = prm; /* promiscuous mode */ 1770 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1771 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1772 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1773 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1774 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1775 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1776 cbp->padding = 1; /* (do) pad short tx packets */ 1777 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1778 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1779 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1780 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1781 /* must set wake_en in PMCSR also */ 1782 cbp->force_fdx = 0; /* (don't) force full duplex */ 1783 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1784 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1785 cbp->mc_all = allm; /* accept all multicasts */ 1786 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1787 cbp->vlan_drop_en = vlan_drop; 1788 1789 if (sc->sc_rev < FXP_REV_82558_A4) { 1790 /* 1791 * The i82557 has no hardware flow control, the values 1792 * here are the defaults for the chip. 1793 */ 1794 cbp->fc_delay_lsb = 0; 1795 cbp->fc_delay_msb = 0x40; 1796 cbp->pri_fc_thresh = 3; 1797 cbp->tx_fc_dis = 0; 1798 cbp->rx_fc_restop = 0; 1799 cbp->rx_fc_restart = 0; 1800 cbp->fc_filter = 0; 1801 cbp->pri_fc_loc = 1; 1802 } else { 1803 cbp->fc_delay_lsb = 0x1f; 1804 cbp->fc_delay_msb = 0x01; 1805 cbp->pri_fc_thresh = 3; 1806 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1807 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1808 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1809 cbp->fc_filter = !prm; /* drop FC frames to host */ 1810 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1811 cbp->ext_stats_dis = 0; /* enable extended stats */ 1812 } 1813 1814 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1815 1816 /* 1817 * Start the config command/DMA. 1818 */ 1819 fxp_scb_wait(sc); 1820 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1821 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1822 /* ...and wait for it to complete. */ 1823 i = 1000; 1824 do { 1825 FXP_CDCONFIGSYNC(sc, 1826 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1827 DELAY(1); 1828 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1829 if (i == 0) { 1830 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1831 sc->sc_dev.dv_xname, __LINE__); 1832 return (ETIMEDOUT); 1833 } 1834 1835 /* 1836 * Initialize the station address. 1837 */ 1838 cb_ias = &sc->sc_control_data->fcd_iascb; 1839 /* BIG_ENDIAN: no need to swap to store 0 */ 1840 cb_ias->cb_status = 0; 1841 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1842 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1843 cb_ias->link_addr = 0xffffffff; 1844 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1845 1846 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1847 1848 /* 1849 * Start the IAS (Individual Address Setup) command/DMA. 1850 */ 1851 fxp_scb_wait(sc); 1852 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1853 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1854 /* ...and wait for it to complete. */ 1855 i = 1000; 1856 do { 1857 FXP_CDIASSYNC(sc, 1858 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1859 DELAY(1); 1860 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1861 if (i == 0) { 1862 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1863 sc->sc_dev.dv_xname, __LINE__); 1864 return (ETIMEDOUT); 1865 } 1866 1867 /* 1868 * Initialize the transmit descriptor ring. txlast is initialized 1869 * to the end of the list so that it will wrap around to the first 1870 * descriptor when the first packet is transmitted. 1871 */ 1872 for (i = 0; i < FXP_NTXCB; i++) { 1873 txd = FXP_CDTX(sc, i); 1874 memset(txd, 0, sizeof(*txd)); 1875 txd->txd_txcb.cb_command = 1876 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1877 txd->txd_txcb.link_addr = 1878 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1879 if (sc->sc_flags & FXPF_EXT_TXCB) 1880 txd->txd_txcb.tbd_array_addr = 1881 htole32(FXP_CDTBDADDR(sc, i) + 1882 (2 * sizeof(struct fxp_tbd))); 1883 else 1884 txd->txd_txcb.tbd_array_addr = 1885 htole32(FXP_CDTBDADDR(sc, i)); 1886 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1887 } 1888 sc->sc_txpending = 0; 1889 sc->sc_txdirty = 0; 1890 sc->sc_txlast = FXP_NTXCB - 1; 1891 1892 /* 1893 * Initialize the receive buffer list. 1894 */ 1895 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1896 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1897 rxmap = FXP_RXMAP_GET(sc); 1898 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1899 log(LOG_ERR, "%s: unable to allocate or map rx " 1900 "buffer %d, error = %d\n", 1901 sc->sc_dev.dv_xname, 1902 sc->sc_rxq.ifq_len, error); 1903 /* 1904 * XXX Should attempt to run with fewer receive 1905 * XXX buffers instead of just failing. 1906 */ 1907 FXP_RXMAP_PUT(sc, rxmap); 1908 fxp_rxdrain(sc); 1909 goto out; 1910 } 1911 } 1912 sc->sc_rxidle = 0; 1913 1914 /* 1915 * Give the transmit ring to the chip. We do this by pointing 1916 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1917 * issuing a start command. It will execute the NOP and then 1918 * suspend, pointing at the first descriptor. 1919 */ 1920 fxp_scb_wait(sc); 1921 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1922 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1923 1924 /* 1925 * Initialize receiver buffer area - RFA. 1926 */ 1927 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1928 fxp_scb_wait(sc); 1929 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1930 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1931 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1932 1933 if (sc->sc_flags & FXPF_MII) { 1934 /* 1935 * Set current media. 1936 */ 1937 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1938 goto out; 1939 } 1940 1941 /* 1942 * ...all done! 1943 */ 1944 ifp->if_flags |= IFF_RUNNING; 1945 ifp->if_flags &= ~IFF_OACTIVE; 1946 1947 /* 1948 * Start the one second timer. 1949 */ 1950 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1951 1952 /* 1953 * Attempt to start output on the interface. 1954 */ 1955 fxp_start(ifp); 1956 1957 out: 1958 if (error) { 1959 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1960 ifp->if_timer = 0; 1961 log(LOG_ERR, "%s: interface not running\n", 1962 sc->sc_dev.dv_xname); 1963 } 1964 return (error); 1965 } 1966 1967 /* 1968 * Notify the world which media we're using. 1969 */ 1970 void 1971 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1972 { 1973 struct fxp_softc *sc = ifp->if_softc; 1974 1975 if (sc->sc_enabled == 0) { 1976 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1977 ifmr->ifm_status = 0; 1978 return; 1979 } 1980 1981 ether_mediastatus(ifp, ifmr); 1982 1983 /* 1984 * XXX Flow control is always turned on if the chip supports 1985 * XXX it; we can't easily control it dynamically, since it 1986 * XXX requires sending a setup packet. 1987 */ 1988 if (sc->sc_rev >= FXP_REV_82558_A4) 1989 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1990 } 1991 1992 int 1993 fxp_80c24_mediachange(struct ifnet *ifp) 1994 { 1995 1996 /* Nothing to do here. */ 1997 return (0); 1998 } 1999 2000 void 2001 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2002 { 2003 struct fxp_softc *sc = ifp->if_softc; 2004 2005 /* 2006 * Media is currently-selected media. We cannot determine 2007 * the link status. 2008 */ 2009 ifmr->ifm_status = 0; 2010 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2011 } 2012 2013 /* 2014 * Add a buffer to the end of the RFA buffer list. 2015 * Return 0 if successful, error code on failure. 2016 * 2017 * The RFA struct is stuck at the beginning of mbuf cluster and the 2018 * data pointer is fixed up to point just past it. 2019 */ 2020 int 2021 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2022 { 2023 struct mbuf *m; 2024 int error; 2025 2026 MGETHDR(m, M_DONTWAIT, MT_DATA); 2027 if (m == NULL) 2028 return (ENOBUFS); 2029 2030 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2031 MCLGET(m, M_DONTWAIT); 2032 if ((m->m_flags & M_EXT) == 0) { 2033 m_freem(m); 2034 return (ENOBUFS); 2035 } 2036 2037 if (unload) 2038 bus_dmamap_unload(sc->sc_dmat, rxmap); 2039 2040 M_SETCTX(m, rxmap); 2041 2042 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2043 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2044 BUS_DMA_READ|BUS_DMA_NOWAIT); 2045 if (error) { 2046 /* XXX XXX XXX */ 2047 printf("%s: can't load rx DMA map %d, error = %d\n", 2048 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2049 panic("fxp_add_rfabuf"); 2050 } 2051 2052 FXP_INIT_RFABUF(sc, m); 2053 2054 return (0); 2055 } 2056 2057 int 2058 fxp_mdi_read(struct device *self, int phy, int reg) 2059 { 2060 struct fxp_softc *sc = (struct fxp_softc *)self; 2061 int count = 10000; 2062 int value; 2063 2064 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2065 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2066 2067 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2068 0x10000000) == 0 && count--) 2069 DELAY(10); 2070 2071 if (count <= 0) 2072 log(LOG_WARNING, 2073 "%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2074 2075 return (value & 0xffff); 2076 } 2077 2078 void 2079 fxp_statchg(struct device *self) 2080 { 2081 2082 /* Nothing to do. */ 2083 } 2084 2085 void 2086 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2087 { 2088 struct fxp_softc *sc = (struct fxp_softc *)self; 2089 int count = 10000; 2090 2091 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2092 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2093 (value & 0xffff)); 2094 2095 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2096 count--) 2097 DELAY(10); 2098 2099 if (count <= 0) 2100 log(LOG_WARNING, 2101 "%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2102 } 2103 2104 int 2105 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2106 { 2107 struct fxp_softc *sc = ifp->if_softc; 2108 struct ifreq *ifr = (struct ifreq *)data; 2109 int s, error; 2110 2111 s = splnet(); 2112 2113 switch (cmd) { 2114 case SIOCSIFMEDIA: 2115 case SIOCGIFMEDIA: 2116 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2117 break; 2118 2119 default: 2120 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2121 break; 2122 2123 error = 0; 2124 2125 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2126 ; 2127 else if (ifp->if_flags & IFF_RUNNING) { 2128 /* 2129 * Multicast list has changed; set the 2130 * hardware filter accordingly. 2131 */ 2132 if (sc->sc_txpending) { 2133 sc->sc_flags |= FXPF_WANTINIT; 2134 } else 2135 error = fxp_init(ifp); 2136 } 2137 break; 2138 } 2139 2140 /* Try to get more packets going. */ 2141 if (sc->sc_enabled) 2142 fxp_start(ifp); 2143 2144 splx(s); 2145 return (error); 2146 } 2147 2148 /* 2149 * Program the multicast filter. 2150 * 2151 * This function must be called at splnet(). 2152 */ 2153 void 2154 fxp_mc_setup(struct fxp_softc *sc) 2155 { 2156 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2158 struct ethercom *ec = &sc->sc_ethercom; 2159 struct ether_multi *enm; 2160 struct ether_multistep step; 2161 int count, nmcasts; 2162 2163 #ifdef DIAGNOSTIC 2164 if (sc->sc_txpending) 2165 panic("fxp_mc_setup: pending transmissions"); 2166 #endif 2167 2168 ifp->if_flags &= ~IFF_ALLMULTI; 2169 2170 /* 2171 * Initialize multicast setup descriptor. 2172 */ 2173 nmcasts = 0; 2174 ETHER_FIRST_MULTI(step, ec, enm); 2175 while (enm != NULL) { 2176 /* 2177 * Check for too many multicast addresses or if we're 2178 * listening to a range. Either way, we simply have 2179 * to accept all multicasts. 2180 */ 2181 if (nmcasts >= MAXMCADDR || 2182 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2183 ETHER_ADDR_LEN) != 0) { 2184 /* 2185 * Callers of this function must do the 2186 * right thing with this. If we're called 2187 * from outside fxp_init(), the caller must 2188 * detect if the state if IFF_ALLMULTI changes. 2189 * If it does, the caller must then call 2190 * fxp_init(), since allmulti is handled by 2191 * the config block. 2192 */ 2193 ifp->if_flags |= IFF_ALLMULTI; 2194 return; 2195 } 2196 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2197 ETHER_ADDR_LEN); 2198 nmcasts++; 2199 ETHER_NEXT_MULTI(step, enm); 2200 } 2201 2202 /* BIG_ENDIAN: no need to swap to store 0 */ 2203 mcsp->cb_status = 0; 2204 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2205 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2206 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2207 2208 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2209 2210 /* 2211 * Wait until the command unit is not active. This should never 2212 * happen since nothing is queued, but make sure anyway. 2213 */ 2214 count = 100; 2215 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2216 FXP_SCB_CUS_ACTIVE && --count) 2217 DELAY(1); 2218 if (count == 0) { 2219 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2220 sc->sc_dev.dv_xname, __LINE__); 2221 return; 2222 } 2223 2224 /* 2225 * Start the multicast setup command/DMA. 2226 */ 2227 fxp_scb_wait(sc); 2228 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2229 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2230 2231 /* ...and wait for it to complete. */ 2232 count = 1000; 2233 do { 2234 FXP_CDMCSSYNC(sc, 2235 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2236 DELAY(1); 2237 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2238 if (count == 0) { 2239 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2240 sc->sc_dev.dv_xname, __LINE__); 2241 return; 2242 } 2243 } 2244 2245 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2246 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2247 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2248 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2249 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2250 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2251 2252 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2253 2254 static const struct ucode { 2255 int32_t revision; 2256 const uint32_t *ucode; 2257 size_t length; 2258 uint16_t int_delay_offset; 2259 uint16_t bundle_max_offset; 2260 } ucode_table[] = { 2261 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2262 D101_CPUSAVER_DWORD, 0 }, 2263 2264 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2265 D101_CPUSAVER_DWORD, 0 }, 2266 2267 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2268 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2269 2270 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2271 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2272 2273 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2274 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2275 2276 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2277 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2278 2279 { 0, NULL, 0, 0, 0 } 2280 }; 2281 2282 void 2283 fxp_load_ucode(struct fxp_softc *sc) 2284 { 2285 const struct ucode *uc; 2286 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2287 int count, i; 2288 2289 if (sc->sc_flags & FXPF_UCODE_LOADED) 2290 return; 2291 2292 /* 2293 * Only load the uCode if the user has requested that 2294 * we do so. 2295 */ 2296 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2297 sc->sc_int_delay = 0; 2298 sc->sc_bundle_max = 0; 2299 return; 2300 } 2301 2302 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2303 if (sc->sc_rev == uc->revision) 2304 break; 2305 } 2306 if (uc->ucode == NULL) 2307 return; 2308 2309 /* BIG ENDIAN: no need to swap to store 0 */ 2310 cbp->cb_status = 0; 2311 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2312 cbp->link_addr = 0xffffffff; /* (no) next command */ 2313 for (i = 0; i < uc->length; i++) 2314 cbp->ucode[i] = htole32(uc->ucode[i]); 2315 2316 if (uc->int_delay_offset) 2317 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2318 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2319 2320 if (uc->bundle_max_offset) 2321 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2322 htole16(fxp_bundle_max); 2323 2324 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2325 2326 /* 2327 * Download the uCode to the chip. 2328 */ 2329 fxp_scb_wait(sc); 2330 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2331 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2332 2333 /* ...and wait for it to complete. */ 2334 count = 10000; 2335 do { 2336 FXP_CDUCODESYNC(sc, 2337 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2338 DELAY(2); 2339 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2340 if (count == 0) { 2341 sc->sc_int_delay = 0; 2342 sc->sc_bundle_max = 0; 2343 log(LOG_WARNING, "%s: timeout loading microcode\n", 2344 sc->sc_dev.dv_xname); 2345 return; 2346 } 2347 2348 if (sc->sc_int_delay != fxp_int_delay || 2349 sc->sc_bundle_max != fxp_bundle_max) { 2350 sc->sc_int_delay = fxp_int_delay; 2351 sc->sc_bundle_max = fxp_bundle_max; 2352 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2353 "max bundle: %d\n", sc->sc_dev.dv_xname, 2354 sc->sc_int_delay, 2355 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2356 } 2357 2358 sc->sc_flags |= FXPF_UCODE_LOADED; 2359 } 2360 2361 int 2362 fxp_enable(struct fxp_softc *sc) 2363 { 2364 2365 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2366 if ((*sc->sc_enable)(sc) != 0) { 2367 log(LOG_ERR, "%s: device enable failed\n", 2368 sc->sc_dev.dv_xname); 2369 return (EIO); 2370 } 2371 } 2372 2373 sc->sc_enabled = 1; 2374 return (0); 2375 } 2376 2377 void 2378 fxp_disable(struct fxp_softc *sc) 2379 { 2380 2381 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2382 (*sc->sc_disable)(sc); 2383 sc->sc_enabled = 0; 2384 } 2385 } 2386 2387 /* 2388 * fxp_activate: 2389 * 2390 * Handle device activation/deactivation requests. 2391 */ 2392 int 2393 fxp_activate(struct device *self, enum devact act) 2394 { 2395 struct fxp_softc *sc = (void *) self; 2396 int s, error = 0; 2397 2398 s = splnet(); 2399 switch (act) { 2400 case DVACT_ACTIVATE: 2401 error = EOPNOTSUPP; 2402 break; 2403 2404 case DVACT_DEACTIVATE: 2405 if (sc->sc_flags & FXPF_MII) 2406 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2407 MII_OFFSET_ANY); 2408 if_deactivate(&sc->sc_ethercom.ec_if); 2409 break; 2410 } 2411 splx(s); 2412 2413 return (error); 2414 } 2415 2416 /* 2417 * fxp_detach: 2418 * 2419 * Detach an i82557 interface. 2420 */ 2421 int 2422 fxp_detach(struct fxp_softc *sc) 2423 { 2424 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2425 int i; 2426 2427 /* Succeed now if there's no work to do. */ 2428 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2429 return (0); 2430 2431 /* Unhook our tick handler. */ 2432 callout_stop(&sc->sc_callout); 2433 2434 if (sc->sc_flags & FXPF_MII) { 2435 /* Detach all PHYs */ 2436 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2437 } 2438 2439 /* Delete all remaining media. */ 2440 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2441 2442 #if NRND > 0 2443 rnd_detach_source(&sc->rnd_source); 2444 #endif 2445 ether_ifdetach(ifp); 2446 if_detach(ifp); 2447 2448 for (i = 0; i < FXP_NRFABUFS; i++) { 2449 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2450 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2451 } 2452 2453 for (i = 0; i < FXP_NTXCB; i++) { 2454 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2455 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2456 } 2457 2458 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2459 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2460 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2461 sizeof(struct fxp_control_data)); 2462 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2463 2464 shutdownhook_disestablish(sc->sc_sdhook); 2465 powerhook_disestablish(sc->sc_powerhook); 2466 2467 return (0); 2468 } 2469
Indexes created Sat Oct 25 10:09:55 GMT 2025