i82557.c revision 1.105.2.1
1 /* $NetBSD: i82557.c,v 1.105.2.1 2007/12/11 15:27:40 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.105.2.1 2007/12/11 15:27:40 yamt Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 int fxp_mii_mediachange(struct ifnet *); 179 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 180 181 void fxp_80c24_initmedia(struct fxp_softc *); 182 int fxp_80c24_mediachange(struct ifnet *); 183 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 184 185 void fxp_start(struct ifnet *); 186 int fxp_ioctl(struct ifnet *, u_long, void *); 187 void fxp_watchdog(struct ifnet *); 188 int fxp_init(struct ifnet *); 189 void fxp_stop(struct ifnet *, int); 190 191 void fxp_txintr(struct fxp_softc *); 192 int fxp_rxintr(struct fxp_softc *); 193 194 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 195 196 void fxp_rxdrain(struct fxp_softc *); 197 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 198 int fxp_mdi_read(struct device *, int, int); 199 void fxp_statchg(struct device *); 200 void fxp_mdi_write(struct device *, int, int, int); 201 void fxp_autosize_eeprom(struct fxp_softc*); 202 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 204 void fxp_eeprom_update_cksum(struct fxp_softc *); 205 void fxp_get_info(struct fxp_softc *, u_int8_t *); 206 void fxp_tick(void *); 207 void fxp_mc_setup(struct fxp_softc *); 208 void fxp_load_ucode(struct fxp_softc *); 209 210 void fxp_shutdown(void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 log(LOG_WARNING, 248 "%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 249 } 250 251 /* 252 * Submit a command to the i82557. 253 */ 254 static inline void 255 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 256 { 257 258 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 259 } 260 261 /* 262 * Finish attaching an i82557 interface. Called by bus-specific front-end. 263 */ 264 void 265 fxp_attach(struct fxp_softc *sc) 266 { 267 u_int8_t enaddr[ETHER_ADDR_LEN]; 268 struct ifnet *ifp; 269 bus_dma_segment_t seg; 270 int rseg, i, error; 271 struct fxp_phytype *fp; 272 273 callout_init(&sc->sc_callout, 0); 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Enable use of extended RFDs and TCBs for 82550 285 * and later chips. Note: we need extended TXCB support 286 * too, but that's already enabled by the code above. 287 * Be careful to do this only on the right devices. 288 */ 289 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 290 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 291 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 292 } else { 293 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 294 } 295 296 sc->sc_rfa_size = 297 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 298 299 /* 300 * Allocate the control data structures, and create and load the 301 * DMA map for it. 302 */ 303 if ((error = bus_dmamem_alloc(sc->sc_dmat, 304 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 305 0)) != 0) { 306 aprint_error( 307 "%s: unable to allocate control data, error = %d\n", 308 sc->sc_dev.dv_xname, error); 309 goto fail_0; 310 } 311 312 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 313 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 314 BUS_DMA_COHERENT)) != 0) { 315 aprint_error("%s: unable to map control data, error = %d\n", 316 sc->sc_dev.dv_xname, error); 317 goto fail_1; 318 } 319 sc->sc_cdseg = seg; 320 sc->sc_cdnseg = rseg; 321 322 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 323 324 if ((error = bus_dmamap_create(sc->sc_dmat, 325 sizeof(struct fxp_control_data), 1, 326 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 327 aprint_error("%s: unable to create control data DMA map, " 328 "error = %d\n", sc->sc_dev.dv_xname, error); 329 goto fail_2; 330 } 331 332 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 333 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 334 0)) != 0) { 335 aprint_error( 336 "%s: can't load control data DMA map, error = %d\n", 337 sc->sc_dev.dv_xname, error); 338 goto fail_3; 339 } 340 341 /* 342 * Create the transmit buffer DMA maps. 343 */ 344 for (i = 0; i < FXP_NTXCB; i++) { 345 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 346 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 347 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 348 aprint_error("%s: unable to create tx DMA map %d, " 349 "error = %d\n", sc->sc_dev.dv_xname, i, error); 350 goto fail_4; 351 } 352 } 353 354 /* 355 * Create the receive buffer DMA maps. 356 */ 357 for (i = 0; i < FXP_NRFABUFS; i++) { 358 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 359 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 360 aprint_error("%s: unable to create rx DMA map %d, " 361 "error = %d\n", sc->sc_dev.dv_xname, i, error); 362 goto fail_5; 363 } 364 } 365 366 /* Initialize MAC address and media structures. */ 367 fxp_get_info(sc, enaddr); 368 369 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 370 ether_sprintf(enaddr)); 371 372 ifp = &sc->sc_ethercom.ec_if; 373 374 /* 375 * Get info about our media interface, and initialize it. Note 376 * the table terminates itself with a phy of -1, indicating 377 * that we're using MII. 378 */ 379 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 380 if (fp->fp_phy == sc->phy_primary_device) 381 break; 382 (*fp->fp_init)(sc); 383 384 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 385 ifp->if_softc = sc; 386 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 387 ifp->if_ioctl = fxp_ioctl; 388 ifp->if_start = fxp_start; 389 ifp->if_watchdog = fxp_watchdog; 390 ifp->if_init = fxp_init; 391 ifp->if_stop = fxp_stop; 392 IFQ_SET_READY(&ifp->if_snd); 393 394 if (sc->sc_flags & FXPF_IPCB) { 395 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 396 /* 397 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 398 * at least, on i82550 rev.12. 399 * specifically, it doesn't calculate ipv4 checksum correctly 400 * when sending 20 byte ipv4 header + 1 or 2 byte data. 401 * FreeBSD driver has related comments. 402 */ 403 ifp->if_capabilities = 404 IFCAP_CSUM_IPv4_Rx | 405 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 406 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 407 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 408 } 409 410 /* 411 * We can support 802.1Q VLAN-sized frames. 412 */ 413 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 414 415 /* 416 * Attach the interface. 417 */ 418 if_attach(ifp); 419 ether_ifattach(ifp, enaddr); 420 #if NRND > 0 421 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 422 RND_TYPE_NET, 0); 423 #endif 424 425 #ifdef FXP_EVENT_COUNTERS 426 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 427 NULL, sc->sc_dev.dv_xname, "txstall"); 428 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 429 NULL, sc->sc_dev.dv_xname, "txintr"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 431 NULL, sc->sc_dev.dv_xname, "rxintr"); 432 if (sc->sc_rev >= FXP_REV_82558_A4) { 433 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 434 NULL, sc->sc_dev.dv_xname, "txpause"); 435 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 436 NULL, sc->sc_dev.dv_xname, "rxpause"); 437 } 438 #endif /* FXP_EVENT_COUNTERS */ 439 440 /* 441 * Add shutdown hook so that DMA is disabled prior to reboot. Not 442 * doing do could allow DMA to corrupt kernel memory during the 443 * reboot before the driver initializes. 444 */ 445 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 446 if (sc->sc_sdhook == NULL) 447 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 448 sc->sc_dev.dv_xname); 449 450 /* The attach is successful. */ 451 sc->sc_flags |= FXPF_ATTACHED; 452 453 return; 454 455 /* 456 * Free any resources we've allocated during the failed attach 457 * attempt. Do this in reverse order and fall though. 458 */ 459 fail_5: 460 for (i = 0; i < FXP_NRFABUFS; i++) { 461 if (sc->sc_rxmaps[i] != NULL) 462 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 463 } 464 fail_4: 465 for (i = 0; i < FXP_NTXCB; i++) { 466 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 467 bus_dmamap_destroy(sc->sc_dmat, 468 FXP_DSTX(sc, i)->txs_dmamap); 469 } 470 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 471 fail_3: 472 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 473 fail_2: 474 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 475 sizeof(struct fxp_control_data)); 476 fail_1: 477 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 478 fail_0: 479 return; 480 } 481 482 void 483 fxp_mii_initmedia(struct fxp_softc *sc) 484 { 485 int flags; 486 487 sc->sc_flags |= FXPF_MII; 488 489 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 490 sc->sc_mii.mii_readreg = fxp_mdi_read; 491 sc->sc_mii.mii_writereg = fxp_mdi_write; 492 sc->sc_mii.mii_statchg = fxp_statchg; 493 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 494 fxp_mii_mediastatus); 495 496 flags = MIIF_NOISOLATE; 497 if (sc->sc_rev >= FXP_REV_82558_A4) 498 flags |= MIIF_DOPAUSE; 499 /* 500 * The i82557 wedges if all of its PHYs are isolated! 501 */ 502 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 503 MII_OFFSET_ANY, flags); 504 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 505 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 506 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 507 } else 508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 509 } 510 511 void 512 fxp_80c24_initmedia(struct fxp_softc *sc) 513 { 514 515 /* 516 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 517 * doesn't have a programming interface of any sort. The 518 * media is sensed automatically based on how the link partner 519 * is configured. This is, in essence, manual configuration. 520 */ 521 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 522 sc->sc_dev.dv_xname); 523 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 524 fxp_80c24_mediastatus); 525 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 526 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 527 } 528 529 /* 530 * Device shutdown routine. Called at system shutdown after sync. The 531 * main purpose of this routine is to shut off receiver DMA so that 532 * kernel memory doesn't get clobbered during warmboot. 533 */ 534 void 535 fxp_shutdown(void *arg) 536 { 537 struct fxp_softc *sc = arg; 538 539 /* 540 * Since the system's going to halt shortly, don't bother 541 * freeing mbufs. 542 */ 543 fxp_stop(&sc->sc_ethercom.ec_if, 0); 544 } 545 546 /* 547 * Initialize the interface media. 548 */ 549 void 550 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 551 { 552 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 553 554 /* 555 * Reset to a stable state. 556 */ 557 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 558 DELAY(100); 559 560 sc->sc_eeprom_size = 0; 561 fxp_autosize_eeprom(sc); 562 if (sc->sc_eeprom_size == 0) { 563 aprint_error("%s: failed to detect EEPROM size\n", 564 sc->sc_dev.dv_xname); 565 sc->sc_eeprom_size = 6; /* XXX panic here? */ 566 } 567 #ifdef DEBUG 568 aprint_debug("%s: detected %d word EEPROM\n", 569 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 570 #endif 571 572 /* 573 * Get info about the primary PHY 574 */ 575 fxp_read_eeprom(sc, &data, 6, 1); 576 sc->phy_primary_device = 577 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 578 579 /* 580 * Read MAC address. 581 */ 582 fxp_read_eeprom(sc, myea, 0, 3); 583 enaddr[0] = myea[0] & 0xff; 584 enaddr[1] = myea[0] >> 8; 585 enaddr[2] = myea[1] & 0xff; 586 enaddr[3] = myea[1] >> 8; 587 enaddr[4] = myea[2] & 0xff; 588 enaddr[5] = myea[2] >> 8; 589 590 /* 591 * Systems based on the ICH2/ICH2-M chip from Intel, as well 592 * as some i82559 designs, have a defect where the chip can 593 * cause a PCI protocol violation if it receives a CU_RESUME 594 * command when it is entering the IDLE state. 595 * 596 * The work-around is to disable Dynamic Standby Mode, so that 597 * the chip never deasserts #CLKRUN, and always remains in the 598 * active state. 599 * 600 * Unfortunately, the only way to disable Dynamic Standby is 601 * to frob an EEPROM setting and reboot (the EEPROM setting 602 * is only consulted when the PCI bus comes out of reset). 603 * 604 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 605 */ 606 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 607 fxp_read_eeprom(sc, &data, 10, 1); 608 if (data & 0x02) { /* STB enable */ 609 aprint_error("%s: WARNING: " 610 "Disabling dynamic standby mode in EEPROM " 611 "to work around a\n", 612 sc->sc_dev.dv_xname); 613 aprint_normal( 614 "%s: WARNING: hardware bug. You must reset " 615 "the system before using this\n", 616 sc->sc_dev.dv_xname); 617 aprint_normal("%s: WARNING: interface.\n", 618 sc->sc_dev.dv_xname); 619 data &= ~0x02; 620 fxp_write_eeprom(sc, &data, 10, 1); 621 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 622 sc->sc_dev.dv_xname, data); 623 fxp_eeprom_update_cksum(sc); 624 } 625 } 626 627 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 628 /* Due to false positives we make it conditional on setting link1 */ 629 fxp_read_eeprom(sc, &data, 3, 1); 630 if ((data & 0x03) != 0x03) { 631 aprint_verbose("%s: May need receiver lock-up workaround\n", 632 sc->sc_dev.dv_xname); 633 } 634 } 635 636 static void 637 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 638 { 639 uint16_t reg; 640 int x; 641 642 for (x = 1 << (len - 1); x != 0; x >>= 1) { 643 DELAY(40); 644 if (data & x) 645 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 646 else 647 reg = FXP_EEPROM_EECS; 648 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 649 DELAY(40); 650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 651 reg | FXP_EEPROM_EESK); 652 DELAY(40); 653 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 654 } 655 DELAY(40); 656 } 657 658 /* 659 * Figure out EEPROM size. 660 * 661 * 559's can have either 64-word or 256-word EEPROMs, the 558 662 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 663 * talks about the existence of 16 to 256 word EEPROMs. 664 * 665 * The only known sizes are 64 and 256, where the 256 version is used 666 * by CardBus cards to store CIS information. 667 * 668 * The address is shifted in msb-to-lsb, and after the last 669 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 670 * after which follows the actual data. We try to detect this zero, by 671 * probing the data-out bit in the EEPROM control register just after 672 * having shifted in a bit. If the bit is zero, we assume we've 673 * shifted enough address bits. The data-out should be tri-state, 674 * before this, which should translate to a logical one. 675 * 676 * Other ways to do this would be to try to read a register with known 677 * contents with a varying number of address bits, but no such 678 * register seem to be available. The high bits of register 10 are 01 679 * on the 558 and 559, but apparently not on the 557. 680 * 681 * The Linux driver computes a checksum on the EEPROM data, but the 682 * value of this checksum is not very well documented. 683 */ 684 685 void 686 fxp_autosize_eeprom(struct fxp_softc *sc) 687 { 688 int x; 689 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 691 DELAY(40); 692 693 /* Shift in read opcode. */ 694 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 695 696 /* 697 * Shift in address, wait for the dummy zero following a correct 698 * address shift. 699 */ 700 for (x = 1; x <= 8; x++) { 701 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 702 DELAY(40); 703 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 704 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 705 DELAY(40); 706 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 707 FXP_EEPROM_EEDO) == 0) 708 break; 709 DELAY(40); 710 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 711 DELAY(40); 712 } 713 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 714 DELAY(40); 715 if (x != 6 && x != 8) { 716 #ifdef DEBUG 717 printf("%s: strange EEPROM size (%d)\n", 718 sc->sc_dev.dv_xname, 1 << x); 719 #endif 720 } else 721 sc->sc_eeprom_size = x; 722 } 723 724 /* 725 * Read from the serial EEPROM. Basically, you manually shift in 726 * the read opcode (one bit at a time) and then shift in the address, 727 * and then you shift out the data (all of this one bit at a time). 728 * The word size is 16 bits, so you have to provide the address for 729 * every 16 bits of data. 730 */ 731 void 732 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 733 { 734 u_int16_t reg; 735 int i, x; 736 737 for (i = 0; i < words; i++) { 738 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 739 740 /* Shift in read opcode. */ 741 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 742 743 /* Shift in address. */ 744 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 745 746 reg = FXP_EEPROM_EECS; 747 data[i] = 0; 748 749 /* Shift out data. */ 750 for (x = 16; x > 0; x--) { 751 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 752 reg | FXP_EEPROM_EESK); 753 DELAY(40); 754 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 755 FXP_EEPROM_EEDO) 756 data[i] |= (1 << (x - 1)); 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 758 DELAY(40); 759 } 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 761 DELAY(40); 762 } 763 } 764 765 /* 766 * Write data to the serial EEPROM. 767 */ 768 void 769 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 770 { 771 int i, j; 772 773 for (i = 0; i < words; i++) { 774 /* Erase/write enable. */ 775 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 776 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 777 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 778 sc->sc_eeprom_size); 779 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 780 DELAY(4); 781 782 /* Shift in write opcode, address, data. */ 783 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 784 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 785 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 786 fxp_eeprom_shiftin(sc, data[i], 16); 787 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 788 DELAY(4); 789 790 /* Wait for the EEPROM to finish up. */ 791 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 792 DELAY(4); 793 for (j = 0; j < 1000; j++) { 794 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 795 FXP_EEPROM_EEDO) 796 break; 797 DELAY(50); 798 } 799 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 800 DELAY(4); 801 802 /* Erase/write disable. */ 803 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 804 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 805 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 806 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 807 DELAY(4); 808 } 809 } 810 811 /* 812 * Update the checksum of the EEPROM. 813 */ 814 void 815 fxp_eeprom_update_cksum(struct fxp_softc *sc) 816 { 817 int i; 818 uint16_t data, cksum; 819 820 cksum = 0; 821 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 822 fxp_read_eeprom(sc, &data, i, 1); 823 cksum += data; 824 } 825 i = (1 << sc->sc_eeprom_size) - 1; 826 cksum = 0xbaba - cksum; 827 fxp_read_eeprom(sc, &data, i, 1); 828 fxp_write_eeprom(sc, &cksum, i, 1); 829 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 830 sc->sc_dev.dv_xname, i, data, cksum); 831 } 832 833 /* 834 * Start packet transmission on the interface. 835 */ 836 void 837 fxp_start(struct ifnet *ifp) 838 { 839 struct fxp_softc *sc = ifp->if_softc; 840 struct mbuf *m0, *m; 841 struct fxp_txdesc *txd; 842 struct fxp_txsoft *txs; 843 bus_dmamap_t dmamap; 844 int error, lasttx, nexttx, opending, seg; 845 846 /* 847 * If we want a re-init, bail out now. 848 */ 849 if (sc->sc_flags & FXPF_WANTINIT) { 850 ifp->if_flags |= IFF_OACTIVE; 851 return; 852 } 853 854 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 855 return; 856 857 /* 858 * Remember the previous txpending and the current lasttx. 859 */ 860 opending = sc->sc_txpending; 861 lasttx = sc->sc_txlast; 862 863 /* 864 * Loop through the send queue, setting up transmit descriptors 865 * until we drain the queue, or use up all available transmit 866 * descriptors. 867 */ 868 for (;;) { 869 struct fxp_tbd *tbdp; 870 int csum_flags; 871 872 /* 873 * Grab a packet off the queue. 874 */ 875 IFQ_POLL(&ifp->if_snd, m0); 876 if (m0 == NULL) 877 break; 878 m = NULL; 879 880 if (sc->sc_txpending == FXP_NTXCB - 1) { 881 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 882 break; 883 } 884 885 /* 886 * Get the next available transmit descriptor. 887 */ 888 nexttx = FXP_NEXTTX(sc->sc_txlast); 889 txd = FXP_CDTX(sc, nexttx); 890 txs = FXP_DSTX(sc, nexttx); 891 dmamap = txs->txs_dmamap; 892 893 /* 894 * Load the DMA map. If this fails, the packet either 895 * didn't fit in the allotted number of frags, or we were 896 * short on resources. In this case, we'll copy and try 897 * again. 898 */ 899 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 900 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 901 MGETHDR(m, M_DONTWAIT, MT_DATA); 902 if (m == NULL) { 903 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 904 sc->sc_dev.dv_xname); 905 break; 906 } 907 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 908 if (m0->m_pkthdr.len > MHLEN) { 909 MCLGET(m, M_DONTWAIT); 910 if ((m->m_flags & M_EXT) == 0) { 911 log(LOG_ERR, 912 "%s: unable to allocate Tx " 913 "cluster\n", sc->sc_dev.dv_xname); 914 m_freem(m); 915 break; 916 } 917 } 918 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 919 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 920 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 921 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 922 if (error) { 923 log(LOG_ERR, "%s: unable to load Tx buffer, " 924 "error = %d\n", sc->sc_dev.dv_xname, error); 925 break; 926 } 927 } 928 929 IFQ_DEQUEUE(&ifp->if_snd, m0); 930 csum_flags = m0->m_pkthdr.csum_flags; 931 if (m != NULL) { 932 m_freem(m0); 933 m0 = m; 934 } 935 936 /* Initialize the fraglist. */ 937 tbdp = txd->txd_tbd; 938 if (sc->sc_flags & FXPF_IPCB) 939 tbdp++; 940 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 941 tbdp[seg].tb_addr = 942 htole32(dmamap->dm_segs[seg].ds_addr); 943 tbdp[seg].tb_size = 944 htole32(dmamap->dm_segs[seg].ds_len); 945 } 946 947 /* Sync the DMA map. */ 948 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 949 BUS_DMASYNC_PREWRITE); 950 951 /* 952 * Store a pointer to the packet so we can free it later. 953 */ 954 txs->txs_mbuf = m0; 955 956 /* 957 * Initialize the transmit descriptor. 958 */ 959 /* BIG_ENDIAN: no need to swap to store 0 */ 960 txd->txd_txcb.cb_status = 0; 961 txd->txd_txcb.cb_command = 962 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 963 txd->txd_txcb.tx_threshold = tx_threshold; 964 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 965 966 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 967 if (sc->sc_flags & FXPF_IPCB) { 968 struct m_tag *vtag; 969 struct fxp_ipcb *ipcb; 970 /* 971 * Deal with TCP/IP checksum offload. Note that 972 * in order for TCP checksum offload to work, 973 * the pseudo header checksum must have already 974 * been computed and stored in the checksum field 975 * in the TCP header. The stack should have 976 * already done this for us. 977 */ 978 ipcb = &txd->txd_u.txdu_ipcb; 979 memset(ipcb, 0, sizeof(*ipcb)); 980 /* 981 * always do hardware parsing. 982 */ 983 ipcb->ipcb_ip_activation_high = 984 FXP_IPCB_HARDWAREPARSING_ENABLE; 985 /* 986 * ip checksum offloading. 987 */ 988 if (csum_flags & M_CSUM_IPv4) { 989 ipcb->ipcb_ip_schedule |= 990 FXP_IPCB_IP_CHECKSUM_ENABLE; 991 } 992 /* 993 * TCP/UDP checksum offloading. 994 */ 995 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 996 ipcb->ipcb_ip_schedule |= 997 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 998 } 999 1000 /* 1001 * request VLAN tag insertion if needed. 1002 */ 1003 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 1004 if (vtag) { 1005 ipcb->ipcb_vlan_id = 1006 htobe16(*(u_int *)(vtag + 1)); 1007 ipcb->ipcb_ip_activation_high |= 1008 FXP_IPCB_INSERTVLAN_ENABLE; 1009 } 1010 } else { 1011 KASSERT((csum_flags & 1012 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1013 } 1014 1015 FXP_CDTXSYNC(sc, nexttx, 1016 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1017 1018 /* Advance the tx pointer. */ 1019 sc->sc_txpending++; 1020 sc->sc_txlast = nexttx; 1021 1022 #if NBPFILTER > 0 1023 /* 1024 * Pass packet to bpf if there is a listener. 1025 */ 1026 if (ifp->if_bpf) 1027 bpf_mtap(ifp->if_bpf, m0); 1028 #endif 1029 } 1030 1031 if (sc->sc_txpending == FXP_NTXCB - 1) { 1032 /* No more slots; notify upper layer. */ 1033 ifp->if_flags |= IFF_OACTIVE; 1034 } 1035 1036 if (sc->sc_txpending != opending) { 1037 /* 1038 * We enqueued packets. If the transmitter was idle, 1039 * reset the txdirty pointer. 1040 */ 1041 if (opending == 0) 1042 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1043 1044 /* 1045 * Cause the chip to interrupt and suspend command 1046 * processing once the last packet we've enqueued 1047 * has been transmitted. 1048 * 1049 * To avoid a race between updating status bits 1050 * by the fxp chip and clearing command bits 1051 * by this function on machines which don't have 1052 * atomic methods to clear/set bits in memory 1053 * smaller than 32bits (both cb_status and cb_command 1054 * members are uint16_t and in the same 32bit word), 1055 * we have to prepare a dummy TX descriptor which has 1056 * NOP command and just causes a TX completion interrupt. 1057 */ 1058 sc->sc_txpending++; 1059 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1060 txd = FXP_CDTX(sc, sc->sc_txlast); 1061 /* BIG_ENDIAN: no need to swap to store 0 */ 1062 txd->txd_txcb.cb_status = 0; 1063 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1064 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1065 FXP_CDTXSYNC(sc, sc->sc_txlast, 1066 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1067 1068 /* 1069 * The entire packet chain is set up. Clear the suspend bit 1070 * on the command prior to the first packet we set up. 1071 */ 1072 FXP_CDTXSYNC(sc, lasttx, 1073 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1074 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1075 htole16(~FXP_CB_COMMAND_S); 1076 FXP_CDTXSYNC(sc, lasttx, 1077 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1078 1079 /* 1080 * Issue a Resume command in case the chip was suspended. 1081 */ 1082 fxp_scb_wait(sc); 1083 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1084 1085 /* Set a watchdog timer in case the chip flakes out. */ 1086 ifp->if_timer = 5; 1087 } 1088 } 1089 1090 /* 1091 * Process interface interrupts. 1092 */ 1093 int 1094 fxp_intr(void *arg) 1095 { 1096 struct fxp_softc *sc = arg; 1097 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1098 bus_dmamap_t rxmap; 1099 int claimed = 0, rnr; 1100 u_int8_t statack; 1101 1102 if (!device_is_active(&sc->sc_dev) || sc->sc_enabled == 0) 1103 return (0); 1104 /* 1105 * If the interface isn't running, don't try to 1106 * service the interrupt.. just ack it and bail. 1107 */ 1108 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1109 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1110 if (statack) { 1111 claimed = 1; 1112 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1113 } 1114 return (claimed); 1115 } 1116 1117 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1118 claimed = 1; 1119 1120 /* 1121 * First ACK all the interrupts in this pass. 1122 */ 1123 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1124 1125 /* 1126 * Process receiver interrupts. If a no-resource (RNR) 1127 * condition exists, get whatever packets we can and 1128 * re-start the receiver. 1129 */ 1130 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1131 1 : 0; 1132 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1133 FXP_SCB_STATACK_SWI)) { 1134 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1135 rnr |= fxp_rxintr(sc); 1136 } 1137 1138 /* 1139 * Free any finished transmit mbuf chains. 1140 */ 1141 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1142 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1143 fxp_txintr(sc); 1144 1145 /* 1146 * Try to get more packets going. 1147 */ 1148 fxp_start(ifp); 1149 1150 if (sc->sc_txpending == 0) { 1151 /* 1152 * If we want a re-init, do that now. 1153 */ 1154 if (sc->sc_flags & FXPF_WANTINIT) 1155 (void) fxp_init(ifp); 1156 } 1157 } 1158 1159 if (rnr) { 1160 fxp_scb_wait(sc); 1161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1162 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1163 fxp_scb_wait(sc); 1164 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1165 rxmap->dm_segs[0].ds_addr + 1166 RFA_ALIGNMENT_FUDGE); 1167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1168 } 1169 } 1170 1171 #if NRND > 0 1172 if (claimed) 1173 rnd_add_uint32(&sc->rnd_source, statack); 1174 #endif 1175 return (claimed); 1176 } 1177 1178 /* 1179 * Handle transmit completion interrupts. 1180 */ 1181 void 1182 fxp_txintr(struct fxp_softc *sc) 1183 { 1184 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1185 struct fxp_txdesc *txd; 1186 struct fxp_txsoft *txs; 1187 int i; 1188 u_int16_t txstat; 1189 1190 ifp->if_flags &= ~IFF_OACTIVE; 1191 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1192 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1193 txd = FXP_CDTX(sc, i); 1194 txs = FXP_DSTX(sc, i); 1195 1196 FXP_CDTXSYNC(sc, i, 1197 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1198 1199 /* skip dummy NOP TX descriptor */ 1200 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1201 == FXP_CB_COMMAND_NOP) 1202 continue; 1203 1204 txstat = le16toh(txd->txd_txcb.cb_status); 1205 1206 if ((txstat & FXP_CB_STATUS_C) == 0) 1207 break; 1208 1209 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1210 0, txs->txs_dmamap->dm_mapsize, 1211 BUS_DMASYNC_POSTWRITE); 1212 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1213 m_freem(txs->txs_mbuf); 1214 txs->txs_mbuf = NULL; 1215 } 1216 1217 /* Update the dirty transmit buffer pointer. */ 1218 sc->sc_txdirty = i; 1219 1220 /* 1221 * Cancel the watchdog timer if there are no pending 1222 * transmissions. 1223 */ 1224 if (sc->sc_txpending == 0) 1225 ifp->if_timer = 0; 1226 } 1227 1228 /* 1229 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1230 */ 1231 1232 int 1233 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1234 { 1235 u_int16_t rxparsestat; 1236 u_int16_t csum_stat; 1237 u_int32_t csum_data; 1238 int csum_flags; 1239 1240 /* 1241 * check VLAN tag stripping. 1242 */ 1243 1244 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1245 struct m_tag *vtag; 1246 1247 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1248 if (vtag == NULL) 1249 return ENOMEM; 1250 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1251 m_tag_prepend(m, vtag); 1252 } 1253 1254 /* 1255 * check H/W Checksumming. 1256 */ 1257 1258 csum_stat = le16toh(rfa->cksum_stat); 1259 rxparsestat = le16toh(rfa->rx_parse_stat); 1260 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1261 return 0; 1262 1263 csum_flags = 0; 1264 csum_data = 0; 1265 1266 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1267 csum_flags = M_CSUM_IPv4; 1268 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1269 csum_flags |= M_CSUM_IPv4_BAD; 1270 } 1271 1272 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1273 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1274 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1275 csum_flags |= M_CSUM_TCP_UDP_BAD; 1276 } 1277 1278 m->m_pkthdr.csum_flags = csum_flags; 1279 m->m_pkthdr.csum_data = csum_data; 1280 1281 return 0; 1282 } 1283 1284 /* 1285 * Handle receive interrupts. 1286 */ 1287 int 1288 fxp_rxintr(struct fxp_softc *sc) 1289 { 1290 struct ethercom *ec = &sc->sc_ethercom; 1291 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1292 struct mbuf *m, *m0; 1293 bus_dmamap_t rxmap; 1294 struct fxp_rfa *rfa; 1295 int rnr; 1296 u_int16_t len, rxstat; 1297 1298 rnr = 0; 1299 1300 for (;;) { 1301 m = sc->sc_rxq.ifq_head; 1302 rfa = FXP_MTORFA(m); 1303 rxmap = M_GETCTX(m, bus_dmamap_t); 1304 1305 FXP_RFASYNC(sc, m, 1306 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1307 1308 rxstat = le16toh(rfa->rfa_status); 1309 1310 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1311 rnr = 1; 1312 1313 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1314 /* 1315 * We have processed all of the 1316 * receive buffers. 1317 */ 1318 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1319 return rnr; 1320 } 1321 1322 IF_DEQUEUE(&sc->sc_rxq, m); 1323 1324 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1325 1326 len = le16toh(rfa->actual_size) & 1327 (m->m_ext.ext_size - 1); 1328 1329 if (len < sizeof(struct ether_header)) { 1330 /* 1331 * Runt packet; drop it now. 1332 */ 1333 FXP_INIT_RFABUF(sc, m); 1334 continue; 1335 } 1336 1337 /* 1338 * If support for 802.1Q VLAN sized frames is 1339 * enabled, we need to do some additional error 1340 * checking (as we are saving bad frames, in 1341 * order to receive the larger ones). 1342 */ 1343 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1344 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1345 FXP_RFA_STATUS_RNR| 1346 FXP_RFA_STATUS_ALIGN| 1347 FXP_RFA_STATUS_CRC)) != 0) { 1348 FXP_INIT_RFABUF(sc, m); 1349 continue; 1350 } 1351 1352 /* Do checksum checking. */ 1353 m->m_pkthdr.csum_flags = 0; 1354 if (sc->sc_flags & FXPF_EXT_RFA) 1355 if (fxp_rx_hwcksum(m, rfa)) 1356 goto dropit; 1357 1358 /* 1359 * If the packet is small enough to fit in a 1360 * single header mbuf, allocate one and copy 1361 * the data into it. This greatly reduces 1362 * memory consumption when we receive lots 1363 * of small packets. 1364 * 1365 * Otherwise, we add a new buffer to the receive 1366 * chain. If this fails, we drop the packet and 1367 * recycle the old buffer. 1368 */ 1369 if (fxp_copy_small != 0 && len <= MHLEN) { 1370 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1371 if (m0 == NULL) 1372 goto dropit; 1373 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1374 memcpy(mtod(m0, void *), 1375 mtod(m, void *), len); 1376 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1377 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1378 FXP_INIT_RFABUF(sc, m); 1379 m = m0; 1380 } else { 1381 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1382 dropit: 1383 ifp->if_ierrors++; 1384 FXP_INIT_RFABUF(sc, m); 1385 continue; 1386 } 1387 } 1388 1389 m->m_pkthdr.rcvif = ifp; 1390 m->m_pkthdr.len = m->m_len = len; 1391 1392 #if NBPFILTER > 0 1393 /* 1394 * Pass this up to any BPF listeners, but only 1395 * pass it up the stack it its for us. 1396 */ 1397 if (ifp->if_bpf) 1398 bpf_mtap(ifp->if_bpf, m); 1399 #endif 1400 1401 /* Pass it on. */ 1402 (*ifp->if_input)(ifp, m); 1403 } 1404 } 1405 1406 /* 1407 * Update packet in/out/collision statistics. The i82557 doesn't 1408 * allow you to access these counters without doing a fairly 1409 * expensive DMA to get _all_ of the statistics it maintains, so 1410 * we do this operation here only once per second. The statistics 1411 * counters in the kernel are updated from the previous dump-stats 1412 * DMA and then a new dump-stats DMA is started. The on-chip 1413 * counters are zeroed when the DMA completes. If we can't start 1414 * the DMA immediately, we don't wait - we just prepare to read 1415 * them again next time. 1416 */ 1417 void 1418 fxp_tick(void *arg) 1419 { 1420 struct fxp_softc *sc = arg; 1421 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1422 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1423 int s; 1424 1425 if (!device_is_active(&sc->sc_dev)) 1426 return; 1427 1428 s = splnet(); 1429 1430 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1431 1432 ifp->if_opackets += le32toh(sp->tx_good); 1433 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1434 if (sp->rx_good) { 1435 ifp->if_ipackets += le32toh(sp->rx_good); 1436 sc->sc_rxidle = 0; 1437 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1438 sc->sc_rxidle++; 1439 } 1440 ifp->if_ierrors += 1441 le32toh(sp->rx_crc_errors) + 1442 le32toh(sp->rx_alignment_errors) + 1443 le32toh(sp->rx_rnr_errors) + 1444 le32toh(sp->rx_overrun_errors); 1445 /* 1446 * If any transmit underruns occurred, bump up the transmit 1447 * threshold by another 512 bytes (64 * 8). 1448 */ 1449 if (sp->tx_underruns) { 1450 ifp->if_oerrors += le32toh(sp->tx_underruns); 1451 if (tx_threshold < 192) 1452 tx_threshold += 64; 1453 } 1454 #ifdef FXP_EVENT_COUNTERS 1455 if (sc->sc_rev >= FXP_REV_82558_A4) { 1456 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1457 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1458 } 1459 #endif 1460 1461 /* 1462 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1463 * then assume the receiver has locked up and attempt to clear 1464 * the condition by reprogramming the multicast filter (actually, 1465 * resetting the interface). This is a work-around for a bug in 1466 * the 82557 where the receiver locks up if it gets certain types 1467 * of garbage in the synchronization bits prior to the packet header. 1468 * This bug is supposed to only occur in 10Mbps mode, but has been 1469 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1470 * speed transition). 1471 */ 1472 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1473 (void) fxp_init(ifp); 1474 splx(s); 1475 return; 1476 } 1477 /* 1478 * If there is no pending command, start another stats 1479 * dump. Otherwise punt for now. 1480 */ 1481 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1482 /* 1483 * Start another stats dump. 1484 */ 1485 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1486 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1487 } else { 1488 /* 1489 * A previous command is still waiting to be accepted. 1490 * Just zero our copy of the stats and wait for the 1491 * next timer event to update them. 1492 */ 1493 /* BIG_ENDIAN: no swap required to store 0 */ 1494 sp->tx_good = 0; 1495 sp->tx_underruns = 0; 1496 sp->tx_total_collisions = 0; 1497 1498 sp->rx_good = 0; 1499 sp->rx_crc_errors = 0; 1500 sp->rx_alignment_errors = 0; 1501 sp->rx_rnr_errors = 0; 1502 sp->rx_overrun_errors = 0; 1503 if (sc->sc_rev >= FXP_REV_82558_A4) { 1504 sp->tx_pauseframes = 0; 1505 sp->rx_pauseframes = 0; 1506 } 1507 } 1508 1509 if (sc->sc_flags & FXPF_MII) { 1510 /* Tick the MII clock. */ 1511 mii_tick(&sc->sc_mii); 1512 } 1513 1514 splx(s); 1515 1516 /* 1517 * Schedule another timeout one second from now. 1518 */ 1519 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1520 } 1521 1522 /* 1523 * Drain the receive queue. 1524 */ 1525 void 1526 fxp_rxdrain(struct fxp_softc *sc) 1527 { 1528 bus_dmamap_t rxmap; 1529 struct mbuf *m; 1530 1531 for (;;) { 1532 IF_DEQUEUE(&sc->sc_rxq, m); 1533 if (m == NULL) 1534 break; 1535 rxmap = M_GETCTX(m, bus_dmamap_t); 1536 bus_dmamap_unload(sc->sc_dmat, rxmap); 1537 FXP_RXMAP_PUT(sc, rxmap); 1538 m_freem(m); 1539 } 1540 } 1541 1542 /* 1543 * Stop the interface. Cancels the statistics updater and resets 1544 * the interface. 1545 */ 1546 void 1547 fxp_stop(struct ifnet *ifp, int disable) 1548 { 1549 struct fxp_softc *sc = ifp->if_softc; 1550 struct fxp_txsoft *txs; 1551 int i; 1552 1553 /* 1554 * Turn down interface (done early to avoid bad interactions 1555 * between panics, shutdown hooks, and the watchdog timer) 1556 */ 1557 ifp->if_timer = 0; 1558 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1559 1560 /* 1561 * Cancel stats updater. 1562 */ 1563 callout_stop(&sc->sc_callout); 1564 if (sc->sc_flags & FXPF_MII) { 1565 /* Down the MII. */ 1566 mii_down(&sc->sc_mii); 1567 } 1568 1569 /* 1570 * Issue software reset. This unloads any microcode that 1571 * might already be loaded. 1572 */ 1573 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1574 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1575 DELAY(50); 1576 1577 /* 1578 * Release any xmit buffers. 1579 */ 1580 for (i = 0; i < FXP_NTXCB; i++) { 1581 txs = FXP_DSTX(sc, i); 1582 if (txs->txs_mbuf != NULL) { 1583 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1584 m_freem(txs->txs_mbuf); 1585 txs->txs_mbuf = NULL; 1586 } 1587 } 1588 sc->sc_txpending = 0; 1589 1590 if (disable) { 1591 fxp_rxdrain(sc); 1592 fxp_disable(sc); 1593 } 1594 1595 } 1596 1597 /* 1598 * Watchdog/transmission transmit timeout handler. Called when a 1599 * transmission is started on the interface, but no interrupt is 1600 * received before the timeout. This usually indicates that the 1601 * card has wedged for some reason. 1602 */ 1603 void 1604 fxp_watchdog(struct ifnet *ifp) 1605 { 1606 struct fxp_softc *sc = ifp->if_softc; 1607 1608 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1609 ifp->if_oerrors++; 1610 1611 (void) fxp_init(ifp); 1612 } 1613 1614 /* 1615 * Initialize the interface. Must be called at splnet(). 1616 */ 1617 int 1618 fxp_init(struct ifnet *ifp) 1619 { 1620 struct fxp_softc *sc = ifp->if_softc; 1621 struct fxp_cb_config *cbp; 1622 struct fxp_cb_ias *cb_ias; 1623 struct fxp_txdesc *txd; 1624 bus_dmamap_t rxmap; 1625 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1626 1627 if ((error = fxp_enable(sc)) != 0) 1628 goto out; 1629 1630 /* 1631 * Cancel any pending I/O 1632 */ 1633 fxp_stop(ifp, 0); 1634 1635 /* 1636 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1637 * flag, and this prevents the MII from detaching resulting in 1638 * a panic. The flags field should perhaps be split in runtime 1639 * flags and more static information. For now, just clear the 1640 * only other flag set. 1641 */ 1642 1643 sc->sc_flags &= ~FXPF_WANTINIT; 1644 1645 /* 1646 * Initialize base of CBL and RFA memory. Loading with zero 1647 * sets it up for regular linear addressing. 1648 */ 1649 fxp_scb_wait(sc); 1650 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1651 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1652 1653 fxp_scb_wait(sc); 1654 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1655 1656 /* 1657 * Initialize the multicast filter. Do this now, since we might 1658 * have to setup the config block differently. 1659 */ 1660 fxp_mc_setup(sc); 1661 1662 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1663 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1664 1665 /* 1666 * In order to support receiving 802.1Q VLAN frames, we have to 1667 * enable "save bad frames", since they are 4 bytes larger than 1668 * the normal Ethernet maximum frame length. On i82558 and later, 1669 * we have a better mechanism for this. 1670 */ 1671 save_bf = 0; 1672 lrxen = 0; 1673 vlan_drop = 0; 1674 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1675 if (sc->sc_rev < FXP_REV_82558_A4) 1676 save_bf = 1; 1677 else 1678 lrxen = 1; 1679 if (sc->sc_rev >= FXP_REV_82550) 1680 vlan_drop = 1; 1681 } 1682 1683 /* 1684 * Initialize base of dump-stats buffer. 1685 */ 1686 fxp_scb_wait(sc); 1687 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1688 sc->sc_cddma + FXP_CDSTATSOFF); 1689 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1690 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1691 1692 cbp = &sc->sc_control_data->fcd_configcb; 1693 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1694 1695 /* 1696 * Load microcode for this controller. 1697 */ 1698 fxp_load_ucode(sc); 1699 1700 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1701 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1702 else 1703 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1704 1705 /* 1706 * This copy is kind of disgusting, but there are a bunch of must be 1707 * zero and must be one bits in this structure and this is the easiest 1708 * way to initialize them all to proper values. 1709 */ 1710 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1711 1712 /* BIG_ENDIAN: no need to swap to store 0 */ 1713 cbp->cb_status = 0; 1714 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1715 FXP_CB_COMMAND_EL); 1716 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1717 cbp->link_addr = 0xffffffff; /* (no) next command */ 1718 /* bytes in config block */ 1719 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1720 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1721 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1722 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1723 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1724 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1725 cbp->type_enable = 0; /* actually reserved */ 1726 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1727 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1728 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1729 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1730 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1731 cbp->late_scb = 0; /* (don't) defer SCB update */ 1732 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1733 cbp->ci_int = 1; /* interrupt on CU idle */ 1734 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1735 cbp->ext_stats_dis = 1; /* disable extended counters */ 1736 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1737 cbp->save_bf = save_bf;/* save bad frames */ 1738 cbp->disc_short_rx = !prm; /* discard short packets */ 1739 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1740 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1741 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1742 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1743 /* interface mode */ 1744 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1745 cbp->csma_dis = 0; /* (don't) disable link */ 1746 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1747 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1748 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1749 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1750 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1751 cbp->nsai = 1; /* (don't) disable source addr insert */ 1752 cbp->preamble_length = 2; /* (7 byte) preamble */ 1753 cbp->loopback = 0; /* (don't) loopback */ 1754 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1755 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1756 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1757 cbp->promiscuous = prm; /* promiscuous mode */ 1758 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1759 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1760 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1761 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1762 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1763 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1764 cbp->padding = 1; /* (do) pad short tx packets */ 1765 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1766 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1767 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1768 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1769 /* must set wake_en in PMCSR also */ 1770 cbp->force_fdx = 0; /* (don't) force full duplex */ 1771 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1772 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1773 cbp->mc_all = allm; /* accept all multicasts */ 1774 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1775 cbp->vlan_drop_en = vlan_drop; 1776 1777 if (sc->sc_rev < FXP_REV_82558_A4) { 1778 /* 1779 * The i82557 has no hardware flow control, the values 1780 * here are the defaults for the chip. 1781 */ 1782 cbp->fc_delay_lsb = 0; 1783 cbp->fc_delay_msb = 0x40; 1784 cbp->pri_fc_thresh = 3; 1785 cbp->tx_fc_dis = 0; 1786 cbp->rx_fc_restop = 0; 1787 cbp->rx_fc_restart = 0; 1788 cbp->fc_filter = 0; 1789 cbp->pri_fc_loc = 1; 1790 } else { 1791 cbp->fc_delay_lsb = 0x1f; 1792 cbp->fc_delay_msb = 0x01; 1793 cbp->pri_fc_thresh = 3; 1794 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1795 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1796 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1797 cbp->fc_filter = !prm; /* drop FC frames to host */ 1798 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1799 cbp->ext_stats_dis = 0; /* enable extended stats */ 1800 } 1801 1802 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1803 1804 /* 1805 * Start the config command/DMA. 1806 */ 1807 fxp_scb_wait(sc); 1808 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1809 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1810 /* ...and wait for it to complete. */ 1811 i = 1000; 1812 do { 1813 FXP_CDCONFIGSYNC(sc, 1814 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1815 DELAY(1); 1816 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1817 if (i == 0) { 1818 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1819 sc->sc_dev.dv_xname, __LINE__); 1820 return (ETIMEDOUT); 1821 } 1822 1823 /* 1824 * Initialize the station address. 1825 */ 1826 cb_ias = &sc->sc_control_data->fcd_iascb; 1827 /* BIG_ENDIAN: no need to swap to store 0 */ 1828 cb_ias->cb_status = 0; 1829 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1830 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1831 cb_ias->link_addr = 0xffffffff; 1832 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1833 1834 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1835 1836 /* 1837 * Start the IAS (Individual Address Setup) command/DMA. 1838 */ 1839 fxp_scb_wait(sc); 1840 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1841 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1842 /* ...and wait for it to complete. */ 1843 i = 1000; 1844 do { 1845 FXP_CDIASSYNC(sc, 1846 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1847 DELAY(1); 1848 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1849 if (i == 0) { 1850 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1851 sc->sc_dev.dv_xname, __LINE__); 1852 return (ETIMEDOUT); 1853 } 1854 1855 /* 1856 * Initialize the transmit descriptor ring. txlast is initialized 1857 * to the end of the list so that it will wrap around to the first 1858 * descriptor when the first packet is transmitted. 1859 */ 1860 for (i = 0; i < FXP_NTXCB; i++) { 1861 txd = FXP_CDTX(sc, i); 1862 memset(txd, 0, sizeof(*txd)); 1863 txd->txd_txcb.cb_command = 1864 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1865 txd->txd_txcb.link_addr = 1866 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1867 if (sc->sc_flags & FXPF_EXT_TXCB) 1868 txd->txd_txcb.tbd_array_addr = 1869 htole32(FXP_CDTBDADDR(sc, i) + 1870 (2 * sizeof(struct fxp_tbd))); 1871 else 1872 txd->txd_txcb.tbd_array_addr = 1873 htole32(FXP_CDTBDADDR(sc, i)); 1874 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1875 } 1876 sc->sc_txpending = 0; 1877 sc->sc_txdirty = 0; 1878 sc->sc_txlast = FXP_NTXCB - 1; 1879 1880 /* 1881 * Initialize the receive buffer list. 1882 */ 1883 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1884 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1885 rxmap = FXP_RXMAP_GET(sc); 1886 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1887 log(LOG_ERR, "%s: unable to allocate or map rx " 1888 "buffer %d, error = %d\n", 1889 sc->sc_dev.dv_xname, 1890 sc->sc_rxq.ifq_len, error); 1891 /* 1892 * XXX Should attempt to run with fewer receive 1893 * XXX buffers instead of just failing. 1894 */ 1895 FXP_RXMAP_PUT(sc, rxmap); 1896 fxp_rxdrain(sc); 1897 goto out; 1898 } 1899 } 1900 sc->sc_rxidle = 0; 1901 1902 /* 1903 * Give the transmit ring to the chip. We do this by pointing 1904 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1905 * issuing a start command. It will execute the NOP and then 1906 * suspend, pointing at the first descriptor. 1907 */ 1908 fxp_scb_wait(sc); 1909 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1910 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1911 1912 /* 1913 * Initialize receiver buffer area - RFA. 1914 */ 1915 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1916 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1917 fxp_scb_wait(sc); 1918 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1919 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1920 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1921 #endif 1922 1923 if (sc->sc_flags & FXPF_MII) { 1924 /* 1925 * Set current media. 1926 */ 1927 mii_mediachg(&sc->sc_mii); 1928 } 1929 1930 /* 1931 * ...all done! 1932 */ 1933 ifp->if_flags |= IFF_RUNNING; 1934 ifp->if_flags &= ~IFF_OACTIVE; 1935 1936 /* 1937 * Request a software generated interrupt that will be used to 1938 * (re)start the RU processing. If we direct the chip to start 1939 * receiving from the start of queue now, instead of letting the 1940 * interrupt handler first process all received packets, we run 1941 * the risk of having it overwrite mbuf clusters while they are 1942 * being processed or after they have been returned to the pool. 1943 */ 1944 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1945 1946 /* 1947 * Start the one second timer. 1948 */ 1949 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1950 1951 /* 1952 * Attempt to start output on the interface. 1953 */ 1954 fxp_start(ifp); 1955 1956 out: 1957 if (error) { 1958 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1959 ifp->if_timer = 0; 1960 log(LOG_ERR, "%s: interface not running\n", 1961 sc->sc_dev.dv_xname); 1962 } 1963 return (error); 1964 } 1965 1966 /* 1967 * Change media according to request. 1968 */ 1969 int 1970 fxp_mii_mediachange(struct ifnet *ifp) 1971 { 1972 struct fxp_softc *sc = ifp->if_softc; 1973 1974 if (ifp->if_flags & IFF_UP) 1975 mii_mediachg(&sc->sc_mii); 1976 return (0); 1977 } 1978 1979 /* 1980 * Notify the world which media we're using. 1981 */ 1982 void 1983 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1984 { 1985 struct fxp_softc *sc = ifp->if_softc; 1986 1987 if (sc->sc_enabled == 0) { 1988 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1989 ifmr->ifm_status = 0; 1990 return; 1991 } 1992 1993 mii_pollstat(&sc->sc_mii); 1994 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1995 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1996 1997 /* 1998 * XXX Flow control is always turned on if the chip supports 1999 * XXX it; we can't easily control it dynamically, since it 2000 * XXX requires sending a setup packet. 2001 */ 2002 if (sc->sc_rev >= FXP_REV_82558_A4) 2003 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 2004 } 2005 2006 int 2007 fxp_80c24_mediachange(struct ifnet *ifp) 2008 { 2009 2010 /* Nothing to do here. */ 2011 return (0); 2012 } 2013 2014 void 2015 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2016 { 2017 struct fxp_softc *sc = ifp->if_softc; 2018 2019 /* 2020 * Media is currently-selected media. We cannot determine 2021 * the link status. 2022 */ 2023 ifmr->ifm_status = 0; 2024 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2025 } 2026 2027 /* 2028 * Add a buffer to the end of the RFA buffer list. 2029 * Return 0 if successful, error code on failure. 2030 * 2031 * The RFA struct is stuck at the beginning of mbuf cluster and the 2032 * data pointer is fixed up to point just past it. 2033 */ 2034 int 2035 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2036 { 2037 struct mbuf *m; 2038 int error; 2039 2040 MGETHDR(m, M_DONTWAIT, MT_DATA); 2041 if (m == NULL) 2042 return (ENOBUFS); 2043 2044 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2045 MCLGET(m, M_DONTWAIT); 2046 if ((m->m_flags & M_EXT) == 0) { 2047 m_freem(m); 2048 return (ENOBUFS); 2049 } 2050 2051 if (unload) 2052 bus_dmamap_unload(sc->sc_dmat, rxmap); 2053 2054 M_SETCTX(m, rxmap); 2055 2056 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2057 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2058 BUS_DMA_READ|BUS_DMA_NOWAIT); 2059 if (error) { 2060 /* XXX XXX XXX */ 2061 printf("%s: can't load rx DMA map %d, error = %d\n", 2062 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2063 panic("fxp_add_rfabuf"); 2064 } 2065 2066 FXP_INIT_RFABUF(sc, m); 2067 2068 return (0); 2069 } 2070 2071 int 2072 fxp_mdi_read(struct device *self, int phy, int reg) 2073 { 2074 struct fxp_softc *sc = (struct fxp_softc *)self; 2075 int count = 10000; 2076 int value; 2077 2078 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2079 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2080 2081 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2082 0x10000000) == 0 && count--) 2083 DELAY(10); 2084 2085 if (count <= 0) 2086 log(LOG_WARNING, 2087 "%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2088 2089 return (value & 0xffff); 2090 } 2091 2092 void 2093 fxp_statchg(struct device *self) 2094 { 2095 2096 /* Nothing to do. */ 2097 } 2098 2099 void 2100 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2101 { 2102 struct fxp_softc *sc = (struct fxp_softc *)self; 2103 int count = 10000; 2104 2105 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2106 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2107 (value & 0xffff)); 2108 2109 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2110 count--) 2111 DELAY(10); 2112 2113 if (count <= 0) 2114 log(LOG_WARNING, 2115 "%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2116 } 2117 2118 int 2119 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2120 { 2121 struct fxp_softc *sc = ifp->if_softc; 2122 struct ifreq *ifr = (struct ifreq *)data; 2123 int s, error; 2124 2125 s = splnet(); 2126 2127 switch (cmd) { 2128 case SIOCSIFMEDIA: 2129 case SIOCGIFMEDIA: 2130 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2131 break; 2132 2133 default: 2134 error = ether_ioctl(ifp, cmd, data); 2135 if (error == ENETRESET) { 2136 if (ifp->if_flags & IFF_RUNNING) { 2137 /* 2138 * Multicast list has changed; set the 2139 * hardware filter accordingly. 2140 */ 2141 if (sc->sc_txpending) { 2142 sc->sc_flags |= FXPF_WANTINIT; 2143 error = 0; 2144 } else 2145 error = fxp_init(ifp); 2146 } else 2147 error = 0; 2148 } 2149 break; 2150 } 2151 2152 /* Try to get more packets going. */ 2153 if (sc->sc_enabled) 2154 fxp_start(ifp); 2155 2156 splx(s); 2157 return (error); 2158 } 2159 2160 /* 2161 * Program the multicast filter. 2162 * 2163 * This function must be called at splnet(). 2164 */ 2165 void 2166 fxp_mc_setup(struct fxp_softc *sc) 2167 { 2168 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2170 struct ethercom *ec = &sc->sc_ethercom; 2171 struct ether_multi *enm; 2172 struct ether_multistep step; 2173 int count, nmcasts; 2174 2175 #ifdef DIAGNOSTIC 2176 if (sc->sc_txpending) 2177 panic("fxp_mc_setup: pending transmissions"); 2178 #endif 2179 2180 ifp->if_flags &= ~IFF_ALLMULTI; 2181 2182 /* 2183 * Initialize multicast setup descriptor. 2184 */ 2185 nmcasts = 0; 2186 ETHER_FIRST_MULTI(step, ec, enm); 2187 while (enm != NULL) { 2188 /* 2189 * Check for too many multicast addresses or if we're 2190 * listening to a range. Either way, we simply have 2191 * to accept all multicasts. 2192 */ 2193 if (nmcasts >= MAXMCADDR || 2194 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2195 ETHER_ADDR_LEN) != 0) { 2196 /* 2197 * Callers of this function must do the 2198 * right thing with this. If we're called 2199 * from outside fxp_init(), the caller must 2200 * detect if the state if IFF_ALLMULTI changes. 2201 * If it does, the caller must then call 2202 * fxp_init(), since allmulti is handled by 2203 * the config block. 2204 */ 2205 ifp->if_flags |= IFF_ALLMULTI; 2206 return; 2207 } 2208 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2209 ETHER_ADDR_LEN); 2210 nmcasts++; 2211 ETHER_NEXT_MULTI(step, enm); 2212 } 2213 2214 /* BIG_ENDIAN: no need to swap to store 0 */ 2215 mcsp->cb_status = 0; 2216 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2217 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2218 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2219 2220 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2221 2222 /* 2223 * Wait until the command unit is not active. This should never 2224 * happen since nothing is queued, but make sure anyway. 2225 */ 2226 count = 100; 2227 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2228 FXP_SCB_CUS_ACTIVE && --count) 2229 DELAY(1); 2230 if (count == 0) { 2231 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2232 sc->sc_dev.dv_xname, __LINE__); 2233 return; 2234 } 2235 2236 /* 2237 * Start the multicast setup command/DMA. 2238 */ 2239 fxp_scb_wait(sc); 2240 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2241 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2242 2243 /* ...and wait for it to complete. */ 2244 count = 1000; 2245 do { 2246 FXP_CDMCSSYNC(sc, 2247 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2248 DELAY(1); 2249 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2250 if (count == 0) { 2251 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2252 sc->sc_dev.dv_xname, __LINE__); 2253 return; 2254 } 2255 } 2256 2257 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2258 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2259 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2260 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2261 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2262 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2263 2264 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2265 2266 static const struct ucode { 2267 int32_t revision; 2268 const uint32_t *ucode; 2269 size_t length; 2270 uint16_t int_delay_offset; 2271 uint16_t bundle_max_offset; 2272 } ucode_table[] = { 2273 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2274 D101_CPUSAVER_DWORD, 0 }, 2275 2276 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2277 D101_CPUSAVER_DWORD, 0 }, 2278 2279 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2280 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2281 2282 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2283 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2284 2285 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2286 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2287 2288 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2289 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2290 2291 { 0, NULL, 0, 0, 0 } 2292 }; 2293 2294 void 2295 fxp_load_ucode(struct fxp_softc *sc) 2296 { 2297 const struct ucode *uc; 2298 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2299 int count, i; 2300 2301 if (sc->sc_flags & FXPF_UCODE_LOADED) 2302 return; 2303 2304 /* 2305 * Only load the uCode if the user has requested that 2306 * we do so. 2307 */ 2308 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2309 sc->sc_int_delay = 0; 2310 sc->sc_bundle_max = 0; 2311 return; 2312 } 2313 2314 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2315 if (sc->sc_rev == uc->revision) 2316 break; 2317 } 2318 if (uc->ucode == NULL) 2319 return; 2320 2321 /* BIG ENDIAN: no need to swap to store 0 */ 2322 cbp->cb_status = 0; 2323 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2324 cbp->link_addr = 0xffffffff; /* (no) next command */ 2325 for (i = 0; i < uc->length; i++) 2326 cbp->ucode[i] = htole32(uc->ucode[i]); 2327 2328 if (uc->int_delay_offset) 2329 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2330 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2331 2332 if (uc->bundle_max_offset) 2333 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2334 htole16(fxp_bundle_max); 2335 2336 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2337 2338 /* 2339 * Download the uCode to the chip. 2340 */ 2341 fxp_scb_wait(sc); 2342 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2343 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2344 2345 /* ...and wait for it to complete. */ 2346 count = 10000; 2347 do { 2348 FXP_CDUCODESYNC(sc, 2349 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2350 DELAY(2); 2351 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2352 if (count == 0) { 2353 sc->sc_int_delay = 0; 2354 sc->sc_bundle_max = 0; 2355 log(LOG_WARNING, "%s: timeout loading microcode\n", 2356 sc->sc_dev.dv_xname); 2357 return; 2358 } 2359 2360 if (sc->sc_int_delay != fxp_int_delay || 2361 sc->sc_bundle_max != fxp_bundle_max) { 2362 sc->sc_int_delay = fxp_int_delay; 2363 sc->sc_bundle_max = fxp_bundle_max; 2364 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2365 "max bundle: %d\n", sc->sc_dev.dv_xname, 2366 sc->sc_int_delay, 2367 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2368 } 2369 2370 sc->sc_flags |= FXPF_UCODE_LOADED; 2371 } 2372 2373 int 2374 fxp_enable(struct fxp_softc *sc) 2375 { 2376 2377 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2378 if ((*sc->sc_enable)(sc) != 0) { 2379 log(LOG_ERR, "%s: device enable failed\n", 2380 sc->sc_dev.dv_xname); 2381 return (EIO); 2382 } 2383 } 2384 2385 sc->sc_enabled = 1; 2386 return (0); 2387 } 2388 2389 void 2390 fxp_disable(struct fxp_softc *sc) 2391 { 2392 2393 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2394 (*sc->sc_disable)(sc); 2395 sc->sc_enabled = 0; 2396 } 2397 } 2398 2399 /* 2400 * fxp_activate: 2401 * 2402 * Handle device activation/deactivation requests. 2403 */ 2404 int 2405 fxp_activate(struct device *self, enum devact act) 2406 { 2407 struct fxp_softc *sc = (void *) self; 2408 int s, error = 0; 2409 2410 s = splnet(); 2411 switch (act) { 2412 case DVACT_ACTIVATE: 2413 error = EOPNOTSUPP; 2414 break; 2415 2416 case DVACT_DEACTIVATE: 2417 if (sc->sc_flags & FXPF_MII) 2418 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2419 MII_OFFSET_ANY); 2420 if_deactivate(&sc->sc_ethercom.ec_if); 2421 break; 2422 } 2423 splx(s); 2424 2425 return (error); 2426 } 2427 2428 /* 2429 * fxp_detach: 2430 * 2431 * Detach an i82557 interface. 2432 */ 2433 int 2434 fxp_detach(struct fxp_softc *sc) 2435 { 2436 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2437 int i; 2438 2439 /* Succeed now if there's no work to do. */ 2440 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2441 return (0); 2442 2443 /* Unhook our tick handler. */ 2444 callout_stop(&sc->sc_callout); 2445 2446 if (sc->sc_flags & FXPF_MII) { 2447 /* Detach all PHYs */ 2448 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2449 } 2450 2451 /* Delete all remaining media. */ 2452 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2453 2454 #if NRND > 0 2455 rnd_detach_source(&sc->rnd_source); 2456 #endif 2457 ether_ifdetach(ifp); 2458 if_detach(ifp); 2459 2460 for (i = 0; i < FXP_NRFABUFS; i++) { 2461 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2462 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2463 } 2464 2465 for (i = 0; i < FXP_NTXCB; i++) { 2466 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2467 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2468 } 2469 2470 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2471 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2472 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2473 sizeof(struct fxp_control_data)); 2474 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2475 2476 shutdownhook_disestablish(sc->sc_sdhook); 2477 2478 return (0); 2479 } 2480
Indexes created Tue Oct 28 12:10:06 GMT 2025