i82557.c revision 1.109
1 /* $NetBSD: i82557.c,v 1.109 2007/12/29 17:59:20 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.109 2007/12/29 17:59:20 tsutsui Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 int fxp_mii_mediachange(struct ifnet *); 179 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 180 181 void fxp_80c24_initmedia(struct fxp_softc *); 182 int fxp_80c24_mediachange(struct ifnet *); 183 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 184 185 void fxp_start(struct ifnet *); 186 int fxp_ioctl(struct ifnet *, u_long, void *); 187 void fxp_watchdog(struct ifnet *); 188 int fxp_init(struct ifnet *); 189 void fxp_stop(struct ifnet *, int); 190 191 void fxp_txintr(struct fxp_softc *); 192 int fxp_rxintr(struct fxp_softc *); 193 194 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 195 196 void fxp_rxdrain(struct fxp_softc *); 197 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 198 int fxp_mdi_read(struct device *, int, int); 199 void fxp_statchg(struct device *); 200 void fxp_mdi_write(struct device *, int, int, int); 201 void fxp_autosize_eeprom(struct fxp_softc*); 202 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 204 void fxp_eeprom_update_cksum(struct fxp_softc *); 205 void fxp_get_info(struct fxp_softc *, u_int8_t *); 206 void fxp_tick(void *); 207 void fxp_mc_setup(struct fxp_softc *); 208 void fxp_load_ucode(struct fxp_softc *); 209 210 int fxp_copy_small = 0; 211 212 /* 213 * Variables for interrupt mitigating microcode. 214 */ 215 int fxp_int_delay = 1000; /* usec */ 216 int fxp_bundle_max = 6; /* packets */ 217 218 struct fxp_phytype { 219 int fp_phy; /* type of PHY, -1 for MII at the end. */ 220 void (*fp_init)(struct fxp_softc *); 221 } fxp_phytype_table[] = { 222 { FXP_PHY_80C24, fxp_80c24_initmedia }, 223 { -1, fxp_mii_initmedia }, 224 }; 225 226 /* 227 * Set initial transmit threshold at 64 (512 bytes). This is 228 * increased by 64 (512 bytes) at a time, to maximum of 192 229 * (1536 bytes), if an underrun occurs. 230 */ 231 static int tx_threshold = 64; 232 233 /* 234 * Wait for the previous command to be accepted (but not necessarily 235 * completed). 236 */ 237 static inline void 238 fxp_scb_wait(struct fxp_softc *sc) 239 { 240 int i = 10000; 241 242 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 243 delay(2); 244 if (i == 0) 245 log(LOG_WARNING, 246 "%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 247 } 248 249 /* 250 * Submit a command to the i82557. 251 */ 252 static inline void 253 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 254 { 255 256 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 257 } 258 259 /* 260 * Finish attaching an i82557 interface. Called by bus-specific front-end. 261 */ 262 void 263 fxp_attach(struct fxp_softc *sc) 264 { 265 u_int8_t enaddr[ETHER_ADDR_LEN]; 266 struct ifnet *ifp; 267 bus_dma_segment_t seg; 268 int rseg, i, error; 269 struct fxp_phytype *fp; 270 271 callout_init(&sc->sc_callout, 0); 272 273 /* 274 * Enable some good stuff on i82558 and later. 275 */ 276 if (sc->sc_rev >= FXP_REV_82558_A4) { 277 /* Enable the extended TxCB. */ 278 sc->sc_flags |= FXPF_EXT_TXCB; 279 } 280 281 /* 282 * Enable use of extended RFDs and TCBs for 82550 283 * and later chips. Note: we need extended TXCB support 284 * too, but that's already enabled by the code above. 285 * Be careful to do this only on the right devices. 286 */ 287 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 288 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 289 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 290 } else { 291 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 292 } 293 294 sc->sc_rfa_size = 295 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 296 297 /* 298 * Allocate the control data structures, and create and load the 299 * DMA map for it. 300 */ 301 if ((error = bus_dmamem_alloc(sc->sc_dmat, 302 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 303 0)) != 0) { 304 aprint_error( 305 "%s: unable to allocate control data, error = %d\n", 306 sc->sc_dev.dv_xname, error); 307 goto fail_0; 308 } 309 310 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 311 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 312 BUS_DMA_COHERENT)) != 0) { 313 aprint_error("%s: unable to map control data, error = %d\n", 314 sc->sc_dev.dv_xname, error); 315 goto fail_1; 316 } 317 sc->sc_cdseg = seg; 318 sc->sc_cdnseg = rseg; 319 320 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 321 322 if ((error = bus_dmamap_create(sc->sc_dmat, 323 sizeof(struct fxp_control_data), 1, 324 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 325 aprint_error("%s: unable to create control data DMA map, " 326 "error = %d\n", sc->sc_dev.dv_xname, error); 327 goto fail_2; 328 } 329 330 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 331 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 332 0)) != 0) { 333 aprint_error( 334 "%s: can't load control data DMA map, error = %d\n", 335 sc->sc_dev.dv_xname, error); 336 goto fail_3; 337 } 338 339 /* 340 * Create the transmit buffer DMA maps. 341 */ 342 for (i = 0; i < FXP_NTXCB; i++) { 343 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 344 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 345 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 346 aprint_error("%s: unable to create tx DMA map %d, " 347 "error = %d\n", sc->sc_dev.dv_xname, i, error); 348 goto fail_4; 349 } 350 } 351 352 /* 353 * Create the receive buffer DMA maps. 354 */ 355 for (i = 0; i < FXP_NRFABUFS; i++) { 356 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 357 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 358 aprint_error("%s: unable to create rx DMA map %d, " 359 "error = %d\n", sc->sc_dev.dv_xname, i, error); 360 goto fail_5; 361 } 362 } 363 364 /* Initialize MAC address and media structures. */ 365 fxp_get_info(sc, enaddr); 366 367 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 368 ether_sprintf(enaddr)); 369 370 ifp = &sc->sc_ethercom.ec_if; 371 372 /* 373 * Get info about our media interface, and initialize it. Note 374 * the table terminates itself with a phy of -1, indicating 375 * that we're using MII. 376 */ 377 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 378 if (fp->fp_phy == sc->phy_primary_device) 379 break; 380 (*fp->fp_init)(sc); 381 382 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 383 ifp->if_softc = sc; 384 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 385 ifp->if_ioctl = fxp_ioctl; 386 ifp->if_start = fxp_start; 387 ifp->if_watchdog = fxp_watchdog; 388 ifp->if_init = fxp_init; 389 ifp->if_stop = fxp_stop; 390 IFQ_SET_READY(&ifp->if_snd); 391 392 if (sc->sc_flags & FXPF_IPCB) { 393 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 394 /* 395 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 396 * at least, on i82550 rev.12. 397 * specifically, it doesn't calculate ipv4 checksum correctly 398 * when sending 20 byte ipv4 header + 1 or 2 byte data. 399 * FreeBSD driver has related comments. 400 */ 401 ifp->if_capabilities = 402 IFCAP_CSUM_IPv4_Rx | 403 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 404 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 405 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 406 } 407 408 /* 409 * We can support 802.1Q VLAN-sized frames. 410 */ 411 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 412 413 /* 414 * Attach the interface. 415 */ 416 if_attach(ifp); 417 ether_ifattach(ifp, enaddr); 418 #if NRND > 0 419 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 420 RND_TYPE_NET, 0); 421 #endif 422 423 #ifdef FXP_EVENT_COUNTERS 424 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 425 NULL, sc->sc_dev.dv_xname, "txstall"); 426 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 427 NULL, sc->sc_dev.dv_xname, "txintr"); 428 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 429 NULL, sc->sc_dev.dv_xname, "rxintr"); 430 if (sc->sc_rev >= FXP_REV_82558_A4) { 431 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 432 NULL, sc->sc_dev.dv_xname, "txpause"); 433 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 434 NULL, sc->sc_dev.dv_xname, "rxpause"); 435 } 436 #endif /* FXP_EVENT_COUNTERS */ 437 438 /* The attach is successful. */ 439 sc->sc_flags |= FXPF_ATTACHED; 440 441 return; 442 443 /* 444 * Free any resources we've allocated during the failed attach 445 * attempt. Do this in reverse order and fall though. 446 */ 447 fail_5: 448 for (i = 0; i < FXP_NRFABUFS; i++) { 449 if (sc->sc_rxmaps[i] != NULL) 450 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 451 } 452 fail_4: 453 for (i = 0; i < FXP_NTXCB; i++) { 454 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 455 bus_dmamap_destroy(sc->sc_dmat, 456 FXP_DSTX(sc, i)->txs_dmamap); 457 } 458 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 459 fail_3: 460 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 461 fail_2: 462 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 463 sizeof(struct fxp_control_data)); 464 fail_1: 465 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 466 fail_0: 467 return; 468 } 469 470 void 471 fxp_mii_initmedia(struct fxp_softc *sc) 472 { 473 int flags; 474 475 sc->sc_flags |= FXPF_MII; 476 477 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 478 sc->sc_mii.mii_readreg = fxp_mdi_read; 479 sc->sc_mii.mii_writereg = fxp_mdi_write; 480 sc->sc_mii.mii_statchg = fxp_statchg; 481 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 482 fxp_mii_mediastatus); 483 484 flags = MIIF_NOISOLATE; 485 if (sc->sc_rev >= FXP_REV_82558_A4) 486 flags |= MIIF_DOPAUSE; 487 /* 488 * The i82557 wedges if all of its PHYs are isolated! 489 */ 490 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 491 MII_OFFSET_ANY, flags); 492 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 493 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 494 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 495 } else 496 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 497 } 498 499 void 500 fxp_80c24_initmedia(struct fxp_softc *sc) 501 { 502 503 /* 504 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 505 * doesn't have a programming interface of any sort. The 506 * media is sensed automatically based on how the link partner 507 * is configured. This is, in essence, manual configuration. 508 */ 509 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 510 sc->sc_dev.dv_xname); 511 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 512 fxp_80c24_mediastatus); 513 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 514 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 515 } 516 517 /* 518 * Initialize the interface media. 519 */ 520 void 521 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 522 { 523 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 524 525 /* 526 * Reset to a stable state. 527 */ 528 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 529 DELAY(100); 530 531 sc->sc_eeprom_size = 0; 532 fxp_autosize_eeprom(sc); 533 if (sc->sc_eeprom_size == 0) { 534 aprint_error("%s: failed to detect EEPROM size\n", 535 sc->sc_dev.dv_xname); 536 sc->sc_eeprom_size = 6; /* XXX panic here? */ 537 } 538 #ifdef DEBUG 539 aprint_debug("%s: detected %d word EEPROM\n", 540 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 541 #endif 542 543 /* 544 * Get info about the primary PHY 545 */ 546 fxp_read_eeprom(sc, &data, 6, 1); 547 sc->phy_primary_device = 548 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 549 550 /* 551 * Read MAC address. 552 */ 553 fxp_read_eeprom(sc, myea, 0, 3); 554 enaddr[0] = myea[0] & 0xff; 555 enaddr[1] = myea[0] >> 8; 556 enaddr[2] = myea[1] & 0xff; 557 enaddr[3] = myea[1] >> 8; 558 enaddr[4] = myea[2] & 0xff; 559 enaddr[5] = myea[2] >> 8; 560 561 /* 562 * Systems based on the ICH2/ICH2-M chip from Intel, as well 563 * as some i82559 designs, have a defect where the chip can 564 * cause a PCI protocol violation if it receives a CU_RESUME 565 * command when it is entering the IDLE state. 566 * 567 * The work-around is to disable Dynamic Standby Mode, so that 568 * the chip never deasserts #CLKRUN, and always remains in the 569 * active state. 570 * 571 * Unfortunately, the only way to disable Dynamic Standby is 572 * to frob an EEPROM setting and reboot (the EEPROM setting 573 * is only consulted when the PCI bus comes out of reset). 574 * 575 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 576 */ 577 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 578 fxp_read_eeprom(sc, &data, 10, 1); 579 if (data & 0x02) { /* STB enable */ 580 aprint_error("%s: WARNING: " 581 "Disabling dynamic standby mode in EEPROM " 582 "to work around a\n", 583 sc->sc_dev.dv_xname); 584 aprint_normal( 585 "%s: WARNING: hardware bug. You must reset " 586 "the system before using this\n", 587 sc->sc_dev.dv_xname); 588 aprint_normal("%s: WARNING: interface.\n", 589 sc->sc_dev.dv_xname); 590 data &= ~0x02; 591 fxp_write_eeprom(sc, &data, 10, 1); 592 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 593 sc->sc_dev.dv_xname, data); 594 fxp_eeprom_update_cksum(sc); 595 } 596 } 597 598 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 599 /* Due to false positives we make it conditional on setting link1 */ 600 fxp_read_eeprom(sc, &data, 3, 1); 601 if ((data & 0x03) != 0x03) { 602 aprint_verbose("%s: May need receiver lock-up workaround\n", 603 sc->sc_dev.dv_xname); 604 } 605 } 606 607 static void 608 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 609 { 610 uint16_t reg; 611 int x; 612 613 for (x = 1 << (len - 1); x != 0; x >>= 1) { 614 DELAY(40); 615 if (data & x) 616 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 617 else 618 reg = FXP_EEPROM_EECS; 619 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 620 DELAY(40); 621 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 622 reg | FXP_EEPROM_EESK); 623 DELAY(40); 624 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 625 } 626 DELAY(40); 627 } 628 629 /* 630 * Figure out EEPROM size. 631 * 632 * 559's can have either 64-word or 256-word EEPROMs, the 558 633 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 634 * talks about the existence of 16 to 256 word EEPROMs. 635 * 636 * The only known sizes are 64 and 256, where the 256 version is used 637 * by CardBus cards to store CIS information. 638 * 639 * The address is shifted in msb-to-lsb, and after the last 640 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 641 * after which follows the actual data. We try to detect this zero, by 642 * probing the data-out bit in the EEPROM control register just after 643 * having shifted in a bit. If the bit is zero, we assume we've 644 * shifted enough address bits. The data-out should be tri-state, 645 * before this, which should translate to a logical one. 646 * 647 * Other ways to do this would be to try to read a register with known 648 * contents with a varying number of address bits, but no such 649 * register seem to be available. The high bits of register 10 are 01 650 * on the 558 and 559, but apparently not on the 557. 651 * 652 * The Linux driver computes a checksum on the EEPROM data, but the 653 * value of this checksum is not very well documented. 654 */ 655 656 void 657 fxp_autosize_eeprom(struct fxp_softc *sc) 658 { 659 int x; 660 661 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 662 DELAY(40); 663 664 /* Shift in read opcode. */ 665 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 666 667 /* 668 * Shift in address, wait for the dummy zero following a correct 669 * address shift. 670 */ 671 for (x = 1; x <= 8; x++) { 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 673 DELAY(40); 674 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 675 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 676 DELAY(40); 677 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 678 FXP_EEPROM_EEDO) == 0) 679 break; 680 DELAY(40); 681 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 682 DELAY(40); 683 } 684 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 685 DELAY(40); 686 if (x != 6 && x != 8) { 687 #ifdef DEBUG 688 printf("%s: strange EEPROM size (%d)\n", 689 sc->sc_dev.dv_xname, 1 << x); 690 #endif 691 } else 692 sc->sc_eeprom_size = x; 693 } 694 695 /* 696 * Read from the serial EEPROM. Basically, you manually shift in 697 * the read opcode (one bit at a time) and then shift in the address, 698 * and then you shift out the data (all of this one bit at a time). 699 * The word size is 16 bits, so you have to provide the address for 700 * every 16 bits of data. 701 */ 702 void 703 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 704 { 705 u_int16_t reg; 706 int i, x; 707 708 for (i = 0; i < words; i++) { 709 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 710 711 /* Shift in read opcode. */ 712 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 713 714 /* Shift in address. */ 715 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 716 717 reg = FXP_EEPROM_EECS; 718 data[i] = 0; 719 720 /* Shift out data. */ 721 for (x = 16; x > 0; x--) { 722 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 723 reg | FXP_EEPROM_EESK); 724 DELAY(40); 725 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 726 FXP_EEPROM_EEDO) 727 data[i] |= (1 << (x - 1)); 728 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 729 DELAY(40); 730 } 731 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 732 DELAY(40); 733 } 734 } 735 736 /* 737 * Write data to the serial EEPROM. 738 */ 739 void 740 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 741 { 742 int i, j; 743 744 for (i = 0; i < words; i++) { 745 /* Erase/write enable. */ 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 747 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 748 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 749 sc->sc_eeprom_size); 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 751 DELAY(4); 752 753 /* Shift in write opcode, address, data. */ 754 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 755 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 756 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 757 fxp_eeprom_shiftin(sc, data[i], 16); 758 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 759 DELAY(4); 760 761 /* Wait for the EEPROM to finish up. */ 762 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 763 DELAY(4); 764 for (j = 0; j < 1000; j++) { 765 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 766 FXP_EEPROM_EEDO) 767 break; 768 DELAY(50); 769 } 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 771 DELAY(4); 772 773 /* Erase/write disable. */ 774 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 775 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 776 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 777 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 778 DELAY(4); 779 } 780 } 781 782 /* 783 * Update the checksum of the EEPROM. 784 */ 785 void 786 fxp_eeprom_update_cksum(struct fxp_softc *sc) 787 { 788 int i; 789 uint16_t data, cksum; 790 791 cksum = 0; 792 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 793 fxp_read_eeprom(sc, &data, i, 1); 794 cksum += data; 795 } 796 i = (1 << sc->sc_eeprom_size) - 1; 797 cksum = 0xbaba - cksum; 798 fxp_read_eeprom(sc, &data, i, 1); 799 fxp_write_eeprom(sc, &cksum, i, 1); 800 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 801 sc->sc_dev.dv_xname, i, data, cksum); 802 } 803 804 /* 805 * Start packet transmission on the interface. 806 */ 807 void 808 fxp_start(struct ifnet *ifp) 809 { 810 struct fxp_softc *sc = ifp->if_softc; 811 struct mbuf *m0, *m; 812 struct fxp_txdesc *txd; 813 struct fxp_txsoft *txs; 814 bus_dmamap_t dmamap; 815 int error, lasttx, nexttx, opending, seg; 816 817 /* 818 * If we want a re-init, bail out now. 819 */ 820 if (sc->sc_flags & FXPF_WANTINIT) { 821 ifp->if_flags |= IFF_OACTIVE; 822 return; 823 } 824 825 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 826 return; 827 828 /* 829 * Remember the previous txpending and the current lasttx. 830 */ 831 opending = sc->sc_txpending; 832 lasttx = sc->sc_txlast; 833 834 /* 835 * Loop through the send queue, setting up transmit descriptors 836 * until we drain the queue, or use up all available transmit 837 * descriptors. 838 */ 839 for (;;) { 840 struct fxp_tbd *tbdp; 841 int csum_flags; 842 843 /* 844 * Grab a packet off the queue. 845 */ 846 IFQ_POLL(&ifp->if_snd, m0); 847 if (m0 == NULL) 848 break; 849 m = NULL; 850 851 if (sc->sc_txpending == FXP_NTXCB - 1) { 852 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 853 break; 854 } 855 856 /* 857 * Get the next available transmit descriptor. 858 */ 859 nexttx = FXP_NEXTTX(sc->sc_txlast); 860 txd = FXP_CDTX(sc, nexttx); 861 txs = FXP_DSTX(sc, nexttx); 862 dmamap = txs->txs_dmamap; 863 864 /* 865 * Load the DMA map. If this fails, the packet either 866 * didn't fit in the allotted number of frags, or we were 867 * short on resources. In this case, we'll copy and try 868 * again. 869 */ 870 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 871 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 872 MGETHDR(m, M_DONTWAIT, MT_DATA); 873 if (m == NULL) { 874 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 875 sc->sc_dev.dv_xname); 876 break; 877 } 878 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 879 if (m0->m_pkthdr.len > MHLEN) { 880 MCLGET(m, M_DONTWAIT); 881 if ((m->m_flags & M_EXT) == 0) { 882 log(LOG_ERR, 883 "%s: unable to allocate Tx " 884 "cluster\n", sc->sc_dev.dv_xname); 885 m_freem(m); 886 break; 887 } 888 } 889 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 890 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 891 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 892 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 893 if (error) { 894 log(LOG_ERR, "%s: unable to load Tx buffer, " 895 "error = %d\n", sc->sc_dev.dv_xname, error); 896 break; 897 } 898 } 899 900 IFQ_DEQUEUE(&ifp->if_snd, m0); 901 csum_flags = m0->m_pkthdr.csum_flags; 902 if (m != NULL) { 903 m_freem(m0); 904 m0 = m; 905 } 906 907 /* Initialize the fraglist. */ 908 tbdp = txd->txd_tbd; 909 if (sc->sc_flags & FXPF_IPCB) 910 tbdp++; 911 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 912 tbdp[seg].tb_addr = 913 htole32(dmamap->dm_segs[seg].ds_addr); 914 tbdp[seg].tb_size = 915 htole32(dmamap->dm_segs[seg].ds_len); 916 } 917 918 /* Sync the DMA map. */ 919 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 920 BUS_DMASYNC_PREWRITE); 921 922 /* 923 * Store a pointer to the packet so we can free it later. 924 */ 925 txs->txs_mbuf = m0; 926 927 /* 928 * Initialize the transmit descriptor. 929 */ 930 /* BIG_ENDIAN: no need to swap to store 0 */ 931 txd->txd_txcb.cb_status = 0; 932 txd->txd_txcb.cb_command = 933 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 934 txd->txd_txcb.tx_threshold = tx_threshold; 935 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 936 937 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 938 if (sc->sc_flags & FXPF_IPCB) { 939 struct m_tag *vtag; 940 struct fxp_ipcb *ipcb; 941 /* 942 * Deal with TCP/IP checksum offload. Note that 943 * in order for TCP checksum offload to work, 944 * the pseudo header checksum must have already 945 * been computed and stored in the checksum field 946 * in the TCP header. The stack should have 947 * already done this for us. 948 */ 949 ipcb = &txd->txd_u.txdu_ipcb; 950 memset(ipcb, 0, sizeof(*ipcb)); 951 /* 952 * always do hardware parsing. 953 */ 954 ipcb->ipcb_ip_activation_high = 955 FXP_IPCB_HARDWAREPARSING_ENABLE; 956 /* 957 * ip checksum offloading. 958 */ 959 if (csum_flags & M_CSUM_IPv4) { 960 ipcb->ipcb_ip_schedule |= 961 FXP_IPCB_IP_CHECKSUM_ENABLE; 962 } 963 /* 964 * TCP/UDP checksum offloading. 965 */ 966 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 967 ipcb->ipcb_ip_schedule |= 968 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 969 } 970 971 /* 972 * request VLAN tag insertion if needed. 973 */ 974 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 975 if (vtag) { 976 ipcb->ipcb_vlan_id = 977 htobe16(*(u_int *)(vtag + 1)); 978 ipcb->ipcb_ip_activation_high |= 979 FXP_IPCB_INSERTVLAN_ENABLE; 980 } 981 } else { 982 KASSERT((csum_flags & 983 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 984 } 985 986 FXP_CDTXSYNC(sc, nexttx, 987 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 988 989 /* Advance the tx pointer. */ 990 sc->sc_txpending++; 991 sc->sc_txlast = nexttx; 992 993 #if NBPFILTER > 0 994 /* 995 * Pass packet to bpf if there is a listener. 996 */ 997 if (ifp->if_bpf) 998 bpf_mtap(ifp->if_bpf, m0); 999 #endif 1000 } 1001 1002 if (sc->sc_txpending == FXP_NTXCB - 1) { 1003 /* No more slots; notify upper layer. */ 1004 ifp->if_flags |= IFF_OACTIVE; 1005 } 1006 1007 if (sc->sc_txpending != opending) { 1008 /* 1009 * We enqueued packets. If the transmitter was idle, 1010 * reset the txdirty pointer. 1011 */ 1012 if (opending == 0) 1013 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1014 1015 /* 1016 * Cause the chip to interrupt and suspend command 1017 * processing once the last packet we've enqueued 1018 * has been transmitted. 1019 * 1020 * To avoid a race between updating status bits 1021 * by the fxp chip and clearing command bits 1022 * by this function on machines which don't have 1023 * atomic methods to clear/set bits in memory 1024 * smaller than 32bits (both cb_status and cb_command 1025 * members are uint16_t and in the same 32bit word), 1026 * we have to prepare a dummy TX descriptor which has 1027 * NOP command and just causes a TX completion interrupt. 1028 */ 1029 sc->sc_txpending++; 1030 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1031 txd = FXP_CDTX(sc, sc->sc_txlast); 1032 /* BIG_ENDIAN: no need to swap to store 0 */ 1033 txd->txd_txcb.cb_status = 0; 1034 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1035 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1036 FXP_CDTXSYNC(sc, sc->sc_txlast, 1037 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1038 1039 /* 1040 * The entire packet chain is set up. Clear the suspend bit 1041 * on the command prior to the first packet we set up. 1042 */ 1043 FXP_CDTXSYNC(sc, lasttx, 1044 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1045 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1046 htole16(~FXP_CB_COMMAND_S); 1047 FXP_CDTXSYNC(sc, lasttx, 1048 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1049 1050 /* 1051 * Issue a Resume command in case the chip was suspended. 1052 */ 1053 fxp_scb_wait(sc); 1054 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1055 1056 /* Set a watchdog timer in case the chip flakes out. */ 1057 ifp->if_timer = 5; 1058 } 1059 } 1060 1061 /* 1062 * Process interface interrupts. 1063 */ 1064 int 1065 fxp_intr(void *arg) 1066 { 1067 struct fxp_softc *sc = arg; 1068 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1069 bus_dmamap_t rxmap; 1070 int claimed = 0, rnr; 1071 u_int8_t statack; 1072 1073 if (!device_is_active(&sc->sc_dev) || sc->sc_enabled == 0) 1074 return (0); 1075 /* 1076 * If the interface isn't running, don't try to 1077 * service the interrupt.. just ack it and bail. 1078 */ 1079 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1080 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1081 if (statack) { 1082 claimed = 1; 1083 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1084 } 1085 return (claimed); 1086 } 1087 1088 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1089 claimed = 1; 1090 1091 /* 1092 * First ACK all the interrupts in this pass. 1093 */ 1094 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1095 1096 /* 1097 * Process receiver interrupts. If a no-resource (RNR) 1098 * condition exists, get whatever packets we can and 1099 * re-start the receiver. 1100 */ 1101 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1102 1 : 0; 1103 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1104 FXP_SCB_STATACK_SWI)) { 1105 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1106 rnr |= fxp_rxintr(sc); 1107 } 1108 1109 /* 1110 * Free any finished transmit mbuf chains. 1111 */ 1112 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1113 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1114 fxp_txintr(sc); 1115 1116 /* 1117 * Try to get more packets going. 1118 */ 1119 fxp_start(ifp); 1120 1121 if (sc->sc_txpending == 0) { 1122 /* 1123 * If we want a re-init, do that now. 1124 */ 1125 if (sc->sc_flags & FXPF_WANTINIT) 1126 (void) fxp_init(ifp); 1127 } 1128 } 1129 1130 if (rnr) { 1131 fxp_scb_wait(sc); 1132 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1133 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1134 fxp_scb_wait(sc); 1135 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1136 rxmap->dm_segs[0].ds_addr + 1137 RFA_ALIGNMENT_FUDGE); 1138 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1139 } 1140 } 1141 1142 #if NRND > 0 1143 if (claimed) 1144 rnd_add_uint32(&sc->rnd_source, statack); 1145 #endif 1146 return (claimed); 1147 } 1148 1149 /* 1150 * Handle transmit completion interrupts. 1151 */ 1152 void 1153 fxp_txintr(struct fxp_softc *sc) 1154 { 1155 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1156 struct fxp_txdesc *txd; 1157 struct fxp_txsoft *txs; 1158 int i; 1159 u_int16_t txstat; 1160 1161 ifp->if_flags &= ~IFF_OACTIVE; 1162 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1163 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1164 txd = FXP_CDTX(sc, i); 1165 txs = FXP_DSTX(sc, i); 1166 1167 FXP_CDTXSYNC(sc, i, 1168 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1169 1170 /* skip dummy NOP TX descriptor */ 1171 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1172 == FXP_CB_COMMAND_NOP) 1173 continue; 1174 1175 txstat = le16toh(txd->txd_txcb.cb_status); 1176 1177 if ((txstat & FXP_CB_STATUS_C) == 0) 1178 break; 1179 1180 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1181 0, txs->txs_dmamap->dm_mapsize, 1182 BUS_DMASYNC_POSTWRITE); 1183 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1184 m_freem(txs->txs_mbuf); 1185 txs->txs_mbuf = NULL; 1186 } 1187 1188 /* Update the dirty transmit buffer pointer. */ 1189 sc->sc_txdirty = i; 1190 1191 /* 1192 * Cancel the watchdog timer if there are no pending 1193 * transmissions. 1194 */ 1195 if (sc->sc_txpending == 0) 1196 ifp->if_timer = 0; 1197 } 1198 1199 /* 1200 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1201 */ 1202 1203 int 1204 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1205 { 1206 u_int16_t rxparsestat; 1207 u_int16_t csum_stat; 1208 u_int32_t csum_data; 1209 int csum_flags; 1210 1211 /* 1212 * check VLAN tag stripping. 1213 */ 1214 1215 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1216 struct m_tag *vtag; 1217 1218 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1219 if (vtag == NULL) 1220 return ENOMEM; 1221 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1222 m_tag_prepend(m, vtag); 1223 } 1224 1225 /* 1226 * check H/W Checksumming. 1227 */ 1228 1229 csum_stat = le16toh(rfa->cksum_stat); 1230 rxparsestat = le16toh(rfa->rx_parse_stat); 1231 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1232 return 0; 1233 1234 csum_flags = 0; 1235 csum_data = 0; 1236 1237 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1238 csum_flags = M_CSUM_IPv4; 1239 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1240 csum_flags |= M_CSUM_IPv4_BAD; 1241 } 1242 1243 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1244 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1245 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1246 csum_flags |= M_CSUM_TCP_UDP_BAD; 1247 } 1248 1249 m->m_pkthdr.csum_flags = csum_flags; 1250 m->m_pkthdr.csum_data = csum_data; 1251 1252 return 0; 1253 } 1254 1255 /* 1256 * Handle receive interrupts. 1257 */ 1258 int 1259 fxp_rxintr(struct fxp_softc *sc) 1260 { 1261 struct ethercom *ec = &sc->sc_ethercom; 1262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1263 struct mbuf *m, *m0; 1264 bus_dmamap_t rxmap; 1265 struct fxp_rfa *rfa; 1266 int rnr; 1267 u_int16_t len, rxstat; 1268 1269 rnr = 0; 1270 1271 for (;;) { 1272 m = sc->sc_rxq.ifq_head; 1273 rfa = FXP_MTORFA(m); 1274 rxmap = M_GETCTX(m, bus_dmamap_t); 1275 1276 FXP_RFASYNC(sc, m, 1277 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1278 1279 rxstat = le16toh(rfa->rfa_status); 1280 1281 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1282 rnr = 1; 1283 1284 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1285 /* 1286 * We have processed all of the 1287 * receive buffers. 1288 */ 1289 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1290 return rnr; 1291 } 1292 1293 IF_DEQUEUE(&sc->sc_rxq, m); 1294 1295 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1296 1297 len = le16toh(rfa->actual_size) & 1298 (m->m_ext.ext_size - 1); 1299 1300 if (len < sizeof(struct ether_header)) { 1301 /* 1302 * Runt packet; drop it now. 1303 */ 1304 FXP_INIT_RFABUF(sc, m); 1305 continue; 1306 } 1307 1308 /* 1309 * If support for 802.1Q VLAN sized frames is 1310 * enabled, we need to do some additional error 1311 * checking (as we are saving bad frames, in 1312 * order to receive the larger ones). 1313 */ 1314 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1315 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1316 FXP_RFA_STATUS_RNR| 1317 FXP_RFA_STATUS_ALIGN| 1318 FXP_RFA_STATUS_CRC)) != 0) { 1319 FXP_INIT_RFABUF(sc, m); 1320 continue; 1321 } 1322 1323 /* Do checksum checking. */ 1324 m->m_pkthdr.csum_flags = 0; 1325 if (sc->sc_flags & FXPF_EXT_RFA) 1326 if (fxp_rx_hwcksum(m, rfa)) 1327 goto dropit; 1328 1329 /* 1330 * If the packet is small enough to fit in a 1331 * single header mbuf, allocate one and copy 1332 * the data into it. This greatly reduces 1333 * memory consumption when we receive lots 1334 * of small packets. 1335 * 1336 * Otherwise, we add a new buffer to the receive 1337 * chain. If this fails, we drop the packet and 1338 * recycle the old buffer. 1339 */ 1340 if (fxp_copy_small != 0 && len <= MHLEN) { 1341 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1342 if (m0 == NULL) 1343 goto dropit; 1344 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1345 memcpy(mtod(m0, void *), 1346 mtod(m, void *), len); 1347 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1348 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1349 FXP_INIT_RFABUF(sc, m); 1350 m = m0; 1351 } else { 1352 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1353 dropit: 1354 ifp->if_ierrors++; 1355 FXP_INIT_RFABUF(sc, m); 1356 continue; 1357 } 1358 } 1359 1360 m->m_pkthdr.rcvif = ifp; 1361 m->m_pkthdr.len = m->m_len = len; 1362 1363 #if NBPFILTER > 0 1364 /* 1365 * Pass this up to any BPF listeners, but only 1366 * pass it up the stack if it's for us. 1367 */ 1368 if (ifp->if_bpf) 1369 bpf_mtap(ifp->if_bpf, m); 1370 #endif 1371 1372 /* Pass it on. */ 1373 (*ifp->if_input)(ifp, m); 1374 } 1375 } 1376 1377 /* 1378 * Update packet in/out/collision statistics. The i82557 doesn't 1379 * allow you to access these counters without doing a fairly 1380 * expensive DMA to get _all_ of the statistics it maintains, so 1381 * we do this operation here only once per second. The statistics 1382 * counters in the kernel are updated from the previous dump-stats 1383 * DMA and then a new dump-stats DMA is started. The on-chip 1384 * counters are zeroed when the DMA completes. If we can't start 1385 * the DMA immediately, we don't wait - we just prepare to read 1386 * them again next time. 1387 */ 1388 void 1389 fxp_tick(void *arg) 1390 { 1391 struct fxp_softc *sc = arg; 1392 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1393 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1394 int s; 1395 1396 if (!device_is_active(&sc->sc_dev)) 1397 return; 1398 1399 s = splnet(); 1400 1401 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1402 1403 ifp->if_opackets += le32toh(sp->tx_good); 1404 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1405 if (sp->rx_good) { 1406 ifp->if_ipackets += le32toh(sp->rx_good); 1407 sc->sc_rxidle = 0; 1408 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1409 sc->sc_rxidle++; 1410 } 1411 ifp->if_ierrors += 1412 le32toh(sp->rx_crc_errors) + 1413 le32toh(sp->rx_alignment_errors) + 1414 le32toh(sp->rx_rnr_errors) + 1415 le32toh(sp->rx_overrun_errors); 1416 /* 1417 * If any transmit underruns occurred, bump up the transmit 1418 * threshold by another 512 bytes (64 * 8). 1419 */ 1420 if (sp->tx_underruns) { 1421 ifp->if_oerrors += le32toh(sp->tx_underruns); 1422 if (tx_threshold < 192) 1423 tx_threshold += 64; 1424 } 1425 #ifdef FXP_EVENT_COUNTERS 1426 if (sc->sc_rev >= FXP_REV_82558_A4) { 1427 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1428 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1429 } 1430 #endif 1431 1432 /* 1433 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1434 * then assume the receiver has locked up and attempt to clear 1435 * the condition by reprogramming the multicast filter (actually, 1436 * resetting the interface). This is a work-around for a bug in 1437 * the 82557 where the receiver locks up if it gets certain types 1438 * of garbage in the synchronization bits prior to the packet header. 1439 * This bug is supposed to only occur in 10Mbps mode, but has been 1440 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1441 * speed transition). 1442 */ 1443 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1444 (void) fxp_init(ifp); 1445 splx(s); 1446 return; 1447 } 1448 /* 1449 * If there is no pending command, start another stats 1450 * dump. Otherwise punt for now. 1451 */ 1452 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1453 /* 1454 * Start another stats dump. 1455 */ 1456 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1457 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1458 } else { 1459 /* 1460 * A previous command is still waiting to be accepted. 1461 * Just zero our copy of the stats and wait for the 1462 * next timer event to update them. 1463 */ 1464 /* BIG_ENDIAN: no swap required to store 0 */ 1465 sp->tx_good = 0; 1466 sp->tx_underruns = 0; 1467 sp->tx_total_collisions = 0; 1468 1469 sp->rx_good = 0; 1470 sp->rx_crc_errors = 0; 1471 sp->rx_alignment_errors = 0; 1472 sp->rx_rnr_errors = 0; 1473 sp->rx_overrun_errors = 0; 1474 if (sc->sc_rev >= FXP_REV_82558_A4) { 1475 sp->tx_pauseframes = 0; 1476 sp->rx_pauseframes = 0; 1477 } 1478 } 1479 1480 if (sc->sc_flags & FXPF_MII) { 1481 /* Tick the MII clock. */ 1482 mii_tick(&sc->sc_mii); 1483 } 1484 1485 splx(s); 1486 1487 /* 1488 * Schedule another timeout one second from now. 1489 */ 1490 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1491 } 1492 1493 /* 1494 * Drain the receive queue. 1495 */ 1496 void 1497 fxp_rxdrain(struct fxp_softc *sc) 1498 { 1499 bus_dmamap_t rxmap; 1500 struct mbuf *m; 1501 1502 for (;;) { 1503 IF_DEQUEUE(&sc->sc_rxq, m); 1504 if (m == NULL) 1505 break; 1506 rxmap = M_GETCTX(m, bus_dmamap_t); 1507 bus_dmamap_unload(sc->sc_dmat, rxmap); 1508 FXP_RXMAP_PUT(sc, rxmap); 1509 m_freem(m); 1510 } 1511 } 1512 1513 /* 1514 * Stop the interface. Cancels the statistics updater and resets 1515 * the interface. 1516 */ 1517 void 1518 fxp_stop(struct ifnet *ifp, int disable) 1519 { 1520 struct fxp_softc *sc = ifp->if_softc; 1521 struct fxp_txsoft *txs; 1522 int i; 1523 1524 /* 1525 * Turn down interface (done early to avoid bad interactions 1526 * between panics, shutdown hooks, and the watchdog timer) 1527 */ 1528 ifp->if_timer = 0; 1529 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1530 1531 /* 1532 * Cancel stats updater. 1533 */ 1534 callout_stop(&sc->sc_callout); 1535 if (sc->sc_flags & FXPF_MII) { 1536 /* Down the MII. */ 1537 mii_down(&sc->sc_mii); 1538 } 1539 1540 /* 1541 * Issue software reset. This unloads any microcode that 1542 * might already be loaded. 1543 */ 1544 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1545 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1546 DELAY(50); 1547 1548 /* 1549 * Release any xmit buffers. 1550 */ 1551 for (i = 0; i < FXP_NTXCB; i++) { 1552 txs = FXP_DSTX(sc, i); 1553 if (txs->txs_mbuf != NULL) { 1554 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1555 m_freem(txs->txs_mbuf); 1556 txs->txs_mbuf = NULL; 1557 } 1558 } 1559 sc->sc_txpending = 0; 1560 1561 if (disable) { 1562 fxp_rxdrain(sc); 1563 fxp_disable(sc); 1564 } 1565 1566 } 1567 1568 /* 1569 * Watchdog/transmission transmit timeout handler. Called when a 1570 * transmission is started on the interface, but no interrupt is 1571 * received before the timeout. This usually indicates that the 1572 * card has wedged for some reason. 1573 */ 1574 void 1575 fxp_watchdog(struct ifnet *ifp) 1576 { 1577 struct fxp_softc *sc = ifp->if_softc; 1578 1579 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1580 ifp->if_oerrors++; 1581 1582 (void) fxp_init(ifp); 1583 } 1584 1585 /* 1586 * Initialize the interface. Must be called at splnet(). 1587 */ 1588 int 1589 fxp_init(struct ifnet *ifp) 1590 { 1591 struct fxp_softc *sc = ifp->if_softc; 1592 struct fxp_cb_config *cbp; 1593 struct fxp_cb_ias *cb_ias; 1594 struct fxp_txdesc *txd; 1595 bus_dmamap_t rxmap; 1596 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1597 1598 if ((error = fxp_enable(sc)) != 0) 1599 goto out; 1600 1601 /* 1602 * Cancel any pending I/O 1603 */ 1604 fxp_stop(ifp, 0); 1605 1606 /* 1607 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1608 * flag, and this prevents the MII from detaching resulting in 1609 * a panic. The flags field should perhaps be split in runtime 1610 * flags and more static information. For now, just clear the 1611 * only other flag set. 1612 */ 1613 1614 sc->sc_flags &= ~FXPF_WANTINIT; 1615 1616 /* 1617 * Initialize base of CBL and RFA memory. Loading with zero 1618 * sets it up for regular linear addressing. 1619 */ 1620 fxp_scb_wait(sc); 1621 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1622 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1623 1624 fxp_scb_wait(sc); 1625 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1626 1627 /* 1628 * Initialize the multicast filter. Do this now, since we might 1629 * have to setup the config block differently. 1630 */ 1631 fxp_mc_setup(sc); 1632 1633 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1634 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1635 1636 /* 1637 * In order to support receiving 802.1Q VLAN frames, we have to 1638 * enable "save bad frames", since they are 4 bytes larger than 1639 * the normal Ethernet maximum frame length. On i82558 and later, 1640 * we have a better mechanism for this. 1641 */ 1642 save_bf = 0; 1643 lrxen = 0; 1644 vlan_drop = 0; 1645 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1646 if (sc->sc_rev < FXP_REV_82558_A4) 1647 save_bf = 1; 1648 else 1649 lrxen = 1; 1650 if (sc->sc_rev >= FXP_REV_82550) 1651 vlan_drop = 1; 1652 } 1653 1654 /* 1655 * Initialize base of dump-stats buffer. 1656 */ 1657 fxp_scb_wait(sc); 1658 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1659 sc->sc_cddma + FXP_CDSTATSOFF); 1660 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1661 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1662 1663 cbp = &sc->sc_control_data->fcd_configcb; 1664 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1665 1666 /* 1667 * Load microcode for this controller. 1668 */ 1669 fxp_load_ucode(sc); 1670 1671 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1672 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1673 else 1674 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1675 1676 /* 1677 * This copy is kind of disgusting, but there are a bunch of must be 1678 * zero and must be one bits in this structure and this is the easiest 1679 * way to initialize them all to proper values. 1680 */ 1681 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1682 1683 /* BIG_ENDIAN: no need to swap to store 0 */ 1684 cbp->cb_status = 0; 1685 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1686 FXP_CB_COMMAND_EL); 1687 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1688 cbp->link_addr = 0xffffffff; /* (no) next command */ 1689 /* bytes in config block */ 1690 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1691 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1692 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1693 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1694 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1695 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1696 cbp->type_enable = 0; /* actually reserved */ 1697 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1698 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1699 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1700 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1701 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1702 cbp->late_scb = 0; /* (don't) defer SCB update */ 1703 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1704 cbp->ci_int = 1; /* interrupt on CU idle */ 1705 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1706 cbp->ext_stats_dis = 1; /* disable extended counters */ 1707 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1708 cbp->save_bf = save_bf;/* save bad frames */ 1709 cbp->disc_short_rx = !prm; /* discard short packets */ 1710 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1711 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1712 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1713 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1714 /* interface mode */ 1715 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1716 cbp->csma_dis = 0; /* (don't) disable link */ 1717 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1718 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1719 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1720 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1721 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1722 cbp->nsai = 1; /* (don't) disable source addr insert */ 1723 cbp->preamble_length = 2; /* (7 byte) preamble */ 1724 cbp->loopback = 0; /* (don't) loopback */ 1725 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1726 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1727 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1728 cbp->promiscuous = prm; /* promiscuous mode */ 1729 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1730 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1731 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1732 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1733 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1734 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1735 cbp->padding = 1; /* (do) pad short tx packets */ 1736 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1737 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1738 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1739 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1740 /* must set wake_en in PMCSR also */ 1741 cbp->force_fdx = 0; /* (don't) force full duplex */ 1742 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1743 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1744 cbp->mc_all = allm; /* accept all multicasts */ 1745 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1746 cbp->vlan_drop_en = vlan_drop; 1747 1748 if (sc->sc_rev < FXP_REV_82558_A4) { 1749 /* 1750 * The i82557 has no hardware flow control, the values 1751 * here are the defaults for the chip. 1752 */ 1753 cbp->fc_delay_lsb = 0; 1754 cbp->fc_delay_msb = 0x40; 1755 cbp->pri_fc_thresh = 3; 1756 cbp->tx_fc_dis = 0; 1757 cbp->rx_fc_restop = 0; 1758 cbp->rx_fc_restart = 0; 1759 cbp->fc_filter = 0; 1760 cbp->pri_fc_loc = 1; 1761 } else { 1762 cbp->fc_delay_lsb = 0x1f; 1763 cbp->fc_delay_msb = 0x01; 1764 cbp->pri_fc_thresh = 3; 1765 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1766 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1767 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1768 cbp->fc_filter = !prm; /* drop FC frames to host */ 1769 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1770 cbp->ext_stats_dis = 0; /* enable extended stats */ 1771 } 1772 1773 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1774 1775 /* 1776 * Start the config command/DMA. 1777 */ 1778 fxp_scb_wait(sc); 1779 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1780 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1781 /* ...and wait for it to complete. */ 1782 i = 1000; 1783 do { 1784 FXP_CDCONFIGSYNC(sc, 1785 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1786 DELAY(1); 1787 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1788 if (i == 0) { 1789 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1790 sc->sc_dev.dv_xname, __LINE__); 1791 return (ETIMEDOUT); 1792 } 1793 1794 /* 1795 * Initialize the station address. 1796 */ 1797 cb_ias = &sc->sc_control_data->fcd_iascb; 1798 /* BIG_ENDIAN: no need to swap to store 0 */ 1799 cb_ias->cb_status = 0; 1800 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1801 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1802 cb_ias->link_addr = 0xffffffff; 1803 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1804 1805 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1806 1807 /* 1808 * Start the IAS (Individual Address Setup) command/DMA. 1809 */ 1810 fxp_scb_wait(sc); 1811 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1812 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1813 /* ...and wait for it to complete. */ 1814 i = 1000; 1815 do { 1816 FXP_CDIASSYNC(sc, 1817 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1818 DELAY(1); 1819 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1820 if (i == 0) { 1821 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1822 sc->sc_dev.dv_xname, __LINE__); 1823 return (ETIMEDOUT); 1824 } 1825 1826 /* 1827 * Initialize the transmit descriptor ring. txlast is initialized 1828 * to the end of the list so that it will wrap around to the first 1829 * descriptor when the first packet is transmitted. 1830 */ 1831 for (i = 0; i < FXP_NTXCB; i++) { 1832 txd = FXP_CDTX(sc, i); 1833 memset(txd, 0, sizeof(*txd)); 1834 txd->txd_txcb.cb_command = 1835 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1836 txd->txd_txcb.link_addr = 1837 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1838 if (sc->sc_flags & FXPF_EXT_TXCB) 1839 txd->txd_txcb.tbd_array_addr = 1840 htole32(FXP_CDTBDADDR(sc, i) + 1841 (2 * sizeof(struct fxp_tbd))); 1842 else 1843 txd->txd_txcb.tbd_array_addr = 1844 htole32(FXP_CDTBDADDR(sc, i)); 1845 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1846 } 1847 sc->sc_txpending = 0; 1848 sc->sc_txdirty = 0; 1849 sc->sc_txlast = FXP_NTXCB - 1; 1850 1851 /* 1852 * Initialize the receive buffer list. 1853 */ 1854 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1855 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1856 rxmap = FXP_RXMAP_GET(sc); 1857 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1858 log(LOG_ERR, "%s: unable to allocate or map rx " 1859 "buffer %d, error = %d\n", 1860 sc->sc_dev.dv_xname, 1861 sc->sc_rxq.ifq_len, error); 1862 /* 1863 * XXX Should attempt to run with fewer receive 1864 * XXX buffers instead of just failing. 1865 */ 1866 FXP_RXMAP_PUT(sc, rxmap); 1867 fxp_rxdrain(sc); 1868 goto out; 1869 } 1870 } 1871 sc->sc_rxidle = 0; 1872 1873 /* 1874 * Give the transmit ring to the chip. We do this by pointing 1875 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1876 * issuing a start command. It will execute the NOP and then 1877 * suspend, pointing at the first descriptor. 1878 */ 1879 fxp_scb_wait(sc); 1880 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1881 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1882 1883 /* 1884 * Initialize receiver buffer area - RFA. 1885 */ 1886 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1887 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1888 fxp_scb_wait(sc); 1889 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1890 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1891 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1892 #endif 1893 1894 if (sc->sc_flags & FXPF_MII) { 1895 /* 1896 * Set current media. 1897 */ 1898 mii_mediachg(&sc->sc_mii); 1899 } 1900 1901 /* 1902 * ...all done! 1903 */ 1904 ifp->if_flags |= IFF_RUNNING; 1905 ifp->if_flags &= ~IFF_OACTIVE; 1906 1907 /* 1908 * Request a software generated interrupt that will be used to 1909 * (re)start the RU processing. If we direct the chip to start 1910 * receiving from the start of queue now, instead of letting the 1911 * interrupt handler first process all received packets, we run 1912 * the risk of having it overwrite mbuf clusters while they are 1913 * being processed or after they have been returned to the pool. 1914 */ 1915 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1916 1917 /* 1918 * Start the one second timer. 1919 */ 1920 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1921 1922 /* 1923 * Attempt to start output on the interface. 1924 */ 1925 fxp_start(ifp); 1926 1927 out: 1928 if (error) { 1929 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1930 ifp->if_timer = 0; 1931 log(LOG_ERR, "%s: interface not running\n", 1932 sc->sc_dev.dv_xname); 1933 } 1934 return (error); 1935 } 1936 1937 /* 1938 * Change media according to request. 1939 */ 1940 int 1941 fxp_mii_mediachange(struct ifnet *ifp) 1942 { 1943 struct fxp_softc *sc = ifp->if_softc; 1944 1945 if (ifp->if_flags & IFF_UP) 1946 mii_mediachg(&sc->sc_mii); 1947 return (0); 1948 } 1949 1950 /* 1951 * Notify the world which media we're using. 1952 */ 1953 void 1954 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1955 { 1956 struct fxp_softc *sc = ifp->if_softc; 1957 1958 if (sc->sc_enabled == 0) { 1959 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1960 ifmr->ifm_status = 0; 1961 return; 1962 } 1963 1964 mii_pollstat(&sc->sc_mii); 1965 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1966 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1967 1968 /* 1969 * XXX Flow control is always turned on if the chip supports 1970 * XXX it; we can't easily control it dynamically, since it 1971 * XXX requires sending a setup packet. 1972 */ 1973 if (sc->sc_rev >= FXP_REV_82558_A4) 1974 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1975 } 1976 1977 int 1978 fxp_80c24_mediachange(struct ifnet *ifp) 1979 { 1980 1981 /* Nothing to do here. */ 1982 return (0); 1983 } 1984 1985 void 1986 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1987 { 1988 struct fxp_softc *sc = ifp->if_softc; 1989 1990 /* 1991 * Media is currently-selected media. We cannot determine 1992 * the link status. 1993 */ 1994 ifmr->ifm_status = 0; 1995 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1996 } 1997 1998 /* 1999 * Add a buffer to the end of the RFA buffer list. 2000 * Return 0 if successful, error code on failure. 2001 * 2002 * The RFA struct is stuck at the beginning of mbuf cluster and the 2003 * data pointer is fixed up to point just past it. 2004 */ 2005 int 2006 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2007 { 2008 struct mbuf *m; 2009 int error; 2010 2011 MGETHDR(m, M_DONTWAIT, MT_DATA); 2012 if (m == NULL) 2013 return (ENOBUFS); 2014 2015 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2016 MCLGET(m, M_DONTWAIT); 2017 if ((m->m_flags & M_EXT) == 0) { 2018 m_freem(m); 2019 return (ENOBUFS); 2020 } 2021 2022 if (unload) 2023 bus_dmamap_unload(sc->sc_dmat, rxmap); 2024 2025 M_SETCTX(m, rxmap); 2026 2027 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2028 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2029 BUS_DMA_READ|BUS_DMA_NOWAIT); 2030 if (error) { 2031 /* XXX XXX XXX */ 2032 printf("%s: can't load rx DMA map %d, error = %d\n", 2033 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2034 panic("fxp_add_rfabuf"); 2035 } 2036 2037 FXP_INIT_RFABUF(sc, m); 2038 2039 return (0); 2040 } 2041 2042 int 2043 fxp_mdi_read(struct device *self, int phy, int reg) 2044 { 2045 struct fxp_softc *sc = (struct fxp_softc *)self; 2046 int count = 10000; 2047 int value; 2048 2049 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2050 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2051 2052 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2053 0x10000000) == 0 && count--) 2054 DELAY(10); 2055 2056 if (count <= 0) 2057 log(LOG_WARNING, 2058 "%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2059 2060 return (value & 0xffff); 2061 } 2062 2063 void 2064 fxp_statchg(struct device *self) 2065 { 2066 2067 /* Nothing to do. */ 2068 } 2069 2070 void 2071 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2072 { 2073 struct fxp_softc *sc = (struct fxp_softc *)self; 2074 int count = 10000; 2075 2076 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2077 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2078 (value & 0xffff)); 2079 2080 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2081 count--) 2082 DELAY(10); 2083 2084 if (count <= 0) 2085 log(LOG_WARNING, 2086 "%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2087 } 2088 2089 int 2090 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2091 { 2092 struct fxp_softc *sc = ifp->if_softc; 2093 struct ifreq *ifr = (struct ifreq *)data; 2094 int s, error; 2095 2096 s = splnet(); 2097 2098 switch (cmd) { 2099 case SIOCSIFMEDIA: 2100 case SIOCGIFMEDIA: 2101 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2102 break; 2103 2104 default: 2105 error = ether_ioctl(ifp, cmd, data); 2106 if (error == ENETRESET) { 2107 if (ifp->if_flags & IFF_RUNNING) { 2108 /* 2109 * Multicast list has changed; set the 2110 * hardware filter accordingly. 2111 */ 2112 if (sc->sc_txpending) { 2113 sc->sc_flags |= FXPF_WANTINIT; 2114 error = 0; 2115 } else 2116 error = fxp_init(ifp); 2117 } else 2118 error = 0; 2119 } 2120 break; 2121 } 2122 2123 /* Try to get more packets going. */ 2124 if (sc->sc_enabled) 2125 fxp_start(ifp); 2126 2127 splx(s); 2128 return (error); 2129 } 2130 2131 /* 2132 * Program the multicast filter. 2133 * 2134 * This function must be called at splnet(). 2135 */ 2136 void 2137 fxp_mc_setup(struct fxp_softc *sc) 2138 { 2139 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2140 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2141 struct ethercom *ec = &sc->sc_ethercom; 2142 struct ether_multi *enm; 2143 struct ether_multistep step; 2144 int count, nmcasts; 2145 2146 #ifdef DIAGNOSTIC 2147 if (sc->sc_txpending) 2148 panic("fxp_mc_setup: pending transmissions"); 2149 #endif 2150 2151 ifp->if_flags &= ~IFF_ALLMULTI; 2152 2153 /* 2154 * Initialize multicast setup descriptor. 2155 */ 2156 nmcasts = 0; 2157 ETHER_FIRST_MULTI(step, ec, enm); 2158 while (enm != NULL) { 2159 /* 2160 * Check for too many multicast addresses or if we're 2161 * listening to a range. Either way, we simply have 2162 * to accept all multicasts. 2163 */ 2164 if (nmcasts >= MAXMCADDR || 2165 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2166 ETHER_ADDR_LEN) != 0) { 2167 /* 2168 * Callers of this function must do the 2169 * right thing with this. If we're called 2170 * from outside fxp_init(), the caller must 2171 * detect if the state if IFF_ALLMULTI changes. 2172 * If it does, the caller must then call 2173 * fxp_init(), since allmulti is handled by 2174 * the config block. 2175 */ 2176 ifp->if_flags |= IFF_ALLMULTI; 2177 return; 2178 } 2179 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2180 ETHER_ADDR_LEN); 2181 nmcasts++; 2182 ETHER_NEXT_MULTI(step, enm); 2183 } 2184 2185 /* BIG_ENDIAN: no need to swap to store 0 */ 2186 mcsp->cb_status = 0; 2187 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2188 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2189 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2190 2191 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2192 2193 /* 2194 * Wait until the command unit is not active. This should never 2195 * happen since nothing is queued, but make sure anyway. 2196 */ 2197 count = 100; 2198 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2199 FXP_SCB_CUS_ACTIVE && --count) 2200 DELAY(1); 2201 if (count == 0) { 2202 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2203 sc->sc_dev.dv_xname, __LINE__); 2204 return; 2205 } 2206 2207 /* 2208 * Start the multicast setup command/DMA. 2209 */ 2210 fxp_scb_wait(sc); 2211 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2212 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2213 2214 /* ...and wait for it to complete. */ 2215 count = 1000; 2216 do { 2217 FXP_CDMCSSYNC(sc, 2218 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2219 DELAY(1); 2220 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2221 if (count == 0) { 2222 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2223 sc->sc_dev.dv_xname, __LINE__); 2224 return; 2225 } 2226 } 2227 2228 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2229 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2230 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2231 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2232 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2233 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2234 2235 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2236 2237 static const struct ucode { 2238 int32_t revision; 2239 const uint32_t *ucode; 2240 size_t length; 2241 uint16_t int_delay_offset; 2242 uint16_t bundle_max_offset; 2243 } ucode_table[] = { 2244 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2245 D101_CPUSAVER_DWORD, 0 }, 2246 2247 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2248 D101_CPUSAVER_DWORD, 0 }, 2249 2250 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2251 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2252 2253 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2254 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2255 2256 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2257 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2258 2259 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2260 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2261 2262 { 0, NULL, 0, 0, 0 } 2263 }; 2264 2265 void 2266 fxp_load_ucode(struct fxp_softc *sc) 2267 { 2268 const struct ucode *uc; 2269 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2270 int count, i; 2271 2272 if (sc->sc_flags & FXPF_UCODE_LOADED) 2273 return; 2274 2275 /* 2276 * Only load the uCode if the user has requested that 2277 * we do so. 2278 */ 2279 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2280 sc->sc_int_delay = 0; 2281 sc->sc_bundle_max = 0; 2282 return; 2283 } 2284 2285 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2286 if (sc->sc_rev == uc->revision) 2287 break; 2288 } 2289 if (uc->ucode == NULL) 2290 return; 2291 2292 /* BIG ENDIAN: no need to swap to store 0 */ 2293 cbp->cb_status = 0; 2294 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2295 cbp->link_addr = 0xffffffff; /* (no) next command */ 2296 for (i = 0; i < uc->length; i++) 2297 cbp->ucode[i] = htole32(uc->ucode[i]); 2298 2299 if (uc->int_delay_offset) 2300 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2301 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2302 2303 if (uc->bundle_max_offset) 2304 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2305 htole16(fxp_bundle_max); 2306 2307 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2308 2309 /* 2310 * Download the uCode to the chip. 2311 */ 2312 fxp_scb_wait(sc); 2313 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2314 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2315 2316 /* ...and wait for it to complete. */ 2317 count = 10000; 2318 do { 2319 FXP_CDUCODESYNC(sc, 2320 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2321 DELAY(2); 2322 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2323 if (count == 0) { 2324 sc->sc_int_delay = 0; 2325 sc->sc_bundle_max = 0; 2326 log(LOG_WARNING, "%s: timeout loading microcode\n", 2327 sc->sc_dev.dv_xname); 2328 return; 2329 } 2330 2331 if (sc->sc_int_delay != fxp_int_delay || 2332 sc->sc_bundle_max != fxp_bundle_max) { 2333 sc->sc_int_delay = fxp_int_delay; 2334 sc->sc_bundle_max = fxp_bundle_max; 2335 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2336 "max bundle: %d\n", sc->sc_dev.dv_xname, 2337 sc->sc_int_delay, 2338 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2339 } 2340 2341 sc->sc_flags |= FXPF_UCODE_LOADED; 2342 } 2343 2344 int 2345 fxp_enable(struct fxp_softc *sc) 2346 { 2347 2348 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2349 if ((*sc->sc_enable)(sc) != 0) { 2350 log(LOG_ERR, "%s: device enable failed\n", 2351 sc->sc_dev.dv_xname); 2352 return (EIO); 2353 } 2354 } 2355 2356 sc->sc_enabled = 1; 2357 return (0); 2358 } 2359 2360 void 2361 fxp_disable(struct fxp_softc *sc) 2362 { 2363 2364 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2365 (*sc->sc_disable)(sc); 2366 sc->sc_enabled = 0; 2367 } 2368 } 2369 2370 /* 2371 * fxp_activate: 2372 * 2373 * Handle device activation/deactivation requests. 2374 */ 2375 int 2376 fxp_activate(struct device *self, enum devact act) 2377 { 2378 struct fxp_softc *sc = (void *) self; 2379 int s, error = 0; 2380 2381 s = splnet(); 2382 switch (act) { 2383 case DVACT_ACTIVATE: 2384 error = EOPNOTSUPP; 2385 break; 2386 2387 case DVACT_DEACTIVATE: 2388 if (sc->sc_flags & FXPF_MII) 2389 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2390 MII_OFFSET_ANY); 2391 if_deactivate(&sc->sc_ethercom.ec_if); 2392 break; 2393 } 2394 splx(s); 2395 2396 return (error); 2397 } 2398 2399 /* 2400 * fxp_detach: 2401 * 2402 * Detach an i82557 interface. 2403 */ 2404 int 2405 fxp_detach(struct fxp_softc *sc) 2406 { 2407 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2408 int i; 2409 2410 /* Succeed now if there's no work to do. */ 2411 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2412 return (0); 2413 2414 /* Unhook our tick handler. */ 2415 callout_stop(&sc->sc_callout); 2416 2417 if (sc->sc_flags & FXPF_MII) { 2418 /* Detach all PHYs */ 2419 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2420 } 2421 2422 /* Delete all remaining media. */ 2423 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2424 2425 #if NRND > 0 2426 rnd_detach_source(&sc->rnd_source); 2427 #endif 2428 ether_ifdetach(ifp); 2429 if_detach(ifp); 2430 2431 for (i = 0; i < FXP_NRFABUFS; i++) { 2432 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2433 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2434 } 2435 2436 for (i = 0; i < FXP_NTXCB; i++) { 2437 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2438 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2439 } 2440 2441 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2442 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2443 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2444 sizeof(struct fxp_control_data)); 2445 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2446 2447 return (0); 2448 } 2449
Indexes created Tue Sep 30 17:09:57 GMT 2025