i82557.c revision 1.111
1 /* $NetBSD: i82557.c,v 1.111 2008/02/07 01:21:53 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.111 2008/02/07 01:21:53 dyoung Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, void *); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 int fxp_rxintr(struct fxp_softc *); 192 193 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 int fxp_copy_small = 0; 210 211 /* 212 * Variables for interrupt mitigating microcode. 213 */ 214 int fxp_int_delay = 1000; /* usec */ 215 int fxp_bundle_max = 6; /* packets */ 216 217 struct fxp_phytype { 218 int fp_phy; /* type of PHY, -1 for MII at the end. */ 219 void (*fp_init)(struct fxp_softc *); 220 } fxp_phytype_table[] = { 221 { FXP_PHY_80C24, fxp_80c24_initmedia }, 222 { -1, fxp_mii_initmedia }, 223 }; 224 225 /* 226 * Set initial transmit threshold at 64 (512 bytes). This is 227 * increased by 64 (512 bytes) at a time, to maximum of 192 228 * (1536 bytes), if an underrun occurs. 229 */ 230 static int tx_threshold = 64; 231 232 /* 233 * Wait for the previous command to be accepted (but not necessarily 234 * completed). 235 */ 236 static inline void 237 fxp_scb_wait(struct fxp_softc *sc) 238 { 239 int i = 10000; 240 241 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 242 delay(2); 243 if (i == 0) 244 log(LOG_WARNING, 245 "%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 246 } 247 248 /* 249 * Submit a command to the i82557. 250 */ 251 static inline void 252 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253 { 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256 } 257 258 /* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261 void 262 fxp_attach(struct fxp_softc *sc) 263 { 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout, 0); 271 272 /* 273 * Enable some good stuff on i82558 and later. 274 */ 275 if (sc->sc_rev >= FXP_REV_82558_A4) { 276 /* Enable the extended TxCB. */ 277 sc->sc_flags |= FXPF_EXT_TXCB; 278 } 279 280 /* 281 * Enable use of extended RFDs and TCBs for 82550 282 * and later chips. Note: we need extended TXCB support 283 * too, but that's already enabled by the code above. 284 * Be careful to do this only on the right devices. 285 */ 286 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 287 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 288 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 289 } else { 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 291 } 292 293 sc->sc_rfa_size = 294 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 295 296 /* 297 * Allocate the control data structures, and create and load the 298 * DMA map for it. 299 */ 300 if ((error = bus_dmamem_alloc(sc->sc_dmat, 301 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 302 0)) != 0) { 303 aprint_error( 304 "%s: unable to allocate control data, error = %d\n", 305 sc->sc_dev.dv_xname, error); 306 goto fail_0; 307 } 308 309 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 310 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 311 BUS_DMA_COHERENT)) != 0) { 312 aprint_error("%s: unable to map control data, error = %d\n", 313 sc->sc_dev.dv_xname, error); 314 goto fail_1; 315 } 316 sc->sc_cdseg = seg; 317 sc->sc_cdnseg = rseg; 318 319 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 320 321 if ((error = bus_dmamap_create(sc->sc_dmat, 322 sizeof(struct fxp_control_data), 1, 323 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 324 aprint_error("%s: unable to create control data DMA map, " 325 "error = %d\n", sc->sc_dev.dv_xname, error); 326 goto fail_2; 327 } 328 329 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 330 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 331 0)) != 0) { 332 aprint_error( 333 "%s: can't load control data DMA map, error = %d\n", 334 sc->sc_dev.dv_xname, error); 335 goto fail_3; 336 } 337 338 /* 339 * Create the transmit buffer DMA maps. 340 */ 341 for (i = 0; i < FXP_NTXCB; i++) { 342 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 343 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 344 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 345 aprint_error("%s: unable to create tx DMA map %d, " 346 "error = %d\n", sc->sc_dev.dv_xname, i, error); 347 goto fail_4; 348 } 349 } 350 351 /* 352 * Create the receive buffer DMA maps. 353 */ 354 for (i = 0; i < FXP_NRFABUFS; i++) { 355 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 356 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 357 aprint_error("%s: unable to create rx DMA map %d, " 358 "error = %d\n", sc->sc_dev.dv_xname, i, error); 359 goto fail_5; 360 } 361 } 362 363 /* Initialize MAC address and media structures. */ 364 fxp_get_info(sc, enaddr); 365 366 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 367 ether_sprintf(enaddr)); 368 369 ifp = &sc->sc_ethercom.ec_if; 370 371 /* 372 * Get info about our media interface, and initialize it. Note 373 * the table terminates itself with a phy of -1, indicating 374 * that we're using MII. 375 */ 376 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 377 if (fp->fp_phy == sc->phy_primary_device) 378 break; 379 (*fp->fp_init)(sc); 380 381 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 382 ifp->if_softc = sc; 383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 384 ifp->if_ioctl = fxp_ioctl; 385 ifp->if_start = fxp_start; 386 ifp->if_watchdog = fxp_watchdog; 387 ifp->if_init = fxp_init; 388 ifp->if_stop = fxp_stop; 389 IFQ_SET_READY(&ifp->if_snd); 390 391 if (sc->sc_flags & FXPF_IPCB) { 392 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 393 /* 394 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 395 * at least, on i82550 rev.12. 396 * specifically, it doesn't calculate ipv4 checksum correctly 397 * when sending 20 byte ipv4 header + 1 or 2 byte data. 398 * FreeBSD driver has related comments. 399 */ 400 ifp->if_capabilities = 401 IFCAP_CSUM_IPv4_Rx | 402 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 403 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 404 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 405 } 406 407 /* 408 * We can support 802.1Q VLAN-sized frames. 409 */ 410 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 411 412 /* 413 * Attach the interface. 414 */ 415 if_attach(ifp); 416 ether_ifattach(ifp, enaddr); 417 #if NRND > 0 418 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 419 RND_TYPE_NET, 0); 420 #endif 421 422 #ifdef FXP_EVENT_COUNTERS 423 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 424 NULL, sc->sc_dev.dv_xname, "txstall"); 425 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 426 NULL, sc->sc_dev.dv_xname, "txintr"); 427 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 428 NULL, sc->sc_dev.dv_xname, "rxintr"); 429 if (sc->sc_rev >= FXP_REV_82558_A4) { 430 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 431 NULL, sc->sc_dev.dv_xname, "txpause"); 432 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 433 NULL, sc->sc_dev.dv_xname, "rxpause"); 434 } 435 #endif /* FXP_EVENT_COUNTERS */ 436 437 /* The attach is successful. */ 438 sc->sc_flags |= FXPF_ATTACHED; 439 440 return; 441 442 /* 443 * Free any resources we've allocated during the failed attach 444 * attempt. Do this in reverse order and fall though. 445 */ 446 fail_5: 447 for (i = 0; i < FXP_NRFABUFS; i++) { 448 if (sc->sc_rxmaps[i] != NULL) 449 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 450 } 451 fail_4: 452 for (i = 0; i < FXP_NTXCB; i++) { 453 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 454 bus_dmamap_destroy(sc->sc_dmat, 455 FXP_DSTX(sc, i)->txs_dmamap); 456 } 457 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 458 fail_3: 459 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 460 fail_2: 461 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 462 sizeof(struct fxp_control_data)); 463 fail_1: 464 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 465 fail_0: 466 return; 467 } 468 469 void 470 fxp_mii_initmedia(struct fxp_softc *sc) 471 { 472 int flags; 473 474 sc->sc_flags |= FXPF_MII; 475 476 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 477 sc->sc_mii.mii_readreg = fxp_mdi_read; 478 sc->sc_mii.mii_writereg = fxp_mdi_write; 479 sc->sc_mii.mii_statchg = fxp_statchg; 480 481 sc->sc_ethercom.ec_mii = &sc->sc_mii; 482 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 483 fxp_mii_mediastatus); 484 485 flags = MIIF_NOISOLATE; 486 if (sc->sc_rev >= FXP_REV_82558_A4) 487 flags |= MIIF_DOPAUSE; 488 /* 489 * The i82557 wedges if all of its PHYs are isolated! 490 */ 491 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 492 MII_OFFSET_ANY, flags); 493 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 495 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 496 } else 497 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 498 } 499 500 void 501 fxp_80c24_initmedia(struct fxp_softc *sc) 502 { 503 504 /* 505 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 506 * doesn't have a programming interface of any sort. The 507 * media is sensed automatically based on how the link partner 508 * is configured. This is, in essence, manual configuration. 509 */ 510 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 511 sc->sc_dev.dv_xname); 512 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 513 fxp_80c24_mediastatus); 514 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 515 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 516 } 517 518 /* 519 * Initialize the interface media. 520 */ 521 void 522 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 523 { 524 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 525 526 /* 527 * Reset to a stable state. 528 */ 529 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 530 DELAY(100); 531 532 sc->sc_eeprom_size = 0; 533 fxp_autosize_eeprom(sc); 534 if (sc->sc_eeprom_size == 0) { 535 aprint_error("%s: failed to detect EEPROM size\n", 536 sc->sc_dev.dv_xname); 537 sc->sc_eeprom_size = 6; /* XXX panic here? */ 538 } 539 #ifdef DEBUG 540 aprint_debug("%s: detected %d word EEPROM\n", 541 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 542 #endif 543 544 /* 545 * Get info about the primary PHY 546 */ 547 fxp_read_eeprom(sc, &data, 6, 1); 548 sc->phy_primary_device = 549 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 550 551 /* 552 * Read MAC address. 553 */ 554 fxp_read_eeprom(sc, myea, 0, 3); 555 enaddr[0] = myea[0] & 0xff; 556 enaddr[1] = myea[0] >> 8; 557 enaddr[2] = myea[1] & 0xff; 558 enaddr[3] = myea[1] >> 8; 559 enaddr[4] = myea[2] & 0xff; 560 enaddr[5] = myea[2] >> 8; 561 562 /* 563 * Systems based on the ICH2/ICH2-M chip from Intel, as well 564 * as some i82559 designs, have a defect where the chip can 565 * cause a PCI protocol violation if it receives a CU_RESUME 566 * command when it is entering the IDLE state. 567 * 568 * The work-around is to disable Dynamic Standby Mode, so that 569 * the chip never deasserts #CLKRUN, and always remains in the 570 * active state. 571 * 572 * Unfortunately, the only way to disable Dynamic Standby is 573 * to frob an EEPROM setting and reboot (the EEPROM setting 574 * is only consulted when the PCI bus comes out of reset). 575 * 576 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 577 */ 578 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 579 fxp_read_eeprom(sc, &data, 10, 1); 580 if (data & 0x02) { /* STB enable */ 581 aprint_error("%s: WARNING: " 582 "Disabling dynamic standby mode in EEPROM " 583 "to work around a\n", 584 sc->sc_dev.dv_xname); 585 aprint_normal( 586 "%s: WARNING: hardware bug. You must reset " 587 "the system before using this\n", 588 sc->sc_dev.dv_xname); 589 aprint_normal("%s: WARNING: interface.\n", 590 sc->sc_dev.dv_xname); 591 data &= ~0x02; 592 fxp_write_eeprom(sc, &data, 10, 1); 593 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 594 sc->sc_dev.dv_xname, data); 595 fxp_eeprom_update_cksum(sc); 596 } 597 } 598 599 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 600 /* Due to false positives we make it conditional on setting link1 */ 601 fxp_read_eeprom(sc, &data, 3, 1); 602 if ((data & 0x03) != 0x03) { 603 aprint_verbose("%s: May need receiver lock-up workaround\n", 604 sc->sc_dev.dv_xname); 605 } 606 } 607 608 static void 609 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 610 { 611 uint16_t reg; 612 int x; 613 614 for (x = 1 << (len - 1); x != 0; x >>= 1) { 615 DELAY(40); 616 if (data & x) 617 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 618 else 619 reg = FXP_EEPROM_EECS; 620 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 621 DELAY(40); 622 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 623 reg | FXP_EEPROM_EESK); 624 DELAY(40); 625 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 626 } 627 DELAY(40); 628 } 629 630 /* 631 * Figure out EEPROM size. 632 * 633 * 559's can have either 64-word or 256-word EEPROMs, the 558 634 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 635 * talks about the existence of 16 to 256 word EEPROMs. 636 * 637 * The only known sizes are 64 and 256, where the 256 version is used 638 * by CardBus cards to store CIS information. 639 * 640 * The address is shifted in msb-to-lsb, and after the last 641 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 642 * after which follows the actual data. We try to detect this zero, by 643 * probing the data-out bit in the EEPROM control register just after 644 * having shifted in a bit. If the bit is zero, we assume we've 645 * shifted enough address bits. The data-out should be tri-state, 646 * before this, which should translate to a logical one. 647 * 648 * Other ways to do this would be to try to read a register with known 649 * contents with a varying number of address bits, but no such 650 * register seem to be available. The high bits of register 10 are 01 651 * on the 558 and 559, but apparently not on the 557. 652 * 653 * The Linux driver computes a checksum on the EEPROM data, but the 654 * value of this checksum is not very well documented. 655 */ 656 657 void 658 fxp_autosize_eeprom(struct fxp_softc *sc) 659 { 660 int x; 661 662 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 663 DELAY(40); 664 665 /* Shift in read opcode. */ 666 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 667 668 /* 669 * Shift in address, wait for the dummy zero following a correct 670 * address shift. 671 */ 672 for (x = 1; x <= 8; x++) { 673 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 674 DELAY(40); 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 676 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 677 DELAY(40); 678 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 679 FXP_EEPROM_EEDO) == 0) 680 break; 681 DELAY(40); 682 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 683 DELAY(40); 684 } 685 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 686 DELAY(40); 687 if (x != 6 && x != 8) { 688 #ifdef DEBUG 689 printf("%s: strange EEPROM size (%d)\n", 690 sc->sc_dev.dv_xname, 1 << x); 691 #endif 692 } else 693 sc->sc_eeprom_size = x; 694 } 695 696 /* 697 * Read from the serial EEPROM. Basically, you manually shift in 698 * the read opcode (one bit at a time) and then shift in the address, 699 * and then you shift out the data (all of this one bit at a time). 700 * The word size is 16 bits, so you have to provide the address for 701 * every 16 bits of data. 702 */ 703 void 704 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 705 { 706 u_int16_t reg; 707 int i, x; 708 709 for (i = 0; i < words; i++) { 710 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 711 712 /* Shift in read opcode. */ 713 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 714 715 /* Shift in address. */ 716 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 717 718 reg = FXP_EEPROM_EECS; 719 data[i] = 0; 720 721 /* Shift out data. */ 722 for (x = 16; x > 0; x--) { 723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 724 reg | FXP_EEPROM_EESK); 725 DELAY(40); 726 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 727 FXP_EEPROM_EEDO) 728 data[i] |= (1 << (x - 1)); 729 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 730 DELAY(40); 731 } 732 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 733 DELAY(40); 734 } 735 } 736 737 /* 738 * Write data to the serial EEPROM. 739 */ 740 void 741 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 742 { 743 int i, j; 744 745 for (i = 0; i < words; i++) { 746 /* Erase/write enable. */ 747 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 748 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 749 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 750 sc->sc_eeprom_size); 751 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 752 DELAY(4); 753 754 /* Shift in write opcode, address, data. */ 755 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 756 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 757 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 758 fxp_eeprom_shiftin(sc, data[i], 16); 759 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 760 DELAY(4); 761 762 /* Wait for the EEPROM to finish up. */ 763 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 764 DELAY(4); 765 for (j = 0; j < 1000; j++) { 766 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 767 FXP_EEPROM_EEDO) 768 break; 769 DELAY(50); 770 } 771 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 772 DELAY(4); 773 774 /* Erase/write disable. */ 775 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 776 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 777 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 778 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 779 DELAY(4); 780 } 781 } 782 783 /* 784 * Update the checksum of the EEPROM. 785 */ 786 void 787 fxp_eeprom_update_cksum(struct fxp_softc *sc) 788 { 789 int i; 790 uint16_t data, cksum; 791 792 cksum = 0; 793 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 794 fxp_read_eeprom(sc, &data, i, 1); 795 cksum += data; 796 } 797 i = (1 << sc->sc_eeprom_size) - 1; 798 cksum = 0xbaba - cksum; 799 fxp_read_eeprom(sc, &data, i, 1); 800 fxp_write_eeprom(sc, &cksum, i, 1); 801 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 802 sc->sc_dev.dv_xname, i, data, cksum); 803 } 804 805 /* 806 * Start packet transmission on the interface. 807 */ 808 void 809 fxp_start(struct ifnet *ifp) 810 { 811 struct fxp_softc *sc = ifp->if_softc; 812 struct mbuf *m0, *m; 813 struct fxp_txdesc *txd; 814 struct fxp_txsoft *txs; 815 bus_dmamap_t dmamap; 816 int error, lasttx, nexttx, opending, seg; 817 818 /* 819 * If we want a re-init, bail out now. 820 */ 821 if (sc->sc_flags & FXPF_WANTINIT) { 822 ifp->if_flags |= IFF_OACTIVE; 823 return; 824 } 825 826 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 827 return; 828 829 /* 830 * Remember the previous txpending and the current lasttx. 831 */ 832 opending = sc->sc_txpending; 833 lasttx = sc->sc_txlast; 834 835 /* 836 * Loop through the send queue, setting up transmit descriptors 837 * until we drain the queue, or use up all available transmit 838 * descriptors. 839 */ 840 for (;;) { 841 struct fxp_tbd *tbdp; 842 int csum_flags; 843 844 /* 845 * Grab a packet off the queue. 846 */ 847 IFQ_POLL(&ifp->if_snd, m0); 848 if (m0 == NULL) 849 break; 850 m = NULL; 851 852 if (sc->sc_txpending == FXP_NTXCB - 1) { 853 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 854 break; 855 } 856 857 /* 858 * Get the next available transmit descriptor. 859 */ 860 nexttx = FXP_NEXTTX(sc->sc_txlast); 861 txd = FXP_CDTX(sc, nexttx); 862 txs = FXP_DSTX(sc, nexttx); 863 dmamap = txs->txs_dmamap; 864 865 /* 866 * Load the DMA map. If this fails, the packet either 867 * didn't fit in the allotted number of frags, or we were 868 * short on resources. In this case, we'll copy and try 869 * again. 870 */ 871 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 872 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 873 MGETHDR(m, M_DONTWAIT, MT_DATA); 874 if (m == NULL) { 875 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 876 sc->sc_dev.dv_xname); 877 break; 878 } 879 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 880 if (m0->m_pkthdr.len > MHLEN) { 881 MCLGET(m, M_DONTWAIT); 882 if ((m->m_flags & M_EXT) == 0) { 883 log(LOG_ERR, 884 "%s: unable to allocate Tx " 885 "cluster\n", sc->sc_dev.dv_xname); 886 m_freem(m); 887 break; 888 } 889 } 890 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 891 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 892 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 893 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 894 if (error) { 895 log(LOG_ERR, "%s: unable to load Tx buffer, " 896 "error = %d\n", sc->sc_dev.dv_xname, error); 897 break; 898 } 899 } 900 901 IFQ_DEQUEUE(&ifp->if_snd, m0); 902 csum_flags = m0->m_pkthdr.csum_flags; 903 if (m != NULL) { 904 m_freem(m0); 905 m0 = m; 906 } 907 908 /* Initialize the fraglist. */ 909 tbdp = txd->txd_tbd; 910 if (sc->sc_flags & FXPF_IPCB) 911 tbdp++; 912 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 913 tbdp[seg].tb_addr = 914 htole32(dmamap->dm_segs[seg].ds_addr); 915 tbdp[seg].tb_size = 916 htole32(dmamap->dm_segs[seg].ds_len); 917 } 918 919 /* Sync the DMA map. */ 920 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 921 BUS_DMASYNC_PREWRITE); 922 923 /* 924 * Store a pointer to the packet so we can free it later. 925 */ 926 txs->txs_mbuf = m0; 927 928 /* 929 * Initialize the transmit descriptor. 930 */ 931 /* BIG_ENDIAN: no need to swap to store 0 */ 932 txd->txd_txcb.cb_status = 0; 933 txd->txd_txcb.cb_command = 934 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 935 txd->txd_txcb.tx_threshold = tx_threshold; 936 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 937 938 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 939 if (sc->sc_flags & FXPF_IPCB) { 940 struct m_tag *vtag; 941 struct fxp_ipcb *ipcb; 942 /* 943 * Deal with TCP/IP checksum offload. Note that 944 * in order for TCP checksum offload to work, 945 * the pseudo header checksum must have already 946 * been computed and stored in the checksum field 947 * in the TCP header. The stack should have 948 * already done this for us. 949 */ 950 ipcb = &txd->txd_u.txdu_ipcb; 951 memset(ipcb, 0, sizeof(*ipcb)); 952 /* 953 * always do hardware parsing. 954 */ 955 ipcb->ipcb_ip_activation_high = 956 FXP_IPCB_HARDWAREPARSING_ENABLE; 957 /* 958 * ip checksum offloading. 959 */ 960 if (csum_flags & M_CSUM_IPv4) { 961 ipcb->ipcb_ip_schedule |= 962 FXP_IPCB_IP_CHECKSUM_ENABLE; 963 } 964 /* 965 * TCP/UDP checksum offloading. 966 */ 967 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 968 ipcb->ipcb_ip_schedule |= 969 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 970 } 971 972 /* 973 * request VLAN tag insertion if needed. 974 */ 975 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 976 if (vtag) { 977 ipcb->ipcb_vlan_id = 978 htobe16(*(u_int *)(vtag + 1)); 979 ipcb->ipcb_ip_activation_high |= 980 FXP_IPCB_INSERTVLAN_ENABLE; 981 } 982 } else { 983 KASSERT((csum_flags & 984 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 985 } 986 987 FXP_CDTXSYNC(sc, nexttx, 988 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 989 990 /* Advance the tx pointer. */ 991 sc->sc_txpending++; 992 sc->sc_txlast = nexttx; 993 994 #if NBPFILTER > 0 995 /* 996 * Pass packet to bpf if there is a listener. 997 */ 998 if (ifp->if_bpf) 999 bpf_mtap(ifp->if_bpf, m0); 1000 #endif 1001 } 1002 1003 if (sc->sc_txpending == FXP_NTXCB - 1) { 1004 /* No more slots; notify upper layer. */ 1005 ifp->if_flags |= IFF_OACTIVE; 1006 } 1007 1008 if (sc->sc_txpending != opending) { 1009 /* 1010 * We enqueued packets. If the transmitter was idle, 1011 * reset the txdirty pointer. 1012 */ 1013 if (opending == 0) 1014 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1015 1016 /* 1017 * Cause the chip to interrupt and suspend command 1018 * processing once the last packet we've enqueued 1019 * has been transmitted. 1020 * 1021 * To avoid a race between updating status bits 1022 * by the fxp chip and clearing command bits 1023 * by this function on machines which don't have 1024 * atomic methods to clear/set bits in memory 1025 * smaller than 32bits (both cb_status and cb_command 1026 * members are uint16_t and in the same 32bit word), 1027 * we have to prepare a dummy TX descriptor which has 1028 * NOP command and just causes a TX completion interrupt. 1029 */ 1030 sc->sc_txpending++; 1031 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1032 txd = FXP_CDTX(sc, sc->sc_txlast); 1033 /* BIG_ENDIAN: no need to swap to store 0 */ 1034 txd->txd_txcb.cb_status = 0; 1035 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1036 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1037 FXP_CDTXSYNC(sc, sc->sc_txlast, 1038 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1039 1040 /* 1041 * The entire packet chain is set up. Clear the suspend bit 1042 * on the command prior to the first packet we set up. 1043 */ 1044 FXP_CDTXSYNC(sc, lasttx, 1045 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1046 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1047 htole16(~FXP_CB_COMMAND_S); 1048 FXP_CDTXSYNC(sc, lasttx, 1049 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1050 1051 /* 1052 * Issue a Resume command in case the chip was suspended. 1053 */ 1054 fxp_scb_wait(sc); 1055 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1056 1057 /* Set a watchdog timer in case the chip flakes out. */ 1058 ifp->if_timer = 5; 1059 } 1060 } 1061 1062 /* 1063 * Process interface interrupts. 1064 */ 1065 int 1066 fxp_intr(void *arg) 1067 { 1068 struct fxp_softc *sc = arg; 1069 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1070 bus_dmamap_t rxmap; 1071 int claimed = 0, rnr; 1072 u_int8_t statack; 1073 1074 if (!device_is_active(&sc->sc_dev) || sc->sc_enabled == 0) 1075 return (0); 1076 /* 1077 * If the interface isn't running, don't try to 1078 * service the interrupt.. just ack it and bail. 1079 */ 1080 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1081 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1082 if (statack) { 1083 claimed = 1; 1084 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1085 } 1086 return (claimed); 1087 } 1088 1089 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1090 claimed = 1; 1091 1092 /* 1093 * First ACK all the interrupts in this pass. 1094 */ 1095 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1096 1097 /* 1098 * Process receiver interrupts. If a no-resource (RNR) 1099 * condition exists, get whatever packets we can and 1100 * re-start the receiver. 1101 */ 1102 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1103 1 : 0; 1104 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1105 FXP_SCB_STATACK_SWI)) { 1106 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1107 rnr |= fxp_rxintr(sc); 1108 } 1109 1110 /* 1111 * Free any finished transmit mbuf chains. 1112 */ 1113 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1114 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1115 fxp_txintr(sc); 1116 1117 /* 1118 * Try to get more packets going. 1119 */ 1120 fxp_start(ifp); 1121 1122 if (sc->sc_txpending == 0) { 1123 /* 1124 * If we want a re-init, do that now. 1125 */ 1126 if (sc->sc_flags & FXPF_WANTINIT) 1127 (void) fxp_init(ifp); 1128 } 1129 } 1130 1131 if (rnr) { 1132 fxp_scb_wait(sc); 1133 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1134 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1135 fxp_scb_wait(sc); 1136 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1137 rxmap->dm_segs[0].ds_addr + 1138 RFA_ALIGNMENT_FUDGE); 1139 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1140 } 1141 } 1142 1143 #if NRND > 0 1144 if (claimed) 1145 rnd_add_uint32(&sc->rnd_source, statack); 1146 #endif 1147 return (claimed); 1148 } 1149 1150 /* 1151 * Handle transmit completion interrupts. 1152 */ 1153 void 1154 fxp_txintr(struct fxp_softc *sc) 1155 { 1156 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1157 struct fxp_txdesc *txd; 1158 struct fxp_txsoft *txs; 1159 int i; 1160 u_int16_t txstat; 1161 1162 ifp->if_flags &= ~IFF_OACTIVE; 1163 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1164 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1165 txd = FXP_CDTX(sc, i); 1166 txs = FXP_DSTX(sc, i); 1167 1168 FXP_CDTXSYNC(sc, i, 1169 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1170 1171 /* skip dummy NOP TX descriptor */ 1172 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1173 == FXP_CB_COMMAND_NOP) 1174 continue; 1175 1176 txstat = le16toh(txd->txd_txcb.cb_status); 1177 1178 if ((txstat & FXP_CB_STATUS_C) == 0) 1179 break; 1180 1181 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1182 0, txs->txs_dmamap->dm_mapsize, 1183 BUS_DMASYNC_POSTWRITE); 1184 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1185 m_freem(txs->txs_mbuf); 1186 txs->txs_mbuf = NULL; 1187 } 1188 1189 /* Update the dirty transmit buffer pointer. */ 1190 sc->sc_txdirty = i; 1191 1192 /* 1193 * Cancel the watchdog timer if there are no pending 1194 * transmissions. 1195 */ 1196 if (sc->sc_txpending == 0) 1197 ifp->if_timer = 0; 1198 } 1199 1200 /* 1201 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1202 */ 1203 1204 int 1205 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1206 { 1207 u_int16_t rxparsestat; 1208 u_int16_t csum_stat; 1209 u_int32_t csum_data; 1210 int csum_flags; 1211 1212 /* 1213 * check VLAN tag stripping. 1214 */ 1215 1216 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1217 struct m_tag *vtag; 1218 1219 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1220 if (vtag == NULL) 1221 return ENOMEM; 1222 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1223 m_tag_prepend(m, vtag); 1224 } 1225 1226 /* 1227 * check H/W Checksumming. 1228 */ 1229 1230 csum_stat = le16toh(rfa->cksum_stat); 1231 rxparsestat = le16toh(rfa->rx_parse_stat); 1232 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1233 return 0; 1234 1235 csum_flags = 0; 1236 csum_data = 0; 1237 1238 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1239 csum_flags = M_CSUM_IPv4; 1240 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1241 csum_flags |= M_CSUM_IPv4_BAD; 1242 } 1243 1244 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1245 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1246 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1247 csum_flags |= M_CSUM_TCP_UDP_BAD; 1248 } 1249 1250 m->m_pkthdr.csum_flags = csum_flags; 1251 m->m_pkthdr.csum_data = csum_data; 1252 1253 return 0; 1254 } 1255 1256 /* 1257 * Handle receive interrupts. 1258 */ 1259 int 1260 fxp_rxintr(struct fxp_softc *sc) 1261 { 1262 struct ethercom *ec = &sc->sc_ethercom; 1263 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1264 struct mbuf *m, *m0; 1265 bus_dmamap_t rxmap; 1266 struct fxp_rfa *rfa; 1267 int rnr; 1268 u_int16_t len, rxstat; 1269 1270 rnr = 0; 1271 1272 for (;;) { 1273 m = sc->sc_rxq.ifq_head; 1274 rfa = FXP_MTORFA(m); 1275 rxmap = M_GETCTX(m, bus_dmamap_t); 1276 1277 FXP_RFASYNC(sc, m, 1278 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1279 1280 rxstat = le16toh(rfa->rfa_status); 1281 1282 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1283 rnr = 1; 1284 1285 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1286 /* 1287 * We have processed all of the 1288 * receive buffers. 1289 */ 1290 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1291 return rnr; 1292 } 1293 1294 IF_DEQUEUE(&sc->sc_rxq, m); 1295 1296 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1297 1298 len = le16toh(rfa->actual_size) & 1299 (m->m_ext.ext_size - 1); 1300 1301 if (len < sizeof(struct ether_header)) { 1302 /* 1303 * Runt packet; drop it now. 1304 */ 1305 FXP_INIT_RFABUF(sc, m); 1306 continue; 1307 } 1308 1309 /* 1310 * If support for 802.1Q VLAN sized frames is 1311 * enabled, we need to do some additional error 1312 * checking (as we are saving bad frames, in 1313 * order to receive the larger ones). 1314 */ 1315 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1316 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1317 FXP_RFA_STATUS_RNR| 1318 FXP_RFA_STATUS_ALIGN| 1319 FXP_RFA_STATUS_CRC)) != 0) { 1320 FXP_INIT_RFABUF(sc, m); 1321 continue; 1322 } 1323 1324 /* Do checksum checking. */ 1325 m->m_pkthdr.csum_flags = 0; 1326 if (sc->sc_flags & FXPF_EXT_RFA) 1327 if (fxp_rx_hwcksum(m, rfa)) 1328 goto dropit; 1329 1330 /* 1331 * If the packet is small enough to fit in a 1332 * single header mbuf, allocate one and copy 1333 * the data into it. This greatly reduces 1334 * memory consumption when we receive lots 1335 * of small packets. 1336 * 1337 * Otherwise, we add a new buffer to the receive 1338 * chain. If this fails, we drop the packet and 1339 * recycle the old buffer. 1340 */ 1341 if (fxp_copy_small != 0 && len <= MHLEN) { 1342 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1343 if (m0 == NULL) 1344 goto dropit; 1345 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1346 memcpy(mtod(m0, void *), 1347 mtod(m, void *), len); 1348 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1349 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1350 FXP_INIT_RFABUF(sc, m); 1351 m = m0; 1352 } else { 1353 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1354 dropit: 1355 ifp->if_ierrors++; 1356 FXP_INIT_RFABUF(sc, m); 1357 continue; 1358 } 1359 } 1360 1361 m->m_pkthdr.rcvif = ifp; 1362 m->m_pkthdr.len = m->m_len = len; 1363 1364 #if NBPFILTER > 0 1365 /* 1366 * Pass this up to any BPF listeners, but only 1367 * pass it up the stack if it's for us. 1368 */ 1369 if (ifp->if_bpf) 1370 bpf_mtap(ifp->if_bpf, m); 1371 #endif 1372 1373 /* Pass it on. */ 1374 (*ifp->if_input)(ifp, m); 1375 } 1376 } 1377 1378 /* 1379 * Update packet in/out/collision statistics. The i82557 doesn't 1380 * allow you to access these counters without doing a fairly 1381 * expensive DMA to get _all_ of the statistics it maintains, so 1382 * we do this operation here only once per second. The statistics 1383 * counters in the kernel are updated from the previous dump-stats 1384 * DMA and then a new dump-stats DMA is started. The on-chip 1385 * counters are zeroed when the DMA completes. If we can't start 1386 * the DMA immediately, we don't wait - we just prepare to read 1387 * them again next time. 1388 */ 1389 void 1390 fxp_tick(void *arg) 1391 { 1392 struct fxp_softc *sc = arg; 1393 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1394 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1395 int s; 1396 1397 if (!device_is_active(&sc->sc_dev)) 1398 return; 1399 1400 s = splnet(); 1401 1402 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1403 1404 ifp->if_opackets += le32toh(sp->tx_good); 1405 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1406 if (sp->rx_good) { 1407 ifp->if_ipackets += le32toh(sp->rx_good); 1408 sc->sc_rxidle = 0; 1409 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1410 sc->sc_rxidle++; 1411 } 1412 ifp->if_ierrors += 1413 le32toh(sp->rx_crc_errors) + 1414 le32toh(sp->rx_alignment_errors) + 1415 le32toh(sp->rx_rnr_errors) + 1416 le32toh(sp->rx_overrun_errors); 1417 /* 1418 * If any transmit underruns occurred, bump up the transmit 1419 * threshold by another 512 bytes (64 * 8). 1420 */ 1421 if (sp->tx_underruns) { 1422 ifp->if_oerrors += le32toh(sp->tx_underruns); 1423 if (tx_threshold < 192) 1424 tx_threshold += 64; 1425 } 1426 #ifdef FXP_EVENT_COUNTERS 1427 if (sc->sc_rev >= FXP_REV_82558_A4) { 1428 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1429 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1430 } 1431 #endif 1432 1433 /* 1434 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1435 * then assume the receiver has locked up and attempt to clear 1436 * the condition by reprogramming the multicast filter (actually, 1437 * resetting the interface). This is a work-around for a bug in 1438 * the 82557 where the receiver locks up if it gets certain types 1439 * of garbage in the synchronization bits prior to the packet header. 1440 * This bug is supposed to only occur in 10Mbps mode, but has been 1441 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1442 * speed transition). 1443 */ 1444 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1445 (void) fxp_init(ifp); 1446 splx(s); 1447 return; 1448 } 1449 /* 1450 * If there is no pending command, start another stats 1451 * dump. Otherwise punt for now. 1452 */ 1453 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1454 /* 1455 * Start another stats dump. 1456 */ 1457 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1458 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1459 } else { 1460 /* 1461 * A previous command is still waiting to be accepted. 1462 * Just zero our copy of the stats and wait for the 1463 * next timer event to update them. 1464 */ 1465 /* BIG_ENDIAN: no swap required to store 0 */ 1466 sp->tx_good = 0; 1467 sp->tx_underruns = 0; 1468 sp->tx_total_collisions = 0; 1469 1470 sp->rx_good = 0; 1471 sp->rx_crc_errors = 0; 1472 sp->rx_alignment_errors = 0; 1473 sp->rx_rnr_errors = 0; 1474 sp->rx_overrun_errors = 0; 1475 if (sc->sc_rev >= FXP_REV_82558_A4) { 1476 sp->tx_pauseframes = 0; 1477 sp->rx_pauseframes = 0; 1478 } 1479 } 1480 1481 if (sc->sc_flags & FXPF_MII) { 1482 /* Tick the MII clock. */ 1483 mii_tick(&sc->sc_mii); 1484 } 1485 1486 splx(s); 1487 1488 /* 1489 * Schedule another timeout one second from now. 1490 */ 1491 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1492 } 1493 1494 /* 1495 * Drain the receive queue. 1496 */ 1497 void 1498 fxp_rxdrain(struct fxp_softc *sc) 1499 { 1500 bus_dmamap_t rxmap; 1501 struct mbuf *m; 1502 1503 for (;;) { 1504 IF_DEQUEUE(&sc->sc_rxq, m); 1505 if (m == NULL) 1506 break; 1507 rxmap = M_GETCTX(m, bus_dmamap_t); 1508 bus_dmamap_unload(sc->sc_dmat, rxmap); 1509 FXP_RXMAP_PUT(sc, rxmap); 1510 m_freem(m); 1511 } 1512 } 1513 1514 /* 1515 * Stop the interface. Cancels the statistics updater and resets 1516 * the interface. 1517 */ 1518 void 1519 fxp_stop(struct ifnet *ifp, int disable) 1520 { 1521 struct fxp_softc *sc = ifp->if_softc; 1522 struct fxp_txsoft *txs; 1523 int i; 1524 1525 /* 1526 * Turn down interface (done early to avoid bad interactions 1527 * between panics, shutdown hooks, and the watchdog timer) 1528 */ 1529 ifp->if_timer = 0; 1530 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1531 1532 /* 1533 * Cancel stats updater. 1534 */ 1535 callout_stop(&sc->sc_callout); 1536 if (sc->sc_flags & FXPF_MII) { 1537 /* Down the MII. */ 1538 mii_down(&sc->sc_mii); 1539 } 1540 1541 /* 1542 * Issue software reset. This unloads any microcode that 1543 * might already be loaded. 1544 */ 1545 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1546 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1547 DELAY(50); 1548 1549 /* 1550 * Release any xmit buffers. 1551 */ 1552 for (i = 0; i < FXP_NTXCB; i++) { 1553 txs = FXP_DSTX(sc, i); 1554 if (txs->txs_mbuf != NULL) { 1555 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1556 m_freem(txs->txs_mbuf); 1557 txs->txs_mbuf = NULL; 1558 } 1559 } 1560 sc->sc_txpending = 0; 1561 1562 if (disable) { 1563 fxp_rxdrain(sc); 1564 fxp_disable(sc); 1565 } 1566 1567 } 1568 1569 /* 1570 * Watchdog/transmission transmit timeout handler. Called when a 1571 * transmission is started on the interface, but no interrupt is 1572 * received before the timeout. This usually indicates that the 1573 * card has wedged for some reason. 1574 */ 1575 void 1576 fxp_watchdog(struct ifnet *ifp) 1577 { 1578 struct fxp_softc *sc = ifp->if_softc; 1579 1580 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1581 ifp->if_oerrors++; 1582 1583 (void) fxp_init(ifp); 1584 } 1585 1586 /* 1587 * Initialize the interface. Must be called at splnet(). 1588 */ 1589 int 1590 fxp_init(struct ifnet *ifp) 1591 { 1592 struct fxp_softc *sc = ifp->if_softc; 1593 struct fxp_cb_config *cbp; 1594 struct fxp_cb_ias *cb_ias; 1595 struct fxp_txdesc *txd; 1596 bus_dmamap_t rxmap; 1597 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1598 1599 if ((error = fxp_enable(sc)) != 0) 1600 goto out; 1601 1602 /* 1603 * Cancel any pending I/O 1604 */ 1605 fxp_stop(ifp, 0); 1606 1607 /* 1608 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1609 * flag, and this prevents the MII from detaching resulting in 1610 * a panic. The flags field should perhaps be split in runtime 1611 * flags and more static information. For now, just clear the 1612 * only other flag set. 1613 */ 1614 1615 sc->sc_flags &= ~FXPF_WANTINIT; 1616 1617 /* 1618 * Initialize base of CBL and RFA memory. Loading with zero 1619 * sets it up for regular linear addressing. 1620 */ 1621 fxp_scb_wait(sc); 1622 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1623 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1624 1625 fxp_scb_wait(sc); 1626 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1627 1628 /* 1629 * Initialize the multicast filter. Do this now, since we might 1630 * have to setup the config block differently. 1631 */ 1632 fxp_mc_setup(sc); 1633 1634 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1635 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1636 1637 /* 1638 * In order to support receiving 802.1Q VLAN frames, we have to 1639 * enable "save bad frames", since they are 4 bytes larger than 1640 * the normal Ethernet maximum frame length. On i82558 and later, 1641 * we have a better mechanism for this. 1642 */ 1643 save_bf = 0; 1644 lrxen = 0; 1645 vlan_drop = 0; 1646 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1647 if (sc->sc_rev < FXP_REV_82558_A4) 1648 save_bf = 1; 1649 else 1650 lrxen = 1; 1651 if (sc->sc_rev >= FXP_REV_82550) 1652 vlan_drop = 1; 1653 } 1654 1655 /* 1656 * Initialize base of dump-stats buffer. 1657 */ 1658 fxp_scb_wait(sc); 1659 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1660 sc->sc_cddma + FXP_CDSTATSOFF); 1661 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1662 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1663 1664 cbp = &sc->sc_control_data->fcd_configcb; 1665 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1666 1667 /* 1668 * Load microcode for this controller. 1669 */ 1670 fxp_load_ucode(sc); 1671 1672 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1673 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1674 else 1675 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1676 1677 /* 1678 * This copy is kind of disgusting, but there are a bunch of must be 1679 * zero and must be one bits in this structure and this is the easiest 1680 * way to initialize them all to proper values. 1681 */ 1682 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1683 1684 /* BIG_ENDIAN: no need to swap to store 0 */ 1685 cbp->cb_status = 0; 1686 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1687 FXP_CB_COMMAND_EL); 1688 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1689 cbp->link_addr = 0xffffffff; /* (no) next command */ 1690 /* bytes in config block */ 1691 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1692 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1693 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1694 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1695 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1696 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1697 cbp->type_enable = 0; /* actually reserved */ 1698 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1699 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1700 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1701 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1702 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1703 cbp->late_scb = 0; /* (don't) defer SCB update */ 1704 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1705 cbp->ci_int = 1; /* interrupt on CU idle */ 1706 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1707 cbp->ext_stats_dis = 1; /* disable extended counters */ 1708 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1709 cbp->save_bf = save_bf;/* save bad frames */ 1710 cbp->disc_short_rx = !prm; /* discard short packets */ 1711 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1712 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1713 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1714 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1715 /* interface mode */ 1716 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1717 cbp->csma_dis = 0; /* (don't) disable link */ 1718 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1719 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1720 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1721 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1722 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1723 cbp->nsai = 1; /* (don't) disable source addr insert */ 1724 cbp->preamble_length = 2; /* (7 byte) preamble */ 1725 cbp->loopback = 0; /* (don't) loopback */ 1726 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1727 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1728 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1729 cbp->promiscuous = prm; /* promiscuous mode */ 1730 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1731 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1732 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1733 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1734 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1735 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1736 cbp->padding = 1; /* (do) pad short tx packets */ 1737 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1738 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1739 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1740 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1741 /* must set wake_en in PMCSR also */ 1742 cbp->force_fdx = 0; /* (don't) force full duplex */ 1743 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1744 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1745 cbp->mc_all = allm; /* accept all multicasts */ 1746 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1747 cbp->vlan_drop_en = vlan_drop; 1748 1749 if (sc->sc_rev < FXP_REV_82558_A4) { 1750 /* 1751 * The i82557 has no hardware flow control, the values 1752 * here are the defaults for the chip. 1753 */ 1754 cbp->fc_delay_lsb = 0; 1755 cbp->fc_delay_msb = 0x40; 1756 cbp->pri_fc_thresh = 3; 1757 cbp->tx_fc_dis = 0; 1758 cbp->rx_fc_restop = 0; 1759 cbp->rx_fc_restart = 0; 1760 cbp->fc_filter = 0; 1761 cbp->pri_fc_loc = 1; 1762 } else { 1763 cbp->fc_delay_lsb = 0x1f; 1764 cbp->fc_delay_msb = 0x01; 1765 cbp->pri_fc_thresh = 3; 1766 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1767 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1768 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1769 cbp->fc_filter = !prm; /* drop FC frames to host */ 1770 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1771 cbp->ext_stats_dis = 0; /* enable extended stats */ 1772 } 1773 1774 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1775 1776 /* 1777 * Start the config command/DMA. 1778 */ 1779 fxp_scb_wait(sc); 1780 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1781 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1782 /* ...and wait for it to complete. */ 1783 i = 1000; 1784 do { 1785 FXP_CDCONFIGSYNC(sc, 1786 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1787 DELAY(1); 1788 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1789 if (i == 0) { 1790 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1791 sc->sc_dev.dv_xname, __LINE__); 1792 return (ETIMEDOUT); 1793 } 1794 1795 /* 1796 * Initialize the station address. 1797 */ 1798 cb_ias = &sc->sc_control_data->fcd_iascb; 1799 /* BIG_ENDIAN: no need to swap to store 0 */ 1800 cb_ias->cb_status = 0; 1801 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1802 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1803 cb_ias->link_addr = 0xffffffff; 1804 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1805 1806 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1807 1808 /* 1809 * Start the IAS (Individual Address Setup) command/DMA. 1810 */ 1811 fxp_scb_wait(sc); 1812 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1813 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1814 /* ...and wait for it to complete. */ 1815 i = 1000; 1816 do { 1817 FXP_CDIASSYNC(sc, 1818 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1819 DELAY(1); 1820 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1821 if (i == 0) { 1822 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1823 sc->sc_dev.dv_xname, __LINE__); 1824 return (ETIMEDOUT); 1825 } 1826 1827 /* 1828 * Initialize the transmit descriptor ring. txlast is initialized 1829 * to the end of the list so that it will wrap around to the first 1830 * descriptor when the first packet is transmitted. 1831 */ 1832 for (i = 0; i < FXP_NTXCB; i++) { 1833 txd = FXP_CDTX(sc, i); 1834 memset(txd, 0, sizeof(*txd)); 1835 txd->txd_txcb.cb_command = 1836 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1837 txd->txd_txcb.link_addr = 1838 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1839 if (sc->sc_flags & FXPF_EXT_TXCB) 1840 txd->txd_txcb.tbd_array_addr = 1841 htole32(FXP_CDTBDADDR(sc, i) + 1842 (2 * sizeof(struct fxp_tbd))); 1843 else 1844 txd->txd_txcb.tbd_array_addr = 1845 htole32(FXP_CDTBDADDR(sc, i)); 1846 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1847 } 1848 sc->sc_txpending = 0; 1849 sc->sc_txdirty = 0; 1850 sc->sc_txlast = FXP_NTXCB - 1; 1851 1852 /* 1853 * Initialize the receive buffer list. 1854 */ 1855 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1856 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1857 rxmap = FXP_RXMAP_GET(sc); 1858 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1859 log(LOG_ERR, "%s: unable to allocate or map rx " 1860 "buffer %d, error = %d\n", 1861 sc->sc_dev.dv_xname, 1862 sc->sc_rxq.ifq_len, error); 1863 /* 1864 * XXX Should attempt to run with fewer receive 1865 * XXX buffers instead of just failing. 1866 */ 1867 FXP_RXMAP_PUT(sc, rxmap); 1868 fxp_rxdrain(sc); 1869 goto out; 1870 } 1871 } 1872 sc->sc_rxidle = 0; 1873 1874 /* 1875 * Give the transmit ring to the chip. We do this by pointing 1876 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1877 * issuing a start command. It will execute the NOP and then 1878 * suspend, pointing at the first descriptor. 1879 */ 1880 fxp_scb_wait(sc); 1881 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1882 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1883 1884 /* 1885 * Initialize receiver buffer area - RFA. 1886 */ 1887 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1888 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1889 fxp_scb_wait(sc); 1890 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1891 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1892 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1893 #endif 1894 1895 if (sc->sc_flags & FXPF_MII) { 1896 /* 1897 * Set current media. 1898 */ 1899 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1900 goto out; 1901 } 1902 1903 /* 1904 * ...all done! 1905 */ 1906 ifp->if_flags |= IFF_RUNNING; 1907 ifp->if_flags &= ~IFF_OACTIVE; 1908 1909 /* 1910 * Request a software generated interrupt that will be used to 1911 * (re)start the RU processing. If we direct the chip to start 1912 * receiving from the start of queue now, instead of letting the 1913 * interrupt handler first process all received packets, we run 1914 * the risk of having it overwrite mbuf clusters while they are 1915 * being processed or after they have been returned to the pool. 1916 */ 1917 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1918 1919 /* 1920 * Start the one second timer. 1921 */ 1922 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1923 1924 /* 1925 * Attempt to start output on the interface. 1926 */ 1927 fxp_start(ifp); 1928 1929 out: 1930 if (error) { 1931 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1932 ifp->if_timer = 0; 1933 log(LOG_ERR, "%s: interface not running\n", 1934 sc->sc_dev.dv_xname); 1935 } 1936 return (error); 1937 } 1938 1939 /* 1940 * Notify the world which media we're using. 1941 */ 1942 void 1943 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1944 { 1945 struct fxp_softc *sc = ifp->if_softc; 1946 1947 if (sc->sc_enabled == 0) { 1948 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1949 ifmr->ifm_status = 0; 1950 return; 1951 } 1952 1953 ether_mediastatus(ifp, ifmr); 1954 1955 /* 1956 * XXX Flow control is always turned on if the chip supports 1957 * XXX it; we can't easily control it dynamically, since it 1958 * XXX requires sending a setup packet. 1959 */ 1960 if (sc->sc_rev >= FXP_REV_82558_A4) 1961 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1962 } 1963 1964 int 1965 fxp_80c24_mediachange(struct ifnet *ifp) 1966 { 1967 1968 /* Nothing to do here. */ 1969 return (0); 1970 } 1971 1972 void 1973 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1974 { 1975 struct fxp_softc *sc = ifp->if_softc; 1976 1977 /* 1978 * Media is currently-selected media. We cannot determine 1979 * the link status. 1980 */ 1981 ifmr->ifm_status = 0; 1982 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1983 } 1984 1985 /* 1986 * Add a buffer to the end of the RFA buffer list. 1987 * Return 0 if successful, error code on failure. 1988 * 1989 * The RFA struct is stuck at the beginning of mbuf cluster and the 1990 * data pointer is fixed up to point just past it. 1991 */ 1992 int 1993 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1994 { 1995 struct mbuf *m; 1996 int error; 1997 1998 MGETHDR(m, M_DONTWAIT, MT_DATA); 1999 if (m == NULL) 2000 return (ENOBUFS); 2001 2002 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2003 MCLGET(m, M_DONTWAIT); 2004 if ((m->m_flags & M_EXT) == 0) { 2005 m_freem(m); 2006 return (ENOBUFS); 2007 } 2008 2009 if (unload) 2010 bus_dmamap_unload(sc->sc_dmat, rxmap); 2011 2012 M_SETCTX(m, rxmap); 2013 2014 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2015 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2016 BUS_DMA_READ|BUS_DMA_NOWAIT); 2017 if (error) { 2018 /* XXX XXX XXX */ 2019 printf("%s: can't load rx DMA map %d, error = %d\n", 2020 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 2021 panic("fxp_add_rfabuf"); 2022 } 2023 2024 FXP_INIT_RFABUF(sc, m); 2025 2026 return (0); 2027 } 2028 2029 int 2030 fxp_mdi_read(struct device *self, int phy, int reg) 2031 { 2032 struct fxp_softc *sc = (struct fxp_softc *)self; 2033 int count = 10000; 2034 int value; 2035 2036 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2037 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2038 2039 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2040 0x10000000) == 0 && count--) 2041 DELAY(10); 2042 2043 if (count <= 0) 2044 log(LOG_WARNING, 2045 "%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 2046 2047 return (value & 0xffff); 2048 } 2049 2050 void 2051 fxp_statchg(struct device *self) 2052 { 2053 2054 /* Nothing to do. */ 2055 } 2056 2057 void 2058 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2059 { 2060 struct fxp_softc *sc = (struct fxp_softc *)self; 2061 int count = 10000; 2062 2063 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2064 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2065 (value & 0xffff)); 2066 2067 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2068 count--) 2069 DELAY(10); 2070 2071 if (count <= 0) 2072 log(LOG_WARNING, 2073 "%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2074 } 2075 2076 int 2077 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2078 { 2079 struct fxp_softc *sc = ifp->if_softc; 2080 struct ifreq *ifr = (struct ifreq *)data; 2081 int s, error; 2082 2083 s = splnet(); 2084 2085 switch (cmd) { 2086 case SIOCSIFMEDIA: 2087 case SIOCGIFMEDIA: 2088 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2089 break; 2090 2091 default: 2092 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2093 break; 2094 2095 error = 0; 2096 2097 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2098 ; 2099 else if (ifp->if_flags & IFF_RUNNING) { 2100 /* 2101 * Multicast list has changed; set the 2102 * hardware filter accordingly. 2103 */ 2104 if (sc->sc_txpending) { 2105 sc->sc_flags |= FXPF_WANTINIT; 2106 } else 2107 error = fxp_init(ifp); 2108 } 2109 break; 2110 } 2111 2112 /* Try to get more packets going. */ 2113 if (sc->sc_enabled) 2114 fxp_start(ifp); 2115 2116 splx(s); 2117 return (error); 2118 } 2119 2120 /* 2121 * Program the multicast filter. 2122 * 2123 * This function must be called at splnet(). 2124 */ 2125 void 2126 fxp_mc_setup(struct fxp_softc *sc) 2127 { 2128 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2129 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2130 struct ethercom *ec = &sc->sc_ethercom; 2131 struct ether_multi *enm; 2132 struct ether_multistep step; 2133 int count, nmcasts; 2134 2135 #ifdef DIAGNOSTIC 2136 if (sc->sc_txpending) 2137 panic("fxp_mc_setup: pending transmissions"); 2138 #endif 2139 2140 ifp->if_flags &= ~IFF_ALLMULTI; 2141 2142 /* 2143 * Initialize multicast setup descriptor. 2144 */ 2145 nmcasts = 0; 2146 ETHER_FIRST_MULTI(step, ec, enm); 2147 while (enm != NULL) { 2148 /* 2149 * Check for too many multicast addresses or if we're 2150 * listening to a range. Either way, we simply have 2151 * to accept all multicasts. 2152 */ 2153 if (nmcasts >= MAXMCADDR || 2154 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2155 ETHER_ADDR_LEN) != 0) { 2156 /* 2157 * Callers of this function must do the 2158 * right thing with this. If we're called 2159 * from outside fxp_init(), the caller must 2160 * detect if the state if IFF_ALLMULTI changes. 2161 * If it does, the caller must then call 2162 * fxp_init(), since allmulti is handled by 2163 * the config block. 2164 */ 2165 ifp->if_flags |= IFF_ALLMULTI; 2166 return; 2167 } 2168 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2169 ETHER_ADDR_LEN); 2170 nmcasts++; 2171 ETHER_NEXT_MULTI(step, enm); 2172 } 2173 2174 /* BIG_ENDIAN: no need to swap to store 0 */ 2175 mcsp->cb_status = 0; 2176 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2177 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2178 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2179 2180 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2181 2182 /* 2183 * Wait until the command unit is not active. This should never 2184 * happen since nothing is queued, but make sure anyway. 2185 */ 2186 count = 100; 2187 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2188 FXP_SCB_CUS_ACTIVE && --count) 2189 DELAY(1); 2190 if (count == 0) { 2191 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2192 sc->sc_dev.dv_xname, __LINE__); 2193 return; 2194 } 2195 2196 /* 2197 * Start the multicast setup command/DMA. 2198 */ 2199 fxp_scb_wait(sc); 2200 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2201 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2202 2203 /* ...and wait for it to complete. */ 2204 count = 1000; 2205 do { 2206 FXP_CDMCSSYNC(sc, 2207 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2208 DELAY(1); 2209 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2210 if (count == 0) { 2211 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2212 sc->sc_dev.dv_xname, __LINE__); 2213 return; 2214 } 2215 } 2216 2217 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2218 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2219 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2220 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2221 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2222 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2223 2224 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2225 2226 static const struct ucode { 2227 int32_t revision; 2228 const uint32_t *ucode; 2229 size_t length; 2230 uint16_t int_delay_offset; 2231 uint16_t bundle_max_offset; 2232 } ucode_table[] = { 2233 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2234 D101_CPUSAVER_DWORD, 0 }, 2235 2236 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2237 D101_CPUSAVER_DWORD, 0 }, 2238 2239 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2240 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2241 2242 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2243 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2244 2245 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2246 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2247 2248 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2249 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2250 2251 { 0, NULL, 0, 0, 0 } 2252 }; 2253 2254 void 2255 fxp_load_ucode(struct fxp_softc *sc) 2256 { 2257 const struct ucode *uc; 2258 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2259 int count, i; 2260 2261 if (sc->sc_flags & FXPF_UCODE_LOADED) 2262 return; 2263 2264 /* 2265 * Only load the uCode if the user has requested that 2266 * we do so. 2267 */ 2268 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2269 sc->sc_int_delay = 0; 2270 sc->sc_bundle_max = 0; 2271 return; 2272 } 2273 2274 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2275 if (sc->sc_rev == uc->revision) 2276 break; 2277 } 2278 if (uc->ucode == NULL) 2279 return; 2280 2281 /* BIG ENDIAN: no need to swap to store 0 */ 2282 cbp->cb_status = 0; 2283 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2284 cbp->link_addr = 0xffffffff; /* (no) next command */ 2285 for (i = 0; i < uc->length; i++) 2286 cbp->ucode[i] = htole32(uc->ucode[i]); 2287 2288 if (uc->int_delay_offset) 2289 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2290 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2291 2292 if (uc->bundle_max_offset) 2293 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2294 htole16(fxp_bundle_max); 2295 2296 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2297 2298 /* 2299 * Download the uCode to the chip. 2300 */ 2301 fxp_scb_wait(sc); 2302 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2303 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2304 2305 /* ...and wait for it to complete. */ 2306 count = 10000; 2307 do { 2308 FXP_CDUCODESYNC(sc, 2309 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2310 DELAY(2); 2311 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2312 if (count == 0) { 2313 sc->sc_int_delay = 0; 2314 sc->sc_bundle_max = 0; 2315 log(LOG_WARNING, "%s: timeout loading microcode\n", 2316 sc->sc_dev.dv_xname); 2317 return; 2318 } 2319 2320 if (sc->sc_int_delay != fxp_int_delay || 2321 sc->sc_bundle_max != fxp_bundle_max) { 2322 sc->sc_int_delay = fxp_int_delay; 2323 sc->sc_bundle_max = fxp_bundle_max; 2324 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2325 "max bundle: %d\n", sc->sc_dev.dv_xname, 2326 sc->sc_int_delay, 2327 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2328 } 2329 2330 sc->sc_flags |= FXPF_UCODE_LOADED; 2331 } 2332 2333 int 2334 fxp_enable(struct fxp_softc *sc) 2335 { 2336 2337 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2338 if ((*sc->sc_enable)(sc) != 0) { 2339 log(LOG_ERR, "%s: device enable failed\n", 2340 sc->sc_dev.dv_xname); 2341 return (EIO); 2342 } 2343 } 2344 2345 sc->sc_enabled = 1; 2346 return (0); 2347 } 2348 2349 void 2350 fxp_disable(struct fxp_softc *sc) 2351 { 2352 2353 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2354 (*sc->sc_disable)(sc); 2355 sc->sc_enabled = 0; 2356 } 2357 } 2358 2359 /* 2360 * fxp_activate: 2361 * 2362 * Handle device activation/deactivation requests. 2363 */ 2364 int 2365 fxp_activate(struct device *self, enum devact act) 2366 { 2367 struct fxp_softc *sc = (void *) self; 2368 int s, error = 0; 2369 2370 s = splnet(); 2371 switch (act) { 2372 case DVACT_ACTIVATE: 2373 error = EOPNOTSUPP; 2374 break; 2375 2376 case DVACT_DEACTIVATE: 2377 if (sc->sc_flags & FXPF_MII) 2378 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2379 MII_OFFSET_ANY); 2380 if_deactivate(&sc->sc_ethercom.ec_if); 2381 break; 2382 } 2383 splx(s); 2384 2385 return (error); 2386 } 2387 2388 /* 2389 * fxp_detach: 2390 * 2391 * Detach an i82557 interface. 2392 */ 2393 int 2394 fxp_detach(struct fxp_softc *sc) 2395 { 2396 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2397 int i; 2398 2399 /* Succeed now if there's no work to do. */ 2400 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2401 return (0); 2402 2403 /* Unhook our tick handler. */ 2404 callout_stop(&sc->sc_callout); 2405 2406 if (sc->sc_flags & FXPF_MII) { 2407 /* Detach all PHYs */ 2408 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2409 } 2410 2411 /* Delete all remaining media. */ 2412 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2413 2414 #if NRND > 0 2415 rnd_detach_source(&sc->rnd_source); 2416 #endif 2417 ether_ifdetach(ifp); 2418 if_detach(ifp); 2419 2420 for (i = 0; i < FXP_NRFABUFS; i++) { 2421 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2422 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2423 } 2424 2425 for (i = 0; i < FXP_NTXCB; i++) { 2426 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2427 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2428 } 2429 2430 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2431 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2432 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2433 sizeof(struct fxp_control_data)); 2434 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2435 2436 return (0); 2437 } 2438
Indexes created Mon Sep 29 03:10:08 GMT 2025