i82557.c revision 1.111.6.3
1 /* $NetBSD: i82557.c,v 1.111.6.3 2009/01/17 13:28:55 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.111.6.3 2009/01/17 13:28:55 mjf Exp $"); 70 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/syslog.h> 85 86 #include <machine/endian.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #if NRND > 0 91 #include <sys/rnd.h> 92 #endif 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 106 #include <dev/mii/miivar.h> 107 108 #include <dev/ic/i82557reg.h> 109 #include <dev/ic/i82557var.h> 110 111 #include <dev/microcode/i8255x/rcvbundl.h> 112 113 /* 114 * NOTE! On the Alpha, we have an alignment constraint. The 115 * card DMAs the packet immediately following the RFA. However, 116 * the first thing in the packet is a 14-byte Ethernet header. 117 * This means that the packet is misaligned. To compensate, 118 * we actually offset the RFA 2 bytes into the cluster. This 119 * alignes the packet after the Ethernet header at a 32-bit 120 * boundary. HOWEVER! This means that the RFA is misaligned! 121 */ 122 #define RFA_ALIGNMENT_FUDGE 2 123 124 /* 125 * The configuration byte map has several undefined fields which 126 * must be one or must be zero. Set up a template for these bits 127 * only (assuming an i82557 chip), leaving the actual configuration 128 * for fxp_init(). 129 * 130 * See the definition of struct fxp_cb_config for the bit definitions. 131 */ 132 const u_int8_t fxp_cb_config_template[] = { 133 0x0, 0x0, /* cb_status */ 134 0x0, 0x0, /* cb_command */ 135 0x0, 0x0, 0x0, 0x0, /* link_addr */ 136 0x0, /* 0 */ 137 0x0, /* 1 */ 138 0x0, /* 2 */ 139 0x0, /* 3 */ 140 0x0, /* 4 */ 141 0x0, /* 5 */ 142 0x32, /* 6 */ 143 0x0, /* 7 */ 144 0x0, /* 8 */ 145 0x0, /* 9 */ 146 0x6, /* 10 */ 147 0x0, /* 11 */ 148 0x0, /* 12 */ 149 0x0, /* 13 */ 150 0xf2, /* 14 */ 151 0x48, /* 15 */ 152 0x0, /* 16 */ 153 0x40, /* 17 */ 154 0xf0, /* 18 */ 155 0x0, /* 19 */ 156 0x3f, /* 20 */ 157 0x5, /* 21 */ 158 0x0, /* 22 */ 159 0x0, /* 23 */ 160 0x0, /* 24 */ 161 0x0, /* 25 */ 162 0x0, /* 26 */ 163 0x0, /* 27 */ 164 0x0, /* 28 */ 165 0x0, /* 29 */ 166 0x0, /* 30 */ 167 0x0, /* 31 */ 168 }; 169 170 void fxp_mii_initmedia(struct fxp_softc *); 171 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 172 173 void fxp_80c24_initmedia(struct fxp_softc *); 174 int fxp_80c24_mediachange(struct ifnet *); 175 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 176 177 void fxp_start(struct ifnet *); 178 int fxp_ioctl(struct ifnet *, u_long, void *); 179 void fxp_watchdog(struct ifnet *); 180 int fxp_init(struct ifnet *); 181 void fxp_stop(struct ifnet *, int); 182 183 void fxp_txintr(struct fxp_softc *); 184 int fxp_rxintr(struct fxp_softc *); 185 186 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 187 188 void fxp_rxdrain(struct fxp_softc *); 189 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 190 int fxp_mdi_read(device_t, int, int); 191 void fxp_statchg(device_t); 192 void fxp_mdi_write(device_t, int, int, int); 193 void fxp_autosize_eeprom(struct fxp_softc*); 194 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 195 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 196 void fxp_eeprom_update_cksum(struct fxp_softc *); 197 void fxp_get_info(struct fxp_softc *, u_int8_t *); 198 void fxp_tick(void *); 199 void fxp_mc_setup(struct fxp_softc *); 200 void fxp_load_ucode(struct fxp_softc *); 201 202 int fxp_copy_small = 0; 203 204 /* 205 * Variables for interrupt mitigating microcode. 206 */ 207 int fxp_int_delay = 1000; /* usec */ 208 int fxp_bundle_max = 6; /* packets */ 209 210 struct fxp_phytype { 211 int fp_phy; /* type of PHY, -1 for MII at the end. */ 212 void (*fp_init)(struct fxp_softc *); 213 } fxp_phytype_table[] = { 214 { FXP_PHY_80C24, fxp_80c24_initmedia }, 215 { -1, fxp_mii_initmedia }, 216 }; 217 218 /* 219 * Set initial transmit threshold at 64 (512 bytes). This is 220 * increased by 64 (512 bytes) at a time, to maximum of 192 221 * (1536 bytes), if an underrun occurs. 222 */ 223 static int tx_threshold = 64; 224 225 /* 226 * Wait for the previous command to be accepted (but not necessarily 227 * completed). 228 */ 229 static inline void 230 fxp_scb_wait(struct fxp_softc *sc) 231 { 232 int i = 10000; 233 234 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 235 delay(2); 236 if (i == 0) 237 log(LOG_WARNING, 238 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 239 } 240 241 /* 242 * Submit a command to the i82557. 243 */ 244 static inline void 245 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 246 { 247 248 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 249 } 250 251 /* 252 * Finish attaching an i82557 interface. Called by bus-specific front-end. 253 */ 254 void 255 fxp_attach(struct fxp_softc *sc) 256 { 257 u_int8_t enaddr[ETHER_ADDR_LEN]; 258 struct ifnet *ifp; 259 bus_dma_segment_t seg; 260 int rseg, i, error; 261 struct fxp_phytype *fp; 262 263 callout_init(&sc->sc_callout, 0); 264 265 /* 266 * Enable some good stuff on i82558 and later. 267 */ 268 if (sc->sc_rev >= FXP_REV_82558_A4) { 269 /* Enable the extended TxCB. */ 270 sc->sc_flags |= FXPF_EXT_TXCB; 271 } 272 273 /* 274 * Enable use of extended RFDs and TCBs for 82550 275 * and later chips. Note: we need extended TXCB support 276 * too, but that's already enabled by the code above. 277 * Be careful to do this only on the right devices. 278 */ 279 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 280 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 281 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 282 } else { 283 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 284 } 285 286 sc->sc_rfa_size = 287 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 288 289 /* 290 * Allocate the control data structures, and create and load the 291 * DMA map for it. 292 */ 293 if ((error = bus_dmamem_alloc(sc->sc_dmat, 294 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 295 0)) != 0) { 296 aprint_error_dev(sc->sc_dev, 297 "unable to allocate control data, error = %d\n", 298 error); 299 goto fail_0; 300 } 301 302 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 303 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 304 BUS_DMA_COHERENT)) != 0) { 305 aprint_error_dev(sc->sc_dev, 306 "unable to map control data, error = %d\n", error); 307 goto fail_1; 308 } 309 sc->sc_cdseg = seg; 310 sc->sc_cdnseg = rseg; 311 312 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 313 314 if ((error = bus_dmamap_create(sc->sc_dmat, 315 sizeof(struct fxp_control_data), 1, 316 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 317 aprint_error_dev(sc->sc_dev, 318 "unable to create control data DMA map, error = %d\n", 319 error); 320 goto fail_2; 321 } 322 323 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 324 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 325 0)) != 0) { 326 aprint_error_dev(sc->sc_dev, 327 "can't load control data DMA map, error = %d\n", 328 error); 329 goto fail_3; 330 } 331 332 /* 333 * Create the transmit buffer DMA maps. 334 */ 335 for (i = 0; i < FXP_NTXCB; i++) { 336 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 337 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 338 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 339 aprint_error_dev(sc->sc_dev, 340 "unable to create tx DMA map %d, error = %d\n", 341 i, error); 342 goto fail_4; 343 } 344 } 345 346 /* 347 * Create the receive buffer DMA maps. 348 */ 349 for (i = 0; i < FXP_NRFABUFS; i++) { 350 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 351 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 352 aprint_error_dev(sc->sc_dev, 353 "unable to create rx DMA map %d, error = %d\n", 354 i, error); 355 goto fail_5; 356 } 357 } 358 359 /* Initialize MAC address and media structures. */ 360 fxp_get_info(sc, enaddr); 361 362 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 363 ether_sprintf(enaddr)); 364 365 ifp = &sc->sc_ethercom.ec_if; 366 367 /* 368 * Get info about our media interface, and initialize it. Note 369 * the table terminates itself with a phy of -1, indicating 370 * that we're using MII. 371 */ 372 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 373 if (fp->fp_phy == sc->phy_primary_device) 374 break; 375 (*fp->fp_init)(sc); 376 377 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 378 ifp->if_softc = sc; 379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 380 ifp->if_ioctl = fxp_ioctl; 381 ifp->if_start = fxp_start; 382 ifp->if_watchdog = fxp_watchdog; 383 ifp->if_init = fxp_init; 384 ifp->if_stop = fxp_stop; 385 IFQ_SET_READY(&ifp->if_snd); 386 387 if (sc->sc_flags & FXPF_IPCB) { 388 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 389 /* 390 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 391 * at least, on i82550 rev.12. 392 * specifically, it doesn't set ipv4 checksum properly 393 * when sending UDP (and probably TCP) packets with 394 * 20 byte ipv4 header + 1 or 2 byte data, 395 * though ICMP packets seem working. 396 * FreeBSD driver has related comments. 397 * We've added a workaround to handle the bug by padding 398 * such packets manually. 399 */ 400 ifp->if_capabilities = 401 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 402 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 403 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 404 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 405 } 406 407 /* 408 * We can support 802.1Q VLAN-sized frames. 409 */ 410 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 411 412 /* 413 * Attach the interface. 414 */ 415 if_attach(ifp); 416 ether_ifattach(ifp, enaddr); 417 #if NRND > 0 418 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 419 RND_TYPE_NET, 0); 420 #endif 421 422 #ifdef FXP_EVENT_COUNTERS 423 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 424 NULL, device_xname(sc->sc_dev), "txstall"); 425 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 426 NULL, device_xname(sc->sc_dev), "txintr"); 427 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 428 NULL, device_xname(sc->sc_dev), "rxintr"); 429 if (sc->sc_rev >= FXP_REV_82558_A4) { 430 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 431 NULL, device_xname(sc->sc_dev), "txpause"); 432 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 433 NULL, device_xname(sc->sc_dev), "rxpause"); 434 } 435 #endif /* FXP_EVENT_COUNTERS */ 436 437 /* The attach is successful. */ 438 sc->sc_flags |= FXPF_ATTACHED; 439 440 return; 441 442 /* 443 * Free any resources we've allocated during the failed attach 444 * attempt. Do this in reverse order and fall though. 445 */ 446 fail_5: 447 for (i = 0; i < FXP_NRFABUFS; i++) { 448 if (sc->sc_rxmaps[i] != NULL) 449 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 450 } 451 fail_4: 452 for (i = 0; i < FXP_NTXCB; i++) { 453 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 454 bus_dmamap_destroy(sc->sc_dmat, 455 FXP_DSTX(sc, i)->txs_dmamap); 456 } 457 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 458 fail_3: 459 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 460 fail_2: 461 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 462 sizeof(struct fxp_control_data)); 463 fail_1: 464 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 465 fail_0: 466 return; 467 } 468 469 void 470 fxp_mii_initmedia(struct fxp_softc *sc) 471 { 472 int flags; 473 474 sc->sc_flags |= FXPF_MII; 475 476 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 477 sc->sc_mii.mii_readreg = fxp_mdi_read; 478 sc->sc_mii.mii_writereg = fxp_mdi_write; 479 sc->sc_mii.mii_statchg = fxp_statchg; 480 481 sc->sc_ethercom.ec_mii = &sc->sc_mii; 482 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 483 fxp_mii_mediastatus); 484 485 flags = MIIF_NOISOLATE; 486 if (sc->sc_rev >= FXP_REV_82558_A4) 487 flags |= MIIF_DOPAUSE; 488 /* 489 * The i82557 wedges if all of its PHYs are isolated! 490 */ 491 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 492 MII_OFFSET_ANY, flags); 493 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 495 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 496 } else 497 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 498 } 499 500 void 501 fxp_80c24_initmedia(struct fxp_softc *sc) 502 { 503 504 /* 505 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 506 * doesn't have a programming interface of any sort. The 507 * media is sensed automatically based on how the link partner 508 * is configured. This is, in essence, manual configuration. 509 */ 510 aprint_normal_dev(sc->sc_dev, 511 "Seeq 80c24 AutoDUPLEX media interface present\n"); 512 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 513 fxp_80c24_mediastatus); 514 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 515 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 516 } 517 518 /* 519 * Initialize the interface media. 520 */ 521 void 522 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 523 { 524 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 525 526 /* 527 * Reset to a stable state. 528 */ 529 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 530 DELAY(100); 531 532 sc->sc_eeprom_size = 0; 533 fxp_autosize_eeprom(sc); 534 if (sc->sc_eeprom_size == 0) { 535 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 536 sc->sc_eeprom_size = 6; /* XXX panic here? */ 537 } 538 #ifdef DEBUG 539 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 540 1 << sc->sc_eeprom_size); 541 #endif 542 543 /* 544 * Get info about the primary PHY 545 */ 546 fxp_read_eeprom(sc, &data, 6, 1); 547 sc->phy_primary_device = 548 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 549 550 /* 551 * Read MAC address. 552 */ 553 fxp_read_eeprom(sc, myea, 0, 3); 554 enaddr[0] = myea[0] & 0xff; 555 enaddr[1] = myea[0] >> 8; 556 enaddr[2] = myea[1] & 0xff; 557 enaddr[3] = myea[1] >> 8; 558 enaddr[4] = myea[2] & 0xff; 559 enaddr[5] = myea[2] >> 8; 560 561 /* 562 * Systems based on the ICH2/ICH2-M chip from Intel, as well 563 * as some i82559 designs, have a defect where the chip can 564 * cause a PCI protocol violation if it receives a CU_RESUME 565 * command when it is entering the IDLE state. 566 * 567 * The work-around is to disable Dynamic Standby Mode, so that 568 * the chip never deasserts #CLKRUN, and always remains in the 569 * active state. 570 * 571 * Unfortunately, the only way to disable Dynamic Standby is 572 * to frob an EEPROM setting and reboot (the EEPROM setting 573 * is only consulted when the PCI bus comes out of reset). 574 * 575 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 576 */ 577 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 578 fxp_read_eeprom(sc, &data, 10, 1); 579 if (data & 0x02) { /* STB enable */ 580 aprint_error_dev(sc->sc_dev, "WARNING: " 581 "Disabling dynamic standby mode in EEPROM " 582 "to work around a\n"); 583 aprint_normal_dev(sc->sc_dev, 584 "WARNING: hardware bug. You must reset " 585 "the system before using this\n"); 586 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 587 data &= ~0x02; 588 fxp_write_eeprom(sc, &data, 10, 1); 589 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 590 data); 591 fxp_eeprom_update_cksum(sc); 592 } 593 } 594 595 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 596 /* Due to false positives we make it conditional on setting link1 */ 597 fxp_read_eeprom(sc, &data, 3, 1); 598 if ((data & 0x03) != 0x03) { 599 aprint_verbose_dev(sc->sc_dev, 600 "May need receiver lock-up workaround\n"); 601 } 602 } 603 604 static void 605 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 606 { 607 uint16_t reg; 608 int x; 609 610 for (x = 1 << (len - 1); x != 0; x >>= 1) { 611 DELAY(40); 612 if (data & x) 613 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 614 else 615 reg = FXP_EEPROM_EECS; 616 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 617 DELAY(40); 618 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 619 reg | FXP_EEPROM_EESK); 620 DELAY(40); 621 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 622 } 623 DELAY(40); 624 } 625 626 /* 627 * Figure out EEPROM size. 628 * 629 * 559's can have either 64-word or 256-word EEPROMs, the 558 630 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 631 * talks about the existence of 16 to 256 word EEPROMs. 632 * 633 * The only known sizes are 64 and 256, where the 256 version is used 634 * by CardBus cards to store CIS information. 635 * 636 * The address is shifted in msb-to-lsb, and after the last 637 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 638 * after which follows the actual data. We try to detect this zero, by 639 * probing the data-out bit in the EEPROM control register just after 640 * having shifted in a bit. If the bit is zero, we assume we've 641 * shifted enough address bits. The data-out should be tri-state, 642 * before this, which should translate to a logical one. 643 * 644 * Other ways to do this would be to try to read a register with known 645 * contents with a varying number of address bits, but no such 646 * register seem to be available. The high bits of register 10 are 01 647 * on the 558 and 559, but apparently not on the 557. 648 * 649 * The Linux driver computes a checksum on the EEPROM data, but the 650 * value of this checksum is not very well documented. 651 */ 652 653 void 654 fxp_autosize_eeprom(struct fxp_softc *sc) 655 { 656 int x; 657 658 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 659 DELAY(40); 660 661 /* Shift in read opcode. */ 662 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 663 664 /* 665 * Shift in address, wait for the dummy zero following a correct 666 * address shift. 667 */ 668 for (x = 1; x <= 8; x++) { 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 670 DELAY(40); 671 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 672 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 673 DELAY(40); 674 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 675 FXP_EEPROM_EEDO) == 0) 676 break; 677 DELAY(40); 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 679 DELAY(40); 680 } 681 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 682 DELAY(40); 683 if (x != 6 && x != 8) { 684 #ifdef DEBUG 685 printf("%s: strange EEPROM size (%d)\n", 686 device_xname(sc->sc_dev), 1 << x); 687 #endif 688 } else 689 sc->sc_eeprom_size = x; 690 } 691 692 /* 693 * Read from the serial EEPROM. Basically, you manually shift in 694 * the read opcode (one bit at a time) and then shift in the address, 695 * and then you shift out the data (all of this one bit at a time). 696 * The word size is 16 bits, so you have to provide the address for 697 * every 16 bits of data. 698 */ 699 void 700 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 701 { 702 u_int16_t reg; 703 int i, x; 704 705 for (i = 0; i < words; i++) { 706 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 707 708 /* Shift in read opcode. */ 709 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 710 711 /* Shift in address. */ 712 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 713 714 reg = FXP_EEPROM_EECS; 715 data[i] = 0; 716 717 /* Shift out data. */ 718 for (x = 16; x > 0; x--) { 719 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 720 reg | FXP_EEPROM_EESK); 721 DELAY(40); 722 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 723 FXP_EEPROM_EEDO) 724 data[i] |= (1 << (x - 1)); 725 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 726 DELAY(40); 727 } 728 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 729 DELAY(40); 730 } 731 } 732 733 /* 734 * Write data to the serial EEPROM. 735 */ 736 void 737 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 738 { 739 int i, j; 740 741 for (i = 0; i < words; i++) { 742 /* Erase/write enable. */ 743 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 744 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 745 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 746 sc->sc_eeprom_size); 747 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 748 DELAY(4); 749 750 /* Shift in write opcode, address, data. */ 751 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 752 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 753 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 754 fxp_eeprom_shiftin(sc, data[i], 16); 755 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 756 DELAY(4); 757 758 /* Wait for the EEPROM to finish up. */ 759 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 760 DELAY(4); 761 for (j = 0; j < 1000; j++) { 762 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 763 FXP_EEPROM_EEDO) 764 break; 765 DELAY(50); 766 } 767 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 768 DELAY(4); 769 770 /* Erase/write disable. */ 771 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 772 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 773 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 774 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 775 DELAY(4); 776 } 777 } 778 779 /* 780 * Update the checksum of the EEPROM. 781 */ 782 void 783 fxp_eeprom_update_cksum(struct fxp_softc *sc) 784 { 785 int i; 786 uint16_t data, cksum; 787 788 cksum = 0; 789 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 790 fxp_read_eeprom(sc, &data, i, 1); 791 cksum += data; 792 } 793 i = (1 << sc->sc_eeprom_size) - 1; 794 cksum = 0xbaba - cksum; 795 fxp_read_eeprom(sc, &data, i, 1); 796 fxp_write_eeprom(sc, &cksum, i, 1); 797 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 798 device_xname(sc->sc_dev), i, data, cksum); 799 } 800 801 /* 802 * Start packet transmission on the interface. 803 */ 804 void 805 fxp_start(struct ifnet *ifp) 806 { 807 struct fxp_softc *sc = ifp->if_softc; 808 struct mbuf *m0, *m; 809 struct fxp_txdesc *txd; 810 struct fxp_txsoft *txs; 811 bus_dmamap_t dmamap; 812 int error, lasttx, nexttx, opending, seg, nsegs, len; 813 814 /* 815 * If we want a re-init, bail out now. 816 */ 817 if (sc->sc_flags & FXPF_WANTINIT) { 818 ifp->if_flags |= IFF_OACTIVE; 819 return; 820 } 821 822 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 823 return; 824 825 /* 826 * Remember the previous txpending and the current lasttx. 827 */ 828 opending = sc->sc_txpending; 829 lasttx = sc->sc_txlast; 830 831 /* 832 * Loop through the send queue, setting up transmit descriptors 833 * until we drain the queue, or use up all available transmit 834 * descriptors. 835 */ 836 for (;;) { 837 struct fxp_tbd *tbdp; 838 int csum_flags; 839 840 /* 841 * Grab a packet off the queue. 842 */ 843 IFQ_POLL(&ifp->if_snd, m0); 844 if (m0 == NULL) 845 break; 846 m = NULL; 847 848 if (sc->sc_txpending == FXP_NTXCB - 1) { 849 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 850 break; 851 } 852 853 /* 854 * Get the next available transmit descriptor. 855 */ 856 nexttx = FXP_NEXTTX(sc->sc_txlast); 857 txd = FXP_CDTX(sc, nexttx); 858 txs = FXP_DSTX(sc, nexttx); 859 dmamap = txs->txs_dmamap; 860 861 /* 862 * Load the DMA map. If this fails, the packet either 863 * didn't fit in the allotted number of frags, or we were 864 * short on resources. In this case, we'll copy and try 865 * again. 866 */ 867 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 868 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 869 MGETHDR(m, M_DONTWAIT, MT_DATA); 870 if (m == NULL) { 871 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 872 device_xname(sc->sc_dev)); 873 break; 874 } 875 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 876 if (m0->m_pkthdr.len > MHLEN) { 877 MCLGET(m, M_DONTWAIT); 878 if ((m->m_flags & M_EXT) == 0) { 879 log(LOG_ERR, "%s: unable to allocate " 880 "Tx cluster\n", 881 device_xname(sc->sc_dev)); 882 m_freem(m); 883 break; 884 } 885 } 886 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 887 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 888 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 889 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 890 if (error) { 891 log(LOG_ERR, "%s: unable to load Tx buffer, " 892 "error = %d\n", 893 device_xname(sc->sc_dev), error); 894 break; 895 } 896 } 897 898 IFQ_DEQUEUE(&ifp->if_snd, m0); 899 csum_flags = m0->m_pkthdr.csum_flags; 900 if (m != NULL) { 901 m_freem(m0); 902 m0 = m; 903 } 904 905 /* Initialize the fraglist. */ 906 tbdp = txd->txd_tbd; 907 len = m0->m_pkthdr.len; 908 nsegs = dmamap->dm_nsegs; 909 if (sc->sc_flags & FXPF_IPCB) 910 tbdp++; 911 for (seg = 0; seg < nsegs; seg++) { 912 tbdp[seg].tb_addr = 913 htole32(dmamap->dm_segs[seg].ds_addr); 914 tbdp[seg].tb_size = 915 htole32(dmamap->dm_segs[seg].ds_len); 916 } 917 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 918 (csum_flags & M_CSUM_IPv4) != 0)) { 919 /* 920 * Pad short packets to avoid ip4csum-tx bug. 921 * 922 * XXX Should we still consider if such short 923 * (36 bytes or less) packets might already 924 * occupy FXP_IPCB_NTXSEG (15) fragments here? 925 */ 926 KASSERT(nsegs < FXP_IPCB_NTXSEG); 927 nsegs++; 928 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 929 tbdp[seg].tb_size = 930 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 931 } 932 933 /* Sync the DMA map. */ 934 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 935 BUS_DMASYNC_PREWRITE); 936 937 /* 938 * Store a pointer to the packet so we can free it later. 939 */ 940 txs->txs_mbuf = m0; 941 942 /* 943 * Initialize the transmit descriptor. 944 */ 945 /* BIG_ENDIAN: no need to swap to store 0 */ 946 txd->txd_txcb.cb_status = 0; 947 txd->txd_txcb.cb_command = 948 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 949 txd->txd_txcb.tx_threshold = tx_threshold; 950 txd->txd_txcb.tbd_number = nsegs; 951 952 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 953 if (sc->sc_flags & FXPF_IPCB) { 954 struct m_tag *vtag; 955 struct fxp_ipcb *ipcb; 956 /* 957 * Deal with TCP/IP checksum offload. Note that 958 * in order for TCP checksum offload to work, 959 * the pseudo header checksum must have already 960 * been computed and stored in the checksum field 961 * in the TCP header. The stack should have 962 * already done this for us. 963 */ 964 ipcb = &txd->txd_u.txdu_ipcb; 965 memset(ipcb, 0, sizeof(*ipcb)); 966 /* 967 * always do hardware parsing. 968 */ 969 ipcb->ipcb_ip_activation_high = 970 FXP_IPCB_HARDWAREPARSING_ENABLE; 971 /* 972 * ip checksum offloading. 973 */ 974 if (csum_flags & M_CSUM_IPv4) { 975 ipcb->ipcb_ip_schedule |= 976 FXP_IPCB_IP_CHECKSUM_ENABLE; 977 } 978 /* 979 * TCP/UDP checksum offloading. 980 */ 981 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 982 ipcb->ipcb_ip_schedule |= 983 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 984 } 985 986 /* 987 * request VLAN tag insertion if needed. 988 */ 989 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 990 if (vtag) { 991 ipcb->ipcb_vlan_id = 992 htobe16(*(u_int *)(vtag + 1)); 993 ipcb->ipcb_ip_activation_high |= 994 FXP_IPCB_INSERTVLAN_ENABLE; 995 } 996 } else { 997 KASSERT((csum_flags & 998 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 999 } 1000 1001 FXP_CDTXSYNC(sc, nexttx, 1002 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1003 1004 /* Advance the tx pointer. */ 1005 sc->sc_txpending++; 1006 sc->sc_txlast = nexttx; 1007 1008 #if NBPFILTER > 0 1009 /* 1010 * Pass packet to bpf if there is a listener. 1011 */ 1012 if (ifp->if_bpf) 1013 bpf_mtap(ifp->if_bpf, m0); 1014 #endif 1015 } 1016 1017 if (sc->sc_txpending == FXP_NTXCB - 1) { 1018 /* No more slots; notify upper layer. */ 1019 ifp->if_flags |= IFF_OACTIVE; 1020 } 1021 1022 if (sc->sc_txpending != opending) { 1023 /* 1024 * We enqueued packets. If the transmitter was idle, 1025 * reset the txdirty pointer. 1026 */ 1027 if (opending == 0) 1028 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1029 1030 /* 1031 * Cause the chip to interrupt and suspend command 1032 * processing once the last packet we've enqueued 1033 * has been transmitted. 1034 * 1035 * To avoid a race between updating status bits 1036 * by the fxp chip and clearing command bits 1037 * by this function on machines which don't have 1038 * atomic methods to clear/set bits in memory 1039 * smaller than 32bits (both cb_status and cb_command 1040 * members are uint16_t and in the same 32bit word), 1041 * we have to prepare a dummy TX descriptor which has 1042 * NOP command and just causes a TX completion interrupt. 1043 */ 1044 sc->sc_txpending++; 1045 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1046 txd = FXP_CDTX(sc, sc->sc_txlast); 1047 /* BIG_ENDIAN: no need to swap to store 0 */ 1048 txd->txd_txcb.cb_status = 0; 1049 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1050 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1051 FXP_CDTXSYNC(sc, sc->sc_txlast, 1052 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1053 1054 /* 1055 * The entire packet chain is set up. Clear the suspend bit 1056 * on the command prior to the first packet we set up. 1057 */ 1058 FXP_CDTXSYNC(sc, lasttx, 1059 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1060 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1061 htole16(~FXP_CB_COMMAND_S); 1062 FXP_CDTXSYNC(sc, lasttx, 1063 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1064 1065 /* 1066 * Issue a Resume command in case the chip was suspended. 1067 */ 1068 fxp_scb_wait(sc); 1069 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1070 1071 /* Set a watchdog timer in case the chip flakes out. */ 1072 ifp->if_timer = 5; 1073 } 1074 } 1075 1076 /* 1077 * Process interface interrupts. 1078 */ 1079 int 1080 fxp_intr(void *arg) 1081 { 1082 struct fxp_softc *sc = arg; 1083 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1084 bus_dmamap_t rxmap; 1085 int claimed = 0, rnr; 1086 u_int8_t statack; 1087 1088 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1089 return (0); 1090 /* 1091 * If the interface isn't running, don't try to 1092 * service the interrupt.. just ack it and bail. 1093 */ 1094 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1095 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1096 if (statack) { 1097 claimed = 1; 1098 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1099 } 1100 return (claimed); 1101 } 1102 1103 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1104 claimed = 1; 1105 1106 /* 1107 * First ACK all the interrupts in this pass. 1108 */ 1109 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1110 1111 /* 1112 * Process receiver interrupts. If a no-resource (RNR) 1113 * condition exists, get whatever packets we can and 1114 * re-start the receiver. 1115 */ 1116 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1117 1 : 0; 1118 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1119 FXP_SCB_STATACK_SWI)) { 1120 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1121 rnr |= fxp_rxintr(sc); 1122 } 1123 1124 /* 1125 * Free any finished transmit mbuf chains. 1126 */ 1127 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1128 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1129 fxp_txintr(sc); 1130 1131 /* 1132 * Try to get more packets going. 1133 */ 1134 fxp_start(ifp); 1135 1136 if (sc->sc_txpending == 0) { 1137 /* 1138 * Tell them that they can re-init now. 1139 */ 1140 if (sc->sc_flags & FXPF_WANTINIT) 1141 wakeup(sc); 1142 } 1143 } 1144 1145 if (rnr) { 1146 fxp_scb_wait(sc); 1147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1148 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1149 fxp_scb_wait(sc); 1150 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1151 rxmap->dm_segs[0].ds_addr + 1152 RFA_ALIGNMENT_FUDGE); 1153 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1154 } 1155 } 1156 1157 #if NRND > 0 1158 if (claimed) 1159 rnd_add_uint32(&sc->rnd_source, statack); 1160 #endif 1161 return (claimed); 1162 } 1163 1164 /* 1165 * Handle transmit completion interrupts. 1166 */ 1167 void 1168 fxp_txintr(struct fxp_softc *sc) 1169 { 1170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1171 struct fxp_txdesc *txd; 1172 struct fxp_txsoft *txs; 1173 int i; 1174 u_int16_t txstat; 1175 1176 ifp->if_flags &= ~IFF_OACTIVE; 1177 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1178 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1179 txd = FXP_CDTX(sc, i); 1180 txs = FXP_DSTX(sc, i); 1181 1182 FXP_CDTXSYNC(sc, i, 1183 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1184 1185 /* skip dummy NOP TX descriptor */ 1186 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1187 == FXP_CB_COMMAND_NOP) 1188 continue; 1189 1190 txstat = le16toh(txd->txd_txcb.cb_status); 1191 1192 if ((txstat & FXP_CB_STATUS_C) == 0) 1193 break; 1194 1195 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1196 0, txs->txs_dmamap->dm_mapsize, 1197 BUS_DMASYNC_POSTWRITE); 1198 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1199 m_freem(txs->txs_mbuf); 1200 txs->txs_mbuf = NULL; 1201 } 1202 1203 /* Update the dirty transmit buffer pointer. */ 1204 sc->sc_txdirty = i; 1205 1206 /* 1207 * Cancel the watchdog timer if there are no pending 1208 * transmissions. 1209 */ 1210 if (sc->sc_txpending == 0) 1211 ifp->if_timer = 0; 1212 } 1213 1214 /* 1215 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1216 */ 1217 1218 int 1219 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1220 { 1221 u_int8_t rxparsestat; 1222 u_int8_t csum_stat; 1223 u_int32_t csum_data; 1224 int csum_flags; 1225 1226 /* 1227 * check VLAN tag stripping. 1228 */ 1229 1230 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1231 struct m_tag *vtag; 1232 1233 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1234 if (vtag == NULL) 1235 return ENOMEM; 1236 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1237 m_tag_prepend(m, vtag); 1238 } 1239 1240 /* 1241 * check H/W Checksumming. 1242 */ 1243 1244 csum_stat = rfa->cksum_stat; 1245 rxparsestat = rfa->rx_parse_stat; 1246 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1247 return 0; 1248 1249 csum_flags = 0; 1250 csum_data = 0; 1251 1252 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1253 csum_flags = M_CSUM_IPv4; 1254 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1255 csum_flags |= M_CSUM_IPv4_BAD; 1256 } 1257 1258 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1259 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1260 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1261 csum_flags |= M_CSUM_TCP_UDP_BAD; 1262 } 1263 1264 m->m_pkthdr.csum_flags = csum_flags; 1265 m->m_pkthdr.csum_data = csum_data; 1266 1267 return 0; 1268 } 1269 1270 /* 1271 * Handle receive interrupts. 1272 */ 1273 int 1274 fxp_rxintr(struct fxp_softc *sc) 1275 { 1276 struct ethercom *ec = &sc->sc_ethercom; 1277 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1278 struct mbuf *m, *m0; 1279 bus_dmamap_t rxmap; 1280 struct fxp_rfa *rfa; 1281 int rnr; 1282 u_int16_t len, rxstat; 1283 1284 rnr = 0; 1285 1286 for (;;) { 1287 m = sc->sc_rxq.ifq_head; 1288 rfa = FXP_MTORFA(m); 1289 rxmap = M_GETCTX(m, bus_dmamap_t); 1290 1291 FXP_RFASYNC(sc, m, 1292 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1293 1294 rxstat = le16toh(rfa->rfa_status); 1295 1296 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1297 rnr = 1; 1298 1299 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1300 /* 1301 * We have processed all of the 1302 * receive buffers. 1303 */ 1304 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1305 return rnr; 1306 } 1307 1308 IF_DEQUEUE(&sc->sc_rxq, m); 1309 1310 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1311 1312 len = le16toh(rfa->actual_size) & 1313 (m->m_ext.ext_size - 1); 1314 1315 if (len < sizeof(struct ether_header)) { 1316 /* 1317 * Runt packet; drop it now. 1318 */ 1319 FXP_INIT_RFABUF(sc, m); 1320 continue; 1321 } 1322 1323 /* 1324 * If support for 802.1Q VLAN sized frames is 1325 * enabled, we need to do some additional error 1326 * checking (as we are saving bad frames, in 1327 * order to receive the larger ones). 1328 */ 1329 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1330 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1331 FXP_RFA_STATUS_RNR| 1332 FXP_RFA_STATUS_ALIGN| 1333 FXP_RFA_STATUS_CRC)) != 0) { 1334 FXP_INIT_RFABUF(sc, m); 1335 continue; 1336 } 1337 1338 /* Do checksum checking. */ 1339 m->m_pkthdr.csum_flags = 0; 1340 if (sc->sc_flags & FXPF_EXT_RFA) 1341 if (fxp_rx_hwcksum(m, rfa)) 1342 goto dropit; 1343 1344 /* 1345 * If the packet is small enough to fit in a 1346 * single header mbuf, allocate one and copy 1347 * the data into it. This greatly reduces 1348 * memory consumption when we receive lots 1349 * of small packets. 1350 * 1351 * Otherwise, we add a new buffer to the receive 1352 * chain. If this fails, we drop the packet and 1353 * recycle the old buffer. 1354 */ 1355 if (fxp_copy_small != 0 && len <= MHLEN) { 1356 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1357 if (m0 == NULL) 1358 goto dropit; 1359 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1360 memcpy(mtod(m0, void *), 1361 mtod(m, void *), len); 1362 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1363 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1364 FXP_INIT_RFABUF(sc, m); 1365 m = m0; 1366 } else { 1367 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1368 dropit: 1369 ifp->if_ierrors++; 1370 FXP_INIT_RFABUF(sc, m); 1371 continue; 1372 } 1373 } 1374 1375 m->m_pkthdr.rcvif = ifp; 1376 m->m_pkthdr.len = m->m_len = len; 1377 1378 #if NBPFILTER > 0 1379 /* 1380 * Pass this up to any BPF listeners, but only 1381 * pass it up the stack if it's for us. 1382 */ 1383 if (ifp->if_bpf) 1384 bpf_mtap(ifp->if_bpf, m); 1385 #endif 1386 1387 /* Pass it on. */ 1388 (*ifp->if_input)(ifp, m); 1389 } 1390 } 1391 1392 /* 1393 * Update packet in/out/collision statistics. The i82557 doesn't 1394 * allow you to access these counters without doing a fairly 1395 * expensive DMA to get _all_ of the statistics it maintains, so 1396 * we do this operation here only once per second. The statistics 1397 * counters in the kernel are updated from the previous dump-stats 1398 * DMA and then a new dump-stats DMA is started. The on-chip 1399 * counters are zeroed when the DMA completes. If we can't start 1400 * the DMA immediately, we don't wait - we just prepare to read 1401 * them again next time. 1402 */ 1403 void 1404 fxp_tick(void *arg) 1405 { 1406 struct fxp_softc *sc = arg; 1407 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1408 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1409 int s; 1410 1411 if (!device_is_active(sc->sc_dev)) 1412 return; 1413 1414 s = splnet(); 1415 1416 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1417 1418 ifp->if_opackets += le32toh(sp->tx_good); 1419 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1420 if (sp->rx_good) { 1421 ifp->if_ipackets += le32toh(sp->rx_good); 1422 sc->sc_rxidle = 0; 1423 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1424 sc->sc_rxidle++; 1425 } 1426 ifp->if_ierrors += 1427 le32toh(sp->rx_crc_errors) + 1428 le32toh(sp->rx_alignment_errors) + 1429 le32toh(sp->rx_rnr_errors) + 1430 le32toh(sp->rx_overrun_errors); 1431 /* 1432 * If any transmit underruns occurred, bump up the transmit 1433 * threshold by another 512 bytes (64 * 8). 1434 */ 1435 if (sp->tx_underruns) { 1436 ifp->if_oerrors += le32toh(sp->tx_underruns); 1437 if (tx_threshold < 192) 1438 tx_threshold += 64; 1439 } 1440 #ifdef FXP_EVENT_COUNTERS 1441 if (sc->sc_rev >= FXP_REV_82558_A4) { 1442 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1443 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1444 } 1445 #endif 1446 1447 /* 1448 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1449 * then assume the receiver has locked up and attempt to clear 1450 * the condition by reprogramming the multicast filter (actually, 1451 * resetting the interface). This is a work-around for a bug in 1452 * the 82557 where the receiver locks up if it gets certain types 1453 * of garbage in the synchronization bits prior to the packet header. 1454 * This bug is supposed to only occur in 10Mbps mode, but has been 1455 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1456 * speed transition). 1457 */ 1458 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1459 (void) fxp_init(ifp); 1460 splx(s); 1461 return; 1462 } 1463 /* 1464 * If there is no pending command, start another stats 1465 * dump. Otherwise punt for now. 1466 */ 1467 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1468 /* 1469 * Start another stats dump. 1470 */ 1471 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1472 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1473 } else { 1474 /* 1475 * A previous command is still waiting to be accepted. 1476 * Just zero our copy of the stats and wait for the 1477 * next timer event to update them. 1478 */ 1479 /* BIG_ENDIAN: no swap required to store 0 */ 1480 sp->tx_good = 0; 1481 sp->tx_underruns = 0; 1482 sp->tx_total_collisions = 0; 1483 1484 sp->rx_good = 0; 1485 sp->rx_crc_errors = 0; 1486 sp->rx_alignment_errors = 0; 1487 sp->rx_rnr_errors = 0; 1488 sp->rx_overrun_errors = 0; 1489 if (sc->sc_rev >= FXP_REV_82558_A4) { 1490 sp->tx_pauseframes = 0; 1491 sp->rx_pauseframes = 0; 1492 } 1493 } 1494 1495 if (sc->sc_flags & FXPF_MII) { 1496 /* Tick the MII clock. */ 1497 mii_tick(&sc->sc_mii); 1498 } 1499 1500 splx(s); 1501 1502 /* 1503 * Schedule another timeout one second from now. 1504 */ 1505 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1506 } 1507 1508 /* 1509 * Drain the receive queue. 1510 */ 1511 void 1512 fxp_rxdrain(struct fxp_softc *sc) 1513 { 1514 bus_dmamap_t rxmap; 1515 struct mbuf *m; 1516 1517 for (;;) { 1518 IF_DEQUEUE(&sc->sc_rxq, m); 1519 if (m == NULL) 1520 break; 1521 rxmap = M_GETCTX(m, bus_dmamap_t); 1522 bus_dmamap_unload(sc->sc_dmat, rxmap); 1523 FXP_RXMAP_PUT(sc, rxmap); 1524 m_freem(m); 1525 } 1526 } 1527 1528 /* 1529 * Stop the interface. Cancels the statistics updater and resets 1530 * the interface. 1531 */ 1532 void 1533 fxp_stop(struct ifnet *ifp, int disable) 1534 { 1535 struct fxp_softc *sc = ifp->if_softc; 1536 struct fxp_txsoft *txs; 1537 int i; 1538 1539 /* 1540 * Turn down interface (done early to avoid bad interactions 1541 * between panics, shutdown hooks, and the watchdog timer) 1542 */ 1543 ifp->if_timer = 0; 1544 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1545 1546 /* 1547 * Cancel stats updater. 1548 */ 1549 callout_stop(&sc->sc_callout); 1550 if (sc->sc_flags & FXPF_MII) { 1551 /* Down the MII. */ 1552 mii_down(&sc->sc_mii); 1553 } 1554 1555 /* 1556 * Issue software reset. This unloads any microcode that 1557 * might already be loaded. 1558 */ 1559 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1560 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1561 DELAY(50); 1562 1563 /* 1564 * Release any xmit buffers. 1565 */ 1566 for (i = 0; i < FXP_NTXCB; i++) { 1567 txs = FXP_DSTX(sc, i); 1568 if (txs->txs_mbuf != NULL) { 1569 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1570 m_freem(txs->txs_mbuf); 1571 txs->txs_mbuf = NULL; 1572 } 1573 } 1574 sc->sc_txpending = 0; 1575 1576 if (disable) { 1577 fxp_rxdrain(sc); 1578 fxp_disable(sc); 1579 } 1580 1581 } 1582 1583 /* 1584 * Watchdog/transmission transmit timeout handler. Called when a 1585 * transmission is started on the interface, but no interrupt is 1586 * received before the timeout. This usually indicates that the 1587 * card has wedged for some reason. 1588 */ 1589 void 1590 fxp_watchdog(struct ifnet *ifp) 1591 { 1592 struct fxp_softc *sc = ifp->if_softc; 1593 1594 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1595 ifp->if_oerrors++; 1596 1597 (void) fxp_init(ifp); 1598 } 1599 1600 /* 1601 * Initialize the interface. Must be called at splnet(). 1602 */ 1603 int 1604 fxp_init(struct ifnet *ifp) 1605 { 1606 struct fxp_softc *sc = ifp->if_softc; 1607 struct fxp_cb_config *cbp; 1608 struct fxp_cb_ias *cb_ias; 1609 struct fxp_txdesc *txd; 1610 bus_dmamap_t rxmap; 1611 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1612 uint16_t status; 1613 1614 if ((error = fxp_enable(sc)) != 0) 1615 goto out; 1616 1617 /* 1618 * Cancel any pending I/O 1619 */ 1620 fxp_stop(ifp, 0); 1621 1622 /* 1623 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1624 * flag, and this prevents the MII from detaching resulting in 1625 * a panic. The flags field should perhaps be split in runtime 1626 * flags and more static information. For now, just clear the 1627 * only other flag set. 1628 */ 1629 1630 sc->sc_flags &= ~FXPF_WANTINIT; 1631 1632 /* 1633 * Initialize base of CBL and RFA memory. Loading with zero 1634 * sets it up for regular linear addressing. 1635 */ 1636 fxp_scb_wait(sc); 1637 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1638 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1639 1640 fxp_scb_wait(sc); 1641 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1642 1643 /* 1644 * Initialize the multicast filter. Do this now, since we might 1645 * have to setup the config block differently. 1646 */ 1647 fxp_mc_setup(sc); 1648 1649 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1650 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1651 1652 /* 1653 * In order to support receiving 802.1Q VLAN frames, we have to 1654 * enable "save bad frames", since they are 4 bytes larger than 1655 * the normal Ethernet maximum frame length. On i82558 and later, 1656 * we have a better mechanism for this. 1657 */ 1658 save_bf = 0; 1659 lrxen = 0; 1660 vlan_drop = 0; 1661 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1662 if (sc->sc_rev < FXP_REV_82558_A4) 1663 save_bf = 1; 1664 else 1665 lrxen = 1; 1666 if (sc->sc_rev >= FXP_REV_82550) 1667 vlan_drop = 1; 1668 } 1669 1670 /* 1671 * Initialize base of dump-stats buffer. 1672 */ 1673 fxp_scb_wait(sc); 1674 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1675 sc->sc_cddma + FXP_CDSTATSOFF); 1676 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1677 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1678 1679 cbp = &sc->sc_control_data->fcd_configcb; 1680 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1681 1682 /* 1683 * Load microcode for this controller. 1684 */ 1685 fxp_load_ucode(sc); 1686 1687 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1688 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1689 else 1690 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1691 1692 /* 1693 * This copy is kind of disgusting, but there are a bunch of must be 1694 * zero and must be one bits in this structure and this is the easiest 1695 * way to initialize them all to proper values. 1696 */ 1697 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1698 1699 /* BIG_ENDIAN: no need to swap to store 0 */ 1700 cbp->cb_status = 0; 1701 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1702 FXP_CB_COMMAND_EL); 1703 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1704 cbp->link_addr = 0xffffffff; /* (no) next command */ 1705 /* bytes in config block */ 1706 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1707 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1708 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1709 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1710 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1711 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1712 cbp->type_enable = 0; /* actually reserved */ 1713 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1714 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1715 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1716 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1717 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1718 cbp->late_scb = 0; /* (don't) defer SCB update */ 1719 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1720 cbp->ci_int = 1; /* interrupt on CU idle */ 1721 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1722 cbp->ext_stats_dis = 1; /* disable extended counters */ 1723 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1724 cbp->save_bf = save_bf;/* save bad frames */ 1725 cbp->disc_short_rx = !prm; /* discard short packets */ 1726 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1727 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1728 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1729 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1730 /* interface mode */ 1731 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1732 cbp->csma_dis = 0; /* (don't) disable link */ 1733 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1734 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1735 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1736 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1737 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1738 cbp->nsai = 1; /* (don't) disable source addr insert */ 1739 cbp->preamble_length = 2; /* (7 byte) preamble */ 1740 cbp->loopback = 0; /* (don't) loopback */ 1741 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1742 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1743 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1744 cbp->promiscuous = prm; /* promiscuous mode */ 1745 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1746 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1747 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1748 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1749 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1750 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1751 cbp->padding = 1; /* (do) pad short tx packets */ 1752 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1753 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1754 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1755 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1756 /* must set wake_en in PMCSR also */ 1757 cbp->force_fdx = 0; /* (don't) force full duplex */ 1758 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1759 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1760 cbp->mc_all = allm; /* accept all multicasts */ 1761 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1762 cbp->vlan_drop_en = vlan_drop; 1763 1764 if (sc->sc_rev < FXP_REV_82558_A4) { 1765 /* 1766 * The i82557 has no hardware flow control, the values 1767 * here are the defaults for the chip. 1768 */ 1769 cbp->fc_delay_lsb = 0; 1770 cbp->fc_delay_msb = 0x40; 1771 cbp->pri_fc_thresh = 3; 1772 cbp->tx_fc_dis = 0; 1773 cbp->rx_fc_restop = 0; 1774 cbp->rx_fc_restart = 0; 1775 cbp->fc_filter = 0; 1776 cbp->pri_fc_loc = 1; 1777 } else { 1778 cbp->fc_delay_lsb = 0x1f; 1779 cbp->fc_delay_msb = 0x01; 1780 cbp->pri_fc_thresh = 3; 1781 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1782 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1783 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1784 cbp->fc_filter = !prm; /* drop FC frames to host */ 1785 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1786 cbp->ext_stats_dis = 0; /* enable extended stats */ 1787 } 1788 1789 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1790 1791 /* 1792 * Start the config command/DMA. 1793 */ 1794 fxp_scb_wait(sc); 1795 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1796 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1797 /* ...and wait for it to complete. */ 1798 for (i = 1000; i > 0; i--) { 1799 FXP_CDCONFIGSYNC(sc, 1800 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1801 status = le16toh(cbp->cb_status); 1802 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1803 if ((status & FXP_CB_STATUS_C) != 0) 1804 break; 1805 DELAY(1); 1806 } 1807 if (i == 0) { 1808 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1809 device_xname(sc->sc_dev), __LINE__); 1810 return (ETIMEDOUT); 1811 } 1812 1813 /* 1814 * Initialize the station address. 1815 */ 1816 cb_ias = &sc->sc_control_data->fcd_iascb; 1817 /* BIG_ENDIAN: no need to swap to store 0 */ 1818 cb_ias->cb_status = 0; 1819 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1820 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1821 cb_ias->link_addr = 0xffffffff; 1822 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1823 1824 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1825 1826 /* 1827 * Start the IAS (Individual Address Setup) command/DMA. 1828 */ 1829 fxp_scb_wait(sc); 1830 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1831 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1832 /* ...and wait for it to complete. */ 1833 for (i = 1000; i > 0; i++) { 1834 FXP_CDIASSYNC(sc, 1835 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1836 status = le16toh(cb_ias->cb_status); 1837 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1838 if ((status & FXP_CB_STATUS_C) != 0) 1839 break; 1840 DELAY(1); 1841 } 1842 if (i == 0) { 1843 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1844 device_xname(sc->sc_dev), __LINE__); 1845 return (ETIMEDOUT); 1846 } 1847 1848 /* 1849 * Initialize the transmit descriptor ring. txlast is initialized 1850 * to the end of the list so that it will wrap around to the first 1851 * descriptor when the first packet is transmitted. 1852 */ 1853 for (i = 0; i < FXP_NTXCB; i++) { 1854 txd = FXP_CDTX(sc, i); 1855 memset(txd, 0, sizeof(*txd)); 1856 txd->txd_txcb.cb_command = 1857 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1858 txd->txd_txcb.link_addr = 1859 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1860 if (sc->sc_flags & FXPF_EXT_TXCB) 1861 txd->txd_txcb.tbd_array_addr = 1862 htole32(FXP_CDTBDADDR(sc, i) + 1863 (2 * sizeof(struct fxp_tbd))); 1864 else 1865 txd->txd_txcb.tbd_array_addr = 1866 htole32(FXP_CDTBDADDR(sc, i)); 1867 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1868 } 1869 sc->sc_txpending = 0; 1870 sc->sc_txdirty = 0; 1871 sc->sc_txlast = FXP_NTXCB - 1; 1872 1873 /* 1874 * Initialize the receive buffer list. 1875 */ 1876 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1877 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1878 rxmap = FXP_RXMAP_GET(sc); 1879 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1880 log(LOG_ERR, "%s: unable to allocate or map rx " 1881 "buffer %d, error = %d\n", 1882 device_xname(sc->sc_dev), 1883 sc->sc_rxq.ifq_len, error); 1884 /* 1885 * XXX Should attempt to run with fewer receive 1886 * XXX buffers instead of just failing. 1887 */ 1888 FXP_RXMAP_PUT(sc, rxmap); 1889 fxp_rxdrain(sc); 1890 goto out; 1891 } 1892 } 1893 sc->sc_rxidle = 0; 1894 1895 /* 1896 * Give the transmit ring to the chip. We do this by pointing 1897 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1898 * issuing a start command. It will execute the NOP and then 1899 * suspend, pointing at the first descriptor. 1900 */ 1901 fxp_scb_wait(sc); 1902 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1903 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1904 1905 /* 1906 * Initialize receiver buffer area - RFA. 1907 */ 1908 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1909 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1910 fxp_scb_wait(sc); 1911 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1912 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1913 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1914 #endif 1915 1916 if (sc->sc_flags & FXPF_MII) { 1917 /* 1918 * Set current media. 1919 */ 1920 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1921 goto out; 1922 } 1923 1924 /* 1925 * ...all done! 1926 */ 1927 ifp->if_flags |= IFF_RUNNING; 1928 ifp->if_flags &= ~IFF_OACTIVE; 1929 1930 /* 1931 * Request a software generated interrupt that will be used to 1932 * (re)start the RU processing. If we direct the chip to start 1933 * receiving from the start of queue now, instead of letting the 1934 * interrupt handler first process all received packets, we run 1935 * the risk of having it overwrite mbuf clusters while they are 1936 * being processed or after they have been returned to the pool. 1937 */ 1938 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1939 1940 /* 1941 * Start the one second timer. 1942 */ 1943 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1944 1945 /* 1946 * Attempt to start output on the interface. 1947 */ 1948 fxp_start(ifp); 1949 1950 out: 1951 if (error) { 1952 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1953 ifp->if_timer = 0; 1954 log(LOG_ERR, "%s: interface not running\n", 1955 device_xname(sc->sc_dev)); 1956 } 1957 return (error); 1958 } 1959 1960 /* 1961 * Notify the world which media we're using. 1962 */ 1963 void 1964 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1965 { 1966 struct fxp_softc *sc = ifp->if_softc; 1967 1968 if (sc->sc_enabled == 0) { 1969 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1970 ifmr->ifm_status = 0; 1971 return; 1972 } 1973 1974 ether_mediastatus(ifp, ifmr); 1975 1976 /* 1977 * XXX Flow control is always turned on if the chip supports 1978 * XXX it; we can't easily control it dynamically, since it 1979 * XXX requires sending a setup packet. 1980 */ 1981 if (sc->sc_rev >= FXP_REV_82558_A4) 1982 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1983 } 1984 1985 int 1986 fxp_80c24_mediachange(struct ifnet *ifp) 1987 { 1988 1989 /* Nothing to do here. */ 1990 return (0); 1991 } 1992 1993 void 1994 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1995 { 1996 struct fxp_softc *sc = ifp->if_softc; 1997 1998 /* 1999 * Media is currently-selected media. We cannot determine 2000 * the link status. 2001 */ 2002 ifmr->ifm_status = 0; 2003 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2004 } 2005 2006 /* 2007 * Add a buffer to the end of the RFA buffer list. 2008 * Return 0 if successful, error code on failure. 2009 * 2010 * The RFA struct is stuck at the beginning of mbuf cluster and the 2011 * data pointer is fixed up to point just past it. 2012 */ 2013 int 2014 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2015 { 2016 struct mbuf *m; 2017 int error; 2018 2019 MGETHDR(m, M_DONTWAIT, MT_DATA); 2020 if (m == NULL) 2021 return (ENOBUFS); 2022 2023 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2024 MCLGET(m, M_DONTWAIT); 2025 if ((m->m_flags & M_EXT) == 0) { 2026 m_freem(m); 2027 return (ENOBUFS); 2028 } 2029 2030 if (unload) 2031 bus_dmamap_unload(sc->sc_dmat, rxmap); 2032 2033 M_SETCTX(m, rxmap); 2034 2035 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2036 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2037 BUS_DMA_READ|BUS_DMA_NOWAIT); 2038 if (error) { 2039 /* XXX XXX XXX */ 2040 aprint_error_dev(sc->sc_dev, 2041 "can't load rx DMA map %d, error = %d\n", 2042 sc->sc_rxq.ifq_len, error); 2043 panic("fxp_add_rfabuf"); 2044 } 2045 2046 FXP_INIT_RFABUF(sc, m); 2047 2048 return (0); 2049 } 2050 2051 int 2052 fxp_mdi_read(device_t self, int phy, int reg) 2053 { 2054 struct fxp_softc *sc = device_private(self); 2055 int count = 10000; 2056 int value; 2057 2058 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2059 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2060 2061 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2062 0x10000000) == 0 && count--) 2063 DELAY(10); 2064 2065 if (count <= 0) 2066 log(LOG_WARNING, 2067 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2068 2069 return (value & 0xffff); 2070 } 2071 2072 void 2073 fxp_statchg(device_t self) 2074 { 2075 2076 /* Nothing to do. */ 2077 } 2078 2079 void 2080 fxp_mdi_write(device_t self, int phy, int reg, int value) 2081 { 2082 struct fxp_softc *sc = device_private(self); 2083 int count = 10000; 2084 2085 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2086 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2087 (value & 0xffff)); 2088 2089 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2090 count--) 2091 DELAY(10); 2092 2093 if (count <= 0) 2094 log(LOG_WARNING, 2095 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2096 } 2097 2098 int 2099 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2100 { 2101 struct fxp_softc *sc = ifp->if_softc; 2102 struct ifreq *ifr = (struct ifreq *)data; 2103 int s, error; 2104 2105 s = splnet(); 2106 2107 switch (cmd) { 2108 case SIOCSIFMEDIA: 2109 case SIOCGIFMEDIA: 2110 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2111 break; 2112 2113 default: 2114 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2115 break; 2116 2117 error = 0; 2118 2119 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2120 ; 2121 else if (ifp->if_flags & IFF_RUNNING) { 2122 /* 2123 * Multicast list has changed; set the 2124 * hardware filter accordingly. 2125 */ 2126 while (sc->sc_txpending) { 2127 sc->sc_flags |= FXPF_WANTINIT; 2128 tsleep(sc, PSOCK, "fxp_init", 0); 2129 } 2130 error = fxp_init(ifp); 2131 } 2132 break; 2133 } 2134 2135 /* Try to get more packets going. */ 2136 if (sc->sc_enabled) 2137 fxp_start(ifp); 2138 2139 splx(s); 2140 return (error); 2141 } 2142 2143 /* 2144 * Program the multicast filter. 2145 * 2146 * This function must be called at splnet(). 2147 */ 2148 void 2149 fxp_mc_setup(struct fxp_softc *sc) 2150 { 2151 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2152 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2153 struct ethercom *ec = &sc->sc_ethercom; 2154 struct ether_multi *enm; 2155 struct ether_multistep step; 2156 int count, nmcasts; 2157 uint16_t status; 2158 2159 #ifdef DIAGNOSTIC 2160 if (sc->sc_txpending) 2161 panic("fxp_mc_setup: pending transmissions"); 2162 #endif 2163 2164 ifp->if_flags &= ~IFF_ALLMULTI; 2165 2166 /* 2167 * Initialize multicast setup descriptor. 2168 */ 2169 nmcasts = 0; 2170 ETHER_FIRST_MULTI(step, ec, enm); 2171 while (enm != NULL) { 2172 /* 2173 * Check for too many multicast addresses or if we're 2174 * listening to a range. Either way, we simply have 2175 * to accept all multicasts. 2176 */ 2177 if (nmcasts >= MAXMCADDR || 2178 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2179 ETHER_ADDR_LEN) != 0) { 2180 /* 2181 * Callers of this function must do the 2182 * right thing with this. If we're called 2183 * from outside fxp_init(), the caller must 2184 * detect if the state if IFF_ALLMULTI changes. 2185 * If it does, the caller must then call 2186 * fxp_init(), since allmulti is handled by 2187 * the config block. 2188 */ 2189 ifp->if_flags |= IFF_ALLMULTI; 2190 return; 2191 } 2192 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2193 ETHER_ADDR_LEN); 2194 nmcasts++; 2195 ETHER_NEXT_MULTI(step, enm); 2196 } 2197 2198 /* BIG_ENDIAN: no need to swap to store 0 */ 2199 mcsp->cb_status = 0; 2200 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2201 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2202 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2203 2204 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2205 2206 /* 2207 * Wait until the command unit is not active. This should never 2208 * happen since nothing is queued, but make sure anyway. 2209 */ 2210 count = 100; 2211 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2212 FXP_SCB_CUS_ACTIVE && --count) 2213 DELAY(1); 2214 if (count == 0) { 2215 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2216 device_xname(sc->sc_dev), __LINE__); 2217 return; 2218 } 2219 2220 /* 2221 * Start the multicast setup command/DMA. 2222 */ 2223 fxp_scb_wait(sc); 2224 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2225 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2226 2227 /* ...and wait for it to complete. */ 2228 for (count = 1000; count > 0; count--) { 2229 FXP_CDMCSSYNC(sc, 2230 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2231 status = le16toh(mcsp->cb_status); 2232 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2233 if ((status & FXP_CB_STATUS_C) != 0) 2234 break; 2235 DELAY(1); 2236 } 2237 if (count == 0) { 2238 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2239 device_xname(sc->sc_dev), __LINE__); 2240 return; 2241 } 2242 } 2243 2244 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2245 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2246 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2247 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2248 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2249 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2250 2251 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2252 2253 static const struct ucode { 2254 int32_t revision; 2255 const uint32_t *ucode; 2256 size_t length; 2257 uint16_t int_delay_offset; 2258 uint16_t bundle_max_offset; 2259 } ucode_table[] = { 2260 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2261 D101_CPUSAVER_DWORD, 0 }, 2262 2263 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2264 D101_CPUSAVER_DWORD, 0 }, 2265 2266 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2267 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2268 2269 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2270 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2271 2272 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2273 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2274 2275 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2276 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2277 2278 { 0, NULL, 0, 0, 0 } 2279 }; 2280 2281 void 2282 fxp_load_ucode(struct fxp_softc *sc) 2283 { 2284 const struct ucode *uc; 2285 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2286 int count, i; 2287 uint16_t status; 2288 2289 if (sc->sc_flags & FXPF_UCODE_LOADED) 2290 return; 2291 2292 /* 2293 * Only load the uCode if the user has requested that 2294 * we do so. 2295 */ 2296 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2297 sc->sc_int_delay = 0; 2298 sc->sc_bundle_max = 0; 2299 return; 2300 } 2301 2302 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2303 if (sc->sc_rev == uc->revision) 2304 break; 2305 } 2306 if (uc->ucode == NULL) 2307 return; 2308 2309 /* BIG ENDIAN: no need to swap to store 0 */ 2310 cbp->cb_status = 0; 2311 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2312 cbp->link_addr = 0xffffffff; /* (no) next command */ 2313 for (i = 0; i < uc->length; i++) 2314 cbp->ucode[i] = htole32(uc->ucode[i]); 2315 2316 if (uc->int_delay_offset) 2317 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2318 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2319 2320 if (uc->bundle_max_offset) 2321 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2322 htole16(fxp_bundle_max); 2323 2324 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2325 2326 /* 2327 * Download the uCode to the chip. 2328 */ 2329 fxp_scb_wait(sc); 2330 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2331 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2332 2333 /* ...and wait for it to complete. */ 2334 for (count = 10000; count > 0; count--) { 2335 FXP_CDUCODESYNC(sc, 2336 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2337 status = le16toh(cbp->cb_status); 2338 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2339 if ((status & FXP_CB_STATUS_C) != 0) 2340 break; 2341 DELAY(2); 2342 } 2343 if (count == 0) { 2344 sc->sc_int_delay = 0; 2345 sc->sc_bundle_max = 0; 2346 log(LOG_WARNING, "%s: timeout loading microcode\n", 2347 device_xname(sc->sc_dev)); 2348 return; 2349 } 2350 2351 if (sc->sc_int_delay != fxp_int_delay || 2352 sc->sc_bundle_max != fxp_bundle_max) { 2353 sc->sc_int_delay = fxp_int_delay; 2354 sc->sc_bundle_max = fxp_bundle_max; 2355 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2356 "max bundle: %d\n", device_xname(sc->sc_dev), 2357 sc->sc_int_delay, 2358 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2359 } 2360 2361 sc->sc_flags |= FXPF_UCODE_LOADED; 2362 } 2363 2364 int 2365 fxp_enable(struct fxp_softc *sc) 2366 { 2367 2368 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2369 if ((*sc->sc_enable)(sc) != 0) { 2370 log(LOG_ERR, "%s: device enable failed\n", 2371 device_xname(sc->sc_dev)); 2372 return (EIO); 2373 } 2374 } 2375 2376 sc->sc_enabled = 1; 2377 return (0); 2378 } 2379 2380 void 2381 fxp_disable(struct fxp_softc *sc) 2382 { 2383 2384 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2385 (*sc->sc_disable)(sc); 2386 sc->sc_enabled = 0; 2387 } 2388 } 2389 2390 /* 2391 * fxp_activate: 2392 * 2393 * Handle device activation/deactivation requests. 2394 */ 2395 int 2396 fxp_activate(device_t self, enum devact act) 2397 { 2398 struct fxp_softc *sc = device_private(self); 2399 int s, error = 0; 2400 2401 s = splnet(); 2402 switch (act) { 2403 case DVACT_ACTIVATE: 2404 error = EOPNOTSUPP; 2405 break; 2406 2407 case DVACT_DEACTIVATE: 2408 if (sc->sc_flags & FXPF_MII) 2409 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2410 MII_OFFSET_ANY); 2411 if_deactivate(&sc->sc_ethercom.ec_if); 2412 break; 2413 } 2414 splx(s); 2415 2416 return (error); 2417 } 2418 2419 /* 2420 * fxp_detach: 2421 * 2422 * Detach an i82557 interface. 2423 */ 2424 int 2425 fxp_detach(struct fxp_softc *sc) 2426 { 2427 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2428 int i; 2429 2430 /* Succeed now if there's no work to do. */ 2431 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2432 return (0); 2433 2434 /* Unhook our tick handler. */ 2435 callout_stop(&sc->sc_callout); 2436 2437 if (sc->sc_flags & FXPF_MII) { 2438 /* Detach all PHYs */ 2439 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2440 } 2441 2442 /* Delete all remaining media. */ 2443 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2444 2445 #if NRND > 0 2446 rnd_detach_source(&sc->rnd_source); 2447 #endif 2448 ether_ifdetach(ifp); 2449 if_detach(ifp); 2450 2451 for (i = 0; i < FXP_NRFABUFS; i++) { 2452 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2453 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2454 } 2455 2456 for (i = 0; i < FXP_NTXCB; i++) { 2457 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2458 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2459 } 2460 2461 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2462 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2463 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2464 sizeof(struct fxp_control_data)); 2465 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2466 2467 return (0); 2468 } 2469
Indexes created Mon Oct 27 02:09:54 GMT 2025