i82557.c revision 1.112
1 /* $NetBSD: i82557.c,v 1.112 2008/04/08 12:07:26 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.112 2008/04/08 12:07:26 cegger Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/syslog.h> 92 93 #include <machine/endian.h> 94 95 #include <uvm/uvm_extern.h> 96 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 113 #include <dev/mii/miivar.h> 114 115 #include <dev/ic/i82557reg.h> 116 #include <dev/ic/i82557var.h> 117 118 #include <dev/microcode/i8255x/rcvbundl.h> 119 120 /* 121 * NOTE! On the Alpha, we have an alignment constraint. The 122 * card DMAs the packet immediately following the RFA. However, 123 * the first thing in the packet is a 14-byte Ethernet header. 124 * This means that the packet is misaligned. To compensate, 125 * we actually offset the RFA 2 bytes into the cluster. This 126 * alignes the packet after the Ethernet header at a 32-bit 127 * boundary. HOWEVER! This means that the RFA is misaligned! 128 */ 129 #define RFA_ALIGNMENT_FUDGE 2 130 131 /* 132 * The configuration byte map has several undefined fields which 133 * must be one or must be zero. Set up a template for these bits 134 * only (assuming an i82557 chip), leaving the actual configuration 135 * for fxp_init(). 136 * 137 * See the definition of struct fxp_cb_config for the bit definitions. 138 */ 139 const u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x0, 0x0, /* cb_command */ 142 0x0, 0x0, 0x0, 0x0, /* link_addr */ 143 0x0, /* 0 */ 144 0x0, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x0, /* 5 */ 149 0x32, /* 6 */ 150 0x0, /* 7 */ 151 0x0, /* 8 */ 152 0x0, /* 9 */ 153 0x6, /* 10 */ 154 0x0, /* 11 */ 155 0x0, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf0, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5, /* 21 */ 165 0x0, /* 22 */ 166 0x0, /* 23 */ 167 0x0, /* 24 */ 168 0x0, /* 25 */ 169 0x0, /* 26 */ 170 0x0, /* 27 */ 171 0x0, /* 28 */ 172 0x0, /* 29 */ 173 0x0, /* 30 */ 174 0x0, /* 31 */ 175 }; 176 177 void fxp_mii_initmedia(struct fxp_softc *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, void *); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 int fxp_rxintr(struct fxp_softc *); 192 193 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 int fxp_copy_small = 0; 210 211 /* 212 * Variables for interrupt mitigating microcode. 213 */ 214 int fxp_int_delay = 1000; /* usec */ 215 int fxp_bundle_max = 6; /* packets */ 216 217 struct fxp_phytype { 218 int fp_phy; /* type of PHY, -1 for MII at the end. */ 219 void (*fp_init)(struct fxp_softc *); 220 } fxp_phytype_table[] = { 221 { FXP_PHY_80C24, fxp_80c24_initmedia }, 222 { -1, fxp_mii_initmedia }, 223 }; 224 225 /* 226 * Set initial transmit threshold at 64 (512 bytes). This is 227 * increased by 64 (512 bytes) at a time, to maximum of 192 228 * (1536 bytes), if an underrun occurs. 229 */ 230 static int tx_threshold = 64; 231 232 /* 233 * Wait for the previous command to be accepted (but not necessarily 234 * completed). 235 */ 236 static inline void 237 fxp_scb_wait(struct fxp_softc *sc) 238 { 239 int i = 10000; 240 241 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 242 delay(2); 243 if (i == 0) 244 log(LOG_WARNING, 245 "%s: WARNING: SCB timed out!\n", device_xname(&sc->sc_dev)); 246 } 247 248 /* 249 * Submit a command to the i82557. 250 */ 251 static inline void 252 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253 { 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256 } 257 258 /* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261 void 262 fxp_attach(struct fxp_softc *sc) 263 { 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout, 0); 271 272 /* 273 * Enable some good stuff on i82558 and later. 274 */ 275 if (sc->sc_rev >= FXP_REV_82558_A4) { 276 /* Enable the extended TxCB. */ 277 sc->sc_flags |= FXPF_EXT_TXCB; 278 } 279 280 /* 281 * Enable use of extended RFDs and TCBs for 82550 282 * and later chips. Note: we need extended TXCB support 283 * too, but that's already enabled by the code above. 284 * Be careful to do this only on the right devices. 285 */ 286 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 287 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 288 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 289 } else { 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 291 } 292 293 sc->sc_rfa_size = 294 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 295 296 /* 297 * Allocate the control data structures, and create and load the 298 * DMA map for it. 299 */ 300 if ((error = bus_dmamem_alloc(sc->sc_dmat, 301 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 302 0)) != 0) { 303 aprint_error_dev(&sc->sc_dev, 304 "unable to allocate control data, error = %d\n", 305 error); 306 goto fail_0; 307 } 308 309 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 310 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 311 BUS_DMA_COHERENT)) != 0) { 312 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 313 error); 314 goto fail_1; 315 } 316 sc->sc_cdseg = seg; 317 sc->sc_cdnseg = rseg; 318 319 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 320 321 if ((error = bus_dmamap_create(sc->sc_dmat, 322 sizeof(struct fxp_control_data), 1, 323 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 324 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 325 "error = %d\n", error); 326 goto fail_2; 327 } 328 329 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 330 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 331 0)) != 0) { 332 aprint_error_dev(&sc->sc_dev, 333 "can't load control data DMA map, error = %d\n", 334 error); 335 goto fail_3; 336 } 337 338 /* 339 * Create the transmit buffer DMA maps. 340 */ 341 for (i = 0; i < FXP_NTXCB; i++) { 342 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 343 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 344 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 345 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 346 "error = %d\n", i, error); 347 goto fail_4; 348 } 349 } 350 351 /* 352 * Create the receive buffer DMA maps. 353 */ 354 for (i = 0; i < FXP_NRFABUFS; i++) { 355 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 356 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 357 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 358 "error = %d\n", i, error); 359 goto fail_5; 360 } 361 } 362 363 /* Initialize MAC address and media structures. */ 364 fxp_get_info(sc, enaddr); 365 366 aprint_normal_dev(&sc->sc_dev, "Ethernet address %s\n", 367 ether_sprintf(enaddr)); 368 369 ifp = &sc->sc_ethercom.ec_if; 370 371 /* 372 * Get info about our media interface, and initialize it. Note 373 * the table terminates itself with a phy of -1, indicating 374 * that we're using MII. 375 */ 376 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 377 if (fp->fp_phy == sc->phy_primary_device) 378 break; 379 (*fp->fp_init)(sc); 380 381 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 382 ifp->if_softc = sc; 383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 384 ifp->if_ioctl = fxp_ioctl; 385 ifp->if_start = fxp_start; 386 ifp->if_watchdog = fxp_watchdog; 387 ifp->if_init = fxp_init; 388 ifp->if_stop = fxp_stop; 389 IFQ_SET_READY(&ifp->if_snd); 390 391 if (sc->sc_flags & FXPF_IPCB) { 392 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 393 /* 394 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 395 * at least, on i82550 rev.12. 396 * specifically, it doesn't calculate ipv4 checksum correctly 397 * when sending 20 byte ipv4 header + 1 or 2 byte data. 398 * FreeBSD driver has related comments. 399 */ 400 ifp->if_capabilities = 401 IFCAP_CSUM_IPv4_Rx | 402 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 403 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 404 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 405 } 406 407 /* 408 * We can support 802.1Q VLAN-sized frames. 409 */ 410 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 411 412 /* 413 * Attach the interface. 414 */ 415 if_attach(ifp); 416 ether_ifattach(ifp, enaddr); 417 #if NRND > 0 418 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 419 RND_TYPE_NET, 0); 420 #endif 421 422 #ifdef FXP_EVENT_COUNTERS 423 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 424 NULL, device_xname(&sc->sc_dev), "txstall"); 425 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 426 NULL, device_xname(&sc->sc_dev), "txintr"); 427 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 428 NULL, device_xname(&sc->sc_dev), "rxintr"); 429 if (sc->sc_rev >= FXP_REV_82558_A4) { 430 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 431 NULL, device_xname(&sc->sc_dev), "txpause"); 432 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 433 NULL, device_xname(&sc->sc_dev), "rxpause"); 434 } 435 #endif /* FXP_EVENT_COUNTERS */ 436 437 /* The attach is successful. */ 438 sc->sc_flags |= FXPF_ATTACHED; 439 440 return; 441 442 /* 443 * Free any resources we've allocated during the failed attach 444 * attempt. Do this in reverse order and fall though. 445 */ 446 fail_5: 447 for (i = 0; i < FXP_NRFABUFS; i++) { 448 if (sc->sc_rxmaps[i] != NULL) 449 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 450 } 451 fail_4: 452 for (i = 0; i < FXP_NTXCB; i++) { 453 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 454 bus_dmamap_destroy(sc->sc_dmat, 455 FXP_DSTX(sc, i)->txs_dmamap); 456 } 457 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 458 fail_3: 459 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 460 fail_2: 461 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 462 sizeof(struct fxp_control_data)); 463 fail_1: 464 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 465 fail_0: 466 return; 467 } 468 469 void 470 fxp_mii_initmedia(struct fxp_softc *sc) 471 { 472 int flags; 473 474 sc->sc_flags |= FXPF_MII; 475 476 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 477 sc->sc_mii.mii_readreg = fxp_mdi_read; 478 sc->sc_mii.mii_writereg = fxp_mdi_write; 479 sc->sc_mii.mii_statchg = fxp_statchg; 480 481 sc->sc_ethercom.ec_mii = &sc->sc_mii; 482 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 483 fxp_mii_mediastatus); 484 485 flags = MIIF_NOISOLATE; 486 if (sc->sc_rev >= FXP_REV_82558_A4) 487 flags |= MIIF_DOPAUSE; 488 /* 489 * The i82557 wedges if all of its PHYs are isolated! 490 */ 491 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 492 MII_OFFSET_ANY, flags); 493 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 495 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 496 } else 497 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 498 } 499 500 void 501 fxp_80c24_initmedia(struct fxp_softc *sc) 502 { 503 504 /* 505 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 506 * doesn't have a programming interface of any sort. The 507 * media is sensed automatically based on how the link partner 508 * is configured. This is, in essence, manual configuration. 509 */ 510 aprint_normal_dev(&sc->sc_dev, "Seeq 80c24 AutoDUPLEX media interface present\n"); 511 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 512 fxp_80c24_mediastatus); 513 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 514 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 515 } 516 517 /* 518 * Initialize the interface media. 519 */ 520 void 521 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 522 { 523 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 524 525 /* 526 * Reset to a stable state. 527 */ 528 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 529 DELAY(100); 530 531 sc->sc_eeprom_size = 0; 532 fxp_autosize_eeprom(sc); 533 if (sc->sc_eeprom_size == 0) { 534 aprint_error_dev(&sc->sc_dev, "failed to detect EEPROM size\n"); 535 sc->sc_eeprom_size = 6; /* XXX panic here? */ 536 } 537 #ifdef DEBUG 538 aprint_debug_dev(&sc->sc_dev, "detected %d word EEPROM\n", 539 1 << sc->sc_eeprom_size); 540 #endif 541 542 /* 543 * Get info about the primary PHY 544 */ 545 fxp_read_eeprom(sc, &data, 6, 1); 546 sc->phy_primary_device = 547 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 548 549 /* 550 * Read MAC address. 551 */ 552 fxp_read_eeprom(sc, myea, 0, 3); 553 enaddr[0] = myea[0] & 0xff; 554 enaddr[1] = myea[0] >> 8; 555 enaddr[2] = myea[1] & 0xff; 556 enaddr[3] = myea[1] >> 8; 557 enaddr[4] = myea[2] & 0xff; 558 enaddr[5] = myea[2] >> 8; 559 560 /* 561 * Systems based on the ICH2/ICH2-M chip from Intel, as well 562 * as some i82559 designs, have a defect where the chip can 563 * cause a PCI protocol violation if it receives a CU_RESUME 564 * command when it is entering the IDLE state. 565 * 566 * The work-around is to disable Dynamic Standby Mode, so that 567 * the chip never deasserts #CLKRUN, and always remains in the 568 * active state. 569 * 570 * Unfortunately, the only way to disable Dynamic Standby is 571 * to frob an EEPROM setting and reboot (the EEPROM setting 572 * is only consulted when the PCI bus comes out of reset). 573 * 574 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 575 */ 576 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 577 fxp_read_eeprom(sc, &data, 10, 1); 578 if (data & 0x02) { /* STB enable */ 579 aprint_error_dev(&sc->sc_dev, "WARNING: " 580 "Disabling dynamic standby mode in EEPROM " 581 "to work around a\n"); 582 aprint_normal_dev(&sc->sc_dev, 583 "WARNING: hardware bug. You must reset " 584 "the system before using this\n"); 585 aprint_normal_dev(&sc->sc_dev, "WARNING: interface.\n"); 586 data &= ~0x02; 587 fxp_write_eeprom(sc, &data, 10, 1); 588 aprint_normal_dev(&sc->sc_dev, "new EEPROM ID: 0x%04x\n", 589 data); 590 fxp_eeprom_update_cksum(sc); 591 } 592 } 593 594 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 595 /* Due to false positives we make it conditional on setting link1 */ 596 fxp_read_eeprom(sc, &data, 3, 1); 597 if ((data & 0x03) != 0x03) { 598 aprint_verbose_dev(&sc->sc_dev, "May need receiver lock-up workaround\n"); 599 } 600 } 601 602 static void 603 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 604 { 605 uint16_t reg; 606 int x; 607 608 for (x = 1 << (len - 1); x != 0; x >>= 1) { 609 DELAY(40); 610 if (data & x) 611 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 612 else 613 reg = FXP_EEPROM_EECS; 614 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 615 DELAY(40); 616 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 617 reg | FXP_EEPROM_EESK); 618 DELAY(40); 619 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 620 } 621 DELAY(40); 622 } 623 624 /* 625 * Figure out EEPROM size. 626 * 627 * 559's can have either 64-word or 256-word EEPROMs, the 558 628 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 629 * talks about the existence of 16 to 256 word EEPROMs. 630 * 631 * The only known sizes are 64 and 256, where the 256 version is used 632 * by CardBus cards to store CIS information. 633 * 634 * The address is shifted in msb-to-lsb, and after the last 635 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 636 * after which follows the actual data. We try to detect this zero, by 637 * probing the data-out bit in the EEPROM control register just after 638 * having shifted in a bit. If the bit is zero, we assume we've 639 * shifted enough address bits. The data-out should be tri-state, 640 * before this, which should translate to a logical one. 641 * 642 * Other ways to do this would be to try to read a register with known 643 * contents with a varying number of address bits, but no such 644 * register seem to be available. The high bits of register 10 are 01 645 * on the 558 and 559, but apparently not on the 557. 646 * 647 * The Linux driver computes a checksum on the EEPROM data, but the 648 * value of this checksum is not very well documented. 649 */ 650 651 void 652 fxp_autosize_eeprom(struct fxp_softc *sc) 653 { 654 int x; 655 656 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 657 DELAY(40); 658 659 /* Shift in read opcode. */ 660 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 661 662 /* 663 * Shift in address, wait for the dummy zero following a correct 664 * address shift. 665 */ 666 for (x = 1; x <= 8; x++) { 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 668 DELAY(40); 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 670 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 671 DELAY(40); 672 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 673 FXP_EEPROM_EEDO) == 0) 674 break; 675 DELAY(40); 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 677 DELAY(40); 678 } 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 680 DELAY(40); 681 if (x != 6 && x != 8) { 682 #ifdef DEBUG 683 printf("%s: strange EEPROM size (%d)\n", 684 device_xname(&sc->sc_dev), 1 << x); 685 #endif 686 } else 687 sc->sc_eeprom_size = x; 688 } 689 690 /* 691 * Read from the serial EEPROM. Basically, you manually shift in 692 * the read opcode (one bit at a time) and then shift in the address, 693 * and then you shift out the data (all of this one bit at a time). 694 * The word size is 16 bits, so you have to provide the address for 695 * every 16 bits of data. 696 */ 697 void 698 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 699 { 700 u_int16_t reg; 701 int i, x; 702 703 for (i = 0; i < words; i++) { 704 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 705 706 /* Shift in read opcode. */ 707 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 708 709 /* Shift in address. */ 710 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 711 712 reg = FXP_EEPROM_EECS; 713 data[i] = 0; 714 715 /* Shift out data. */ 716 for (x = 16; x > 0; x--) { 717 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 718 reg | FXP_EEPROM_EESK); 719 DELAY(40); 720 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 721 FXP_EEPROM_EEDO) 722 data[i] |= (1 << (x - 1)); 723 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 724 DELAY(40); 725 } 726 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 727 DELAY(40); 728 } 729 } 730 731 /* 732 * Write data to the serial EEPROM. 733 */ 734 void 735 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 736 { 737 int i, j; 738 739 for (i = 0; i < words; i++) { 740 /* Erase/write enable. */ 741 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 742 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 743 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 744 sc->sc_eeprom_size); 745 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 746 DELAY(4); 747 748 /* Shift in write opcode, address, data. */ 749 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 750 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 751 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 752 fxp_eeprom_shiftin(sc, data[i], 16); 753 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 754 DELAY(4); 755 756 /* Wait for the EEPROM to finish up. */ 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 758 DELAY(4); 759 for (j = 0; j < 1000; j++) { 760 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 761 FXP_EEPROM_EEDO) 762 break; 763 DELAY(50); 764 } 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 766 DELAY(4); 767 768 /* Erase/write disable. */ 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 770 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 771 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 772 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 773 DELAY(4); 774 } 775 } 776 777 /* 778 * Update the checksum of the EEPROM. 779 */ 780 void 781 fxp_eeprom_update_cksum(struct fxp_softc *sc) 782 { 783 int i; 784 uint16_t data, cksum; 785 786 cksum = 0; 787 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 788 fxp_read_eeprom(sc, &data, i, 1); 789 cksum += data; 790 } 791 i = (1 << sc->sc_eeprom_size) - 1; 792 cksum = 0xbaba - cksum; 793 fxp_read_eeprom(sc, &data, i, 1); 794 fxp_write_eeprom(sc, &cksum, i, 1); 795 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 796 device_xname(&sc->sc_dev), i, data, cksum); 797 } 798 799 /* 800 * Start packet transmission on the interface. 801 */ 802 void 803 fxp_start(struct ifnet *ifp) 804 { 805 struct fxp_softc *sc = ifp->if_softc; 806 struct mbuf *m0, *m; 807 struct fxp_txdesc *txd; 808 struct fxp_txsoft *txs; 809 bus_dmamap_t dmamap; 810 int error, lasttx, nexttx, opending, seg; 811 812 /* 813 * If we want a re-init, bail out now. 814 */ 815 if (sc->sc_flags & FXPF_WANTINIT) { 816 ifp->if_flags |= IFF_OACTIVE; 817 return; 818 } 819 820 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 821 return; 822 823 /* 824 * Remember the previous txpending and the current lasttx. 825 */ 826 opending = sc->sc_txpending; 827 lasttx = sc->sc_txlast; 828 829 /* 830 * Loop through the send queue, setting up transmit descriptors 831 * until we drain the queue, or use up all available transmit 832 * descriptors. 833 */ 834 for (;;) { 835 struct fxp_tbd *tbdp; 836 int csum_flags; 837 838 /* 839 * Grab a packet off the queue. 840 */ 841 IFQ_POLL(&ifp->if_snd, m0); 842 if (m0 == NULL) 843 break; 844 m = NULL; 845 846 if (sc->sc_txpending == FXP_NTXCB - 1) { 847 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 848 break; 849 } 850 851 /* 852 * Get the next available transmit descriptor. 853 */ 854 nexttx = FXP_NEXTTX(sc->sc_txlast); 855 txd = FXP_CDTX(sc, nexttx); 856 txs = FXP_DSTX(sc, nexttx); 857 dmamap = txs->txs_dmamap; 858 859 /* 860 * Load the DMA map. If this fails, the packet either 861 * didn't fit in the allotted number of frags, or we were 862 * short on resources. In this case, we'll copy and try 863 * again. 864 */ 865 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 866 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 867 MGETHDR(m, M_DONTWAIT, MT_DATA); 868 if (m == NULL) { 869 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 870 device_xname(&sc->sc_dev)); 871 break; 872 } 873 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 874 if (m0->m_pkthdr.len > MHLEN) { 875 MCLGET(m, M_DONTWAIT); 876 if ((m->m_flags & M_EXT) == 0) { 877 log(LOG_ERR, 878 "%s: unable to allocate Tx " 879 "cluster\n", device_xname(&sc->sc_dev)); 880 m_freem(m); 881 break; 882 } 883 } 884 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 885 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 886 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 887 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 888 if (error) { 889 log(LOG_ERR, "%s: unable to load Tx buffer, " 890 "error = %d\n", device_xname(&sc->sc_dev), error); 891 break; 892 } 893 } 894 895 IFQ_DEQUEUE(&ifp->if_snd, m0); 896 csum_flags = m0->m_pkthdr.csum_flags; 897 if (m != NULL) { 898 m_freem(m0); 899 m0 = m; 900 } 901 902 /* Initialize the fraglist. */ 903 tbdp = txd->txd_tbd; 904 if (sc->sc_flags & FXPF_IPCB) 905 tbdp++; 906 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 907 tbdp[seg].tb_addr = 908 htole32(dmamap->dm_segs[seg].ds_addr); 909 tbdp[seg].tb_size = 910 htole32(dmamap->dm_segs[seg].ds_len); 911 } 912 913 /* Sync the DMA map. */ 914 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 915 BUS_DMASYNC_PREWRITE); 916 917 /* 918 * Store a pointer to the packet so we can free it later. 919 */ 920 txs->txs_mbuf = m0; 921 922 /* 923 * Initialize the transmit descriptor. 924 */ 925 /* BIG_ENDIAN: no need to swap to store 0 */ 926 txd->txd_txcb.cb_status = 0; 927 txd->txd_txcb.cb_command = 928 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 929 txd->txd_txcb.tx_threshold = tx_threshold; 930 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 931 932 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 933 if (sc->sc_flags & FXPF_IPCB) { 934 struct m_tag *vtag; 935 struct fxp_ipcb *ipcb; 936 /* 937 * Deal with TCP/IP checksum offload. Note that 938 * in order for TCP checksum offload to work, 939 * the pseudo header checksum must have already 940 * been computed and stored in the checksum field 941 * in the TCP header. The stack should have 942 * already done this for us. 943 */ 944 ipcb = &txd->txd_u.txdu_ipcb; 945 memset(ipcb, 0, sizeof(*ipcb)); 946 /* 947 * always do hardware parsing. 948 */ 949 ipcb->ipcb_ip_activation_high = 950 FXP_IPCB_HARDWAREPARSING_ENABLE; 951 /* 952 * ip checksum offloading. 953 */ 954 if (csum_flags & M_CSUM_IPv4) { 955 ipcb->ipcb_ip_schedule |= 956 FXP_IPCB_IP_CHECKSUM_ENABLE; 957 } 958 /* 959 * TCP/UDP checksum offloading. 960 */ 961 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 962 ipcb->ipcb_ip_schedule |= 963 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 964 } 965 966 /* 967 * request VLAN tag insertion if needed. 968 */ 969 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 970 if (vtag) { 971 ipcb->ipcb_vlan_id = 972 htobe16(*(u_int *)(vtag + 1)); 973 ipcb->ipcb_ip_activation_high |= 974 FXP_IPCB_INSERTVLAN_ENABLE; 975 } 976 } else { 977 KASSERT((csum_flags & 978 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 979 } 980 981 FXP_CDTXSYNC(sc, nexttx, 982 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 983 984 /* Advance the tx pointer. */ 985 sc->sc_txpending++; 986 sc->sc_txlast = nexttx; 987 988 #if NBPFILTER > 0 989 /* 990 * Pass packet to bpf if there is a listener. 991 */ 992 if (ifp->if_bpf) 993 bpf_mtap(ifp->if_bpf, m0); 994 #endif 995 } 996 997 if (sc->sc_txpending == FXP_NTXCB - 1) { 998 /* No more slots; notify upper layer. */ 999 ifp->if_flags |= IFF_OACTIVE; 1000 } 1001 1002 if (sc->sc_txpending != opending) { 1003 /* 1004 * We enqueued packets. If the transmitter was idle, 1005 * reset the txdirty pointer. 1006 */ 1007 if (opending == 0) 1008 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1009 1010 /* 1011 * Cause the chip to interrupt and suspend command 1012 * processing once the last packet we've enqueued 1013 * has been transmitted. 1014 * 1015 * To avoid a race between updating status bits 1016 * by the fxp chip and clearing command bits 1017 * by this function on machines which don't have 1018 * atomic methods to clear/set bits in memory 1019 * smaller than 32bits (both cb_status and cb_command 1020 * members are uint16_t and in the same 32bit word), 1021 * we have to prepare a dummy TX descriptor which has 1022 * NOP command and just causes a TX completion interrupt. 1023 */ 1024 sc->sc_txpending++; 1025 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1026 txd = FXP_CDTX(sc, sc->sc_txlast); 1027 /* BIG_ENDIAN: no need to swap to store 0 */ 1028 txd->txd_txcb.cb_status = 0; 1029 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1030 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1031 FXP_CDTXSYNC(sc, sc->sc_txlast, 1032 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1033 1034 /* 1035 * The entire packet chain is set up. Clear the suspend bit 1036 * on the command prior to the first packet we set up. 1037 */ 1038 FXP_CDTXSYNC(sc, lasttx, 1039 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1040 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1041 htole16(~FXP_CB_COMMAND_S); 1042 FXP_CDTXSYNC(sc, lasttx, 1043 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1044 1045 /* 1046 * Issue a Resume command in case the chip was suspended. 1047 */ 1048 fxp_scb_wait(sc); 1049 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1050 1051 /* Set a watchdog timer in case the chip flakes out. */ 1052 ifp->if_timer = 5; 1053 } 1054 } 1055 1056 /* 1057 * Process interface interrupts. 1058 */ 1059 int 1060 fxp_intr(void *arg) 1061 { 1062 struct fxp_softc *sc = arg; 1063 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1064 bus_dmamap_t rxmap; 1065 int claimed = 0, rnr; 1066 u_int8_t statack; 1067 1068 if (!device_is_active(&sc->sc_dev) || sc->sc_enabled == 0) 1069 return (0); 1070 /* 1071 * If the interface isn't running, don't try to 1072 * service the interrupt.. just ack it and bail. 1073 */ 1074 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1075 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1076 if (statack) { 1077 claimed = 1; 1078 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1079 } 1080 return (claimed); 1081 } 1082 1083 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1084 claimed = 1; 1085 1086 /* 1087 * First ACK all the interrupts in this pass. 1088 */ 1089 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1090 1091 /* 1092 * Process receiver interrupts. If a no-resource (RNR) 1093 * condition exists, get whatever packets we can and 1094 * re-start the receiver. 1095 */ 1096 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1097 1 : 0; 1098 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1099 FXP_SCB_STATACK_SWI)) { 1100 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1101 rnr |= fxp_rxintr(sc); 1102 } 1103 1104 /* 1105 * Free any finished transmit mbuf chains. 1106 */ 1107 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1108 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1109 fxp_txintr(sc); 1110 1111 /* 1112 * Try to get more packets going. 1113 */ 1114 fxp_start(ifp); 1115 1116 if (sc->sc_txpending == 0) { 1117 /* 1118 * If we want a re-init, do that now. 1119 */ 1120 if (sc->sc_flags & FXPF_WANTINIT) 1121 (void) fxp_init(ifp); 1122 } 1123 } 1124 1125 if (rnr) { 1126 fxp_scb_wait(sc); 1127 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1128 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1129 fxp_scb_wait(sc); 1130 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1131 rxmap->dm_segs[0].ds_addr + 1132 RFA_ALIGNMENT_FUDGE); 1133 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1134 } 1135 } 1136 1137 #if NRND > 0 1138 if (claimed) 1139 rnd_add_uint32(&sc->rnd_source, statack); 1140 #endif 1141 return (claimed); 1142 } 1143 1144 /* 1145 * Handle transmit completion interrupts. 1146 */ 1147 void 1148 fxp_txintr(struct fxp_softc *sc) 1149 { 1150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1151 struct fxp_txdesc *txd; 1152 struct fxp_txsoft *txs; 1153 int i; 1154 u_int16_t txstat; 1155 1156 ifp->if_flags &= ~IFF_OACTIVE; 1157 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1158 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1159 txd = FXP_CDTX(sc, i); 1160 txs = FXP_DSTX(sc, i); 1161 1162 FXP_CDTXSYNC(sc, i, 1163 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1164 1165 /* skip dummy NOP TX descriptor */ 1166 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1167 == FXP_CB_COMMAND_NOP) 1168 continue; 1169 1170 txstat = le16toh(txd->txd_txcb.cb_status); 1171 1172 if ((txstat & FXP_CB_STATUS_C) == 0) 1173 break; 1174 1175 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1176 0, txs->txs_dmamap->dm_mapsize, 1177 BUS_DMASYNC_POSTWRITE); 1178 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1179 m_freem(txs->txs_mbuf); 1180 txs->txs_mbuf = NULL; 1181 } 1182 1183 /* Update the dirty transmit buffer pointer. */ 1184 sc->sc_txdirty = i; 1185 1186 /* 1187 * Cancel the watchdog timer if there are no pending 1188 * transmissions. 1189 */ 1190 if (sc->sc_txpending == 0) 1191 ifp->if_timer = 0; 1192 } 1193 1194 /* 1195 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1196 */ 1197 1198 int 1199 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1200 { 1201 u_int16_t rxparsestat; 1202 u_int16_t csum_stat; 1203 u_int32_t csum_data; 1204 int csum_flags; 1205 1206 /* 1207 * check VLAN tag stripping. 1208 */ 1209 1210 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1211 struct m_tag *vtag; 1212 1213 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1214 if (vtag == NULL) 1215 return ENOMEM; 1216 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1217 m_tag_prepend(m, vtag); 1218 } 1219 1220 /* 1221 * check H/W Checksumming. 1222 */ 1223 1224 csum_stat = le16toh(rfa->cksum_stat); 1225 rxparsestat = le16toh(rfa->rx_parse_stat); 1226 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1227 return 0; 1228 1229 csum_flags = 0; 1230 csum_data = 0; 1231 1232 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1233 csum_flags = M_CSUM_IPv4; 1234 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1235 csum_flags |= M_CSUM_IPv4_BAD; 1236 } 1237 1238 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1239 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1240 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1241 csum_flags |= M_CSUM_TCP_UDP_BAD; 1242 } 1243 1244 m->m_pkthdr.csum_flags = csum_flags; 1245 m->m_pkthdr.csum_data = csum_data; 1246 1247 return 0; 1248 } 1249 1250 /* 1251 * Handle receive interrupts. 1252 */ 1253 int 1254 fxp_rxintr(struct fxp_softc *sc) 1255 { 1256 struct ethercom *ec = &sc->sc_ethercom; 1257 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1258 struct mbuf *m, *m0; 1259 bus_dmamap_t rxmap; 1260 struct fxp_rfa *rfa; 1261 int rnr; 1262 u_int16_t len, rxstat; 1263 1264 rnr = 0; 1265 1266 for (;;) { 1267 m = sc->sc_rxq.ifq_head; 1268 rfa = FXP_MTORFA(m); 1269 rxmap = M_GETCTX(m, bus_dmamap_t); 1270 1271 FXP_RFASYNC(sc, m, 1272 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1273 1274 rxstat = le16toh(rfa->rfa_status); 1275 1276 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1277 rnr = 1; 1278 1279 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1280 /* 1281 * We have processed all of the 1282 * receive buffers. 1283 */ 1284 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1285 return rnr; 1286 } 1287 1288 IF_DEQUEUE(&sc->sc_rxq, m); 1289 1290 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1291 1292 len = le16toh(rfa->actual_size) & 1293 (m->m_ext.ext_size - 1); 1294 1295 if (len < sizeof(struct ether_header)) { 1296 /* 1297 * Runt packet; drop it now. 1298 */ 1299 FXP_INIT_RFABUF(sc, m); 1300 continue; 1301 } 1302 1303 /* 1304 * If support for 802.1Q VLAN sized frames is 1305 * enabled, we need to do some additional error 1306 * checking (as we are saving bad frames, in 1307 * order to receive the larger ones). 1308 */ 1309 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1310 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1311 FXP_RFA_STATUS_RNR| 1312 FXP_RFA_STATUS_ALIGN| 1313 FXP_RFA_STATUS_CRC)) != 0) { 1314 FXP_INIT_RFABUF(sc, m); 1315 continue; 1316 } 1317 1318 /* Do checksum checking. */ 1319 m->m_pkthdr.csum_flags = 0; 1320 if (sc->sc_flags & FXPF_EXT_RFA) 1321 if (fxp_rx_hwcksum(m, rfa)) 1322 goto dropit; 1323 1324 /* 1325 * If the packet is small enough to fit in a 1326 * single header mbuf, allocate one and copy 1327 * the data into it. This greatly reduces 1328 * memory consumption when we receive lots 1329 * of small packets. 1330 * 1331 * Otherwise, we add a new buffer to the receive 1332 * chain. If this fails, we drop the packet and 1333 * recycle the old buffer. 1334 */ 1335 if (fxp_copy_small != 0 && len <= MHLEN) { 1336 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1337 if (m0 == NULL) 1338 goto dropit; 1339 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1340 memcpy(mtod(m0, void *), 1341 mtod(m, void *), len); 1342 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1343 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1344 FXP_INIT_RFABUF(sc, m); 1345 m = m0; 1346 } else { 1347 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1348 dropit: 1349 ifp->if_ierrors++; 1350 FXP_INIT_RFABUF(sc, m); 1351 continue; 1352 } 1353 } 1354 1355 m->m_pkthdr.rcvif = ifp; 1356 m->m_pkthdr.len = m->m_len = len; 1357 1358 #if NBPFILTER > 0 1359 /* 1360 * Pass this up to any BPF listeners, but only 1361 * pass it up the stack if it's for us. 1362 */ 1363 if (ifp->if_bpf) 1364 bpf_mtap(ifp->if_bpf, m); 1365 #endif 1366 1367 /* Pass it on. */ 1368 (*ifp->if_input)(ifp, m); 1369 } 1370 } 1371 1372 /* 1373 * Update packet in/out/collision statistics. The i82557 doesn't 1374 * allow you to access these counters without doing a fairly 1375 * expensive DMA to get _all_ of the statistics it maintains, so 1376 * we do this operation here only once per second. The statistics 1377 * counters in the kernel are updated from the previous dump-stats 1378 * DMA and then a new dump-stats DMA is started. The on-chip 1379 * counters are zeroed when the DMA completes. If we can't start 1380 * the DMA immediately, we don't wait - we just prepare to read 1381 * them again next time. 1382 */ 1383 void 1384 fxp_tick(void *arg) 1385 { 1386 struct fxp_softc *sc = arg; 1387 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1388 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1389 int s; 1390 1391 if (!device_is_active(&sc->sc_dev)) 1392 return; 1393 1394 s = splnet(); 1395 1396 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1397 1398 ifp->if_opackets += le32toh(sp->tx_good); 1399 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1400 if (sp->rx_good) { 1401 ifp->if_ipackets += le32toh(sp->rx_good); 1402 sc->sc_rxidle = 0; 1403 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1404 sc->sc_rxidle++; 1405 } 1406 ifp->if_ierrors += 1407 le32toh(sp->rx_crc_errors) + 1408 le32toh(sp->rx_alignment_errors) + 1409 le32toh(sp->rx_rnr_errors) + 1410 le32toh(sp->rx_overrun_errors); 1411 /* 1412 * If any transmit underruns occurred, bump up the transmit 1413 * threshold by another 512 bytes (64 * 8). 1414 */ 1415 if (sp->tx_underruns) { 1416 ifp->if_oerrors += le32toh(sp->tx_underruns); 1417 if (tx_threshold < 192) 1418 tx_threshold += 64; 1419 } 1420 #ifdef FXP_EVENT_COUNTERS 1421 if (sc->sc_rev >= FXP_REV_82558_A4) { 1422 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1423 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1424 } 1425 #endif 1426 1427 /* 1428 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1429 * then assume the receiver has locked up and attempt to clear 1430 * the condition by reprogramming the multicast filter (actually, 1431 * resetting the interface). This is a work-around for a bug in 1432 * the 82557 where the receiver locks up if it gets certain types 1433 * of garbage in the synchronization bits prior to the packet header. 1434 * This bug is supposed to only occur in 10Mbps mode, but has been 1435 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1436 * speed transition). 1437 */ 1438 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1439 (void) fxp_init(ifp); 1440 splx(s); 1441 return; 1442 } 1443 /* 1444 * If there is no pending command, start another stats 1445 * dump. Otherwise punt for now. 1446 */ 1447 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1448 /* 1449 * Start another stats dump. 1450 */ 1451 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1452 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1453 } else { 1454 /* 1455 * A previous command is still waiting to be accepted. 1456 * Just zero our copy of the stats and wait for the 1457 * next timer event to update them. 1458 */ 1459 /* BIG_ENDIAN: no swap required to store 0 */ 1460 sp->tx_good = 0; 1461 sp->tx_underruns = 0; 1462 sp->tx_total_collisions = 0; 1463 1464 sp->rx_good = 0; 1465 sp->rx_crc_errors = 0; 1466 sp->rx_alignment_errors = 0; 1467 sp->rx_rnr_errors = 0; 1468 sp->rx_overrun_errors = 0; 1469 if (sc->sc_rev >= FXP_REV_82558_A4) { 1470 sp->tx_pauseframes = 0; 1471 sp->rx_pauseframes = 0; 1472 } 1473 } 1474 1475 if (sc->sc_flags & FXPF_MII) { 1476 /* Tick the MII clock. */ 1477 mii_tick(&sc->sc_mii); 1478 } 1479 1480 splx(s); 1481 1482 /* 1483 * Schedule another timeout one second from now. 1484 */ 1485 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1486 } 1487 1488 /* 1489 * Drain the receive queue. 1490 */ 1491 void 1492 fxp_rxdrain(struct fxp_softc *sc) 1493 { 1494 bus_dmamap_t rxmap; 1495 struct mbuf *m; 1496 1497 for (;;) { 1498 IF_DEQUEUE(&sc->sc_rxq, m); 1499 if (m == NULL) 1500 break; 1501 rxmap = M_GETCTX(m, bus_dmamap_t); 1502 bus_dmamap_unload(sc->sc_dmat, rxmap); 1503 FXP_RXMAP_PUT(sc, rxmap); 1504 m_freem(m); 1505 } 1506 } 1507 1508 /* 1509 * Stop the interface. Cancels the statistics updater and resets 1510 * the interface. 1511 */ 1512 void 1513 fxp_stop(struct ifnet *ifp, int disable) 1514 { 1515 struct fxp_softc *sc = ifp->if_softc; 1516 struct fxp_txsoft *txs; 1517 int i; 1518 1519 /* 1520 * Turn down interface (done early to avoid bad interactions 1521 * between panics, shutdown hooks, and the watchdog timer) 1522 */ 1523 ifp->if_timer = 0; 1524 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1525 1526 /* 1527 * Cancel stats updater. 1528 */ 1529 callout_stop(&sc->sc_callout); 1530 if (sc->sc_flags & FXPF_MII) { 1531 /* Down the MII. */ 1532 mii_down(&sc->sc_mii); 1533 } 1534 1535 /* 1536 * Issue software reset. This unloads any microcode that 1537 * might already be loaded. 1538 */ 1539 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1540 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1541 DELAY(50); 1542 1543 /* 1544 * Release any xmit buffers. 1545 */ 1546 for (i = 0; i < FXP_NTXCB; i++) { 1547 txs = FXP_DSTX(sc, i); 1548 if (txs->txs_mbuf != NULL) { 1549 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1550 m_freem(txs->txs_mbuf); 1551 txs->txs_mbuf = NULL; 1552 } 1553 } 1554 sc->sc_txpending = 0; 1555 1556 if (disable) { 1557 fxp_rxdrain(sc); 1558 fxp_disable(sc); 1559 } 1560 1561 } 1562 1563 /* 1564 * Watchdog/transmission transmit timeout handler. Called when a 1565 * transmission is started on the interface, but no interrupt is 1566 * received before the timeout. This usually indicates that the 1567 * card has wedged for some reason. 1568 */ 1569 void 1570 fxp_watchdog(struct ifnet *ifp) 1571 { 1572 struct fxp_softc *sc = ifp->if_softc; 1573 1574 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1575 ifp->if_oerrors++; 1576 1577 (void) fxp_init(ifp); 1578 } 1579 1580 /* 1581 * Initialize the interface. Must be called at splnet(). 1582 */ 1583 int 1584 fxp_init(struct ifnet *ifp) 1585 { 1586 struct fxp_softc *sc = ifp->if_softc; 1587 struct fxp_cb_config *cbp; 1588 struct fxp_cb_ias *cb_ias; 1589 struct fxp_txdesc *txd; 1590 bus_dmamap_t rxmap; 1591 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1592 1593 if ((error = fxp_enable(sc)) != 0) 1594 goto out; 1595 1596 /* 1597 * Cancel any pending I/O 1598 */ 1599 fxp_stop(ifp, 0); 1600 1601 /* 1602 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1603 * flag, and this prevents the MII from detaching resulting in 1604 * a panic. The flags field should perhaps be split in runtime 1605 * flags and more static information. For now, just clear the 1606 * only other flag set. 1607 */ 1608 1609 sc->sc_flags &= ~FXPF_WANTINIT; 1610 1611 /* 1612 * Initialize base of CBL and RFA memory. Loading with zero 1613 * sets it up for regular linear addressing. 1614 */ 1615 fxp_scb_wait(sc); 1616 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1617 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1618 1619 fxp_scb_wait(sc); 1620 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1621 1622 /* 1623 * Initialize the multicast filter. Do this now, since we might 1624 * have to setup the config block differently. 1625 */ 1626 fxp_mc_setup(sc); 1627 1628 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1629 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1630 1631 /* 1632 * In order to support receiving 802.1Q VLAN frames, we have to 1633 * enable "save bad frames", since they are 4 bytes larger than 1634 * the normal Ethernet maximum frame length. On i82558 and later, 1635 * we have a better mechanism for this. 1636 */ 1637 save_bf = 0; 1638 lrxen = 0; 1639 vlan_drop = 0; 1640 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1641 if (sc->sc_rev < FXP_REV_82558_A4) 1642 save_bf = 1; 1643 else 1644 lrxen = 1; 1645 if (sc->sc_rev >= FXP_REV_82550) 1646 vlan_drop = 1; 1647 } 1648 1649 /* 1650 * Initialize base of dump-stats buffer. 1651 */ 1652 fxp_scb_wait(sc); 1653 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1654 sc->sc_cddma + FXP_CDSTATSOFF); 1655 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1656 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1657 1658 cbp = &sc->sc_control_data->fcd_configcb; 1659 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1660 1661 /* 1662 * Load microcode for this controller. 1663 */ 1664 fxp_load_ucode(sc); 1665 1666 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1667 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1668 else 1669 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1670 1671 /* 1672 * This copy is kind of disgusting, but there are a bunch of must be 1673 * zero and must be one bits in this structure and this is the easiest 1674 * way to initialize them all to proper values. 1675 */ 1676 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1677 1678 /* BIG_ENDIAN: no need to swap to store 0 */ 1679 cbp->cb_status = 0; 1680 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1681 FXP_CB_COMMAND_EL); 1682 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1683 cbp->link_addr = 0xffffffff; /* (no) next command */ 1684 /* bytes in config block */ 1685 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1686 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1687 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1688 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1689 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1690 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1691 cbp->type_enable = 0; /* actually reserved */ 1692 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1693 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1694 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1695 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1696 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1697 cbp->late_scb = 0; /* (don't) defer SCB update */ 1698 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1699 cbp->ci_int = 1; /* interrupt on CU idle */ 1700 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1701 cbp->ext_stats_dis = 1; /* disable extended counters */ 1702 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1703 cbp->save_bf = save_bf;/* save bad frames */ 1704 cbp->disc_short_rx = !prm; /* discard short packets */ 1705 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1706 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1707 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1708 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1709 /* interface mode */ 1710 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1711 cbp->csma_dis = 0; /* (don't) disable link */ 1712 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1713 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1714 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1715 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1716 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1717 cbp->nsai = 1; /* (don't) disable source addr insert */ 1718 cbp->preamble_length = 2; /* (7 byte) preamble */ 1719 cbp->loopback = 0; /* (don't) loopback */ 1720 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1721 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1722 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1723 cbp->promiscuous = prm; /* promiscuous mode */ 1724 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1725 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1726 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1727 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1728 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1729 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1730 cbp->padding = 1; /* (do) pad short tx packets */ 1731 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1732 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1733 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1734 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1735 /* must set wake_en in PMCSR also */ 1736 cbp->force_fdx = 0; /* (don't) force full duplex */ 1737 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1738 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1739 cbp->mc_all = allm; /* accept all multicasts */ 1740 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1741 cbp->vlan_drop_en = vlan_drop; 1742 1743 if (sc->sc_rev < FXP_REV_82558_A4) { 1744 /* 1745 * The i82557 has no hardware flow control, the values 1746 * here are the defaults for the chip. 1747 */ 1748 cbp->fc_delay_lsb = 0; 1749 cbp->fc_delay_msb = 0x40; 1750 cbp->pri_fc_thresh = 3; 1751 cbp->tx_fc_dis = 0; 1752 cbp->rx_fc_restop = 0; 1753 cbp->rx_fc_restart = 0; 1754 cbp->fc_filter = 0; 1755 cbp->pri_fc_loc = 1; 1756 } else { 1757 cbp->fc_delay_lsb = 0x1f; 1758 cbp->fc_delay_msb = 0x01; 1759 cbp->pri_fc_thresh = 3; 1760 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1761 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1762 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1763 cbp->fc_filter = !prm; /* drop FC frames to host */ 1764 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1765 cbp->ext_stats_dis = 0; /* enable extended stats */ 1766 } 1767 1768 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1769 1770 /* 1771 * Start the config command/DMA. 1772 */ 1773 fxp_scb_wait(sc); 1774 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1775 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1776 /* ...and wait for it to complete. */ 1777 i = 1000; 1778 do { 1779 FXP_CDCONFIGSYNC(sc, 1780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1781 DELAY(1); 1782 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1783 if (i == 0) { 1784 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1785 device_xname(&sc->sc_dev), __LINE__); 1786 return (ETIMEDOUT); 1787 } 1788 1789 /* 1790 * Initialize the station address. 1791 */ 1792 cb_ias = &sc->sc_control_data->fcd_iascb; 1793 /* BIG_ENDIAN: no need to swap to store 0 */ 1794 cb_ias->cb_status = 0; 1795 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1796 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1797 cb_ias->link_addr = 0xffffffff; 1798 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1799 1800 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1801 1802 /* 1803 * Start the IAS (Individual Address Setup) command/DMA. 1804 */ 1805 fxp_scb_wait(sc); 1806 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1807 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1808 /* ...and wait for it to complete. */ 1809 i = 1000; 1810 do { 1811 FXP_CDIASSYNC(sc, 1812 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1813 DELAY(1); 1814 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1815 if (i == 0) { 1816 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1817 device_xname(&sc->sc_dev), __LINE__); 1818 return (ETIMEDOUT); 1819 } 1820 1821 /* 1822 * Initialize the transmit descriptor ring. txlast is initialized 1823 * to the end of the list so that it will wrap around to the first 1824 * descriptor when the first packet is transmitted. 1825 */ 1826 for (i = 0; i < FXP_NTXCB; i++) { 1827 txd = FXP_CDTX(sc, i); 1828 memset(txd, 0, sizeof(*txd)); 1829 txd->txd_txcb.cb_command = 1830 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1831 txd->txd_txcb.link_addr = 1832 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1833 if (sc->sc_flags & FXPF_EXT_TXCB) 1834 txd->txd_txcb.tbd_array_addr = 1835 htole32(FXP_CDTBDADDR(sc, i) + 1836 (2 * sizeof(struct fxp_tbd))); 1837 else 1838 txd->txd_txcb.tbd_array_addr = 1839 htole32(FXP_CDTBDADDR(sc, i)); 1840 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1841 } 1842 sc->sc_txpending = 0; 1843 sc->sc_txdirty = 0; 1844 sc->sc_txlast = FXP_NTXCB - 1; 1845 1846 /* 1847 * Initialize the receive buffer list. 1848 */ 1849 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1850 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1851 rxmap = FXP_RXMAP_GET(sc); 1852 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1853 log(LOG_ERR, "%s: unable to allocate or map rx " 1854 "buffer %d, error = %d\n", 1855 device_xname(&sc->sc_dev), 1856 sc->sc_rxq.ifq_len, error); 1857 /* 1858 * XXX Should attempt to run with fewer receive 1859 * XXX buffers instead of just failing. 1860 */ 1861 FXP_RXMAP_PUT(sc, rxmap); 1862 fxp_rxdrain(sc); 1863 goto out; 1864 } 1865 } 1866 sc->sc_rxidle = 0; 1867 1868 /* 1869 * Give the transmit ring to the chip. We do this by pointing 1870 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1871 * issuing a start command. It will execute the NOP and then 1872 * suspend, pointing at the first descriptor. 1873 */ 1874 fxp_scb_wait(sc); 1875 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1876 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1877 1878 /* 1879 * Initialize receiver buffer area - RFA. 1880 */ 1881 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1882 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1883 fxp_scb_wait(sc); 1884 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1885 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1886 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1887 #endif 1888 1889 if (sc->sc_flags & FXPF_MII) { 1890 /* 1891 * Set current media. 1892 */ 1893 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1894 goto out; 1895 } 1896 1897 /* 1898 * ...all done! 1899 */ 1900 ifp->if_flags |= IFF_RUNNING; 1901 ifp->if_flags &= ~IFF_OACTIVE; 1902 1903 /* 1904 * Request a software generated interrupt that will be used to 1905 * (re)start the RU processing. If we direct the chip to start 1906 * receiving from the start of queue now, instead of letting the 1907 * interrupt handler first process all received packets, we run 1908 * the risk of having it overwrite mbuf clusters while they are 1909 * being processed or after they have been returned to the pool. 1910 */ 1911 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1912 1913 /* 1914 * Start the one second timer. 1915 */ 1916 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1917 1918 /* 1919 * Attempt to start output on the interface. 1920 */ 1921 fxp_start(ifp); 1922 1923 out: 1924 if (error) { 1925 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1926 ifp->if_timer = 0; 1927 log(LOG_ERR, "%s: interface not running\n", 1928 device_xname(&sc->sc_dev)); 1929 } 1930 return (error); 1931 } 1932 1933 /* 1934 * Notify the world which media we're using. 1935 */ 1936 void 1937 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1938 { 1939 struct fxp_softc *sc = ifp->if_softc; 1940 1941 if (sc->sc_enabled == 0) { 1942 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1943 ifmr->ifm_status = 0; 1944 return; 1945 } 1946 1947 ether_mediastatus(ifp, ifmr); 1948 1949 /* 1950 * XXX Flow control is always turned on if the chip supports 1951 * XXX it; we can't easily control it dynamically, since it 1952 * XXX requires sending a setup packet. 1953 */ 1954 if (sc->sc_rev >= FXP_REV_82558_A4) 1955 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1956 } 1957 1958 int 1959 fxp_80c24_mediachange(struct ifnet *ifp) 1960 { 1961 1962 /* Nothing to do here. */ 1963 return (0); 1964 } 1965 1966 void 1967 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1968 { 1969 struct fxp_softc *sc = ifp->if_softc; 1970 1971 /* 1972 * Media is currently-selected media. We cannot determine 1973 * the link status. 1974 */ 1975 ifmr->ifm_status = 0; 1976 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1977 } 1978 1979 /* 1980 * Add a buffer to the end of the RFA buffer list. 1981 * Return 0 if successful, error code on failure. 1982 * 1983 * The RFA struct is stuck at the beginning of mbuf cluster and the 1984 * data pointer is fixed up to point just past it. 1985 */ 1986 int 1987 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1988 { 1989 struct mbuf *m; 1990 int error; 1991 1992 MGETHDR(m, M_DONTWAIT, MT_DATA); 1993 if (m == NULL) 1994 return (ENOBUFS); 1995 1996 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1997 MCLGET(m, M_DONTWAIT); 1998 if ((m->m_flags & M_EXT) == 0) { 1999 m_freem(m); 2000 return (ENOBUFS); 2001 } 2002 2003 if (unload) 2004 bus_dmamap_unload(sc->sc_dmat, rxmap); 2005 2006 M_SETCTX(m, rxmap); 2007 2008 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2009 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2010 BUS_DMA_READ|BUS_DMA_NOWAIT); 2011 if (error) { 2012 /* XXX XXX XXX */ 2013 aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2014 sc->sc_rxq.ifq_len, error); 2015 panic("fxp_add_rfabuf"); 2016 } 2017 2018 FXP_INIT_RFABUF(sc, m); 2019 2020 return (0); 2021 } 2022 2023 int 2024 fxp_mdi_read(struct device *self, int phy, int reg) 2025 { 2026 struct fxp_softc *sc = (struct fxp_softc *)self; 2027 int count = 10000; 2028 int value; 2029 2030 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2031 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2032 2033 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2034 0x10000000) == 0 && count--) 2035 DELAY(10); 2036 2037 if (count <= 0) 2038 log(LOG_WARNING, 2039 "%s: fxp_mdi_read: timed out\n", device_xname(&sc->sc_dev)); 2040 2041 return (value & 0xffff); 2042 } 2043 2044 void 2045 fxp_statchg(struct device *self) 2046 { 2047 2048 /* Nothing to do. */ 2049 } 2050 2051 void 2052 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2053 { 2054 struct fxp_softc *sc = (struct fxp_softc *)self; 2055 int count = 10000; 2056 2057 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2058 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2059 (value & 0xffff)); 2060 2061 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2062 count--) 2063 DELAY(10); 2064 2065 if (count <= 0) 2066 log(LOG_WARNING, 2067 "%s: fxp_mdi_write: timed out\n", device_xname(&sc->sc_dev)); 2068 } 2069 2070 int 2071 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2072 { 2073 struct fxp_softc *sc = ifp->if_softc; 2074 struct ifreq *ifr = (struct ifreq *)data; 2075 int s, error; 2076 2077 s = splnet(); 2078 2079 switch (cmd) { 2080 case SIOCSIFMEDIA: 2081 case SIOCGIFMEDIA: 2082 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2083 break; 2084 2085 default: 2086 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2087 break; 2088 2089 error = 0; 2090 2091 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2092 ; 2093 else if (ifp->if_flags & IFF_RUNNING) { 2094 /* 2095 * Multicast list has changed; set the 2096 * hardware filter accordingly. 2097 */ 2098 if (sc->sc_txpending) { 2099 sc->sc_flags |= FXPF_WANTINIT; 2100 } else 2101 error = fxp_init(ifp); 2102 } 2103 break; 2104 } 2105 2106 /* Try to get more packets going. */ 2107 if (sc->sc_enabled) 2108 fxp_start(ifp); 2109 2110 splx(s); 2111 return (error); 2112 } 2113 2114 /* 2115 * Program the multicast filter. 2116 * 2117 * This function must be called at splnet(). 2118 */ 2119 void 2120 fxp_mc_setup(struct fxp_softc *sc) 2121 { 2122 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2124 struct ethercom *ec = &sc->sc_ethercom; 2125 struct ether_multi *enm; 2126 struct ether_multistep step; 2127 int count, nmcasts; 2128 2129 #ifdef DIAGNOSTIC 2130 if (sc->sc_txpending) 2131 panic("fxp_mc_setup: pending transmissions"); 2132 #endif 2133 2134 ifp->if_flags &= ~IFF_ALLMULTI; 2135 2136 /* 2137 * Initialize multicast setup descriptor. 2138 */ 2139 nmcasts = 0; 2140 ETHER_FIRST_MULTI(step, ec, enm); 2141 while (enm != NULL) { 2142 /* 2143 * Check for too many multicast addresses or if we're 2144 * listening to a range. Either way, we simply have 2145 * to accept all multicasts. 2146 */ 2147 if (nmcasts >= MAXMCADDR || 2148 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2149 ETHER_ADDR_LEN) != 0) { 2150 /* 2151 * Callers of this function must do the 2152 * right thing with this. If we're called 2153 * from outside fxp_init(), the caller must 2154 * detect if the state if IFF_ALLMULTI changes. 2155 * If it does, the caller must then call 2156 * fxp_init(), since allmulti is handled by 2157 * the config block. 2158 */ 2159 ifp->if_flags |= IFF_ALLMULTI; 2160 return; 2161 } 2162 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2163 ETHER_ADDR_LEN); 2164 nmcasts++; 2165 ETHER_NEXT_MULTI(step, enm); 2166 } 2167 2168 /* BIG_ENDIAN: no need to swap to store 0 */ 2169 mcsp->cb_status = 0; 2170 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2171 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2172 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2173 2174 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2175 2176 /* 2177 * Wait until the command unit is not active. This should never 2178 * happen since nothing is queued, but make sure anyway. 2179 */ 2180 count = 100; 2181 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2182 FXP_SCB_CUS_ACTIVE && --count) 2183 DELAY(1); 2184 if (count == 0) { 2185 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2186 device_xname(&sc->sc_dev), __LINE__); 2187 return; 2188 } 2189 2190 /* 2191 * Start the multicast setup command/DMA. 2192 */ 2193 fxp_scb_wait(sc); 2194 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2195 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2196 2197 /* ...and wait for it to complete. */ 2198 count = 1000; 2199 do { 2200 FXP_CDMCSSYNC(sc, 2201 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2202 DELAY(1); 2203 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2204 if (count == 0) { 2205 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2206 device_xname(&sc->sc_dev), __LINE__); 2207 return; 2208 } 2209 } 2210 2211 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2212 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2213 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2214 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2215 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2216 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2217 2218 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2219 2220 static const struct ucode { 2221 int32_t revision; 2222 const uint32_t *ucode; 2223 size_t length; 2224 uint16_t int_delay_offset; 2225 uint16_t bundle_max_offset; 2226 } ucode_table[] = { 2227 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2228 D101_CPUSAVER_DWORD, 0 }, 2229 2230 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2231 D101_CPUSAVER_DWORD, 0 }, 2232 2233 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2234 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2235 2236 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2237 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2238 2239 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2240 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2241 2242 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2243 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2244 2245 { 0, NULL, 0, 0, 0 } 2246 }; 2247 2248 void 2249 fxp_load_ucode(struct fxp_softc *sc) 2250 { 2251 const struct ucode *uc; 2252 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2253 int count, i; 2254 2255 if (sc->sc_flags & FXPF_UCODE_LOADED) 2256 return; 2257 2258 /* 2259 * Only load the uCode if the user has requested that 2260 * we do so. 2261 */ 2262 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2263 sc->sc_int_delay = 0; 2264 sc->sc_bundle_max = 0; 2265 return; 2266 } 2267 2268 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2269 if (sc->sc_rev == uc->revision) 2270 break; 2271 } 2272 if (uc->ucode == NULL) 2273 return; 2274 2275 /* BIG ENDIAN: no need to swap to store 0 */ 2276 cbp->cb_status = 0; 2277 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2278 cbp->link_addr = 0xffffffff; /* (no) next command */ 2279 for (i = 0; i < uc->length; i++) 2280 cbp->ucode[i] = htole32(uc->ucode[i]); 2281 2282 if (uc->int_delay_offset) 2283 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2284 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2285 2286 if (uc->bundle_max_offset) 2287 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2288 htole16(fxp_bundle_max); 2289 2290 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2291 2292 /* 2293 * Download the uCode to the chip. 2294 */ 2295 fxp_scb_wait(sc); 2296 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2297 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2298 2299 /* ...and wait for it to complete. */ 2300 count = 10000; 2301 do { 2302 FXP_CDUCODESYNC(sc, 2303 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2304 DELAY(2); 2305 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2306 if (count == 0) { 2307 sc->sc_int_delay = 0; 2308 sc->sc_bundle_max = 0; 2309 log(LOG_WARNING, "%s: timeout loading microcode\n", 2310 device_xname(&sc->sc_dev)); 2311 return; 2312 } 2313 2314 if (sc->sc_int_delay != fxp_int_delay || 2315 sc->sc_bundle_max != fxp_bundle_max) { 2316 sc->sc_int_delay = fxp_int_delay; 2317 sc->sc_bundle_max = fxp_bundle_max; 2318 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2319 "max bundle: %d\n", device_xname(&sc->sc_dev), 2320 sc->sc_int_delay, 2321 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2322 } 2323 2324 sc->sc_flags |= FXPF_UCODE_LOADED; 2325 } 2326 2327 int 2328 fxp_enable(struct fxp_softc *sc) 2329 { 2330 2331 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2332 if ((*sc->sc_enable)(sc) != 0) { 2333 log(LOG_ERR, "%s: device enable failed\n", 2334 device_xname(&sc->sc_dev)); 2335 return (EIO); 2336 } 2337 } 2338 2339 sc->sc_enabled = 1; 2340 return (0); 2341 } 2342 2343 void 2344 fxp_disable(struct fxp_softc *sc) 2345 { 2346 2347 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2348 (*sc->sc_disable)(sc); 2349 sc->sc_enabled = 0; 2350 } 2351 } 2352 2353 /* 2354 * fxp_activate: 2355 * 2356 * Handle device activation/deactivation requests. 2357 */ 2358 int 2359 fxp_activate(struct device *self, enum devact act) 2360 { 2361 struct fxp_softc *sc = (void *) self; 2362 int s, error = 0; 2363 2364 s = splnet(); 2365 switch (act) { 2366 case DVACT_ACTIVATE: 2367 error = EOPNOTSUPP; 2368 break; 2369 2370 case DVACT_DEACTIVATE: 2371 if (sc->sc_flags & FXPF_MII) 2372 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2373 MII_OFFSET_ANY); 2374 if_deactivate(&sc->sc_ethercom.ec_if); 2375 break; 2376 } 2377 splx(s); 2378 2379 return (error); 2380 } 2381 2382 /* 2383 * fxp_detach: 2384 * 2385 * Detach an i82557 interface. 2386 */ 2387 int 2388 fxp_detach(struct fxp_softc *sc) 2389 { 2390 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2391 int i; 2392 2393 /* Succeed now if there's no work to do. */ 2394 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2395 return (0); 2396 2397 /* Unhook our tick handler. */ 2398 callout_stop(&sc->sc_callout); 2399 2400 if (sc->sc_flags & FXPF_MII) { 2401 /* Detach all PHYs */ 2402 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2403 } 2404 2405 /* Delete all remaining media. */ 2406 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2407 2408 #if NRND > 0 2409 rnd_detach_source(&sc->rnd_source); 2410 #endif 2411 ether_ifdetach(ifp); 2412 if_detach(ifp); 2413 2414 for (i = 0; i < FXP_NRFABUFS; i++) { 2415 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2416 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2417 } 2418 2419 for (i = 0; i < FXP_NTXCB; i++) { 2420 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2421 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2422 } 2423 2424 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2425 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2426 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2427 sizeof(struct fxp_control_data)); 2428 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2429 2430 return (0); 2431 } 2432
Indexes created Fri Sep 26 20:09:58 GMT 2025