i82557.c revision 1.116
1 /* $NetBSD: i82557.c,v 1.116 2008/12/03 14:21:15 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.116 2008/12/03 14:21:15 tsutsui Exp $"); 70 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/socket.h> 81 #include <sys/ioctl.h> 82 #include <sys/errno.h> 83 #include <sys/device.h> 84 #include <sys/syslog.h> 85 86 #include <machine/endian.h> 87 88 #include <uvm/uvm_extern.h> 89 90 #if NRND > 0 91 #include <sys/rnd.h> 92 #endif 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 106 #include <dev/mii/miivar.h> 107 108 #include <dev/ic/i82557reg.h> 109 #include <dev/ic/i82557var.h> 110 111 #include <dev/microcode/i8255x/rcvbundl.h> 112 113 /* 114 * NOTE! On the Alpha, we have an alignment constraint. The 115 * card DMAs the packet immediately following the RFA. However, 116 * the first thing in the packet is a 14-byte Ethernet header. 117 * This means that the packet is misaligned. To compensate, 118 * we actually offset the RFA 2 bytes into the cluster. This 119 * alignes the packet after the Ethernet header at a 32-bit 120 * boundary. HOWEVER! This means that the RFA is misaligned! 121 */ 122 #define RFA_ALIGNMENT_FUDGE 2 123 124 /* 125 * The configuration byte map has several undefined fields which 126 * must be one or must be zero. Set up a template for these bits 127 * only (assuming an i82557 chip), leaving the actual configuration 128 * for fxp_init(). 129 * 130 * See the definition of struct fxp_cb_config for the bit definitions. 131 */ 132 const u_int8_t fxp_cb_config_template[] = { 133 0x0, 0x0, /* cb_status */ 134 0x0, 0x0, /* cb_command */ 135 0x0, 0x0, 0x0, 0x0, /* link_addr */ 136 0x0, /* 0 */ 137 0x0, /* 1 */ 138 0x0, /* 2 */ 139 0x0, /* 3 */ 140 0x0, /* 4 */ 141 0x0, /* 5 */ 142 0x32, /* 6 */ 143 0x0, /* 7 */ 144 0x0, /* 8 */ 145 0x0, /* 9 */ 146 0x6, /* 10 */ 147 0x0, /* 11 */ 148 0x0, /* 12 */ 149 0x0, /* 13 */ 150 0xf2, /* 14 */ 151 0x48, /* 15 */ 152 0x0, /* 16 */ 153 0x40, /* 17 */ 154 0xf0, /* 18 */ 155 0x0, /* 19 */ 156 0x3f, /* 20 */ 157 0x5, /* 21 */ 158 0x0, /* 22 */ 159 0x0, /* 23 */ 160 0x0, /* 24 */ 161 0x0, /* 25 */ 162 0x0, /* 26 */ 163 0x0, /* 27 */ 164 0x0, /* 28 */ 165 0x0, /* 29 */ 166 0x0, /* 30 */ 167 0x0, /* 31 */ 168 }; 169 170 void fxp_mii_initmedia(struct fxp_softc *); 171 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 172 173 void fxp_80c24_initmedia(struct fxp_softc *); 174 int fxp_80c24_mediachange(struct ifnet *); 175 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 176 177 void fxp_start(struct ifnet *); 178 int fxp_ioctl(struct ifnet *, u_long, void *); 179 void fxp_watchdog(struct ifnet *); 180 int fxp_init(struct ifnet *); 181 void fxp_stop(struct ifnet *, int); 182 183 void fxp_txintr(struct fxp_softc *); 184 int fxp_rxintr(struct fxp_softc *); 185 186 int fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 187 188 void fxp_rxdrain(struct fxp_softc *); 189 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 190 int fxp_mdi_read(device_t, int, int); 191 void fxp_statchg(device_t); 192 void fxp_mdi_write(device_t, int, int, int); 193 void fxp_autosize_eeprom(struct fxp_softc*); 194 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 195 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 196 void fxp_eeprom_update_cksum(struct fxp_softc *); 197 void fxp_get_info(struct fxp_softc *, u_int8_t *); 198 void fxp_tick(void *); 199 void fxp_mc_setup(struct fxp_softc *); 200 void fxp_load_ucode(struct fxp_softc *); 201 202 int fxp_copy_small = 0; 203 204 /* 205 * Variables for interrupt mitigating microcode. 206 */ 207 int fxp_int_delay = 1000; /* usec */ 208 int fxp_bundle_max = 6; /* packets */ 209 210 struct fxp_phytype { 211 int fp_phy; /* type of PHY, -1 for MII at the end. */ 212 void (*fp_init)(struct fxp_softc *); 213 } fxp_phytype_table[] = { 214 { FXP_PHY_80C24, fxp_80c24_initmedia }, 215 { -1, fxp_mii_initmedia }, 216 }; 217 218 /* 219 * Set initial transmit threshold at 64 (512 bytes). This is 220 * increased by 64 (512 bytes) at a time, to maximum of 192 221 * (1536 bytes), if an underrun occurs. 222 */ 223 static int tx_threshold = 64; 224 225 /* 226 * Wait for the previous command to be accepted (but not necessarily 227 * completed). 228 */ 229 static inline void 230 fxp_scb_wait(struct fxp_softc *sc) 231 { 232 int i = 10000; 233 234 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 235 delay(2); 236 if (i == 0) 237 log(LOG_WARNING, 238 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 239 } 240 241 /* 242 * Submit a command to the i82557. 243 */ 244 static inline void 245 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 246 { 247 248 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 249 } 250 251 /* 252 * Finish attaching an i82557 interface. Called by bus-specific front-end. 253 */ 254 void 255 fxp_attach(struct fxp_softc *sc) 256 { 257 u_int8_t enaddr[ETHER_ADDR_LEN]; 258 struct ifnet *ifp; 259 bus_dma_segment_t seg; 260 int rseg, i, error; 261 struct fxp_phytype *fp; 262 263 callout_init(&sc->sc_callout, 0); 264 265 /* 266 * Enable some good stuff on i82558 and later. 267 */ 268 if (sc->sc_rev >= FXP_REV_82558_A4) { 269 /* Enable the extended TxCB. */ 270 sc->sc_flags |= FXPF_EXT_TXCB; 271 } 272 273 /* 274 * Enable use of extended RFDs and TCBs for 82550 275 * and later chips. Note: we need extended TXCB support 276 * too, but that's already enabled by the code above. 277 * Be careful to do this only on the right devices. 278 */ 279 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 280 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 281 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 282 } else { 283 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 284 } 285 286 sc->sc_rfa_size = 287 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 288 289 /* 290 * Allocate the control data structures, and create and load the 291 * DMA map for it. 292 */ 293 if ((error = bus_dmamem_alloc(sc->sc_dmat, 294 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 295 0)) != 0) { 296 aprint_error_dev(sc->sc_dev, 297 "unable to allocate control data, error = %d\n", 298 error); 299 goto fail_0; 300 } 301 302 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 303 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 304 BUS_DMA_COHERENT)) != 0) { 305 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 306 error); 307 goto fail_1; 308 } 309 sc->sc_cdseg = seg; 310 sc->sc_cdnseg = rseg; 311 312 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 313 314 if ((error = bus_dmamap_create(sc->sc_dmat, 315 sizeof(struct fxp_control_data), 1, 316 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 317 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 318 "error = %d\n", error); 319 goto fail_2; 320 } 321 322 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 323 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 324 0)) != 0) { 325 aprint_error_dev(sc->sc_dev, 326 "can't load control data DMA map, error = %d\n", 327 error); 328 goto fail_3; 329 } 330 331 /* 332 * Create the transmit buffer DMA maps. 333 */ 334 for (i = 0; i < FXP_NTXCB; i++) { 335 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 336 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 337 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 338 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 339 "error = %d\n", i, error); 340 goto fail_4; 341 } 342 } 343 344 /* 345 * Create the receive buffer DMA maps. 346 */ 347 for (i = 0; i < FXP_NRFABUFS; i++) { 348 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 349 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 350 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 351 "error = %d\n", i, error); 352 goto fail_5; 353 } 354 } 355 356 /* Initialize MAC address and media structures. */ 357 fxp_get_info(sc, enaddr); 358 359 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 360 ether_sprintf(enaddr)); 361 362 ifp = &sc->sc_ethercom.ec_if; 363 364 /* 365 * Get info about our media interface, and initialize it. Note 366 * the table terminates itself with a phy of -1, indicating 367 * that we're using MII. 368 */ 369 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 370 if (fp->fp_phy == sc->phy_primary_device) 371 break; 372 (*fp->fp_init)(sc); 373 374 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 375 ifp->if_softc = sc; 376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 377 ifp->if_ioctl = fxp_ioctl; 378 ifp->if_start = fxp_start; 379 ifp->if_watchdog = fxp_watchdog; 380 ifp->if_init = fxp_init; 381 ifp->if_stop = fxp_stop; 382 IFQ_SET_READY(&ifp->if_snd); 383 384 if (sc->sc_flags & FXPF_IPCB) { 385 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 386 /* 387 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 388 * at least, on i82550 rev.12. 389 * specifically, it doesn't calculate ipv4 checksum correctly 390 * when sending 20 byte ipv4 header + 1 or 2 byte data. 391 * FreeBSD driver has related comments. 392 */ 393 ifp->if_capabilities = 394 IFCAP_CSUM_IPv4_Rx | 395 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 396 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 397 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 398 } 399 400 /* 401 * We can support 802.1Q VLAN-sized frames. 402 */ 403 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 404 405 /* 406 * Attach the interface. 407 */ 408 if_attach(ifp); 409 ether_ifattach(ifp, enaddr); 410 #if NRND > 0 411 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 412 RND_TYPE_NET, 0); 413 #endif 414 415 #ifdef FXP_EVENT_COUNTERS 416 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 417 NULL, device_xname(sc->sc_dev), "txstall"); 418 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 419 NULL, device_xname(sc->sc_dev), "txintr"); 420 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 421 NULL, device_xname(sc->sc_dev), "rxintr"); 422 if (sc->sc_rev >= FXP_REV_82558_A4) { 423 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 424 NULL, device_xname(sc->sc_dev), "txpause"); 425 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 426 NULL, device_xname(sc->sc_dev), "rxpause"); 427 } 428 #endif /* FXP_EVENT_COUNTERS */ 429 430 /* The attach is successful. */ 431 sc->sc_flags |= FXPF_ATTACHED; 432 433 return; 434 435 /* 436 * Free any resources we've allocated during the failed attach 437 * attempt. Do this in reverse order and fall though. 438 */ 439 fail_5: 440 for (i = 0; i < FXP_NRFABUFS; i++) { 441 if (sc->sc_rxmaps[i] != NULL) 442 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 443 } 444 fail_4: 445 for (i = 0; i < FXP_NTXCB; i++) { 446 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 447 bus_dmamap_destroy(sc->sc_dmat, 448 FXP_DSTX(sc, i)->txs_dmamap); 449 } 450 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 451 fail_3: 452 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 453 fail_2: 454 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 455 sizeof(struct fxp_control_data)); 456 fail_1: 457 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 458 fail_0: 459 return; 460 } 461 462 void 463 fxp_mii_initmedia(struct fxp_softc *sc) 464 { 465 int flags; 466 467 sc->sc_flags |= FXPF_MII; 468 469 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 470 sc->sc_mii.mii_readreg = fxp_mdi_read; 471 sc->sc_mii.mii_writereg = fxp_mdi_write; 472 sc->sc_mii.mii_statchg = fxp_statchg; 473 474 sc->sc_ethercom.ec_mii = &sc->sc_mii; 475 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 476 fxp_mii_mediastatus); 477 478 flags = MIIF_NOISOLATE; 479 if (sc->sc_rev >= FXP_REV_82558_A4) 480 flags |= MIIF_DOPAUSE; 481 /* 482 * The i82557 wedges if all of its PHYs are isolated! 483 */ 484 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 485 MII_OFFSET_ANY, flags); 486 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 487 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 488 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 489 } else 490 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 491 } 492 493 void 494 fxp_80c24_initmedia(struct fxp_softc *sc) 495 { 496 497 /* 498 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 499 * doesn't have a programming interface of any sort. The 500 * media is sensed automatically based on how the link partner 501 * is configured. This is, in essence, manual configuration. 502 */ 503 aprint_normal_dev(sc->sc_dev, "Seeq 80c24 AutoDUPLEX media interface present\n"); 504 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 505 fxp_80c24_mediastatus); 506 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 507 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 508 } 509 510 /* 511 * Initialize the interface media. 512 */ 513 void 514 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 515 { 516 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 517 518 /* 519 * Reset to a stable state. 520 */ 521 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 522 DELAY(100); 523 524 sc->sc_eeprom_size = 0; 525 fxp_autosize_eeprom(sc); 526 if (sc->sc_eeprom_size == 0) { 527 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 528 sc->sc_eeprom_size = 6; /* XXX panic here? */ 529 } 530 #ifdef DEBUG 531 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 532 1 << sc->sc_eeprom_size); 533 #endif 534 535 /* 536 * Get info about the primary PHY 537 */ 538 fxp_read_eeprom(sc, &data, 6, 1); 539 sc->phy_primary_device = 540 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 541 542 /* 543 * Read MAC address. 544 */ 545 fxp_read_eeprom(sc, myea, 0, 3); 546 enaddr[0] = myea[0] & 0xff; 547 enaddr[1] = myea[0] >> 8; 548 enaddr[2] = myea[1] & 0xff; 549 enaddr[3] = myea[1] >> 8; 550 enaddr[4] = myea[2] & 0xff; 551 enaddr[5] = myea[2] >> 8; 552 553 /* 554 * Systems based on the ICH2/ICH2-M chip from Intel, as well 555 * as some i82559 designs, have a defect where the chip can 556 * cause a PCI protocol violation if it receives a CU_RESUME 557 * command when it is entering the IDLE state. 558 * 559 * The work-around is to disable Dynamic Standby Mode, so that 560 * the chip never deasserts #CLKRUN, and always remains in the 561 * active state. 562 * 563 * Unfortunately, the only way to disable Dynamic Standby is 564 * to frob an EEPROM setting and reboot (the EEPROM setting 565 * is only consulted when the PCI bus comes out of reset). 566 * 567 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 568 */ 569 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 570 fxp_read_eeprom(sc, &data, 10, 1); 571 if (data & 0x02) { /* STB enable */ 572 aprint_error_dev(sc->sc_dev, "WARNING: " 573 "Disabling dynamic standby mode in EEPROM " 574 "to work around a\n"); 575 aprint_normal_dev(sc->sc_dev, 576 "WARNING: hardware bug. You must reset " 577 "the system before using this\n"); 578 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 579 data &= ~0x02; 580 fxp_write_eeprom(sc, &data, 10, 1); 581 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 582 data); 583 fxp_eeprom_update_cksum(sc); 584 } 585 } 586 587 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 588 /* Due to false positives we make it conditional on setting link1 */ 589 fxp_read_eeprom(sc, &data, 3, 1); 590 if ((data & 0x03) != 0x03) { 591 aprint_verbose_dev(sc->sc_dev, "May need receiver lock-up workaround\n"); 592 } 593 } 594 595 static void 596 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 597 { 598 uint16_t reg; 599 int x; 600 601 for (x = 1 << (len - 1); x != 0; x >>= 1) { 602 DELAY(40); 603 if (data & x) 604 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 605 else 606 reg = FXP_EEPROM_EECS; 607 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 608 DELAY(40); 609 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 610 reg | FXP_EEPROM_EESK); 611 DELAY(40); 612 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 613 } 614 DELAY(40); 615 } 616 617 /* 618 * Figure out EEPROM size. 619 * 620 * 559's can have either 64-word or 256-word EEPROMs, the 558 621 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 622 * talks about the existence of 16 to 256 word EEPROMs. 623 * 624 * The only known sizes are 64 and 256, where the 256 version is used 625 * by CardBus cards to store CIS information. 626 * 627 * The address is shifted in msb-to-lsb, and after the last 628 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 629 * after which follows the actual data. We try to detect this zero, by 630 * probing the data-out bit in the EEPROM control register just after 631 * having shifted in a bit. If the bit is zero, we assume we've 632 * shifted enough address bits. The data-out should be tri-state, 633 * before this, which should translate to a logical one. 634 * 635 * Other ways to do this would be to try to read a register with known 636 * contents with a varying number of address bits, but no such 637 * register seem to be available. The high bits of register 10 are 01 638 * on the 558 and 559, but apparently not on the 557. 639 * 640 * The Linux driver computes a checksum on the EEPROM data, but the 641 * value of this checksum is not very well documented. 642 */ 643 644 void 645 fxp_autosize_eeprom(struct fxp_softc *sc) 646 { 647 int x; 648 649 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 650 DELAY(40); 651 652 /* Shift in read opcode. */ 653 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 654 655 /* 656 * Shift in address, wait for the dummy zero following a correct 657 * address shift. 658 */ 659 for (x = 1; x <= 8; x++) { 660 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 661 DELAY(40); 662 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 663 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 664 DELAY(40); 665 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 666 FXP_EEPROM_EEDO) == 0) 667 break; 668 DELAY(40); 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 670 DELAY(40); 671 } 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 673 DELAY(40); 674 if (x != 6 && x != 8) { 675 #ifdef DEBUG 676 printf("%s: strange EEPROM size (%d)\n", 677 device_xname(sc->sc_dev), 1 << x); 678 #endif 679 } else 680 sc->sc_eeprom_size = x; 681 } 682 683 /* 684 * Read from the serial EEPROM. Basically, you manually shift in 685 * the read opcode (one bit at a time) and then shift in the address, 686 * and then you shift out the data (all of this one bit at a time). 687 * The word size is 16 bits, so you have to provide the address for 688 * every 16 bits of data. 689 */ 690 void 691 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 692 { 693 u_int16_t reg; 694 int i, x; 695 696 for (i = 0; i < words; i++) { 697 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 698 699 /* Shift in read opcode. */ 700 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 701 702 /* Shift in address. */ 703 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 704 705 reg = FXP_EEPROM_EECS; 706 data[i] = 0; 707 708 /* Shift out data. */ 709 for (x = 16; x > 0; x--) { 710 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 711 reg | FXP_EEPROM_EESK); 712 DELAY(40); 713 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 714 FXP_EEPROM_EEDO) 715 data[i] |= (1 << (x - 1)); 716 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 717 DELAY(40); 718 } 719 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 720 DELAY(40); 721 } 722 } 723 724 /* 725 * Write data to the serial EEPROM. 726 */ 727 void 728 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 729 { 730 int i, j; 731 732 for (i = 0; i < words; i++) { 733 /* Erase/write enable. */ 734 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 735 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 736 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 737 sc->sc_eeprom_size); 738 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 739 DELAY(4); 740 741 /* Shift in write opcode, address, data. */ 742 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 743 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 744 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 745 fxp_eeprom_shiftin(sc, data[i], 16); 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 747 DELAY(4); 748 749 /* Wait for the EEPROM to finish up. */ 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 751 DELAY(4); 752 for (j = 0; j < 1000; j++) { 753 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 754 FXP_EEPROM_EEDO) 755 break; 756 DELAY(50); 757 } 758 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 759 DELAY(4); 760 761 /* Erase/write disable. */ 762 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 763 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 764 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 766 DELAY(4); 767 } 768 } 769 770 /* 771 * Update the checksum of the EEPROM. 772 */ 773 void 774 fxp_eeprom_update_cksum(struct fxp_softc *sc) 775 { 776 int i; 777 uint16_t data, cksum; 778 779 cksum = 0; 780 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 781 fxp_read_eeprom(sc, &data, i, 1); 782 cksum += data; 783 } 784 i = (1 << sc->sc_eeprom_size) - 1; 785 cksum = 0xbaba - cksum; 786 fxp_read_eeprom(sc, &data, i, 1); 787 fxp_write_eeprom(sc, &cksum, i, 1); 788 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 789 device_xname(sc->sc_dev), i, data, cksum); 790 } 791 792 /* 793 * Start packet transmission on the interface. 794 */ 795 void 796 fxp_start(struct ifnet *ifp) 797 { 798 struct fxp_softc *sc = ifp->if_softc; 799 struct mbuf *m0, *m; 800 struct fxp_txdesc *txd; 801 struct fxp_txsoft *txs; 802 bus_dmamap_t dmamap; 803 int error, lasttx, nexttx, opending, seg; 804 805 /* 806 * If we want a re-init, bail out now. 807 */ 808 if (sc->sc_flags & FXPF_WANTINIT) { 809 ifp->if_flags |= IFF_OACTIVE; 810 return; 811 } 812 813 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 814 return; 815 816 /* 817 * Remember the previous txpending and the current lasttx. 818 */ 819 opending = sc->sc_txpending; 820 lasttx = sc->sc_txlast; 821 822 /* 823 * Loop through the send queue, setting up transmit descriptors 824 * until we drain the queue, or use up all available transmit 825 * descriptors. 826 */ 827 for (;;) { 828 struct fxp_tbd *tbdp; 829 int csum_flags; 830 831 /* 832 * Grab a packet off the queue. 833 */ 834 IFQ_POLL(&ifp->if_snd, m0); 835 if (m0 == NULL) 836 break; 837 m = NULL; 838 839 if (sc->sc_txpending == FXP_NTXCB - 1) { 840 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 841 break; 842 } 843 844 /* 845 * Get the next available transmit descriptor. 846 */ 847 nexttx = FXP_NEXTTX(sc->sc_txlast); 848 txd = FXP_CDTX(sc, nexttx); 849 txs = FXP_DSTX(sc, nexttx); 850 dmamap = txs->txs_dmamap; 851 852 /* 853 * Load the DMA map. If this fails, the packet either 854 * didn't fit in the allotted number of frags, or we were 855 * short on resources. In this case, we'll copy and try 856 * again. 857 */ 858 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 859 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 860 MGETHDR(m, M_DONTWAIT, MT_DATA); 861 if (m == NULL) { 862 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 863 device_xname(sc->sc_dev)); 864 break; 865 } 866 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 867 if (m0->m_pkthdr.len > MHLEN) { 868 MCLGET(m, M_DONTWAIT); 869 if ((m->m_flags & M_EXT) == 0) { 870 log(LOG_ERR, 871 "%s: unable to allocate Tx " 872 "cluster\n", device_xname(sc->sc_dev)); 873 m_freem(m); 874 break; 875 } 876 } 877 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 878 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 879 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 880 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 881 if (error) { 882 log(LOG_ERR, "%s: unable to load Tx buffer, " 883 "error = %d\n", device_xname(sc->sc_dev), error); 884 break; 885 } 886 } 887 888 IFQ_DEQUEUE(&ifp->if_snd, m0); 889 csum_flags = m0->m_pkthdr.csum_flags; 890 if (m != NULL) { 891 m_freem(m0); 892 m0 = m; 893 } 894 895 /* Initialize the fraglist. */ 896 tbdp = txd->txd_tbd; 897 if (sc->sc_flags & FXPF_IPCB) 898 tbdp++; 899 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 900 tbdp[seg].tb_addr = 901 htole32(dmamap->dm_segs[seg].ds_addr); 902 tbdp[seg].tb_size = 903 htole32(dmamap->dm_segs[seg].ds_len); 904 } 905 906 /* Sync the DMA map. */ 907 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 908 BUS_DMASYNC_PREWRITE); 909 910 /* 911 * Store a pointer to the packet so we can free it later. 912 */ 913 txs->txs_mbuf = m0; 914 915 /* 916 * Initialize the transmit descriptor. 917 */ 918 /* BIG_ENDIAN: no need to swap to store 0 */ 919 txd->txd_txcb.cb_status = 0; 920 txd->txd_txcb.cb_command = 921 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 922 txd->txd_txcb.tx_threshold = tx_threshold; 923 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 924 925 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 926 if (sc->sc_flags & FXPF_IPCB) { 927 struct m_tag *vtag; 928 struct fxp_ipcb *ipcb; 929 /* 930 * Deal with TCP/IP checksum offload. Note that 931 * in order for TCP checksum offload to work, 932 * the pseudo header checksum must have already 933 * been computed and stored in the checksum field 934 * in the TCP header. The stack should have 935 * already done this for us. 936 */ 937 ipcb = &txd->txd_u.txdu_ipcb; 938 memset(ipcb, 0, sizeof(*ipcb)); 939 /* 940 * always do hardware parsing. 941 */ 942 ipcb->ipcb_ip_activation_high = 943 FXP_IPCB_HARDWAREPARSING_ENABLE; 944 /* 945 * ip checksum offloading. 946 */ 947 if (csum_flags & M_CSUM_IPv4) { 948 ipcb->ipcb_ip_schedule |= 949 FXP_IPCB_IP_CHECKSUM_ENABLE; 950 } 951 /* 952 * TCP/UDP checksum offloading. 953 */ 954 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 955 ipcb->ipcb_ip_schedule |= 956 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 957 } 958 959 /* 960 * request VLAN tag insertion if needed. 961 */ 962 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 963 if (vtag) { 964 ipcb->ipcb_vlan_id = 965 htobe16(*(u_int *)(vtag + 1)); 966 ipcb->ipcb_ip_activation_high |= 967 FXP_IPCB_INSERTVLAN_ENABLE; 968 } 969 } else { 970 KASSERT((csum_flags & 971 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 972 } 973 974 FXP_CDTXSYNC(sc, nexttx, 975 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 976 977 /* Advance the tx pointer. */ 978 sc->sc_txpending++; 979 sc->sc_txlast = nexttx; 980 981 #if NBPFILTER > 0 982 /* 983 * Pass packet to bpf if there is a listener. 984 */ 985 if (ifp->if_bpf) 986 bpf_mtap(ifp->if_bpf, m0); 987 #endif 988 } 989 990 if (sc->sc_txpending == FXP_NTXCB - 1) { 991 /* No more slots; notify upper layer. */ 992 ifp->if_flags |= IFF_OACTIVE; 993 } 994 995 if (sc->sc_txpending != opending) { 996 /* 997 * We enqueued packets. If the transmitter was idle, 998 * reset the txdirty pointer. 999 */ 1000 if (opending == 0) 1001 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1002 1003 /* 1004 * Cause the chip to interrupt and suspend command 1005 * processing once the last packet we've enqueued 1006 * has been transmitted. 1007 * 1008 * To avoid a race between updating status bits 1009 * by the fxp chip and clearing command bits 1010 * by this function on machines which don't have 1011 * atomic methods to clear/set bits in memory 1012 * smaller than 32bits (both cb_status and cb_command 1013 * members are uint16_t and in the same 32bit word), 1014 * we have to prepare a dummy TX descriptor which has 1015 * NOP command and just causes a TX completion interrupt. 1016 */ 1017 sc->sc_txpending++; 1018 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1019 txd = FXP_CDTX(sc, sc->sc_txlast); 1020 /* BIG_ENDIAN: no need to swap to store 0 */ 1021 txd->txd_txcb.cb_status = 0; 1022 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1023 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1024 FXP_CDTXSYNC(sc, sc->sc_txlast, 1025 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1026 1027 /* 1028 * The entire packet chain is set up. Clear the suspend bit 1029 * on the command prior to the first packet we set up. 1030 */ 1031 FXP_CDTXSYNC(sc, lasttx, 1032 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1033 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1034 htole16(~FXP_CB_COMMAND_S); 1035 FXP_CDTXSYNC(sc, lasttx, 1036 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1037 1038 /* 1039 * Issue a Resume command in case the chip was suspended. 1040 */ 1041 fxp_scb_wait(sc); 1042 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1043 1044 /* Set a watchdog timer in case the chip flakes out. */ 1045 ifp->if_timer = 5; 1046 } 1047 } 1048 1049 /* 1050 * Process interface interrupts. 1051 */ 1052 int 1053 fxp_intr(void *arg) 1054 { 1055 struct fxp_softc *sc = arg; 1056 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1057 bus_dmamap_t rxmap; 1058 int claimed = 0, rnr; 1059 u_int8_t statack; 1060 1061 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1062 return (0); 1063 /* 1064 * If the interface isn't running, don't try to 1065 * service the interrupt.. just ack it and bail. 1066 */ 1067 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1068 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1069 if (statack) { 1070 claimed = 1; 1071 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1072 } 1073 return (claimed); 1074 } 1075 1076 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1077 claimed = 1; 1078 1079 /* 1080 * First ACK all the interrupts in this pass. 1081 */ 1082 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1083 1084 /* 1085 * Process receiver interrupts. If a no-resource (RNR) 1086 * condition exists, get whatever packets we can and 1087 * re-start the receiver. 1088 */ 1089 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1090 1 : 0; 1091 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1092 FXP_SCB_STATACK_SWI)) { 1093 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1094 rnr |= fxp_rxintr(sc); 1095 } 1096 1097 /* 1098 * Free any finished transmit mbuf chains. 1099 */ 1100 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1101 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1102 fxp_txintr(sc); 1103 1104 /* 1105 * Try to get more packets going. 1106 */ 1107 fxp_start(ifp); 1108 1109 if (sc->sc_txpending == 0) { 1110 /* 1111 * Tell them that they can re-init now. 1112 */ 1113 if (sc->sc_flags & FXPF_WANTINIT) 1114 wakeup(sc); 1115 } 1116 } 1117 1118 if (rnr) { 1119 fxp_scb_wait(sc); 1120 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1121 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1122 fxp_scb_wait(sc); 1123 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1124 rxmap->dm_segs[0].ds_addr + 1125 RFA_ALIGNMENT_FUDGE); 1126 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1127 } 1128 } 1129 1130 #if NRND > 0 1131 if (claimed) 1132 rnd_add_uint32(&sc->rnd_source, statack); 1133 #endif 1134 return (claimed); 1135 } 1136 1137 /* 1138 * Handle transmit completion interrupts. 1139 */ 1140 void 1141 fxp_txintr(struct fxp_softc *sc) 1142 { 1143 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1144 struct fxp_txdesc *txd; 1145 struct fxp_txsoft *txs; 1146 int i; 1147 u_int16_t txstat; 1148 1149 ifp->if_flags &= ~IFF_OACTIVE; 1150 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1151 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1152 txd = FXP_CDTX(sc, i); 1153 txs = FXP_DSTX(sc, i); 1154 1155 FXP_CDTXSYNC(sc, i, 1156 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1157 1158 /* skip dummy NOP TX descriptor */ 1159 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1160 == FXP_CB_COMMAND_NOP) 1161 continue; 1162 1163 txstat = le16toh(txd->txd_txcb.cb_status); 1164 1165 if ((txstat & FXP_CB_STATUS_C) == 0) 1166 break; 1167 1168 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1169 0, txs->txs_dmamap->dm_mapsize, 1170 BUS_DMASYNC_POSTWRITE); 1171 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1172 m_freem(txs->txs_mbuf); 1173 txs->txs_mbuf = NULL; 1174 } 1175 1176 /* Update the dirty transmit buffer pointer. */ 1177 sc->sc_txdirty = i; 1178 1179 /* 1180 * Cancel the watchdog timer if there are no pending 1181 * transmissions. 1182 */ 1183 if (sc->sc_txpending == 0) 1184 ifp->if_timer = 0; 1185 } 1186 1187 /* 1188 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1189 */ 1190 1191 int 1192 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1193 { 1194 u_int16_t rxparsestat; 1195 u_int16_t csum_stat; 1196 u_int32_t csum_data; 1197 int csum_flags; 1198 1199 /* 1200 * check VLAN tag stripping. 1201 */ 1202 1203 if (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) { 1204 struct m_tag *vtag; 1205 1206 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), M_NOWAIT); 1207 if (vtag == NULL) 1208 return ENOMEM; 1209 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1210 m_tag_prepend(m, vtag); 1211 } 1212 1213 /* 1214 * check H/W Checksumming. 1215 */ 1216 1217 csum_stat = le16toh(rfa->cksum_stat); 1218 rxparsestat = le16toh(rfa->rx_parse_stat); 1219 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1220 return 0; 1221 1222 csum_flags = 0; 1223 csum_data = 0; 1224 1225 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1226 csum_flags = M_CSUM_IPv4; 1227 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1228 csum_flags |= M_CSUM_IPv4_BAD; 1229 } 1230 1231 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1232 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1233 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1234 csum_flags |= M_CSUM_TCP_UDP_BAD; 1235 } 1236 1237 m->m_pkthdr.csum_flags = csum_flags; 1238 m->m_pkthdr.csum_data = csum_data; 1239 1240 return 0; 1241 } 1242 1243 /* 1244 * Handle receive interrupts. 1245 */ 1246 int 1247 fxp_rxintr(struct fxp_softc *sc) 1248 { 1249 struct ethercom *ec = &sc->sc_ethercom; 1250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1251 struct mbuf *m, *m0; 1252 bus_dmamap_t rxmap; 1253 struct fxp_rfa *rfa; 1254 int rnr; 1255 u_int16_t len, rxstat; 1256 1257 rnr = 0; 1258 1259 for (;;) { 1260 m = sc->sc_rxq.ifq_head; 1261 rfa = FXP_MTORFA(m); 1262 rxmap = M_GETCTX(m, bus_dmamap_t); 1263 1264 FXP_RFASYNC(sc, m, 1265 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1266 1267 rxstat = le16toh(rfa->rfa_status); 1268 1269 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1270 rnr = 1; 1271 1272 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1273 /* 1274 * We have processed all of the 1275 * receive buffers. 1276 */ 1277 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1278 return rnr; 1279 } 1280 1281 IF_DEQUEUE(&sc->sc_rxq, m); 1282 1283 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1284 1285 len = le16toh(rfa->actual_size) & 1286 (m->m_ext.ext_size - 1); 1287 1288 if (len < sizeof(struct ether_header)) { 1289 /* 1290 * Runt packet; drop it now. 1291 */ 1292 FXP_INIT_RFABUF(sc, m); 1293 continue; 1294 } 1295 1296 /* 1297 * If support for 802.1Q VLAN sized frames is 1298 * enabled, we need to do some additional error 1299 * checking (as we are saving bad frames, in 1300 * order to receive the larger ones). 1301 */ 1302 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1303 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1304 FXP_RFA_STATUS_RNR| 1305 FXP_RFA_STATUS_ALIGN| 1306 FXP_RFA_STATUS_CRC)) != 0) { 1307 FXP_INIT_RFABUF(sc, m); 1308 continue; 1309 } 1310 1311 /* Do checksum checking. */ 1312 m->m_pkthdr.csum_flags = 0; 1313 if (sc->sc_flags & FXPF_EXT_RFA) 1314 if (fxp_rx_hwcksum(m, rfa)) 1315 goto dropit; 1316 1317 /* 1318 * If the packet is small enough to fit in a 1319 * single header mbuf, allocate one and copy 1320 * the data into it. This greatly reduces 1321 * memory consumption when we receive lots 1322 * of small packets. 1323 * 1324 * Otherwise, we add a new buffer to the receive 1325 * chain. If this fails, we drop the packet and 1326 * recycle the old buffer. 1327 */ 1328 if (fxp_copy_small != 0 && len <= MHLEN) { 1329 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1330 if (m0 == NULL) 1331 goto dropit; 1332 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1333 memcpy(mtod(m0, void *), 1334 mtod(m, void *), len); 1335 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1336 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1337 FXP_INIT_RFABUF(sc, m); 1338 m = m0; 1339 } else { 1340 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1341 dropit: 1342 ifp->if_ierrors++; 1343 FXP_INIT_RFABUF(sc, m); 1344 continue; 1345 } 1346 } 1347 1348 m->m_pkthdr.rcvif = ifp; 1349 m->m_pkthdr.len = m->m_len = len; 1350 1351 #if NBPFILTER > 0 1352 /* 1353 * Pass this up to any BPF listeners, but only 1354 * pass it up the stack if it's for us. 1355 */ 1356 if (ifp->if_bpf) 1357 bpf_mtap(ifp->if_bpf, m); 1358 #endif 1359 1360 /* Pass it on. */ 1361 (*ifp->if_input)(ifp, m); 1362 } 1363 } 1364 1365 /* 1366 * Update packet in/out/collision statistics. The i82557 doesn't 1367 * allow you to access these counters without doing a fairly 1368 * expensive DMA to get _all_ of the statistics it maintains, so 1369 * we do this operation here only once per second. The statistics 1370 * counters in the kernel are updated from the previous dump-stats 1371 * DMA and then a new dump-stats DMA is started. The on-chip 1372 * counters are zeroed when the DMA completes. If we can't start 1373 * the DMA immediately, we don't wait - we just prepare to read 1374 * them again next time. 1375 */ 1376 void 1377 fxp_tick(void *arg) 1378 { 1379 struct fxp_softc *sc = arg; 1380 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1381 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1382 int s; 1383 1384 if (!device_is_active(sc->sc_dev)) 1385 return; 1386 1387 s = splnet(); 1388 1389 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1390 1391 ifp->if_opackets += le32toh(sp->tx_good); 1392 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1393 if (sp->rx_good) { 1394 ifp->if_ipackets += le32toh(sp->rx_good); 1395 sc->sc_rxidle = 0; 1396 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1397 sc->sc_rxidle++; 1398 } 1399 ifp->if_ierrors += 1400 le32toh(sp->rx_crc_errors) + 1401 le32toh(sp->rx_alignment_errors) + 1402 le32toh(sp->rx_rnr_errors) + 1403 le32toh(sp->rx_overrun_errors); 1404 /* 1405 * If any transmit underruns occurred, bump up the transmit 1406 * threshold by another 512 bytes (64 * 8). 1407 */ 1408 if (sp->tx_underruns) { 1409 ifp->if_oerrors += le32toh(sp->tx_underruns); 1410 if (tx_threshold < 192) 1411 tx_threshold += 64; 1412 } 1413 #ifdef FXP_EVENT_COUNTERS 1414 if (sc->sc_rev >= FXP_REV_82558_A4) { 1415 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1416 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1417 } 1418 #endif 1419 1420 /* 1421 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1422 * then assume the receiver has locked up and attempt to clear 1423 * the condition by reprogramming the multicast filter (actually, 1424 * resetting the interface). This is a work-around for a bug in 1425 * the 82557 where the receiver locks up if it gets certain types 1426 * of garbage in the synchronization bits prior to the packet header. 1427 * This bug is supposed to only occur in 10Mbps mode, but has been 1428 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1429 * speed transition). 1430 */ 1431 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1432 (void) fxp_init(ifp); 1433 splx(s); 1434 return; 1435 } 1436 /* 1437 * If there is no pending command, start another stats 1438 * dump. Otherwise punt for now. 1439 */ 1440 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1441 /* 1442 * Start another stats dump. 1443 */ 1444 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1445 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1446 } else { 1447 /* 1448 * A previous command is still waiting to be accepted. 1449 * Just zero our copy of the stats and wait for the 1450 * next timer event to update them. 1451 */ 1452 /* BIG_ENDIAN: no swap required to store 0 */ 1453 sp->tx_good = 0; 1454 sp->tx_underruns = 0; 1455 sp->tx_total_collisions = 0; 1456 1457 sp->rx_good = 0; 1458 sp->rx_crc_errors = 0; 1459 sp->rx_alignment_errors = 0; 1460 sp->rx_rnr_errors = 0; 1461 sp->rx_overrun_errors = 0; 1462 if (sc->sc_rev >= FXP_REV_82558_A4) { 1463 sp->tx_pauseframes = 0; 1464 sp->rx_pauseframes = 0; 1465 } 1466 } 1467 1468 if (sc->sc_flags & FXPF_MII) { 1469 /* Tick the MII clock. */ 1470 mii_tick(&sc->sc_mii); 1471 } 1472 1473 splx(s); 1474 1475 /* 1476 * Schedule another timeout one second from now. 1477 */ 1478 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1479 } 1480 1481 /* 1482 * Drain the receive queue. 1483 */ 1484 void 1485 fxp_rxdrain(struct fxp_softc *sc) 1486 { 1487 bus_dmamap_t rxmap; 1488 struct mbuf *m; 1489 1490 for (;;) { 1491 IF_DEQUEUE(&sc->sc_rxq, m); 1492 if (m == NULL) 1493 break; 1494 rxmap = M_GETCTX(m, bus_dmamap_t); 1495 bus_dmamap_unload(sc->sc_dmat, rxmap); 1496 FXP_RXMAP_PUT(sc, rxmap); 1497 m_freem(m); 1498 } 1499 } 1500 1501 /* 1502 * Stop the interface. Cancels the statistics updater and resets 1503 * the interface. 1504 */ 1505 void 1506 fxp_stop(struct ifnet *ifp, int disable) 1507 { 1508 struct fxp_softc *sc = ifp->if_softc; 1509 struct fxp_txsoft *txs; 1510 int i; 1511 1512 /* 1513 * Turn down interface (done early to avoid bad interactions 1514 * between panics, shutdown hooks, and the watchdog timer) 1515 */ 1516 ifp->if_timer = 0; 1517 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1518 1519 /* 1520 * Cancel stats updater. 1521 */ 1522 callout_stop(&sc->sc_callout); 1523 if (sc->sc_flags & FXPF_MII) { 1524 /* Down the MII. */ 1525 mii_down(&sc->sc_mii); 1526 } 1527 1528 /* 1529 * Issue software reset. This unloads any microcode that 1530 * might already be loaded. 1531 */ 1532 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1533 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1534 DELAY(50); 1535 1536 /* 1537 * Release any xmit buffers. 1538 */ 1539 for (i = 0; i < FXP_NTXCB; i++) { 1540 txs = FXP_DSTX(sc, i); 1541 if (txs->txs_mbuf != NULL) { 1542 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1543 m_freem(txs->txs_mbuf); 1544 txs->txs_mbuf = NULL; 1545 } 1546 } 1547 sc->sc_txpending = 0; 1548 1549 if (disable) { 1550 fxp_rxdrain(sc); 1551 fxp_disable(sc); 1552 } 1553 1554 } 1555 1556 /* 1557 * Watchdog/transmission transmit timeout handler. Called when a 1558 * transmission is started on the interface, but no interrupt is 1559 * received before the timeout. This usually indicates that the 1560 * card has wedged for some reason. 1561 */ 1562 void 1563 fxp_watchdog(struct ifnet *ifp) 1564 { 1565 struct fxp_softc *sc = ifp->if_softc; 1566 1567 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1568 ifp->if_oerrors++; 1569 1570 (void) fxp_init(ifp); 1571 } 1572 1573 /* 1574 * Initialize the interface. Must be called at splnet(). 1575 */ 1576 int 1577 fxp_init(struct ifnet *ifp) 1578 { 1579 struct fxp_softc *sc = ifp->if_softc; 1580 struct fxp_cb_config *cbp; 1581 struct fxp_cb_ias *cb_ias; 1582 struct fxp_txdesc *txd; 1583 bus_dmamap_t rxmap; 1584 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1585 uint16_t status; 1586 1587 if ((error = fxp_enable(sc)) != 0) 1588 goto out; 1589 1590 /* 1591 * Cancel any pending I/O 1592 */ 1593 fxp_stop(ifp, 0); 1594 1595 /* 1596 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1597 * flag, and this prevents the MII from detaching resulting in 1598 * a panic. The flags field should perhaps be split in runtime 1599 * flags and more static information. For now, just clear the 1600 * only other flag set. 1601 */ 1602 1603 sc->sc_flags &= ~FXPF_WANTINIT; 1604 1605 /* 1606 * Initialize base of CBL and RFA memory. Loading with zero 1607 * sets it up for regular linear addressing. 1608 */ 1609 fxp_scb_wait(sc); 1610 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1611 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1612 1613 fxp_scb_wait(sc); 1614 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1615 1616 /* 1617 * Initialize the multicast filter. Do this now, since we might 1618 * have to setup the config block differently. 1619 */ 1620 fxp_mc_setup(sc); 1621 1622 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1623 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1624 1625 /* 1626 * In order to support receiving 802.1Q VLAN frames, we have to 1627 * enable "save bad frames", since they are 4 bytes larger than 1628 * the normal Ethernet maximum frame length. On i82558 and later, 1629 * we have a better mechanism for this. 1630 */ 1631 save_bf = 0; 1632 lrxen = 0; 1633 vlan_drop = 0; 1634 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1635 if (sc->sc_rev < FXP_REV_82558_A4) 1636 save_bf = 1; 1637 else 1638 lrxen = 1; 1639 if (sc->sc_rev >= FXP_REV_82550) 1640 vlan_drop = 1; 1641 } 1642 1643 /* 1644 * Initialize base of dump-stats buffer. 1645 */ 1646 fxp_scb_wait(sc); 1647 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1648 sc->sc_cddma + FXP_CDSTATSOFF); 1649 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1650 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1651 1652 cbp = &sc->sc_control_data->fcd_configcb; 1653 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1654 1655 /* 1656 * Load microcode for this controller. 1657 */ 1658 fxp_load_ucode(sc); 1659 1660 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1661 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1662 else 1663 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1664 1665 /* 1666 * This copy is kind of disgusting, but there are a bunch of must be 1667 * zero and must be one bits in this structure and this is the easiest 1668 * way to initialize them all to proper values. 1669 */ 1670 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1671 1672 /* BIG_ENDIAN: no need to swap to store 0 */ 1673 cbp->cb_status = 0; 1674 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1675 FXP_CB_COMMAND_EL); 1676 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1677 cbp->link_addr = 0xffffffff; /* (no) next command */ 1678 /* bytes in config block */ 1679 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1680 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1681 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1682 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1683 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1684 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1685 cbp->type_enable = 0; /* actually reserved */ 1686 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1687 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1688 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1689 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1690 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1691 cbp->late_scb = 0; /* (don't) defer SCB update */ 1692 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1693 cbp->ci_int = 1; /* interrupt on CU idle */ 1694 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1695 cbp->ext_stats_dis = 1; /* disable extended counters */ 1696 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1697 cbp->save_bf = save_bf;/* save bad frames */ 1698 cbp->disc_short_rx = !prm; /* discard short packets */ 1699 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1700 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1701 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1702 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1703 /* interface mode */ 1704 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1705 cbp->csma_dis = 0; /* (don't) disable link */ 1706 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1707 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1708 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1709 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1710 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1711 cbp->nsai = 1; /* (don't) disable source addr insert */ 1712 cbp->preamble_length = 2; /* (7 byte) preamble */ 1713 cbp->loopback = 0; /* (don't) loopback */ 1714 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1715 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1716 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1717 cbp->promiscuous = prm; /* promiscuous mode */ 1718 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1719 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1720 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1721 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1722 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1723 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1724 cbp->padding = 1; /* (do) pad short tx packets */ 1725 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1726 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1727 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1728 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1729 /* must set wake_en in PMCSR also */ 1730 cbp->force_fdx = 0; /* (don't) force full duplex */ 1731 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1732 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1733 cbp->mc_all = allm; /* accept all multicasts */ 1734 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1735 cbp->vlan_drop_en = vlan_drop; 1736 1737 if (sc->sc_rev < FXP_REV_82558_A4) { 1738 /* 1739 * The i82557 has no hardware flow control, the values 1740 * here are the defaults for the chip. 1741 */ 1742 cbp->fc_delay_lsb = 0; 1743 cbp->fc_delay_msb = 0x40; 1744 cbp->pri_fc_thresh = 3; 1745 cbp->tx_fc_dis = 0; 1746 cbp->rx_fc_restop = 0; 1747 cbp->rx_fc_restart = 0; 1748 cbp->fc_filter = 0; 1749 cbp->pri_fc_loc = 1; 1750 } else { 1751 cbp->fc_delay_lsb = 0x1f; 1752 cbp->fc_delay_msb = 0x01; 1753 cbp->pri_fc_thresh = 3; 1754 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1755 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1756 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1757 cbp->fc_filter = !prm; /* drop FC frames to host */ 1758 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1759 cbp->ext_stats_dis = 0; /* enable extended stats */ 1760 } 1761 1762 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1763 1764 /* 1765 * Start the config command/DMA. 1766 */ 1767 fxp_scb_wait(sc); 1768 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1769 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1770 /* ...and wait for it to complete. */ 1771 for (i = 1000; i > 0; i--) { 1772 FXP_CDCONFIGSYNC(sc, 1773 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1774 status = le16toh(cbp->cb_status); 1775 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1776 if ((status & FXP_CB_STATUS_C) != 0) 1777 break; 1778 DELAY(1); 1779 } 1780 if (i == 0) { 1781 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1782 device_xname(sc->sc_dev), __LINE__); 1783 return (ETIMEDOUT); 1784 } 1785 1786 /* 1787 * Initialize the station address. 1788 */ 1789 cb_ias = &sc->sc_control_data->fcd_iascb; 1790 /* BIG_ENDIAN: no need to swap to store 0 */ 1791 cb_ias->cb_status = 0; 1792 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1793 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1794 cb_ias->link_addr = 0xffffffff; 1795 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1796 1797 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1798 1799 /* 1800 * Start the IAS (Individual Address Setup) command/DMA. 1801 */ 1802 fxp_scb_wait(sc); 1803 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1804 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1805 /* ...and wait for it to complete. */ 1806 for (i = 1000; i > 0; i++) { 1807 FXP_CDIASSYNC(sc, 1808 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1809 status = le16toh(cb_ias->cb_status); 1810 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1811 if ((status & FXP_CB_STATUS_C) != 0) 1812 break; 1813 DELAY(1); 1814 } 1815 if (i == 0) { 1816 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1817 device_xname(sc->sc_dev), __LINE__); 1818 return (ETIMEDOUT); 1819 } 1820 1821 /* 1822 * Initialize the transmit descriptor ring. txlast is initialized 1823 * to the end of the list so that it will wrap around to the first 1824 * descriptor when the first packet is transmitted. 1825 */ 1826 for (i = 0; i < FXP_NTXCB; i++) { 1827 txd = FXP_CDTX(sc, i); 1828 memset(txd, 0, sizeof(*txd)); 1829 txd->txd_txcb.cb_command = 1830 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1831 txd->txd_txcb.link_addr = 1832 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1833 if (sc->sc_flags & FXPF_EXT_TXCB) 1834 txd->txd_txcb.tbd_array_addr = 1835 htole32(FXP_CDTBDADDR(sc, i) + 1836 (2 * sizeof(struct fxp_tbd))); 1837 else 1838 txd->txd_txcb.tbd_array_addr = 1839 htole32(FXP_CDTBDADDR(sc, i)); 1840 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1841 } 1842 sc->sc_txpending = 0; 1843 sc->sc_txdirty = 0; 1844 sc->sc_txlast = FXP_NTXCB - 1; 1845 1846 /* 1847 * Initialize the receive buffer list. 1848 */ 1849 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1850 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1851 rxmap = FXP_RXMAP_GET(sc); 1852 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1853 log(LOG_ERR, "%s: unable to allocate or map rx " 1854 "buffer %d, error = %d\n", 1855 device_xname(sc->sc_dev), 1856 sc->sc_rxq.ifq_len, error); 1857 /* 1858 * XXX Should attempt to run with fewer receive 1859 * XXX buffers instead of just failing. 1860 */ 1861 FXP_RXMAP_PUT(sc, rxmap); 1862 fxp_rxdrain(sc); 1863 goto out; 1864 } 1865 } 1866 sc->sc_rxidle = 0; 1867 1868 /* 1869 * Give the transmit ring to the chip. We do this by pointing 1870 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1871 * issuing a start command. It will execute the NOP and then 1872 * suspend, pointing at the first descriptor. 1873 */ 1874 fxp_scb_wait(sc); 1875 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1876 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1877 1878 /* 1879 * Initialize receiver buffer area - RFA. 1880 */ 1881 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1882 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1883 fxp_scb_wait(sc); 1884 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1885 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1886 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1887 #endif 1888 1889 if (sc->sc_flags & FXPF_MII) { 1890 /* 1891 * Set current media. 1892 */ 1893 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1894 goto out; 1895 } 1896 1897 /* 1898 * ...all done! 1899 */ 1900 ifp->if_flags |= IFF_RUNNING; 1901 ifp->if_flags &= ~IFF_OACTIVE; 1902 1903 /* 1904 * Request a software generated interrupt that will be used to 1905 * (re)start the RU processing. If we direct the chip to start 1906 * receiving from the start of queue now, instead of letting the 1907 * interrupt handler first process all received packets, we run 1908 * the risk of having it overwrite mbuf clusters while they are 1909 * being processed or after they have been returned to the pool. 1910 */ 1911 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1912 1913 /* 1914 * Start the one second timer. 1915 */ 1916 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1917 1918 /* 1919 * Attempt to start output on the interface. 1920 */ 1921 fxp_start(ifp); 1922 1923 out: 1924 if (error) { 1925 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1926 ifp->if_timer = 0; 1927 log(LOG_ERR, "%s: interface not running\n", 1928 device_xname(sc->sc_dev)); 1929 } 1930 return (error); 1931 } 1932 1933 /* 1934 * Notify the world which media we're using. 1935 */ 1936 void 1937 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1938 { 1939 struct fxp_softc *sc = ifp->if_softc; 1940 1941 if (sc->sc_enabled == 0) { 1942 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1943 ifmr->ifm_status = 0; 1944 return; 1945 } 1946 1947 ether_mediastatus(ifp, ifmr); 1948 1949 /* 1950 * XXX Flow control is always turned on if the chip supports 1951 * XXX it; we can't easily control it dynamically, since it 1952 * XXX requires sending a setup packet. 1953 */ 1954 if (sc->sc_rev >= FXP_REV_82558_A4) 1955 ifmr->ifm_active |= IFM_FLOW|IFM_ETH_TXPAUSE|IFM_ETH_RXPAUSE; 1956 } 1957 1958 int 1959 fxp_80c24_mediachange(struct ifnet *ifp) 1960 { 1961 1962 /* Nothing to do here. */ 1963 return (0); 1964 } 1965 1966 void 1967 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1968 { 1969 struct fxp_softc *sc = ifp->if_softc; 1970 1971 /* 1972 * Media is currently-selected media. We cannot determine 1973 * the link status. 1974 */ 1975 ifmr->ifm_status = 0; 1976 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1977 } 1978 1979 /* 1980 * Add a buffer to the end of the RFA buffer list. 1981 * Return 0 if successful, error code on failure. 1982 * 1983 * The RFA struct is stuck at the beginning of mbuf cluster and the 1984 * data pointer is fixed up to point just past it. 1985 */ 1986 int 1987 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1988 { 1989 struct mbuf *m; 1990 int error; 1991 1992 MGETHDR(m, M_DONTWAIT, MT_DATA); 1993 if (m == NULL) 1994 return (ENOBUFS); 1995 1996 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1997 MCLGET(m, M_DONTWAIT); 1998 if ((m->m_flags & M_EXT) == 0) { 1999 m_freem(m); 2000 return (ENOBUFS); 2001 } 2002 2003 if (unload) 2004 bus_dmamap_unload(sc->sc_dmat, rxmap); 2005 2006 M_SETCTX(m, rxmap); 2007 2008 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2009 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2010 BUS_DMA_READ|BUS_DMA_NOWAIT); 2011 if (error) { 2012 /* XXX XXX XXX */ 2013 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 2014 sc->sc_rxq.ifq_len, error); 2015 panic("fxp_add_rfabuf"); 2016 } 2017 2018 FXP_INIT_RFABUF(sc, m); 2019 2020 return (0); 2021 } 2022 2023 int 2024 fxp_mdi_read(device_t self, int phy, int reg) 2025 { 2026 struct fxp_softc *sc = device_private(self); 2027 int count = 10000; 2028 int value; 2029 2030 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2031 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2032 2033 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2034 0x10000000) == 0 && count--) 2035 DELAY(10); 2036 2037 if (count <= 0) 2038 log(LOG_WARNING, 2039 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2040 2041 return (value & 0xffff); 2042 } 2043 2044 void 2045 fxp_statchg(device_t self) 2046 { 2047 2048 /* Nothing to do. */ 2049 } 2050 2051 void 2052 fxp_mdi_write(device_t self, int phy, int reg, int value) 2053 { 2054 struct fxp_softc *sc = device_private(self); 2055 int count = 10000; 2056 2057 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2058 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2059 (value & 0xffff)); 2060 2061 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2062 count--) 2063 DELAY(10); 2064 2065 if (count <= 0) 2066 log(LOG_WARNING, 2067 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2068 } 2069 2070 int 2071 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2072 { 2073 struct fxp_softc *sc = ifp->if_softc; 2074 struct ifreq *ifr = (struct ifreq *)data; 2075 int s, error; 2076 2077 s = splnet(); 2078 2079 switch (cmd) { 2080 case SIOCSIFMEDIA: 2081 case SIOCGIFMEDIA: 2082 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2083 break; 2084 2085 default: 2086 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2087 break; 2088 2089 error = 0; 2090 2091 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2092 ; 2093 else if (ifp->if_flags & IFF_RUNNING) { 2094 /* 2095 * Multicast list has changed; set the 2096 * hardware filter accordingly. 2097 */ 2098 while (sc->sc_txpending) { 2099 sc->sc_flags |= FXPF_WANTINIT; 2100 tsleep(sc, PSOCK, "fxp_init", 0); 2101 } 2102 error = fxp_init(ifp); 2103 } 2104 break; 2105 } 2106 2107 /* Try to get more packets going. */ 2108 if (sc->sc_enabled) 2109 fxp_start(ifp); 2110 2111 splx(s); 2112 return (error); 2113 } 2114 2115 /* 2116 * Program the multicast filter. 2117 * 2118 * This function must be called at splnet(). 2119 */ 2120 void 2121 fxp_mc_setup(struct fxp_softc *sc) 2122 { 2123 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2125 struct ethercom *ec = &sc->sc_ethercom; 2126 struct ether_multi *enm; 2127 struct ether_multistep step; 2128 int count, nmcasts; 2129 uint16_t status; 2130 2131 #ifdef DIAGNOSTIC 2132 if (sc->sc_txpending) 2133 panic("fxp_mc_setup: pending transmissions"); 2134 #endif 2135 2136 ifp->if_flags &= ~IFF_ALLMULTI; 2137 2138 /* 2139 * Initialize multicast setup descriptor. 2140 */ 2141 nmcasts = 0; 2142 ETHER_FIRST_MULTI(step, ec, enm); 2143 while (enm != NULL) { 2144 /* 2145 * Check for too many multicast addresses or if we're 2146 * listening to a range. Either way, we simply have 2147 * to accept all multicasts. 2148 */ 2149 if (nmcasts >= MAXMCADDR || 2150 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2151 ETHER_ADDR_LEN) != 0) { 2152 /* 2153 * Callers of this function must do the 2154 * right thing with this. If we're called 2155 * from outside fxp_init(), the caller must 2156 * detect if the state if IFF_ALLMULTI changes. 2157 * If it does, the caller must then call 2158 * fxp_init(), since allmulti is handled by 2159 * the config block. 2160 */ 2161 ifp->if_flags |= IFF_ALLMULTI; 2162 return; 2163 } 2164 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2165 ETHER_ADDR_LEN); 2166 nmcasts++; 2167 ETHER_NEXT_MULTI(step, enm); 2168 } 2169 2170 /* BIG_ENDIAN: no need to swap to store 0 */ 2171 mcsp->cb_status = 0; 2172 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2173 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2174 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2175 2176 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2177 2178 /* 2179 * Wait until the command unit is not active. This should never 2180 * happen since nothing is queued, but make sure anyway. 2181 */ 2182 count = 100; 2183 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2184 FXP_SCB_CUS_ACTIVE && --count) 2185 DELAY(1); 2186 if (count == 0) { 2187 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2188 device_xname(sc->sc_dev), __LINE__); 2189 return; 2190 } 2191 2192 /* 2193 * Start the multicast setup command/DMA. 2194 */ 2195 fxp_scb_wait(sc); 2196 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2197 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2198 2199 /* ...and wait for it to complete. */ 2200 for (count = 1000; count > 0; count--) { 2201 FXP_CDMCSSYNC(sc, 2202 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2203 status = le16toh(mcsp->cb_status); 2204 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2205 if ((status & FXP_CB_STATUS_C) != 0) 2206 break; 2207 DELAY(1); 2208 } 2209 if (count == 0) { 2210 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2211 device_xname(sc->sc_dev), __LINE__); 2212 return; 2213 } 2214 } 2215 2216 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2217 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2218 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2219 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2220 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2221 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2222 2223 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2224 2225 static const struct ucode { 2226 int32_t revision; 2227 const uint32_t *ucode; 2228 size_t length; 2229 uint16_t int_delay_offset; 2230 uint16_t bundle_max_offset; 2231 } ucode_table[] = { 2232 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2233 D101_CPUSAVER_DWORD, 0 }, 2234 2235 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2236 D101_CPUSAVER_DWORD, 0 }, 2237 2238 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2239 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2240 2241 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2242 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2243 2244 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2245 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2246 2247 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2248 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2249 2250 { 0, NULL, 0, 0, 0 } 2251 }; 2252 2253 void 2254 fxp_load_ucode(struct fxp_softc *sc) 2255 { 2256 const struct ucode *uc; 2257 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2258 int count, i; 2259 uint16_t status; 2260 2261 if (sc->sc_flags & FXPF_UCODE_LOADED) 2262 return; 2263 2264 /* 2265 * Only load the uCode if the user has requested that 2266 * we do so. 2267 */ 2268 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2269 sc->sc_int_delay = 0; 2270 sc->sc_bundle_max = 0; 2271 return; 2272 } 2273 2274 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2275 if (sc->sc_rev == uc->revision) 2276 break; 2277 } 2278 if (uc->ucode == NULL) 2279 return; 2280 2281 /* BIG ENDIAN: no need to swap to store 0 */ 2282 cbp->cb_status = 0; 2283 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2284 cbp->link_addr = 0xffffffff; /* (no) next command */ 2285 for (i = 0; i < uc->length; i++) 2286 cbp->ucode[i] = htole32(uc->ucode[i]); 2287 2288 if (uc->int_delay_offset) 2289 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2290 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2291 2292 if (uc->bundle_max_offset) 2293 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2294 htole16(fxp_bundle_max); 2295 2296 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2297 2298 /* 2299 * Download the uCode to the chip. 2300 */ 2301 fxp_scb_wait(sc); 2302 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2303 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2304 2305 /* ...and wait for it to complete. */ 2306 for (count = 10000; count > 0; count--) { 2307 FXP_CDUCODESYNC(sc, 2308 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2309 status = le16toh(cbp->cb_status); 2310 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2311 if ((status & FXP_CB_STATUS_C) != 0) 2312 break; 2313 DELAY(2); 2314 } 2315 if (count == 0) { 2316 sc->sc_int_delay = 0; 2317 sc->sc_bundle_max = 0; 2318 log(LOG_WARNING, "%s: timeout loading microcode\n", 2319 device_xname(sc->sc_dev)); 2320 return; 2321 } 2322 2323 if (sc->sc_int_delay != fxp_int_delay || 2324 sc->sc_bundle_max != fxp_bundle_max) { 2325 sc->sc_int_delay = fxp_int_delay; 2326 sc->sc_bundle_max = fxp_bundle_max; 2327 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2328 "max bundle: %d\n", device_xname(sc->sc_dev), 2329 sc->sc_int_delay, 2330 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2331 } 2332 2333 sc->sc_flags |= FXPF_UCODE_LOADED; 2334 } 2335 2336 int 2337 fxp_enable(struct fxp_softc *sc) 2338 { 2339 2340 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2341 if ((*sc->sc_enable)(sc) != 0) { 2342 log(LOG_ERR, "%s: device enable failed\n", 2343 device_xname(sc->sc_dev)); 2344 return (EIO); 2345 } 2346 } 2347 2348 sc->sc_enabled = 1; 2349 return (0); 2350 } 2351 2352 void 2353 fxp_disable(struct fxp_softc *sc) 2354 { 2355 2356 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2357 (*sc->sc_disable)(sc); 2358 sc->sc_enabled = 0; 2359 } 2360 } 2361 2362 /* 2363 * fxp_activate: 2364 * 2365 * Handle device activation/deactivation requests. 2366 */ 2367 int 2368 fxp_activate(device_t self, enum devact act) 2369 { 2370 struct fxp_softc *sc = device_private(self); 2371 int s, error = 0; 2372 2373 s = splnet(); 2374 switch (act) { 2375 case DVACT_ACTIVATE: 2376 error = EOPNOTSUPP; 2377 break; 2378 2379 case DVACT_DEACTIVATE: 2380 if (sc->sc_flags & FXPF_MII) 2381 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2382 MII_OFFSET_ANY); 2383 if_deactivate(&sc->sc_ethercom.ec_if); 2384 break; 2385 } 2386 splx(s); 2387 2388 return (error); 2389 } 2390 2391 /* 2392 * fxp_detach: 2393 * 2394 * Detach an i82557 interface. 2395 */ 2396 int 2397 fxp_detach(struct fxp_softc *sc) 2398 { 2399 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2400 int i; 2401 2402 /* Succeed now if there's no work to do. */ 2403 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2404 return (0); 2405 2406 /* Unhook our tick handler. */ 2407 callout_stop(&sc->sc_callout); 2408 2409 if (sc->sc_flags & FXPF_MII) { 2410 /* Detach all PHYs */ 2411 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2412 } 2413 2414 /* Delete all remaining media. */ 2415 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2416 2417 #if NRND > 0 2418 rnd_detach_source(&sc->rnd_source); 2419 #endif 2420 ether_ifdetach(ifp); 2421 if_detach(ifp); 2422 2423 for (i = 0; i < FXP_NRFABUFS; i++) { 2424 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2425 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2426 } 2427 2428 for (i = 0; i < FXP_NTXCB; i++) { 2429 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2430 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2431 } 2432 2433 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2434 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2435 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2436 sizeof(struct fxp_control_data)); 2437 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2438 2439 return (0); 2440 } 2441
Indexes created Mon Sep 29 18:09:42 GMT 2025