i82557.c revision 1.12
1 /* $NetBSD: i82557.c,v 1.12 1999/11/12 18:14:18 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller. 71 */ 72 73 #include "opt_inet.h" 74 #include "opt_ns.h" 75 #include "bpfilter.h" 76 #include "rnd.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/ioctl.h> 85 #include <sys/errno.h> 86 #include <sys/device.h> 87 88 #include <vm/vm.h> /* for PAGE_SIZE */ 89 90 #if NRND > 0 91 #include <sys/rnd.h> 92 #endif 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #if NBPFILTER > 0 100 #include <net/bpf.h> 101 #endif 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/if_inarp.h> 106 #endif 107 108 #ifdef NS 109 #include <netns/ns.h> 110 #include <netns/ns_if.h> 111 #endif 112 113 #include <machine/bus.h> 114 #include <machine/intr.h> 115 116 #include <dev/mii/miivar.h> 117 118 #include <dev/ic/i82557reg.h> 119 #include <dev/ic/i82557var.h> 120 121 /* 122 * NOTE! On the Alpha, we have an alignment constraint. The 123 * card DMAs the packet immediately following the RFA. However, 124 * the first thing in the packet is a 14-byte Ethernet header. 125 * This means that the packet is misaligned. To compensate, 126 * we actually offset the RFA 2 bytes into the cluster. This 127 * alignes the packet after the Ethernet header at a 32-bit 128 * boundary. HOWEVER! This means that the RFA is misaligned! 129 */ 130 #define RFA_ALIGNMENT_FUDGE 2 131 132 /* 133 * Template for default configuration parameters. 134 * See struct fxp_cb_config for the bit definitions. 135 */ 136 u_int8_t fxp_cb_config_template[] = { 137 0x0, 0x0, /* cb_status */ 138 0x80, 0x2, /* cb_command */ 139 0xff, 0xff, 0xff, 0xff, /* link_addr */ 140 0x16, /* 0 */ 141 0x8, /* 1 */ 142 0x0, /* 2 */ 143 0x0, /* 3 */ 144 0x0, /* 4 */ 145 0x80, /* 5 */ 146 0xb2, /* 6 */ 147 0x3, /* 7 */ 148 0x1, /* 8 */ 149 0x0, /* 9 */ 150 0x26, /* 10 */ 151 0x0, /* 11 */ 152 0x60, /* 12 */ 153 0x0, /* 13 */ 154 0xf2, /* 14 */ 155 0x48, /* 15 */ 156 0x0, /* 16 */ 157 0x40, /* 17 */ 158 0xf3, /* 18 */ 159 0x0, /* 19 */ 160 0x3f, /* 20 */ 161 0x5 /* 21 */ 162 }; 163 164 void fxp_mii_initmedia __P((struct fxp_softc *)); 165 int fxp_mii_mediachange __P((struct ifnet *)); 166 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 167 168 void fxp_80c24_initmedia __P((struct fxp_softc *)); 169 int fxp_80c24_mediachange __P((struct ifnet *)); 170 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 inline void fxp_scb_wait __P((struct fxp_softc *)); 173 174 void fxp_start __P((struct ifnet *)); 175 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 176 int fxp_init __P((struct fxp_softc *)); 177 void fxp_rxdrain __P((struct fxp_softc *)); 178 void fxp_stop __P((struct fxp_softc *, int)); 179 void fxp_watchdog __P((struct ifnet *)); 180 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 181 int fxp_mdi_read __P((struct device *, int, int)); 182 void fxp_statchg __P((struct device *)); 183 void fxp_mdi_write __P((struct device *, int, int, int)); 184 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 185 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 186 void fxp_tick __P((void *)); 187 void fxp_mc_setup __P((struct fxp_softc *)); 188 189 void fxp_shutdown __P((void *)); 190 void fxp_power __P((int, void *)); 191 192 int fxp_copy_small = 0; 193 194 int fxp_enable __P((struct fxp_softc*)); 195 void fxp_disable __P((struct fxp_softc*)); 196 197 struct fxp_phytype { 198 int fp_phy; /* type of PHY, -1 for MII at the end. */ 199 void (*fp_init) __P((struct fxp_softc *)); 200 } fxp_phytype_table[] = { 201 { FXP_PHY_80C24, fxp_80c24_initmedia }, 202 { -1, fxp_mii_initmedia }, 203 }; 204 205 /* 206 * Set initial transmit threshold at 64 (512 bytes). This is 207 * increased by 64 (512 bytes) at a time, to maximum of 192 208 * (1536 bytes), if an underrun occurs. 209 */ 210 static int tx_threshold = 64; 211 212 /* 213 * Wait for the previous command to be accepted (but not necessarily 214 * completed). 215 */ 216 inline void 217 fxp_scb_wait(sc) 218 struct fxp_softc *sc; 219 { 220 int i = 10000; 221 222 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 223 delay(2); 224 if (i == 0) 225 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 226 } 227 228 /* 229 * Finish attaching an i82557 interface. Called by bus-specific front-end. 230 */ 231 void 232 fxp_attach(sc) 233 struct fxp_softc *sc; 234 { 235 u_int8_t enaddr[6]; 236 struct ifnet *ifp; 237 bus_dma_segment_t seg; 238 int rseg, i, error; 239 struct fxp_phytype *fp; 240 241 /* 242 * Allocate the control data structures, and create and load the 243 * DMA map for it. 244 */ 245 if ((error = bus_dmamem_alloc(sc->sc_dmat, 246 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 247 0)) != 0) { 248 printf("%s: unable to allocate control data, error = %d\n", 249 sc->sc_dev.dv_xname, error); 250 goto fail_0; 251 } 252 253 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 254 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 255 BUS_DMA_COHERENT)) != 0) { 256 printf("%s: unable to map control data, error = %d\n", 257 sc->sc_dev.dv_xname, error); 258 goto fail_1; 259 } 260 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 261 262 if ((error = bus_dmamap_create(sc->sc_dmat, 263 sizeof(struct fxp_control_data), 1, 264 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 265 printf("%s: unable to create control data DMA map, " 266 "error = %d\n", sc->sc_dev.dv_xname, error); 267 goto fail_2; 268 } 269 270 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 271 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 272 0)) != 0) { 273 printf("%s: can't load control data DMA map, error = %d\n", 274 sc->sc_dev.dv_xname, error); 275 goto fail_3; 276 } 277 278 /* 279 * Create the transmit buffer DMA maps. 280 */ 281 for (i = 0; i < FXP_NTXCB; i++) { 282 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 283 FXP_NTXSEG, MCLBYTES, 0, 0, 284 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 285 printf("%s: unable to create tx DMA map %d, " 286 "error = %d\n", sc->sc_dev.dv_xname, i, error); 287 goto fail_4; 288 } 289 } 290 291 /* 292 * Create the receive buffer DMA maps. 293 */ 294 for (i = 0; i < FXP_NRFABUFS; i++) { 295 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 296 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 297 printf("%s: unable to create rx DMA map %d, " 298 "error = %d\n", sc->sc_dev.dv_xname, i, error); 299 goto fail_5; 300 } 301 } 302 303 /* Initialize MAC address and media structures. */ 304 fxp_get_info(sc, enaddr); 305 306 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 307 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 308 309 ifp = &sc->sc_ethercom.ec_if; 310 311 /* 312 * Get info about our media interface, and initialize it. Note 313 * the table terminates itself with a phy of -1, indicating 314 * that we're using MII. 315 */ 316 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 317 if (fp->fp_phy == sc->phy_primary_device) 318 break; 319 (*fp->fp_init)(sc); 320 321 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 322 ifp->if_softc = sc; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_ioctl = fxp_ioctl; 325 ifp->if_start = fxp_start; 326 ifp->if_watchdog = fxp_watchdog; 327 328 /* 329 * Attach the interface. 330 */ 331 if_attach(ifp); 332 ether_ifattach(ifp, enaddr); 333 #if NBPFILTER > 0 334 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 335 sizeof(struct ether_header)); 336 #endif 337 #if NRND > 0 338 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 339 RND_TYPE_NET, 0); 340 #endif 341 342 /* 343 * Add shutdown hook so that DMA is disabled prior to reboot. Not 344 * doing do could allow DMA to corrupt kernel memory during the 345 * reboot before the driver initializes. 346 */ 347 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 348 if (sc->sc_sdhook == NULL) 349 printf("%s: WARNING: unable to establish shutdown hook\n", 350 sc->sc_dev.dv_xname); 351 /* 352 * Add suspend hook, for similar reasons.. 353 */ 354 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 355 if (sc->sc_powerhook == NULL) 356 printf("%s: WARNING: unable to establish power hook\n", 357 sc->sc_dev.dv_xname); 358 return; 359 360 /* 361 * Free any resources we've allocated during the failed attach 362 * attempt. Do this in reverse order and fall though. 363 */ 364 fail_5: 365 for (i = 0; i < FXP_NRFABUFS; i++) { 366 if (sc->sc_rxmaps[i] != NULL) 367 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 368 } 369 fail_4: 370 for (i = 0; i < FXP_NTXCB; i++) { 371 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 372 bus_dmamap_destroy(sc->sc_dmat, 373 FXP_DSTX(sc, i)->txs_dmamap); 374 } 375 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 376 fail_3: 377 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 378 fail_2: 379 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 380 sizeof(struct fxp_control_data)); 381 fail_1: 382 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 383 fail_0: 384 return; 385 } 386 387 void 388 fxp_mii_initmedia(sc) 389 struct fxp_softc *sc; 390 { 391 392 sc->sc_flags |= FXPF_MII; 393 394 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 395 sc->sc_mii.mii_readreg = fxp_mdi_read; 396 sc->sc_mii.mii_writereg = fxp_mdi_write; 397 sc->sc_mii.mii_statchg = fxp_statchg; 398 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 399 fxp_mii_mediastatus); 400 mii_phy_probe(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 401 MII_OFFSET_ANY); 402 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 403 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 404 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 405 } else 406 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 407 } 408 409 void 410 fxp_80c24_initmedia(sc) 411 struct fxp_softc *sc; 412 { 413 414 /* 415 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 416 * doesn't have a programming interface of any sort. The 417 * media is sensed automatically based on how the link partner 418 * is configured. This is, in essence, manual configuration. 419 */ 420 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 421 sc->sc_dev.dv_xname); 422 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 423 fxp_80c24_mediastatus); 424 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 425 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 426 } 427 428 /* 429 * Device shutdown routine. Called at system shutdown after sync. The 430 * main purpose of this routine is to shut off receiver DMA so that 431 * kernel memory doesn't get clobbered during warmboot. 432 */ 433 void 434 fxp_shutdown(arg) 435 void *arg; 436 { 437 struct fxp_softc *sc = arg; 438 439 /* 440 * Since the system's going to halt shortly, don't bother 441 * freeing mbufs. 442 */ 443 fxp_stop(sc, 0); 444 } 445 /* 446 * Power handler routine. Called when the system is transitioning 447 * into/out of power save modes. As with fxp_shutdown, the main 448 * purpose of this routine is to shut off receiver DMA so it doesn't 449 * clobber kernel memory at the wrong time. 450 */ 451 void 452 fxp_power(why, arg) 453 int why; 454 void *arg; 455 { 456 struct fxp_softc *sc = arg; 457 struct ifnet *ifp; 458 int s; 459 460 s = splnet(); 461 if (why != PWR_RESUME) 462 fxp_stop(sc, 0); 463 else { 464 ifp = &sc->sc_ethercom.ec_if; 465 if (ifp->if_flags & IFF_UP) 466 fxp_init(sc); 467 } 468 splx(s); 469 } 470 471 /* 472 * Initialize the interface media. 473 */ 474 void 475 fxp_get_info(sc, enaddr) 476 struct fxp_softc *sc; 477 u_int8_t *enaddr; 478 { 479 u_int16_t data, myea[3]; 480 481 /* 482 * Reset to a stable state. 483 */ 484 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 485 DELAY(10); 486 487 /* 488 * Figure out EEPROM size. 489 * 490 * Cards can have either 64-word or 256-word EEPROMs, with 491 * addresses fed in using a bit-at-a-time protocol, MSB first. 492 * 493 * XXX this is probably not the best way to do this; the linux 494 * driver does a checksum of the eeprom, but there is 495 * (AFAIK) no on-line documentation on what this checksum 496 * should look like (you could just steal the code from 497 * linux, but that's cheating); for now we just use the fact 498 * that the upper two bits of word 10 should be 01 499 */ 500 for(sc->sc_eeprom_size = 6; 501 sc->sc_eeprom_size <= 8; 502 sc->sc_eeprom_size += 2) { 503 fxp_read_eeprom(sc, &data, 10, 1); 504 if((data & 0xc000) == 0x4000) 505 break; 506 } 507 if(sc->sc_eeprom_size > 8) 508 panic("%s: failed to get EEPROM size", sc->sc_dev.dv_xname); 509 #ifdef DEBUG 510 printf("%s: assuming %d word EEPROM\n", 511 sc->sc_dev.dv_xname, 512 1 << sc->sc_eeprom_size); 513 #endif 514 515 /* 516 * Get info about the primary PHY 517 */ 518 fxp_read_eeprom(sc, &data, 6, 1); 519 sc->phy_primary_addr = data & 0xff; 520 sc->phy_primary_device = (data >> 8) & 0x3f; 521 sc->phy_10Mbps_only = data >> 15; 522 523 /* 524 * Read MAC address. 525 */ 526 fxp_read_eeprom(sc, myea, 0, 3); 527 bcopy(myea, enaddr, ETHER_ADDR_LEN); 528 } 529 530 /* 531 * Read from the serial EEPROM. Basically, you manually shift in 532 * the read opcode (one bit at a time) and then shift in the address, 533 * and then you shift out the data (all of this one bit at a time). 534 * The word size is 16 bits, so you have to provide the address for 535 * every 16 bits of data. 536 */ 537 void 538 fxp_read_eeprom(sc, data, offset, words) 539 struct fxp_softc *sc; 540 u_int16_t *data; 541 int offset; 542 int words; 543 { 544 u_int16_t reg; 545 int i, x; 546 547 for (i = 0; i < words; i++) { 548 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 549 /* 550 * Shift in read opcode. 551 */ 552 for (x = 3; x > 0; x--) { 553 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 554 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 555 } else { 556 reg = FXP_EEPROM_EECS; 557 } 558 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 559 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 560 reg | FXP_EEPROM_EESK); 561 DELAY(1); 562 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 563 DELAY(1); 564 } 565 /* 566 * Shift in address. 567 */ 568 for (x = sc->sc_eeprom_size; x > 0; x--) { 569 if ((i + offset) & (1 << (x - 1))) { 570 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 571 } else { 572 reg = FXP_EEPROM_EECS; 573 } 574 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 575 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 576 reg | FXP_EEPROM_EESK); 577 DELAY(1); 578 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 579 DELAY(1); 580 } 581 reg = FXP_EEPROM_EECS; 582 data[i] = 0; 583 /* 584 * Shift out data. 585 */ 586 for (x = 16; x > 0; x--) { 587 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 588 reg | FXP_EEPROM_EESK); 589 DELAY(1); 590 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 591 FXP_EEPROM_EEDO) 592 data[i] |= (1 << (x - 1)); 593 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 594 DELAY(1); 595 } 596 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 597 DELAY(1); 598 } 599 } 600 601 /* 602 * Start packet transmission on the interface. 603 */ 604 void 605 fxp_start(ifp) 606 struct ifnet *ifp; 607 { 608 struct fxp_softc *sc = ifp->if_softc; 609 struct mbuf *m0, *m; 610 struct fxp_cb_tx *txd; 611 struct fxp_txsoft *txs; 612 struct fxp_tbdlist *tbd; 613 bus_dmamap_t dmamap; 614 int error, lasttx, nexttx, opending, seg; 615 616 /* 617 * If we want a re-init, bail out now. 618 */ 619 if (sc->sc_flags & FXPF_WANTINIT) { 620 ifp->if_flags |= IFF_OACTIVE; 621 return; 622 } 623 624 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 625 return; 626 627 /* 628 * Remember the previous txpending and the current lasttx. 629 */ 630 opending = sc->sc_txpending; 631 lasttx = sc->sc_txlast; 632 633 /* 634 * Loop through the send queue, setting up transmit descriptors 635 * until we drain the queue, or use up all available transmit 636 * descriptors. 637 */ 638 while (sc->sc_txpending < FXP_NTXCB) { 639 /* 640 * Grab a packet off the queue. 641 */ 642 IF_DEQUEUE(&ifp->if_snd, m0); 643 if (m0 == NULL) 644 break; 645 646 /* 647 * Get the next available transmit descriptor. 648 */ 649 nexttx = FXP_NEXTTX(sc->sc_txlast); 650 txd = FXP_CDTX(sc, nexttx); 651 tbd = FXP_CDTBD(sc, nexttx); 652 txs = FXP_DSTX(sc, nexttx); 653 dmamap = txs->txs_dmamap; 654 655 /* 656 * Load the DMA map. If this fails, the packet either 657 * didn't fit in the allotted number of frags, or we were 658 * short on resources. In this case, we'll copy and try 659 * again. 660 */ 661 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 662 BUS_DMA_NOWAIT) != 0) { 663 MGETHDR(m, M_DONTWAIT, MT_DATA); 664 if (m == NULL) { 665 printf("%s: unable to allocate Tx mbuf\n", 666 sc->sc_dev.dv_xname); 667 IF_PREPEND(&ifp->if_snd, m0); 668 break; 669 } 670 if (m0->m_pkthdr.len > MHLEN) { 671 MCLGET(m, M_DONTWAIT); 672 if ((m->m_flags & M_EXT) == 0) { 673 printf("%s: unable to allocate Tx " 674 "cluster\n", sc->sc_dev.dv_xname); 675 m_freem(m); 676 IF_PREPEND(&ifp->if_snd, m0); 677 break; 678 } 679 } 680 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 681 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 682 m_freem(m0); 683 m0 = m; 684 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 685 m0, BUS_DMA_NOWAIT); 686 if (error) { 687 printf("%s: unable to load Tx buffer, " 688 "error = %d\n", sc->sc_dev.dv_xname, error); 689 IF_PREPEND(&ifp->if_snd, m0); 690 break; 691 } 692 } 693 694 /* Initialize the fraglist. */ 695 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 696 tbd->tbd_d[seg].tb_addr = 697 dmamap->dm_segs[seg].ds_addr; 698 tbd->tbd_d[seg].tb_size = 699 dmamap->dm_segs[seg].ds_len; 700 } 701 702 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 703 704 /* Sync the DMA map. */ 705 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 706 BUS_DMASYNC_PREWRITE); 707 708 /* 709 * Store a pointer to the packet so we can free it later. 710 */ 711 txs->txs_mbuf = m0; 712 713 /* 714 * Initialize the transmit descriptor. 715 */ 716 txd->cb_status = 0; 717 txd->cb_command = 718 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF; 719 txd->tx_threshold = tx_threshold; 720 txd->tbd_number = dmamap->dm_nsegs; 721 722 FXP_CDTXSYNC(sc, nexttx, 723 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 724 725 /* Advance the tx pointer. */ 726 sc->sc_txpending++; 727 sc->sc_txlast = nexttx; 728 729 #if NBPFILTER > 0 730 /* 731 * Pass packet to bpf if there is a listener. 732 */ 733 if (ifp->if_bpf) 734 bpf_mtap(ifp->if_bpf, m0); 735 #endif 736 } 737 738 if (sc->sc_txpending == FXP_NTXCB) { 739 /* No more slots; notify upper layer. */ 740 ifp->if_flags |= IFF_OACTIVE; 741 } 742 743 if (sc->sc_txpending != opending) { 744 /* 745 * We enqueued packets. If the transmitter was idle, 746 * reset the txdirty pointer. 747 */ 748 if (opending == 0) 749 sc->sc_txdirty = FXP_NEXTTX(lasttx); 750 751 /* 752 * Cause the chip to interrupt and suspend command 753 * processing once the last packet we've enqueued 754 * has been transmitted. 755 */ 756 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 757 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S; 758 FXP_CDTXSYNC(sc, sc->sc_txlast, 759 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 760 761 /* 762 * The entire packet chain is set up. Clear the suspend bit 763 * on the command prior to the first packet we set up. 764 */ 765 FXP_CDTXSYNC(sc, lasttx, 766 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 767 FXP_CDTX(sc, lasttx)->cb_command &= ~FXP_CB_COMMAND_S; 768 FXP_CDTXSYNC(sc, lasttx, 769 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 770 771 /* 772 * Issue a Resume command in case the chip was suspended. 773 */ 774 fxp_scb_wait(sc); 775 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 776 777 /* Set a watchdog timer in case the chip flakes out. */ 778 ifp->if_timer = 5; 779 } 780 } 781 782 /* 783 * Process interface interrupts. 784 */ 785 int 786 fxp_intr(arg) 787 void *arg; 788 { 789 struct fxp_softc *sc = arg; 790 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 791 struct fxp_cb_tx *txd; 792 struct fxp_txsoft *txs; 793 struct mbuf *m, *m0; 794 bus_dmamap_t rxmap; 795 struct fxp_rfa *rfa; 796 struct ether_header *eh; 797 int i, claimed = 0; 798 u_int16_t len; 799 u_int8_t statack; 800 801 /* 802 * If the interface isn't running, don't try to 803 * service the interrupt.. just ack it and bail. 804 */ 805 if ((ifp->if_flags & IFF_RUNNING) == 0) { 806 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 807 if (statack) { 808 claimed = 1; 809 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 810 } 811 return claimed; 812 } 813 814 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 815 claimed = 1; 816 817 /* 818 * First ACK all the interrupts in this pass. 819 */ 820 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 821 822 /* 823 * Process receiver interrupts. If a no-resource (RNR) 824 * condition exists, get whatever packets we can and 825 * re-start the receiver. 826 */ 827 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 828 rcvloop: 829 m = sc->sc_rxq.ifq_head; 830 rfa = FXP_MTORFA(m); 831 rxmap = M_GETCTX(m, bus_dmamap_t); 832 833 FXP_RFASYNC(sc, m, 834 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 835 836 if ((rfa->rfa_status & FXP_RFA_STATUS_C) == 0) { 837 /* 838 * We have processed all of the 839 * receive buffers. 840 */ 841 goto do_transmit; 842 } 843 844 IF_DEQUEUE(&sc->sc_rxq, m); 845 846 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 847 848 len = rfa->actual_size & (m->m_ext.ext_size - 1); 849 850 if (len < sizeof(struct ether_header)) { 851 /* 852 * Runt packet; drop it now. 853 */ 854 FXP_INIT_RFABUF(sc, m); 855 goto rcvloop; 856 } 857 858 /* 859 * If the packet is small enough to fit in a 860 * single header mbuf, allocate one and copy 861 * the data into it. This greatly reduces 862 * memory consumption when we receive lots 863 * of small packets. 864 * 865 * Otherwise, we add a new buffer to the receive 866 * chain. If this fails, we drop the packet and 867 * recycle the old buffer. 868 */ 869 if (fxp_copy_small != 0 && len <= MHLEN) { 870 MGETHDR(m0, M_DONTWAIT, MT_DATA); 871 if (m == NULL) 872 goto dropit; 873 memcpy(mtod(m0, caddr_t), 874 mtod(m, caddr_t), len); 875 FXP_INIT_RFABUF(sc, m); 876 m = m0; 877 } else { 878 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 879 dropit: 880 ifp->if_ierrors++; 881 FXP_INIT_RFABUF(sc, m); 882 goto rcvloop; 883 } 884 } 885 886 m->m_pkthdr.rcvif = ifp; 887 m->m_pkthdr.len = m->m_len = len; 888 eh = mtod(m, struct ether_header *); 889 890 #if NBPFILTER > 0 891 /* 892 * Pass this up to any BPF listeners, but only 893 * pass it up the stack it its for us. 894 */ 895 if (ifp->if_bpf) { 896 bpf_mtap(ifp->if_bpf, m); 897 898 if ((ifp->if_flags & IFF_PROMISC) != 0 && 899 (rfa->rfa_status & 900 FXP_RFA_STATUS_IAMATCH) != 0 && 901 (eh->ether_dhost[0] & 1) == 0) { 902 m_freem(m); 903 goto rcvloop; 904 } 905 } 906 #endif /* NBPFILTER > 0 */ 907 908 /* Pass it on. */ 909 (*ifp->if_input)(ifp, m); 910 goto rcvloop; 911 } 912 913 do_transmit: 914 if (statack & FXP_SCB_STATACK_RNR) { 915 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 916 fxp_scb_wait(sc); 917 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 918 rxmap->dm_segs[0].ds_addr + 919 RFA_ALIGNMENT_FUDGE); 920 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 921 FXP_SCB_COMMAND_RU_START); 922 } 923 924 /* 925 * Free any finished transmit mbuf chains. 926 */ 927 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 928 ifp->if_flags &= ~IFF_OACTIVE; 929 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 930 i = FXP_NEXTTX(i), sc->sc_txpending--) { 931 txd = FXP_CDTX(sc, i); 932 txs = FXP_DSTX(sc, i); 933 934 FXP_CDTXSYNC(sc, i, 935 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 936 937 if ((txd->cb_status & FXP_CB_STATUS_C) == 0) 938 break; 939 940 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 941 942 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 943 0, txs->txs_dmamap->dm_mapsize, 944 BUS_DMASYNC_POSTWRITE); 945 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 946 m_freem(txs->txs_mbuf); 947 txs->txs_mbuf = NULL; 948 } 949 950 /* Update the dirty transmit buffer pointer. */ 951 sc->sc_txdirty = i; 952 953 /* 954 * Cancel the watchdog timer if there are no pending 955 * transmissions. 956 */ 957 if (sc->sc_txpending == 0) { 958 ifp->if_timer = 0; 959 960 /* 961 * If we want a re-init, do that now. 962 */ 963 if (sc->sc_flags & FXPF_WANTINIT) 964 (void) fxp_init(sc); 965 } 966 967 /* 968 * Try to get more packets going. 969 */ 970 fxp_start(ifp); 971 } 972 } 973 974 #if NRND > 0 975 if (claimed) 976 rnd_add_uint32(&sc->rnd_source, statack); 977 #endif 978 return (claimed); 979 } 980 981 /* 982 * Update packet in/out/collision statistics. The i82557 doesn't 983 * allow you to access these counters without doing a fairly 984 * expensive DMA to get _all_ of the statistics it maintains, so 985 * we do this operation here only once per second. The statistics 986 * counters in the kernel are updated from the previous dump-stats 987 * DMA and then a new dump-stats DMA is started. The on-chip 988 * counters are zeroed when the DMA completes. If we can't start 989 * the DMA immediately, we don't wait - we just prepare to read 990 * them again next time. 991 */ 992 void 993 fxp_tick(arg) 994 void *arg; 995 { 996 struct fxp_softc *sc = arg; 997 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 998 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 999 int s; 1000 1001 s = splnet(); 1002 1003 ifp->if_opackets += sp->tx_good; 1004 ifp->if_collisions += sp->tx_total_collisions; 1005 if (sp->rx_good) { 1006 ifp->if_ipackets += sp->rx_good; 1007 sc->sc_rxidle = 0; 1008 } else { 1009 sc->sc_rxidle++; 1010 } 1011 ifp->if_ierrors += 1012 sp->rx_crc_errors + 1013 sp->rx_alignment_errors + 1014 sp->rx_rnr_errors + 1015 sp->rx_overrun_errors; 1016 /* 1017 * If any transmit underruns occured, bump up the transmit 1018 * threshold by another 512 bytes (64 * 8). 1019 */ 1020 if (sp->tx_underruns) { 1021 ifp->if_oerrors += sp->tx_underruns; 1022 if (tx_threshold < 192) 1023 tx_threshold += 64; 1024 } 1025 1026 /* 1027 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1028 * then assume the receiver has locked up and attempt to clear 1029 * the condition by reprogramming the multicast filter (actually, 1030 * resetting the interface). This is a work-around for a bug in 1031 * the 82557 where the receiver locks up if it gets certain types 1032 * of garbage in the syncronization bits prior to the packet header. 1033 * This bug is supposed to only occur in 10Mbps mode, but has been 1034 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1035 * speed transition). 1036 */ 1037 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1038 (void) fxp_init(sc); 1039 splx(s); 1040 return; 1041 } 1042 /* 1043 * If there is no pending command, start another stats 1044 * dump. Otherwise punt for now. 1045 */ 1046 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1047 /* 1048 * Start another stats dump. 1049 */ 1050 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1051 FXP_SCB_COMMAND_CU_DUMPRESET); 1052 } else { 1053 /* 1054 * A previous command is still waiting to be accepted. 1055 * Just zero our copy of the stats and wait for the 1056 * next timer event to update them. 1057 */ 1058 sp->tx_good = 0; 1059 sp->tx_underruns = 0; 1060 sp->tx_total_collisions = 0; 1061 1062 sp->rx_good = 0; 1063 sp->rx_crc_errors = 0; 1064 sp->rx_alignment_errors = 0; 1065 sp->rx_rnr_errors = 0; 1066 sp->rx_overrun_errors = 0; 1067 } 1068 1069 if (sc->sc_flags & FXPF_MII) { 1070 /* Tick the MII clock. */ 1071 mii_tick(&sc->sc_mii); 1072 } 1073 1074 splx(s); 1075 1076 /* 1077 * Schedule another timeout one second from now. 1078 */ 1079 timeout(fxp_tick, sc, hz); 1080 } 1081 1082 /* 1083 * Drain the receive queue. 1084 */ 1085 void 1086 fxp_rxdrain(sc) 1087 struct fxp_softc *sc; 1088 { 1089 bus_dmamap_t rxmap; 1090 struct mbuf *m; 1091 1092 for (;;) { 1093 IF_DEQUEUE(&sc->sc_rxq, m); 1094 if (m == NULL) 1095 break; 1096 rxmap = M_GETCTX(m, bus_dmamap_t); 1097 bus_dmamap_unload(sc->sc_dmat, rxmap); 1098 FXP_RXMAP_PUT(sc, rxmap); 1099 m_freem(m); 1100 } 1101 } 1102 1103 /* 1104 * Stop the interface. Cancels the statistics updater and resets 1105 * the interface. 1106 */ 1107 void 1108 fxp_stop(sc, drain) 1109 struct fxp_softc *sc; 1110 int drain; 1111 { 1112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1113 struct fxp_txsoft *txs; 1114 int i; 1115 1116 /* 1117 * Turn down interface (done early to avoid bad interactions 1118 * between panics, shutdown hooks, and the watchdog timer) 1119 */ 1120 ifp->if_timer = 0; 1121 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1122 1123 /* 1124 * Cancel stats updater. 1125 */ 1126 untimeout(fxp_tick, sc); 1127 if (sc->sc_flags & FXPF_MII) { 1128 /* Down the MII. */ 1129 mii_down(&sc->sc_mii); 1130 } 1131 1132 /* 1133 * Issue software reset 1134 */ 1135 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1136 DELAY(10); 1137 1138 /* 1139 * Release any xmit buffers. 1140 */ 1141 for (i = 0; i < FXP_NTXCB; i++) { 1142 txs = FXP_DSTX(sc, i); 1143 if (txs->txs_mbuf != NULL) { 1144 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1145 m_freem(txs->txs_mbuf); 1146 txs->txs_mbuf = NULL; 1147 } 1148 } 1149 sc->sc_txpending = 0; 1150 1151 if (drain) { 1152 /* 1153 * Release the receive buffers. 1154 */ 1155 fxp_rxdrain(sc); 1156 } 1157 1158 } 1159 1160 /* 1161 * Watchdog/transmission transmit timeout handler. Called when a 1162 * transmission is started on the interface, but no interrupt is 1163 * received before the timeout. This usually indicates that the 1164 * card has wedged for some reason. 1165 */ 1166 void 1167 fxp_watchdog(ifp) 1168 struct ifnet *ifp; 1169 { 1170 struct fxp_softc *sc = ifp->if_softc; 1171 1172 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1173 ifp->if_oerrors++; 1174 1175 (void) fxp_init(sc); 1176 } 1177 1178 /* 1179 * Initialize the interface. Must be called at splnet(). 1180 */ 1181 int 1182 fxp_init(sc) 1183 struct fxp_softc *sc; 1184 { 1185 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1186 struct fxp_cb_config *cbp; 1187 struct fxp_cb_ias *cb_ias; 1188 struct fxp_cb_tx *txd; 1189 bus_dmamap_t rxmap; 1190 int i, prm, allm, error = 0; 1191 1192 /* 1193 * Cancel any pending I/O 1194 */ 1195 fxp_stop(sc, 0); 1196 1197 sc->sc_flags = 0; 1198 1199 /* 1200 * Initialize base of CBL and RFA memory. Loading with zero 1201 * sets it up for regular linear addressing. 1202 */ 1203 fxp_scb_wait(sc); 1204 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1205 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1206 1207 fxp_scb_wait(sc); 1208 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1209 1210 /* 1211 * Initialize the multicast filter. Do this now, since we might 1212 * have to setup the config block differently. 1213 */ 1214 fxp_mc_setup(sc); 1215 1216 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1217 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1218 1219 /* 1220 * Initialize base of dump-stats buffer. 1221 */ 1222 fxp_scb_wait(sc); 1223 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1224 sc->sc_cddma + FXP_CDSTATSOFF); 1225 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1226 1227 cbp = &sc->sc_control_data->fcd_configcb; 1228 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1229 1230 /* 1231 * This copy is kind of disgusting, but there are a bunch of must be 1232 * zero and must be one bits in this structure and this is the easiest 1233 * way to initialize them all to proper values. 1234 */ 1235 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1236 1237 cbp->cb_status = 0; 1238 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1239 cbp->link_addr = -1; /* (no) next command */ 1240 cbp->byte_count = 22; /* (22) bytes to config */ 1241 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1242 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1243 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1244 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1245 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1246 cbp->dma_bce = 0; /* (disable) dma max counters */ 1247 cbp->late_scb = 0; /* (don't) defer SCB update */ 1248 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1249 cbp->ci_int = 1; /* interrupt on CU idle */ 1250 cbp->save_bf = prm; /* save bad frames */ 1251 cbp->disc_short_rx = !prm; /* discard short packets */ 1252 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1253 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1254 cbp->nsai = 1; /* (don't) disable source addr insert */ 1255 cbp->preamble_length = 2; /* (7 byte) preamble */ 1256 cbp->loopback = 0; /* (don't) loopback */ 1257 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1258 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1259 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1260 cbp->promiscuous = prm; /* promiscuous mode */ 1261 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1262 cbp->crscdt = 0; /* (CRS only) */ 1263 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1264 cbp->padding = 1; /* (do) pad short tx packets */ 1265 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1266 cbp->force_fdx = 0; /* (don't) force full duplex */ 1267 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1268 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1269 cbp->mc_all = allm; /* accept all multicasts */ 1270 1271 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1272 1273 /* 1274 * Start the config command/DMA. 1275 */ 1276 fxp_scb_wait(sc); 1277 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1278 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1279 /* ...and wait for it to complete. */ 1280 do { 1281 FXP_CDCONFIGSYNC(sc, 1282 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1283 } while ((cbp->cb_status & FXP_CB_STATUS_C) == 0); 1284 1285 /* 1286 * Initialize the station address. 1287 */ 1288 cb_ias = &sc->sc_control_data->fcd_iascb; 1289 cb_ias->cb_status = 0; 1290 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1291 cb_ias->link_addr = -1; 1292 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1293 1294 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1295 1296 /* 1297 * Start the IAS (Individual Address Setup) command/DMA. 1298 */ 1299 fxp_scb_wait(sc); 1300 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1301 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1302 /* ...and wait for it to complete. */ 1303 do { 1304 FXP_CDIASSYNC(sc, 1305 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1306 } while ((cb_ias->cb_status & FXP_CB_STATUS_C) == 0); 1307 1308 /* 1309 * Initialize the transmit descriptor ring. txlast is initialized 1310 * to the end of the list so that it will wrap around to the first 1311 * descriptor when the first packet is transmitted. 1312 */ 1313 for (i = 0; i < FXP_NTXCB; i++) { 1314 txd = FXP_CDTX(sc, i); 1315 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1316 txd->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1317 txd->tbd_array_addr = FXP_CDTBDADDR(sc, i); 1318 txd->link_addr = FXP_CDTXADDR(sc, FXP_NEXTTX(i)); 1319 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1320 } 1321 sc->sc_txpending = 0; 1322 sc->sc_txdirty = 0; 1323 sc->sc_txlast = FXP_NTXCB - 1; 1324 1325 /* 1326 * Initialize the receive buffer list. 1327 */ 1328 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1329 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1330 rxmap = FXP_RXMAP_GET(sc); 1331 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1332 printf("%s: unable to allocate or map rx " 1333 "buffer %d, error = %d\n", 1334 sc->sc_dev.dv_xname, 1335 sc->sc_rxq.ifq_len, error); 1336 /* 1337 * XXX Should attempt to run with fewer receive 1338 * XXX buffers instead of just failing. 1339 */ 1340 FXP_RXMAP_PUT(sc, rxmap); 1341 fxp_rxdrain(sc); 1342 goto out; 1343 } 1344 } 1345 sc->sc_rxidle = 0; 1346 1347 /* 1348 * Give the transmit ring to the chip. We do this by pointing 1349 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1350 * issuing a start command. It will execute the NOP and then 1351 * suspend, pointing at the first descriptor. 1352 */ 1353 fxp_scb_wait(sc); 1354 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1355 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1356 1357 /* 1358 * Initialize receiver buffer area - RFA. 1359 */ 1360 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1361 fxp_scb_wait(sc); 1362 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1363 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1364 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1365 1366 if (sc->sc_flags & FXPF_MII) { 1367 /* 1368 * Set current media. 1369 */ 1370 mii_mediachg(&sc->sc_mii); 1371 } 1372 1373 /* 1374 * ...all done! 1375 */ 1376 ifp->if_flags |= IFF_RUNNING; 1377 ifp->if_flags &= ~IFF_OACTIVE; 1378 1379 /* 1380 * Start the one second timer. 1381 */ 1382 timeout(fxp_tick, sc, hz); 1383 1384 /* 1385 * Attempt to start output on the interface. 1386 */ 1387 fxp_start(ifp); 1388 1389 out: 1390 if (error) 1391 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1392 return (error); 1393 } 1394 1395 /* 1396 * Change media according to request. 1397 */ 1398 int 1399 fxp_mii_mediachange(ifp) 1400 struct ifnet *ifp; 1401 { 1402 struct fxp_softc *sc = ifp->if_softc; 1403 1404 if (ifp->if_flags & IFF_UP) 1405 mii_mediachg(&sc->sc_mii); 1406 return (0); 1407 } 1408 1409 /* 1410 * Notify the world which media we're using. 1411 */ 1412 void 1413 fxp_mii_mediastatus(ifp, ifmr) 1414 struct ifnet *ifp; 1415 struct ifmediareq *ifmr; 1416 { 1417 struct fxp_softc *sc = ifp->if_softc; 1418 1419 if(sc->sc_enabled == 0) { 1420 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1421 ifmr->ifm_status = 0; 1422 return; 1423 } 1424 1425 mii_pollstat(&sc->sc_mii); 1426 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1427 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1428 } 1429 1430 int 1431 fxp_80c24_mediachange(ifp) 1432 struct ifnet *ifp; 1433 { 1434 1435 /* Nothing to do here. */ 1436 return (0); 1437 } 1438 1439 void 1440 fxp_80c24_mediastatus(ifp, ifmr) 1441 struct ifnet *ifp; 1442 struct ifmediareq *ifmr; 1443 { 1444 struct fxp_softc *sc = ifp->if_softc; 1445 1446 /* 1447 * Media is currently-selected media. We cannot determine 1448 * the link status. 1449 */ 1450 ifmr->ifm_status = 0; 1451 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1452 } 1453 1454 /* 1455 * Add a buffer to the end of the RFA buffer list. 1456 * Return 0 if successful, error code on failure. 1457 * 1458 * The RFA struct is stuck at the beginning of mbuf cluster and the 1459 * data pointer is fixed up to point just past it. 1460 */ 1461 int 1462 fxp_add_rfabuf(sc, rxmap, unload) 1463 struct fxp_softc *sc; 1464 bus_dmamap_t rxmap; 1465 int unload; 1466 { 1467 struct mbuf *m; 1468 int error; 1469 1470 MGETHDR(m, M_DONTWAIT, MT_DATA); 1471 if (m == NULL) 1472 return (ENOBUFS); 1473 1474 MCLGET(m, M_DONTWAIT); 1475 if ((m->m_flags & M_EXT) == 0) { 1476 m_freem(m); 1477 return (ENOBUFS); 1478 } 1479 1480 if (unload) 1481 bus_dmamap_unload(sc->sc_dmat, rxmap); 1482 1483 M_SETCTX(m, rxmap); 1484 1485 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1486 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1487 if (error) { 1488 printf("%s: can't load rx DMA map %d, error = %d\n", 1489 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1490 panic("fxp_add_rfabuf"); /* XXX */ 1491 } 1492 1493 FXP_INIT_RFABUF(sc, m); 1494 1495 return (0); 1496 } 1497 1498 volatile int 1499 fxp_mdi_read(self, phy, reg) 1500 struct device *self; 1501 int phy; 1502 int reg; 1503 { 1504 struct fxp_softc *sc = (struct fxp_softc *)self; 1505 int count = 10000; 1506 int value; 1507 1508 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1509 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1510 1511 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1512 && count--) 1513 DELAY(10); 1514 1515 if (count <= 0) 1516 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1517 1518 return (value & 0xffff); 1519 } 1520 1521 void 1522 fxp_statchg(self) 1523 struct device *self; 1524 { 1525 1526 /* XXX Update ifp->if_baudrate */ 1527 } 1528 1529 void 1530 fxp_mdi_write(self, phy, reg, value) 1531 struct device *self; 1532 int phy; 1533 int reg; 1534 int value; 1535 { 1536 struct fxp_softc *sc = (struct fxp_softc *)self; 1537 int count = 10000; 1538 1539 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1540 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1541 (value & 0xffff)); 1542 1543 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1544 count--) 1545 DELAY(10); 1546 1547 if (count <= 0) 1548 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1549 } 1550 1551 int 1552 fxp_ioctl(ifp, command, data) 1553 struct ifnet *ifp; 1554 u_long command; 1555 caddr_t data; 1556 { 1557 struct fxp_softc *sc = ifp->if_softc; 1558 struct ifreq *ifr = (struct ifreq *)data; 1559 struct ifaddr *ifa = (struct ifaddr *)data; 1560 int s, error = 0; 1561 1562 s = splnet(); 1563 1564 switch (command) { 1565 case SIOCSIFADDR: 1566 if ((error = fxp_enable(sc)) != 0) 1567 break; 1568 ifp->if_flags |= IFF_UP; 1569 1570 switch (ifa->ifa_addr->sa_family) { 1571 #ifdef INET 1572 case AF_INET: 1573 if ((error = fxp_init(sc)) != 0) 1574 break; 1575 arp_ifinit(ifp, ifa); 1576 break; 1577 #endif /* INET */ 1578 #ifdef NS 1579 case AF_NS: 1580 { 1581 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1582 1583 if (ns_nullhost(*ina)) 1584 ina->x_host = *(union ns_host *) 1585 LLADDR(ifp->if_sadl); 1586 else 1587 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1588 ifp->if_addrlen); 1589 /* Set new address. */ 1590 error = fxp_init(sc); 1591 break; 1592 } 1593 #endif /* NS */ 1594 default: 1595 error = fxp_init(sc); 1596 break; 1597 } 1598 break; 1599 1600 case SIOCSIFMTU: 1601 if (ifr->ifr_mtu > ETHERMTU) 1602 error = EINVAL; 1603 else 1604 ifp->if_mtu = ifr->ifr_mtu; 1605 break; 1606 1607 case SIOCSIFFLAGS: 1608 if ((ifp->if_flags & IFF_UP) == 0 && 1609 (ifp->if_flags & IFF_RUNNING) != 0) { 1610 /* 1611 * If interface is marked down and it is running, then 1612 * stop it. 1613 */ 1614 fxp_stop(sc, 1); 1615 fxp_disable(sc); 1616 } else if ((ifp->if_flags & IFF_UP) != 0 && 1617 (ifp->if_flags & IFF_RUNNING) == 0) { 1618 /* 1619 * If interface is marked up and it is stopped, then 1620 * start it. 1621 */ 1622 if((error = fxp_enable(sc)) != 0) 1623 break; 1624 error = fxp_init(sc); 1625 } else if ((ifp->if_flags & IFF_UP) != 0) { 1626 /* 1627 * Reset the interface to pick up change in any other 1628 * flags that affect the hardware state. 1629 */ 1630 if((error = fxp_enable(sc)) != 0) 1631 break; 1632 error = fxp_init(sc); 1633 } 1634 break; 1635 1636 case SIOCADDMULTI: 1637 case SIOCDELMULTI: 1638 if(sc->sc_enabled == 0) { 1639 error = EIO; 1640 break; 1641 } 1642 error = (command == SIOCADDMULTI) ? 1643 ether_addmulti(ifr, &sc->sc_ethercom) : 1644 ether_delmulti(ifr, &sc->sc_ethercom); 1645 1646 if (error == ENETRESET) { 1647 /* 1648 * Multicast list has changed; set the hardware 1649 * filter accordingly. 1650 */ 1651 if (sc->sc_txpending) { 1652 sc->sc_flags |= FXPF_WANTINIT; 1653 error = 0; 1654 } else 1655 error = fxp_init(sc); 1656 } 1657 break; 1658 1659 case SIOCSIFMEDIA: 1660 case SIOCGIFMEDIA: 1661 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1662 break; 1663 1664 default: 1665 error = EINVAL; 1666 break; 1667 } 1668 1669 splx(s); 1670 return (error); 1671 } 1672 1673 /* 1674 * Program the multicast filter. 1675 * 1676 * This function must be called at splnet(). 1677 */ 1678 void 1679 fxp_mc_setup(sc) 1680 struct fxp_softc *sc; 1681 { 1682 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1683 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1684 struct ethercom *ec = &sc->sc_ethercom; 1685 struct ether_multi *enm; 1686 struct ether_multistep step; 1687 int nmcasts; 1688 1689 #ifdef DIAGNOSTIC 1690 if (sc->sc_txpending) 1691 panic("fxp_mc_setup: pending transmissions"); 1692 #endif 1693 1694 ifp->if_flags &= ~IFF_ALLMULTI; 1695 1696 /* 1697 * Initialize multicast setup descriptor. 1698 */ 1699 nmcasts = 0; 1700 ETHER_FIRST_MULTI(step, ec, enm); 1701 while (enm != NULL) { 1702 /* 1703 * Check for too many multicast addresses or if we're 1704 * listening to a range. Either way, we simply have 1705 * to accept all multicasts. 1706 */ 1707 if (nmcasts >= MAXMCADDR || 1708 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1709 ETHER_ADDR_LEN) != 0) { 1710 /* 1711 * Callers of this function must do the 1712 * right thing with this. If we're called 1713 * from outside fxp_init(), the caller must 1714 * detect if the state if IFF_ALLMULTI changes. 1715 * If it does, the caller must then call 1716 * fxp_init(), since allmulti is handled by 1717 * the config block. 1718 */ 1719 ifp->if_flags |= IFF_ALLMULTI; 1720 return; 1721 } 1722 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1723 ETHER_ADDR_LEN); 1724 nmcasts++; 1725 ETHER_NEXT_MULTI(step, enm); 1726 } 1727 1728 mcsp->cb_status = 0; 1729 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1730 mcsp->link_addr = FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast)); 1731 mcsp->mc_cnt = nmcasts * ETHER_ADDR_LEN; 1732 1733 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1734 1735 /* 1736 * Wait until the command unit is not active. This should never 1737 * happen since nothing is queued, but make sure anyway. 1738 */ 1739 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1740 FXP_SCB_CUS_ACTIVE) 1741 /* nothing */ ; 1742 1743 /* 1744 * Start the multicast setup command/DMA. 1745 */ 1746 fxp_scb_wait(sc); 1747 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1748 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1749 1750 /* ...and wait for it to complete. */ 1751 do { 1752 FXP_CDMCSSYNC(sc, 1753 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1754 } while ((mcsp->cb_status & FXP_CB_STATUS_C) == 0); 1755 } 1756 1757 int 1758 fxp_enable(sc) 1759 struct fxp_softc *sc; 1760 { 1761 1762 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1763 if ((*sc->sc_enable)(sc) != 0) { 1764 printf("%s: device enable failed\n", 1765 sc->sc_dev.dv_xname); 1766 return (EIO); 1767 } 1768 } 1769 1770 sc->sc_enabled = 1; 1771 1772 return 0; 1773 } 1774 1775 void 1776 fxp_disable(sc) 1777 struct fxp_softc *sc; 1778 { 1779 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1780 (*sc->sc_disable)(sc); 1781 sc->sc_enabled = 0; 1782 } 1783 } 1784
Indexes created Mon Sep 29 21:09:56 GMT 2025