i82557.c revision 1.135
1 /* $NetBSD: i82557.c,v 1.135 2010/04/05 07:19:34 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.135 2010/04/05 07:19:34 joerg Exp $"); 70 71 #include "rnd.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/callout.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/ioctl.h> 81 #include <sys/errno.h> 82 #include <sys/device.h> 83 #include <sys/syslog.h> 84 85 #include <machine/endian.h> 86 87 #include <uvm/uvm_extern.h> 88 89 #if NRND > 0 90 #include <sys/rnd.h> 91 #endif 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #include <netinet/in.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/ip.h> 101 #include <netinet/tcp.h> 102 #include <netinet/udp.h> 103 104 #include <net/bpf.h> 105 106 #include <sys/bus.h> 107 #include <sys/intr.h> 108 109 #include <dev/mii/miivar.h> 110 111 #include <dev/ic/i82557reg.h> 112 #include <dev/ic/i82557var.h> 113 114 #include <dev/microcode/i8255x/rcvbundl.h> 115 116 /* 117 * NOTE! On the Alpha, we have an alignment constraint. The 118 * card DMAs the packet immediately following the RFA. However, 119 * the first thing in the packet is a 14-byte Ethernet header. 120 * This means that the packet is misaligned. To compensate, 121 * we actually offset the RFA 2 bytes into the cluster. This 122 * alignes the packet after the Ethernet header at a 32-bit 123 * boundary. HOWEVER! This means that the RFA is misaligned! 124 */ 125 #define RFA_ALIGNMENT_FUDGE 2 126 127 /* 128 * The configuration byte map has several undefined fields which 129 * must be one or must be zero. Set up a template for these bits 130 * only (assuming an i82557 chip), leaving the actual configuration 131 * for fxp_init(). 132 * 133 * See the definition of struct fxp_cb_config for the bit definitions. 134 */ 135 const uint8_t fxp_cb_config_template[] = { 136 0x0, 0x0, /* cb_status */ 137 0x0, 0x0, /* cb_command */ 138 0x0, 0x0, 0x0, 0x0, /* link_addr */ 139 0x0, /* 0 */ 140 0x0, /* 1 */ 141 0x0, /* 2 */ 142 0x0, /* 3 */ 143 0x0, /* 4 */ 144 0x0, /* 5 */ 145 0x32, /* 6 */ 146 0x0, /* 7 */ 147 0x0, /* 8 */ 148 0x0, /* 9 */ 149 0x6, /* 10 */ 150 0x0, /* 11 */ 151 0x0, /* 12 */ 152 0x0, /* 13 */ 153 0xf2, /* 14 */ 154 0x48, /* 15 */ 155 0x0, /* 16 */ 156 0x40, /* 17 */ 157 0xf0, /* 18 */ 158 0x0, /* 19 */ 159 0x3f, /* 20 */ 160 0x5, /* 21 */ 161 0x0, /* 22 */ 162 0x0, /* 23 */ 163 0x0, /* 24 */ 164 0x0, /* 25 */ 165 0x0, /* 26 */ 166 0x0, /* 27 */ 167 0x0, /* 28 */ 168 0x0, /* 29 */ 169 0x0, /* 30 */ 170 0x0, /* 31 */ 171 }; 172 173 void fxp_mii_initmedia(struct fxp_softc *); 174 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 175 176 void fxp_80c24_initmedia(struct fxp_softc *); 177 int fxp_80c24_mediachange(struct ifnet *); 178 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_start(struct ifnet *); 181 int fxp_ioctl(struct ifnet *, u_long, void *); 182 void fxp_watchdog(struct ifnet *); 183 int fxp_init(struct ifnet *); 184 void fxp_stop(struct ifnet *, int); 185 186 void fxp_txintr(struct fxp_softc *); 187 int fxp_rxintr(struct fxp_softc *); 188 189 void fxp_rx_hwcksum(struct fxp_softc *,struct mbuf *, 190 const struct fxp_rfa *, u_int); 191 192 void fxp_rxdrain(struct fxp_softc *); 193 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 194 int fxp_mdi_read(device_t, int, int); 195 void fxp_statchg(device_t); 196 void fxp_mdi_write(device_t, int, int, int); 197 void fxp_autosize_eeprom(struct fxp_softc*); 198 void fxp_read_eeprom(struct fxp_softc *, uint16_t *, int, int); 199 void fxp_write_eeprom(struct fxp_softc *, uint16_t *, int, int); 200 void fxp_eeprom_update_cksum(struct fxp_softc *); 201 void fxp_get_info(struct fxp_softc *, uint8_t *); 202 void fxp_tick(void *); 203 void fxp_mc_setup(struct fxp_softc *); 204 void fxp_load_ucode(struct fxp_softc *); 205 206 int fxp_copy_small = 0; 207 208 /* 209 * Variables for interrupt mitigating microcode. 210 */ 211 int fxp_int_delay = 1000; /* usec */ 212 int fxp_bundle_max = 6; /* packets */ 213 214 struct fxp_phytype { 215 int fp_phy; /* type of PHY, -1 for MII at the end. */ 216 void (*fp_init)(struct fxp_softc *); 217 } fxp_phytype_table[] = { 218 { FXP_PHY_80C24, fxp_80c24_initmedia }, 219 { -1, fxp_mii_initmedia }, 220 }; 221 222 /* 223 * Set initial transmit threshold at 64 (512 bytes). This is 224 * increased by 64 (512 bytes) at a time, to maximum of 192 225 * (1536 bytes), if an underrun occurs. 226 */ 227 static int tx_threshold = 64; 228 229 /* 230 * Wait for the previous command to be accepted (but not necessarily 231 * completed). 232 */ 233 static inline void 234 fxp_scb_wait(struct fxp_softc *sc) 235 { 236 int i = 10000; 237 238 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 239 delay(2); 240 if (i == 0) 241 log(LOG_WARNING, 242 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 243 } 244 245 /* 246 * Submit a command to the i82557. 247 */ 248 static inline void 249 fxp_scb_cmd(struct fxp_softc *sc, uint8_t cmd) 250 { 251 252 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 253 } 254 255 /* 256 * Finish attaching an i82557 interface. Called by bus-specific front-end. 257 */ 258 void 259 fxp_attach(struct fxp_softc *sc) 260 { 261 uint8_t enaddr[ETHER_ADDR_LEN]; 262 struct ifnet *ifp; 263 bus_dma_segment_t seg; 264 int rseg, i, error; 265 struct fxp_phytype *fp; 266 267 callout_init(&sc->sc_callout, 0); 268 269 /* 270 * Enable use of extended RFDs and IPCBs for 82550 and later chips. 271 * Note: to use IPCB we need extended TXCB support too, and 272 * these feature flags should be set in each bus attachment. 273 */ 274 if (sc->sc_flags & FXPF_EXT_RFA) { 275 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 276 sc->sc_rfa_size = RFA_EXT_SIZE; 277 } else { 278 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 279 sc->sc_rfa_size = RFA_SIZE; 280 } 281 282 /* 283 * Allocate the control data structures, and create and load the 284 * DMA map for it. 285 */ 286 if ((error = bus_dmamem_alloc(sc->sc_dmat, 287 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 288 0)) != 0) { 289 aprint_error_dev(sc->sc_dev, 290 "unable to allocate control data, error = %d\n", 291 error); 292 goto fail_0; 293 } 294 295 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 296 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 297 BUS_DMA_COHERENT)) != 0) { 298 aprint_error_dev(sc->sc_dev, 299 "unable to map control data, error = %d\n", error); 300 goto fail_1; 301 } 302 sc->sc_cdseg = seg; 303 sc->sc_cdnseg = rseg; 304 305 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 306 307 if ((error = bus_dmamap_create(sc->sc_dmat, 308 sizeof(struct fxp_control_data), 1, 309 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 310 aprint_error_dev(sc->sc_dev, 311 "unable to create control data DMA map, error = %d\n", 312 error); 313 goto fail_2; 314 } 315 316 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 317 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 318 0)) != 0) { 319 aprint_error_dev(sc->sc_dev, 320 "can't load control data DMA map, error = %d\n", 321 error); 322 goto fail_3; 323 } 324 325 /* 326 * Create the transmit buffer DMA maps. 327 */ 328 for (i = 0; i < FXP_NTXCB; i++) { 329 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 330 (sc->sc_flags & FXPF_EXT_RFA) ? 331 FXP_IPCB_NTXSEG : FXP_NTXSEG, 332 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 333 aprint_error_dev(sc->sc_dev, 334 "unable to create tx DMA map %d, error = %d\n", 335 i, error); 336 goto fail_4; 337 } 338 } 339 340 /* 341 * Create the receive buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NRFABUFS; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 345 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 346 aprint_error_dev(sc->sc_dev, 347 "unable to create rx DMA map %d, error = %d\n", 348 i, error); 349 goto fail_5; 350 } 351 } 352 353 /* Initialize MAC address and media structures. */ 354 fxp_get_info(sc, enaddr); 355 356 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 357 ether_sprintf(enaddr)); 358 359 ifp = &sc->sc_ethercom.ec_if; 360 361 /* 362 * Get info about our media interface, and initialize it. Note 363 * the table terminates itself with a phy of -1, indicating 364 * that we're using MII. 365 */ 366 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 367 if (fp->fp_phy == sc->phy_primary_device) 368 break; 369 (*fp->fp_init)(sc); 370 371 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 372 ifp->if_softc = sc; 373 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 374 ifp->if_ioctl = fxp_ioctl; 375 ifp->if_start = fxp_start; 376 ifp->if_watchdog = fxp_watchdog; 377 ifp->if_init = fxp_init; 378 ifp->if_stop = fxp_stop; 379 IFQ_SET_READY(&ifp->if_snd); 380 381 if (sc->sc_flags & FXPF_EXT_RFA) { 382 /* 383 * Enable hardware cksum support by EXT_RFA and IPCB. 384 * 385 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 386 * at least, on i82550 rev.12. 387 * specifically, it doesn't set ipv4 checksum properly 388 * when sending UDP (and probably TCP) packets with 389 * 20 byte ipv4 header + 1 or 2 byte data, 390 * though ICMP packets seem working. 391 * FreeBSD driver has related comments. 392 * We've added a workaround to handle the bug by padding 393 * such packets manually. 394 */ 395 ifp->if_capabilities = 396 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 397 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 398 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 399 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 400 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 401 ifp->if_capabilities = 402 IFCAP_CSUM_TCPv4_Rx | 403 IFCAP_CSUM_UDPv4_Rx; 404 } 405 406 /* 407 * We can support 802.1Q VLAN-sized frames. 408 */ 409 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 410 411 /* 412 * Attach the interface. 413 */ 414 if_attach(ifp); 415 ether_ifattach(ifp, enaddr); 416 #if NRND > 0 417 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 418 RND_TYPE_NET, 0); 419 #endif 420 421 #ifdef FXP_EVENT_COUNTERS 422 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 423 NULL, device_xname(sc->sc_dev), "txstall"); 424 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 425 NULL, device_xname(sc->sc_dev), "txintr"); 426 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 427 NULL, device_xname(sc->sc_dev), "rxintr"); 428 if (sc->sc_flags & FXPF_FC) { 429 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 430 NULL, device_xname(sc->sc_dev), "txpause"); 431 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 432 NULL, device_xname(sc->sc_dev), "rxpause"); 433 } 434 #endif /* FXP_EVENT_COUNTERS */ 435 436 /* The attach is successful. */ 437 sc->sc_flags |= FXPF_ATTACHED; 438 439 return; 440 441 /* 442 * Free any resources we've allocated during the failed attach 443 * attempt. Do this in reverse order and fall though. 444 */ 445 fail_5: 446 for (i = 0; i < FXP_NRFABUFS; i++) { 447 if (sc->sc_rxmaps[i] != NULL) 448 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 449 } 450 fail_4: 451 for (i = 0; i < FXP_NTXCB; i++) { 452 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 453 bus_dmamap_destroy(sc->sc_dmat, 454 FXP_DSTX(sc, i)->txs_dmamap); 455 } 456 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 457 fail_3: 458 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 459 fail_2: 460 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 461 sizeof(struct fxp_control_data)); 462 fail_1: 463 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 464 fail_0: 465 return; 466 } 467 468 void 469 fxp_mii_initmedia(struct fxp_softc *sc) 470 { 471 int flags; 472 473 sc->sc_flags |= FXPF_MII; 474 475 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 476 sc->sc_mii.mii_readreg = fxp_mdi_read; 477 sc->sc_mii.mii_writereg = fxp_mdi_write; 478 sc->sc_mii.mii_statchg = fxp_statchg; 479 480 sc->sc_ethercom.ec_mii = &sc->sc_mii; 481 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 482 fxp_mii_mediastatus); 483 484 flags = MIIF_NOISOLATE; 485 if (sc->sc_flags & FXPF_FC) 486 flags |= MIIF_FORCEANEG|MIIF_DOPAUSE; 487 /* 488 * The i82557 wedges if all of its PHYs are isolated! 489 */ 490 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 491 MII_OFFSET_ANY, flags); 492 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 493 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 494 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 495 } else 496 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 497 } 498 499 void 500 fxp_80c24_initmedia(struct fxp_softc *sc) 501 { 502 503 /* 504 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 505 * doesn't have a programming interface of any sort. The 506 * media is sensed automatically based on how the link partner 507 * is configured. This is, in essence, manual configuration. 508 */ 509 aprint_normal_dev(sc->sc_dev, 510 "Seeq 80c24 AutoDUPLEX media interface present\n"); 511 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 512 fxp_80c24_mediastatus); 513 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 514 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 515 } 516 517 /* 518 * Initialize the interface media. 519 */ 520 void 521 fxp_get_info(struct fxp_softc *sc, uint8_t *enaddr) 522 { 523 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 524 525 /* 526 * Reset to a stable state. 527 */ 528 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 529 DELAY(100); 530 531 sc->sc_eeprom_size = 0; 532 fxp_autosize_eeprom(sc); 533 if (sc->sc_eeprom_size == 0) { 534 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 535 sc->sc_eeprom_size = 6; /* XXX panic here? */ 536 } 537 #ifdef DEBUG 538 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 539 1 << sc->sc_eeprom_size); 540 #endif 541 542 /* 543 * Get info about the primary PHY 544 */ 545 fxp_read_eeprom(sc, &data, 6, 1); 546 sc->phy_primary_device = 547 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 548 549 /* 550 * Read MAC address. 551 */ 552 fxp_read_eeprom(sc, myea, 0, 3); 553 enaddr[0] = myea[0] & 0xff; 554 enaddr[1] = myea[0] >> 8; 555 enaddr[2] = myea[1] & 0xff; 556 enaddr[3] = myea[1] >> 8; 557 enaddr[4] = myea[2] & 0xff; 558 enaddr[5] = myea[2] >> 8; 559 560 /* 561 * Systems based on the ICH2/ICH2-M chip from Intel, as well 562 * as some i82559 designs, have a defect where the chip can 563 * cause a PCI protocol violation if it receives a CU_RESUME 564 * command when it is entering the IDLE state. 565 * 566 * The work-around is to disable Dynamic Standby Mode, so that 567 * the chip never deasserts #CLKRUN, and always remains in the 568 * active state. 569 * 570 * Unfortunately, the only way to disable Dynamic Standby is 571 * to frob an EEPROM setting and reboot (the EEPROM setting 572 * is only consulted when the PCI bus comes out of reset). 573 * 574 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 575 */ 576 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 577 fxp_read_eeprom(sc, &data, 10, 1); 578 if (data & 0x02) { /* STB enable */ 579 aprint_error_dev(sc->sc_dev, "WARNING: " 580 "Disabling dynamic standby mode in EEPROM " 581 "to work around a\n"); 582 aprint_normal_dev(sc->sc_dev, 583 "WARNING: hardware bug. You must reset " 584 "the system before using this\n"); 585 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 586 data &= ~0x02; 587 fxp_write_eeprom(sc, &data, 10, 1); 588 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 589 data); 590 fxp_eeprom_update_cksum(sc); 591 } 592 } 593 594 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 595 /* Due to false positives we make it conditional on setting link1 */ 596 fxp_read_eeprom(sc, &data, 3, 1); 597 if ((data & 0x03) != 0x03) { 598 aprint_verbose_dev(sc->sc_dev, 599 "May need receiver lock-up workaround\n"); 600 } 601 } 602 603 static void 604 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 605 { 606 uint16_t reg; 607 int x; 608 609 for (x = 1 << (len - 1); x != 0; x >>= 1) { 610 DELAY(40); 611 if (data & x) 612 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 613 else 614 reg = FXP_EEPROM_EECS; 615 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 616 DELAY(40); 617 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 618 reg | FXP_EEPROM_EESK); 619 DELAY(40); 620 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 621 } 622 DELAY(40); 623 } 624 625 /* 626 * Figure out EEPROM size. 627 * 628 * 559's can have either 64-word or 256-word EEPROMs, the 558 629 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 630 * talks about the existence of 16 to 256 word EEPROMs. 631 * 632 * The only known sizes are 64 and 256, where the 256 version is used 633 * by CardBus cards to store CIS information. 634 * 635 * The address is shifted in msb-to-lsb, and after the last 636 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 637 * after which follows the actual data. We try to detect this zero, by 638 * probing the data-out bit in the EEPROM control register just after 639 * having shifted in a bit. If the bit is zero, we assume we've 640 * shifted enough address bits. The data-out should be tri-state, 641 * before this, which should translate to a logical one. 642 * 643 * Other ways to do this would be to try to read a register with known 644 * contents with a varying number of address bits, but no such 645 * register seem to be available. The high bits of register 10 are 01 646 * on the 558 and 559, but apparently not on the 557. 647 * 648 * The Linux driver computes a checksum on the EEPROM data, but the 649 * value of this checksum is not very well documented. 650 */ 651 652 void 653 fxp_autosize_eeprom(struct fxp_softc *sc) 654 { 655 int x; 656 657 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 658 DELAY(40); 659 660 /* Shift in read opcode. */ 661 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 662 663 /* 664 * Shift in address, wait for the dummy zero following a correct 665 * address shift. 666 */ 667 for (x = 1; x <= 8; x++) { 668 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 669 DELAY(40); 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 671 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 672 DELAY(40); 673 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 674 FXP_EEPROM_EEDO) == 0) 675 break; 676 DELAY(40); 677 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 678 DELAY(40); 679 } 680 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 681 DELAY(40); 682 if (x != 6 && x != 8) { 683 #ifdef DEBUG 684 printf("%s: strange EEPROM size (%d)\n", 685 device_xname(sc->sc_dev), 1 << x); 686 #endif 687 } else 688 sc->sc_eeprom_size = x; 689 } 690 691 /* 692 * Read from the serial EEPROM. Basically, you manually shift in 693 * the read opcode (one bit at a time) and then shift in the address, 694 * and then you shift out the data (all of this one bit at a time). 695 * The word size is 16 bits, so you have to provide the address for 696 * every 16 bits of data. 697 */ 698 void 699 fxp_read_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 700 { 701 uint16_t reg; 702 int i, x; 703 704 for (i = 0; i < words; i++) { 705 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 706 707 /* Shift in read opcode. */ 708 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 709 710 /* Shift in address. */ 711 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 712 713 reg = FXP_EEPROM_EECS; 714 data[i] = 0; 715 716 /* Shift out data. */ 717 for (x = 16; x > 0; x--) { 718 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 719 reg | FXP_EEPROM_EESK); 720 DELAY(40); 721 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 722 FXP_EEPROM_EEDO) 723 data[i] |= (1 << (x - 1)); 724 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 725 DELAY(40); 726 } 727 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 728 DELAY(40); 729 } 730 } 731 732 /* 733 * Write data to the serial EEPROM. 734 */ 735 void 736 fxp_write_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 737 { 738 int i, j; 739 740 for (i = 0; i < words; i++) { 741 /* Erase/write enable. */ 742 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 743 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 744 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 745 sc->sc_eeprom_size); 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 747 DELAY(4); 748 749 /* Shift in write opcode, address, data. */ 750 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 751 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 752 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 753 fxp_eeprom_shiftin(sc, data[i], 16); 754 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 755 DELAY(4); 756 757 /* Wait for the EEPROM to finish up. */ 758 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 759 DELAY(4); 760 for (j = 0; j < 1000; j++) { 761 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 762 FXP_EEPROM_EEDO) 763 break; 764 DELAY(50); 765 } 766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 767 DELAY(4); 768 769 /* Erase/write disable. */ 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 771 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 772 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 774 DELAY(4); 775 } 776 } 777 778 /* 779 * Update the checksum of the EEPROM. 780 */ 781 void 782 fxp_eeprom_update_cksum(struct fxp_softc *sc) 783 { 784 int i; 785 uint16_t data, cksum; 786 787 cksum = 0; 788 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 789 fxp_read_eeprom(sc, &data, i, 1); 790 cksum += data; 791 } 792 i = (1 << sc->sc_eeprom_size) - 1; 793 cksum = 0xbaba - cksum; 794 fxp_read_eeprom(sc, &data, i, 1); 795 fxp_write_eeprom(sc, &cksum, i, 1); 796 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 797 device_xname(sc->sc_dev), i, data, cksum); 798 } 799 800 /* 801 * Start packet transmission on the interface. 802 */ 803 void 804 fxp_start(struct ifnet *ifp) 805 { 806 struct fxp_softc *sc = ifp->if_softc; 807 struct mbuf *m0, *m; 808 struct fxp_txdesc *txd; 809 struct fxp_txsoft *txs; 810 bus_dmamap_t dmamap; 811 int error, lasttx, nexttx, opending, seg, nsegs, len; 812 813 /* 814 * If we want a re-init, bail out now. 815 */ 816 if (sc->sc_flags & FXPF_WANTINIT) { 817 ifp->if_flags |= IFF_OACTIVE; 818 return; 819 } 820 821 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 822 return; 823 824 /* 825 * Remember the previous txpending and the current lasttx. 826 */ 827 opending = sc->sc_txpending; 828 lasttx = sc->sc_txlast; 829 830 /* 831 * Loop through the send queue, setting up transmit descriptors 832 * until we drain the queue, or use up all available transmit 833 * descriptors. 834 */ 835 for (;;) { 836 struct fxp_tbd *tbdp; 837 int csum_flags; 838 839 /* 840 * Grab a packet off the queue. 841 */ 842 IFQ_POLL(&ifp->if_snd, m0); 843 if (m0 == NULL) 844 break; 845 m = NULL; 846 847 if (sc->sc_txpending == FXP_NTXCB - 1) { 848 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 849 break; 850 } 851 852 /* 853 * Get the next available transmit descriptor. 854 */ 855 nexttx = FXP_NEXTTX(sc->sc_txlast); 856 txd = FXP_CDTX(sc, nexttx); 857 txs = FXP_DSTX(sc, nexttx); 858 dmamap = txs->txs_dmamap; 859 860 /* 861 * Load the DMA map. If this fails, the packet either 862 * didn't fit in the allotted number of frags, or we were 863 * short on resources. In this case, we'll copy and try 864 * again. 865 */ 866 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 867 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 868 MGETHDR(m, M_DONTWAIT, MT_DATA); 869 if (m == NULL) { 870 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 871 device_xname(sc->sc_dev)); 872 break; 873 } 874 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 875 if (m0->m_pkthdr.len > MHLEN) { 876 MCLGET(m, M_DONTWAIT); 877 if ((m->m_flags & M_EXT) == 0) { 878 log(LOG_ERR, "%s: unable to allocate " 879 "Tx cluster\n", 880 device_xname(sc->sc_dev)); 881 m_freem(m); 882 break; 883 } 884 } 885 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 886 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 887 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 888 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 889 if (error) { 890 log(LOG_ERR, "%s: unable to load Tx buffer, " 891 "error = %d\n", 892 device_xname(sc->sc_dev), error); 893 break; 894 } 895 } 896 897 IFQ_DEQUEUE(&ifp->if_snd, m0); 898 csum_flags = m0->m_pkthdr.csum_flags; 899 if (m != NULL) { 900 m_freem(m0); 901 m0 = m; 902 } 903 904 /* Initialize the fraglist. */ 905 tbdp = txd->txd_tbd; 906 len = m0->m_pkthdr.len; 907 nsegs = dmamap->dm_nsegs; 908 if (sc->sc_flags & FXPF_EXT_RFA) 909 tbdp++; 910 for (seg = 0; seg < nsegs; seg++) { 911 tbdp[seg].tb_addr = 912 htole32(dmamap->dm_segs[seg].ds_addr); 913 tbdp[seg].tb_size = 914 htole32(dmamap->dm_segs[seg].ds_len); 915 } 916 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 917 (csum_flags & M_CSUM_IPv4) != 0)) { 918 /* 919 * Pad short packets to avoid ip4csum-tx bug. 920 * 921 * XXX Should we still consider if such short 922 * (36 bytes or less) packets might already 923 * occupy FXP_IPCB_NTXSEG (15) fragments here? 924 */ 925 KASSERT(nsegs < FXP_IPCB_NTXSEG); 926 nsegs++; 927 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 928 tbdp[seg].tb_size = 929 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 930 } 931 932 /* Sync the DMA map. */ 933 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 934 BUS_DMASYNC_PREWRITE); 935 936 /* 937 * Store a pointer to the packet so we can free it later. 938 */ 939 txs->txs_mbuf = m0; 940 941 /* 942 * Initialize the transmit descriptor. 943 */ 944 /* BIG_ENDIAN: no need to swap to store 0 */ 945 txd->txd_txcb.cb_status = 0; 946 txd->txd_txcb.cb_command = 947 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 948 txd->txd_txcb.tx_threshold = tx_threshold; 949 txd->txd_txcb.tbd_number = nsegs; 950 951 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 952 if (sc->sc_flags & FXPF_EXT_RFA) { 953 struct m_tag *vtag; 954 struct fxp_ipcb *ipcb; 955 /* 956 * Deal with TCP/IP checksum offload. Note that 957 * in order for TCP checksum offload to work, 958 * the pseudo header checksum must have already 959 * been computed and stored in the checksum field 960 * in the TCP header. The stack should have 961 * already done this for us. 962 */ 963 ipcb = &txd->txd_u.txdu_ipcb; 964 memset(ipcb, 0, sizeof(*ipcb)); 965 /* 966 * always do hardware parsing. 967 */ 968 ipcb->ipcb_ip_activation_high = 969 FXP_IPCB_HARDWAREPARSING_ENABLE; 970 /* 971 * ip checksum offloading. 972 */ 973 if (csum_flags & M_CSUM_IPv4) { 974 ipcb->ipcb_ip_schedule |= 975 FXP_IPCB_IP_CHECKSUM_ENABLE; 976 } 977 /* 978 * TCP/UDP checksum offloading. 979 */ 980 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 981 ipcb->ipcb_ip_schedule |= 982 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 983 } 984 985 /* 986 * request VLAN tag insertion if needed. 987 */ 988 vtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0); 989 if (vtag) { 990 ipcb->ipcb_vlan_id = 991 htobe16(*(u_int *)(vtag + 1)); 992 ipcb->ipcb_ip_activation_high |= 993 FXP_IPCB_INSERTVLAN_ENABLE; 994 } 995 } else { 996 KASSERT((csum_flags & 997 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 998 } 999 1000 FXP_CDTXSYNC(sc, nexttx, 1001 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1002 1003 /* Advance the tx pointer. */ 1004 sc->sc_txpending++; 1005 sc->sc_txlast = nexttx; 1006 1007 /* 1008 * Pass packet to bpf if there is a listener. 1009 */ 1010 bpf_mtap(ifp, m0); 1011 } 1012 1013 if (sc->sc_txpending == FXP_NTXCB - 1) { 1014 /* No more slots; notify upper layer. */ 1015 ifp->if_flags |= IFF_OACTIVE; 1016 } 1017 1018 if (sc->sc_txpending != opending) { 1019 /* 1020 * We enqueued packets. If the transmitter was idle, 1021 * reset the txdirty pointer. 1022 */ 1023 if (opending == 0) 1024 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1025 1026 /* 1027 * Cause the chip to interrupt and suspend command 1028 * processing once the last packet we've enqueued 1029 * has been transmitted. 1030 * 1031 * To avoid a race between updating status bits 1032 * by the fxp chip and clearing command bits 1033 * by this function on machines which don't have 1034 * atomic methods to clear/set bits in memory 1035 * smaller than 32bits (both cb_status and cb_command 1036 * members are uint16_t and in the same 32bit word), 1037 * we have to prepare a dummy TX descriptor which has 1038 * NOP command and just causes a TX completion interrupt. 1039 */ 1040 sc->sc_txpending++; 1041 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1042 txd = FXP_CDTX(sc, sc->sc_txlast); 1043 /* BIG_ENDIAN: no need to swap to store 0 */ 1044 txd->txd_txcb.cb_status = 0; 1045 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1046 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1047 FXP_CDTXSYNC(sc, sc->sc_txlast, 1048 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1049 1050 /* 1051 * The entire packet chain is set up. Clear the suspend bit 1052 * on the command prior to the first packet we set up. 1053 */ 1054 FXP_CDTXSYNC(sc, lasttx, 1055 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1056 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1057 htole16(~FXP_CB_COMMAND_S); 1058 FXP_CDTXSYNC(sc, lasttx, 1059 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1060 1061 /* 1062 * Issue a Resume command in case the chip was suspended. 1063 */ 1064 fxp_scb_wait(sc); 1065 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1066 1067 /* Set a watchdog timer in case the chip flakes out. */ 1068 ifp->if_timer = 5; 1069 } 1070 } 1071 1072 /* 1073 * Process interface interrupts. 1074 */ 1075 int 1076 fxp_intr(void *arg) 1077 { 1078 struct fxp_softc *sc = arg; 1079 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1080 bus_dmamap_t rxmap; 1081 int claimed = 0, rnr; 1082 uint8_t statack; 1083 1084 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1085 return (0); 1086 /* 1087 * If the interface isn't running, don't try to 1088 * service the interrupt.. just ack it and bail. 1089 */ 1090 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1091 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1092 if (statack) { 1093 claimed = 1; 1094 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1095 } 1096 return (claimed); 1097 } 1098 1099 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1100 claimed = 1; 1101 1102 /* 1103 * First ACK all the interrupts in this pass. 1104 */ 1105 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1106 1107 /* 1108 * Process receiver interrupts. If a no-resource (RNR) 1109 * condition exists, get whatever packets we can and 1110 * re-start the receiver. 1111 */ 1112 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1113 1 : 0; 1114 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1115 FXP_SCB_STATACK_SWI)) { 1116 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1117 rnr |= fxp_rxintr(sc); 1118 } 1119 1120 /* 1121 * Free any finished transmit mbuf chains. 1122 */ 1123 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1124 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1125 fxp_txintr(sc); 1126 1127 /* 1128 * Try to get more packets going. 1129 */ 1130 fxp_start(ifp); 1131 1132 if (sc->sc_txpending == 0) { 1133 /* 1134 * Tell them that they can re-init now. 1135 */ 1136 if (sc->sc_flags & FXPF_WANTINIT) 1137 wakeup(sc); 1138 } 1139 } 1140 1141 if (rnr) { 1142 fxp_scb_wait(sc); 1143 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1144 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1145 fxp_scb_wait(sc); 1146 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1147 rxmap->dm_segs[0].ds_addr + 1148 RFA_ALIGNMENT_FUDGE); 1149 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1150 } 1151 } 1152 1153 #if NRND > 0 1154 if (claimed) 1155 rnd_add_uint32(&sc->rnd_source, statack); 1156 #endif 1157 return (claimed); 1158 } 1159 1160 /* 1161 * Handle transmit completion interrupts. 1162 */ 1163 void 1164 fxp_txintr(struct fxp_softc *sc) 1165 { 1166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1167 struct fxp_txdesc *txd; 1168 struct fxp_txsoft *txs; 1169 int i; 1170 uint16_t txstat; 1171 1172 ifp->if_flags &= ~IFF_OACTIVE; 1173 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1174 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1175 txd = FXP_CDTX(sc, i); 1176 txs = FXP_DSTX(sc, i); 1177 1178 FXP_CDTXSYNC(sc, i, 1179 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1180 1181 /* skip dummy NOP TX descriptor */ 1182 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1183 == FXP_CB_COMMAND_NOP) 1184 continue; 1185 1186 txstat = le16toh(txd->txd_txcb.cb_status); 1187 1188 if ((txstat & FXP_CB_STATUS_C) == 0) 1189 break; 1190 1191 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1192 0, txs->txs_dmamap->dm_mapsize, 1193 BUS_DMASYNC_POSTWRITE); 1194 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1195 m_freem(txs->txs_mbuf); 1196 txs->txs_mbuf = NULL; 1197 } 1198 1199 /* Update the dirty transmit buffer pointer. */ 1200 sc->sc_txdirty = i; 1201 1202 /* 1203 * Cancel the watchdog timer if there are no pending 1204 * transmissions. 1205 */ 1206 if (sc->sc_txpending == 0) 1207 ifp->if_timer = 0; 1208 } 1209 1210 /* 1211 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1212 */ 1213 1214 void 1215 fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1216 u_int len) 1217 { 1218 uint32_t csum_data; 1219 int csum_flags; 1220 1221 /* 1222 * check H/W Checksumming. 1223 */ 1224 1225 csum_flags = 0; 1226 csum_data = 0; 1227 1228 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1229 uint8_t rxparsestat; 1230 uint8_t csum_stat; 1231 1232 csum_stat = rfa->cksum_stat; 1233 rxparsestat = rfa->rx_parse_stat; 1234 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1235 goto out; 1236 1237 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1238 csum_flags = M_CSUM_IPv4; 1239 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1240 csum_flags |= M_CSUM_IPv4_BAD; 1241 } 1242 1243 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1244 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1245 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1246 csum_flags |= M_CSUM_TCP_UDP_BAD; 1247 } 1248 1249 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1251 struct ether_header *eh; 1252 struct ip *ip; 1253 struct udphdr *uh; 1254 u_int hlen, pktlen; 1255 1256 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1257 goto out; 1258 pktlen = len - ETHER_HDR_LEN; 1259 eh = mtod(m, struct ether_header *); 1260 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1261 goto out; 1262 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1263 if (ip->ip_v != IPVERSION) 1264 goto out; 1265 1266 hlen = ip->ip_hl << 2; 1267 if (hlen < sizeof(struct ip)) 1268 goto out; 1269 1270 /* 1271 * Bail if too short, has random trailing garbage, truncated, 1272 * fragment, or has ethernet pad. 1273 */ 1274 if (ntohs(ip->ip_len) < hlen || 1275 ntohs(ip->ip_len) != pktlen || 1276 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1277 goto out; 1278 1279 switch (ip->ip_p) { 1280 case IPPROTO_TCP: 1281 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1282 pktlen < (hlen + sizeof(struct tcphdr))) 1283 goto out; 1284 csum_flags = 1285 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1286 break; 1287 case IPPROTO_UDP: 1288 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1289 pktlen < (hlen + sizeof(struct udphdr))) 1290 goto out; 1291 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1292 if (uh->uh_sum == 0) 1293 goto out; /* no checksum */ 1294 csum_flags = 1295 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1296 break; 1297 default: 1298 goto out; 1299 } 1300 1301 /* Extract computed checksum. */ 1302 csum_data = be16dec(mtod(m, uint8_t *) + len); 1303 1304 /* 1305 * The computed checksum includes IP headers, 1306 * so we have to deduct them. 1307 */ 1308 #if 0 1309 /* 1310 * But in TCP/UDP layer we can assume the IP header is valid, 1311 * i.e. a sum of the whole IP header should be 0xffff, 1312 * so we don't have to bother to deduct it. 1313 */ 1314 if (hlen > 0) { 1315 uint32_t hsum; 1316 const uint16_t *iphdr; 1317 hsum = 0; 1318 iphdr = (uint16_t *)ip; 1319 1320 while (hlen > 1) { 1321 hsum += ntohs(*iphdr++); 1322 hlen -= sizeof(uint16_t); 1323 } 1324 while (hsum >> 16) 1325 hsum = (hsum >> 16) + (hsum & 0xffff); 1326 1327 csum_data += (uint16_t)~hsum; 1328 1329 while (csum_data >> 16) 1330 csum_data = 1331 (csum_data >> 16) + (csum_data & 0xffff); 1332 } 1333 #endif 1334 } 1335 out: 1336 m->m_pkthdr.csum_flags = csum_flags; 1337 m->m_pkthdr.csum_data = csum_data; 1338 } 1339 1340 /* 1341 * Handle receive interrupts. 1342 */ 1343 int 1344 fxp_rxintr(struct fxp_softc *sc) 1345 { 1346 struct ethercom *ec = &sc->sc_ethercom; 1347 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1348 struct mbuf *m, *m0; 1349 bus_dmamap_t rxmap; 1350 struct fxp_rfa *rfa; 1351 int rnr; 1352 uint16_t len, rxstat; 1353 1354 rnr = 0; 1355 1356 for (;;) { 1357 m = sc->sc_rxq.ifq_head; 1358 rfa = FXP_MTORFA(m); 1359 rxmap = M_GETCTX(m, bus_dmamap_t); 1360 1361 FXP_RFASYNC(sc, m, 1362 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1363 1364 rxstat = le16toh(rfa->rfa_status); 1365 1366 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1367 rnr = 1; 1368 1369 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1370 /* 1371 * We have processed all of the 1372 * receive buffers. 1373 */ 1374 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1375 return rnr; 1376 } 1377 1378 IF_DEQUEUE(&sc->sc_rxq, m); 1379 1380 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1381 1382 len = le16toh(rfa->actual_size) & 1383 (m->m_ext.ext_size - 1); 1384 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1385 /* Adjust for appended checksum bytes. */ 1386 len -= sizeof(uint16_t); 1387 } 1388 1389 if (len < sizeof(struct ether_header)) { 1390 /* 1391 * Runt packet; drop it now. 1392 */ 1393 FXP_INIT_RFABUF(sc, m); 1394 continue; 1395 } 1396 1397 /* 1398 * If support for 802.1Q VLAN sized frames is 1399 * enabled, we need to do some additional error 1400 * checking (as we are saving bad frames, in 1401 * order to receive the larger ones). 1402 */ 1403 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1404 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1405 FXP_RFA_STATUS_RNR| 1406 FXP_RFA_STATUS_ALIGN| 1407 FXP_RFA_STATUS_CRC)) != 0) { 1408 FXP_INIT_RFABUF(sc, m); 1409 continue; 1410 } 1411 1412 /* 1413 * check VLAN tag stripping. 1414 */ 1415 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1416 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) { 1417 struct m_tag *vtag; 1418 1419 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1420 M_NOWAIT); 1421 if (vtag == NULL) 1422 goto dropit; 1423 *(u_int *)(vtag + 1) = be16toh(rfa->vlan_id); 1424 m_tag_prepend(m, vtag); 1425 } 1426 1427 /* Do checksum checking. */ 1428 if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 1429 fxp_rx_hwcksum(sc, m, rfa, len); 1430 1431 /* 1432 * If the packet is small enough to fit in a 1433 * single header mbuf, allocate one and copy 1434 * the data into it. This greatly reduces 1435 * memory consumption when we receive lots 1436 * of small packets. 1437 * 1438 * Otherwise, we add a new buffer to the receive 1439 * chain. If this fails, we drop the packet and 1440 * recycle the old buffer. 1441 */ 1442 if (fxp_copy_small != 0 && len <= MHLEN) { 1443 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1444 if (m0 == NULL) 1445 goto dropit; 1446 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1447 memcpy(mtod(m0, void *), 1448 mtod(m, void *), len); 1449 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1450 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1451 FXP_INIT_RFABUF(sc, m); 1452 m = m0; 1453 } else { 1454 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1455 dropit: 1456 ifp->if_ierrors++; 1457 FXP_INIT_RFABUF(sc, m); 1458 continue; 1459 } 1460 } 1461 1462 m->m_pkthdr.rcvif = ifp; 1463 m->m_pkthdr.len = m->m_len = len; 1464 1465 /* 1466 * Pass this up to any BPF listeners, but only 1467 * pass it up the stack if it's for us. 1468 */ 1469 bpf_mtap(ifp, m); 1470 1471 /* Pass it on. */ 1472 (*ifp->if_input)(ifp, m); 1473 } 1474 } 1475 1476 /* 1477 * Update packet in/out/collision statistics. The i82557 doesn't 1478 * allow you to access these counters without doing a fairly 1479 * expensive DMA to get _all_ of the statistics it maintains, so 1480 * we do this operation here only once per second. The statistics 1481 * counters in the kernel are updated from the previous dump-stats 1482 * DMA and then a new dump-stats DMA is started. The on-chip 1483 * counters are zeroed when the DMA completes. If we can't start 1484 * the DMA immediately, we don't wait - we just prepare to read 1485 * them again next time. 1486 */ 1487 void 1488 fxp_tick(void *arg) 1489 { 1490 struct fxp_softc *sc = arg; 1491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1492 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1493 int s; 1494 1495 if (!device_is_active(sc->sc_dev)) 1496 return; 1497 1498 s = splnet(); 1499 1500 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1501 1502 ifp->if_opackets += le32toh(sp->tx_good); 1503 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1504 if (sp->rx_good) { 1505 ifp->if_ipackets += le32toh(sp->rx_good); 1506 sc->sc_rxidle = 0; 1507 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1508 sc->sc_rxidle++; 1509 } 1510 ifp->if_ierrors += 1511 le32toh(sp->rx_crc_errors) + 1512 le32toh(sp->rx_alignment_errors) + 1513 le32toh(sp->rx_rnr_errors) + 1514 le32toh(sp->rx_overrun_errors); 1515 /* 1516 * If any transmit underruns occurred, bump up the transmit 1517 * threshold by another 512 bytes (64 * 8). 1518 */ 1519 if (sp->tx_underruns) { 1520 ifp->if_oerrors += le32toh(sp->tx_underruns); 1521 if (tx_threshold < 192) 1522 tx_threshold += 64; 1523 } 1524 #ifdef FXP_EVENT_COUNTERS 1525 if (sc->sc_flags & FXPF_FC) { 1526 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1527 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1528 } 1529 #endif 1530 1531 /* 1532 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1533 * then assume the receiver has locked up and attempt to clear 1534 * the condition by reprogramming the multicast filter (actually, 1535 * resetting the interface). This is a work-around for a bug in 1536 * the 82557 where the receiver locks up if it gets certain types 1537 * of garbage in the synchronization bits prior to the packet header. 1538 * This bug is supposed to only occur in 10Mbps mode, but has been 1539 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1540 * speed transition). 1541 */ 1542 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1543 (void) fxp_init(ifp); 1544 splx(s); 1545 return; 1546 } 1547 /* 1548 * If there is no pending command, start another stats 1549 * dump. Otherwise punt for now. 1550 */ 1551 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1552 /* 1553 * Start another stats dump. 1554 */ 1555 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1556 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1557 } else { 1558 /* 1559 * A previous command is still waiting to be accepted. 1560 * Just zero our copy of the stats and wait for the 1561 * next timer event to update them. 1562 */ 1563 /* BIG_ENDIAN: no swap required to store 0 */ 1564 sp->tx_good = 0; 1565 sp->tx_underruns = 0; 1566 sp->tx_total_collisions = 0; 1567 1568 sp->rx_good = 0; 1569 sp->rx_crc_errors = 0; 1570 sp->rx_alignment_errors = 0; 1571 sp->rx_rnr_errors = 0; 1572 sp->rx_overrun_errors = 0; 1573 if (sc->sc_flags & FXPF_FC) { 1574 sp->tx_pauseframes = 0; 1575 sp->rx_pauseframes = 0; 1576 } 1577 } 1578 1579 if (sc->sc_flags & FXPF_MII) { 1580 /* Tick the MII clock. */ 1581 mii_tick(&sc->sc_mii); 1582 } 1583 1584 splx(s); 1585 1586 /* 1587 * Schedule another timeout one second from now. 1588 */ 1589 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1590 } 1591 1592 /* 1593 * Drain the receive queue. 1594 */ 1595 void 1596 fxp_rxdrain(struct fxp_softc *sc) 1597 { 1598 bus_dmamap_t rxmap; 1599 struct mbuf *m; 1600 1601 for (;;) { 1602 IF_DEQUEUE(&sc->sc_rxq, m); 1603 if (m == NULL) 1604 break; 1605 rxmap = M_GETCTX(m, bus_dmamap_t); 1606 bus_dmamap_unload(sc->sc_dmat, rxmap); 1607 FXP_RXMAP_PUT(sc, rxmap); 1608 m_freem(m); 1609 } 1610 } 1611 1612 /* 1613 * Stop the interface. Cancels the statistics updater and resets 1614 * the interface. 1615 */ 1616 void 1617 fxp_stop(struct ifnet *ifp, int disable) 1618 { 1619 struct fxp_softc *sc = ifp->if_softc; 1620 struct fxp_txsoft *txs; 1621 int i; 1622 1623 /* 1624 * Turn down interface (done early to avoid bad interactions 1625 * between panics, shutdown hooks, and the watchdog timer) 1626 */ 1627 ifp->if_timer = 0; 1628 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1629 1630 /* 1631 * Cancel stats updater. 1632 */ 1633 callout_stop(&sc->sc_callout); 1634 if (sc->sc_flags & FXPF_MII) { 1635 /* Down the MII. */ 1636 mii_down(&sc->sc_mii); 1637 } 1638 1639 /* 1640 * Issue software reset. This unloads any microcode that 1641 * might already be loaded. 1642 */ 1643 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1644 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1645 DELAY(50); 1646 1647 /* 1648 * Release any xmit buffers. 1649 */ 1650 for (i = 0; i < FXP_NTXCB; i++) { 1651 txs = FXP_DSTX(sc, i); 1652 if (txs->txs_mbuf != NULL) { 1653 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1654 m_freem(txs->txs_mbuf); 1655 txs->txs_mbuf = NULL; 1656 } 1657 } 1658 sc->sc_txpending = 0; 1659 1660 if (disable) { 1661 fxp_rxdrain(sc); 1662 fxp_disable(sc); 1663 } 1664 1665 } 1666 1667 /* 1668 * Watchdog/transmission transmit timeout handler. Called when a 1669 * transmission is started on the interface, but no interrupt is 1670 * received before the timeout. This usually indicates that the 1671 * card has wedged for some reason. 1672 */ 1673 void 1674 fxp_watchdog(struct ifnet *ifp) 1675 { 1676 struct fxp_softc *sc = ifp->if_softc; 1677 1678 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1679 ifp->if_oerrors++; 1680 1681 (void) fxp_init(ifp); 1682 } 1683 1684 /* 1685 * Initialize the interface. Must be called at splnet(). 1686 */ 1687 int 1688 fxp_init(struct ifnet *ifp) 1689 { 1690 struct fxp_softc *sc = ifp->if_softc; 1691 struct fxp_cb_config *cbp; 1692 struct fxp_cb_ias *cb_ias; 1693 struct fxp_txdesc *txd; 1694 bus_dmamap_t rxmap; 1695 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1696 uint16_t status; 1697 1698 if ((error = fxp_enable(sc)) != 0) 1699 goto out; 1700 1701 /* 1702 * Cancel any pending I/O 1703 */ 1704 fxp_stop(ifp, 0); 1705 1706 /* 1707 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1708 * flag, and this prevents the MII from detaching resulting in 1709 * a panic. The flags field should perhaps be split in runtime 1710 * flags and more static information. For now, just clear the 1711 * only other flag set. 1712 */ 1713 1714 sc->sc_flags &= ~FXPF_WANTINIT; 1715 1716 /* 1717 * Initialize base of CBL and RFA memory. Loading with zero 1718 * sets it up for regular linear addressing. 1719 */ 1720 fxp_scb_wait(sc); 1721 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1722 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1723 1724 fxp_scb_wait(sc); 1725 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1726 1727 /* 1728 * Initialize the multicast filter. Do this now, since we might 1729 * have to setup the config block differently. 1730 */ 1731 fxp_mc_setup(sc); 1732 1733 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1734 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1735 1736 /* 1737 * In order to support receiving 802.1Q VLAN frames, we have to 1738 * enable "save bad frames", since they are 4 bytes larger than 1739 * the normal Ethernet maximum frame length. On i82558 and later, 1740 * we have a better mechanism for this. 1741 */ 1742 save_bf = 0; 1743 lrxen = 0; 1744 vlan_drop = 0; 1745 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1746 if (sc->sc_rev < FXP_REV_82558_A4) 1747 save_bf = 1; 1748 else 1749 lrxen = 1; 1750 if (sc->sc_rev >= FXP_REV_82550) 1751 vlan_drop = 1; 1752 } 1753 1754 /* 1755 * Initialize base of dump-stats buffer. 1756 */ 1757 fxp_scb_wait(sc); 1758 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1759 sc->sc_cddma + FXP_CDSTATSOFF); 1760 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1761 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1762 1763 cbp = &sc->sc_control_data->fcd_configcb; 1764 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1765 1766 /* 1767 * Load microcode for this controller. 1768 */ 1769 fxp_load_ucode(sc); 1770 1771 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1772 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1773 else 1774 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1775 1776 /* 1777 * This copy is kind of disgusting, but there are a bunch of must be 1778 * zero and must be one bits in this structure and this is the easiest 1779 * way to initialize them all to proper values. 1780 */ 1781 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1782 1783 /* BIG_ENDIAN: no need to swap to store 0 */ 1784 cbp->cb_status = 0; 1785 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1786 FXP_CB_COMMAND_EL); 1787 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1788 cbp->link_addr = 0xffffffff; /* (no) next command */ 1789 /* bytes in config block */ 1790 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1791 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1792 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1793 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1794 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1795 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1796 cbp->type_enable = 0; /* actually reserved */ 1797 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1798 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1799 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1800 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1801 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1802 cbp->late_scb = 0; /* (don't) defer SCB update */ 1803 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1804 cbp->ci_int = 1; /* interrupt on CU idle */ 1805 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1806 cbp->ext_stats_dis = 1; /* disable extended counters */ 1807 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1808 cbp->save_bf = save_bf;/* save bad frames */ 1809 cbp->disc_short_rx = !prm; /* discard short packets */ 1810 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1811 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1812 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1813 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1814 /* interface mode */ 1815 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1816 cbp->csma_dis = 0; /* (don't) disable link */ 1817 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1818 /* (don't) enable RX checksum */ 1819 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1820 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1821 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1822 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1823 cbp->nsai = 1; /* (don't) disable source addr insert */ 1824 cbp->preamble_length = 2; /* (7 byte) preamble */ 1825 cbp->loopback = 0; /* (don't) loopback */ 1826 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1827 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1828 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1829 cbp->promiscuous = prm; /* promiscuous mode */ 1830 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1831 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1832 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1833 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1834 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1835 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1836 cbp->padding = 1; /* (do) pad short tx packets */ 1837 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1838 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1839 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1840 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1841 /* must set wake_en in PMCSR also */ 1842 cbp->force_fdx = 0; /* (don't) force full duplex */ 1843 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1844 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1845 cbp->mc_all = allm; /* accept all multicasts */ 1846 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1847 cbp->vlan_drop_en = vlan_drop; 1848 1849 if (!(sc->sc_flags & FXPF_FC)) { 1850 /* 1851 * The i82557 has no hardware flow control, the values 1852 * here are the defaults for the chip. 1853 */ 1854 cbp->fc_delay_lsb = 0; 1855 cbp->fc_delay_msb = 0x40; 1856 cbp->pri_fc_thresh = 3; 1857 cbp->tx_fc_dis = 0; 1858 cbp->rx_fc_restop = 0; 1859 cbp->rx_fc_restart = 0; 1860 cbp->fc_filter = 0; 1861 cbp->pri_fc_loc = 1; 1862 } else { 1863 cbp->fc_delay_lsb = 0x1f; 1864 cbp->fc_delay_msb = 0x01; 1865 cbp->pri_fc_thresh = 3; 1866 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1867 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1868 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1869 cbp->fc_filter = !prm; /* drop FC frames to host */ 1870 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1871 cbp->ext_stats_dis = 0; /* enable extended stats */ 1872 } 1873 1874 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1875 1876 /* 1877 * Start the config command/DMA. 1878 */ 1879 fxp_scb_wait(sc); 1880 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1881 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1882 /* ...and wait for it to complete. */ 1883 for (i = 1000; i > 0; i--) { 1884 FXP_CDCONFIGSYNC(sc, 1885 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1886 status = le16toh(cbp->cb_status); 1887 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1888 if ((status & FXP_CB_STATUS_C) != 0) 1889 break; 1890 DELAY(1); 1891 } 1892 if (i == 0) { 1893 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1894 device_xname(sc->sc_dev), __LINE__); 1895 return (ETIMEDOUT); 1896 } 1897 1898 /* 1899 * Initialize the station address. 1900 */ 1901 cb_ias = &sc->sc_control_data->fcd_iascb; 1902 /* BIG_ENDIAN: no need to swap to store 0 */ 1903 cb_ias->cb_status = 0; 1904 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1905 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1906 cb_ias->link_addr = 0xffffffff; 1907 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1908 1909 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1910 1911 /* 1912 * Start the IAS (Individual Address Setup) command/DMA. 1913 */ 1914 fxp_scb_wait(sc); 1915 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1916 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1917 /* ...and wait for it to complete. */ 1918 for (i = 1000; i > 0; i++) { 1919 FXP_CDIASSYNC(sc, 1920 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1921 status = le16toh(cb_ias->cb_status); 1922 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1923 if ((status & FXP_CB_STATUS_C) != 0) 1924 break; 1925 DELAY(1); 1926 } 1927 if (i == 0) { 1928 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1929 device_xname(sc->sc_dev), __LINE__); 1930 return (ETIMEDOUT); 1931 } 1932 1933 /* 1934 * Initialize the transmit descriptor ring. txlast is initialized 1935 * to the end of the list so that it will wrap around to the first 1936 * descriptor when the first packet is transmitted. 1937 */ 1938 for (i = 0; i < FXP_NTXCB; i++) { 1939 txd = FXP_CDTX(sc, i); 1940 memset(txd, 0, sizeof(*txd)); 1941 txd->txd_txcb.cb_command = 1942 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1943 txd->txd_txcb.link_addr = 1944 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1945 if (sc->sc_flags & FXPF_EXT_TXCB) 1946 txd->txd_txcb.tbd_array_addr = 1947 htole32(FXP_CDTBDADDR(sc, i) + 1948 (2 * sizeof(struct fxp_tbd))); 1949 else 1950 txd->txd_txcb.tbd_array_addr = 1951 htole32(FXP_CDTBDADDR(sc, i)); 1952 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1953 } 1954 sc->sc_txpending = 0; 1955 sc->sc_txdirty = 0; 1956 sc->sc_txlast = FXP_NTXCB - 1; 1957 1958 /* 1959 * Initialize the receive buffer list. 1960 */ 1961 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1962 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1963 rxmap = FXP_RXMAP_GET(sc); 1964 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1965 log(LOG_ERR, "%s: unable to allocate or map rx " 1966 "buffer %d, error = %d\n", 1967 device_xname(sc->sc_dev), 1968 sc->sc_rxq.ifq_len, error); 1969 /* 1970 * XXX Should attempt to run with fewer receive 1971 * XXX buffers instead of just failing. 1972 */ 1973 FXP_RXMAP_PUT(sc, rxmap); 1974 fxp_rxdrain(sc); 1975 goto out; 1976 } 1977 } 1978 sc->sc_rxidle = 0; 1979 1980 /* 1981 * Give the transmit ring to the chip. We do this by pointing 1982 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1983 * issuing a start command. It will execute the NOP and then 1984 * suspend, pointing at the first descriptor. 1985 */ 1986 fxp_scb_wait(sc); 1987 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1988 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1989 1990 /* 1991 * Initialize receiver buffer area - RFA. 1992 */ 1993 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1994 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1995 fxp_scb_wait(sc); 1996 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1997 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1998 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1999 #endif 2000 2001 if (sc->sc_flags & FXPF_MII) { 2002 /* 2003 * Set current media. 2004 */ 2005 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 2006 goto out; 2007 } 2008 2009 /* 2010 * ...all done! 2011 */ 2012 ifp->if_flags |= IFF_RUNNING; 2013 ifp->if_flags &= ~IFF_OACTIVE; 2014 2015 /* 2016 * Request a software generated interrupt that will be used to 2017 * (re)start the RU processing. If we direct the chip to start 2018 * receiving from the start of queue now, instead of letting the 2019 * interrupt handler first process all received packets, we run 2020 * the risk of having it overwrite mbuf clusters while they are 2021 * being processed or after they have been returned to the pool. 2022 */ 2023 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 2024 2025 /* 2026 * Start the one second timer. 2027 */ 2028 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 2029 2030 /* 2031 * Attempt to start output on the interface. 2032 */ 2033 fxp_start(ifp); 2034 2035 out: 2036 if (error) { 2037 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2038 ifp->if_timer = 0; 2039 log(LOG_ERR, "%s: interface not running\n", 2040 device_xname(sc->sc_dev)); 2041 } 2042 return (error); 2043 } 2044 2045 /* 2046 * Notify the world which media we're using. 2047 */ 2048 void 2049 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2050 { 2051 struct fxp_softc *sc = ifp->if_softc; 2052 2053 if (sc->sc_enabled == 0) { 2054 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2055 ifmr->ifm_status = 0; 2056 return; 2057 } 2058 2059 ether_mediastatus(ifp, ifmr); 2060 } 2061 2062 int 2063 fxp_80c24_mediachange(struct ifnet *ifp) 2064 { 2065 2066 /* Nothing to do here. */ 2067 return (0); 2068 } 2069 2070 void 2071 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2072 { 2073 struct fxp_softc *sc = ifp->if_softc; 2074 2075 /* 2076 * Media is currently-selected media. We cannot determine 2077 * the link status. 2078 */ 2079 ifmr->ifm_status = 0; 2080 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2081 } 2082 2083 /* 2084 * Add a buffer to the end of the RFA buffer list. 2085 * Return 0 if successful, error code on failure. 2086 * 2087 * The RFA struct is stuck at the beginning of mbuf cluster and the 2088 * data pointer is fixed up to point just past it. 2089 */ 2090 int 2091 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2092 { 2093 struct mbuf *m; 2094 int error; 2095 2096 MGETHDR(m, M_DONTWAIT, MT_DATA); 2097 if (m == NULL) 2098 return (ENOBUFS); 2099 2100 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2101 MCLGET(m, M_DONTWAIT); 2102 if ((m->m_flags & M_EXT) == 0) { 2103 m_freem(m); 2104 return (ENOBUFS); 2105 } 2106 2107 if (unload) 2108 bus_dmamap_unload(sc->sc_dmat, rxmap); 2109 2110 M_SETCTX(m, rxmap); 2111 2112 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2113 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2114 BUS_DMA_READ|BUS_DMA_NOWAIT); 2115 if (error) { 2116 /* XXX XXX XXX */ 2117 aprint_error_dev(sc->sc_dev, 2118 "can't load rx DMA map %d, error = %d\n", 2119 sc->sc_rxq.ifq_len, error); 2120 panic("fxp_add_rfabuf"); 2121 } 2122 2123 FXP_INIT_RFABUF(sc, m); 2124 2125 return (0); 2126 } 2127 2128 int 2129 fxp_mdi_read(device_t self, int phy, int reg) 2130 { 2131 struct fxp_softc *sc = device_private(self); 2132 int count = 10000; 2133 int value; 2134 2135 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2136 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2137 2138 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2139 0x10000000) == 0 && count--) 2140 DELAY(10); 2141 2142 if (count <= 0) 2143 log(LOG_WARNING, 2144 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2145 2146 return (value & 0xffff); 2147 } 2148 2149 void 2150 fxp_statchg(device_t self) 2151 { 2152 2153 /* Nothing to do. */ 2154 } 2155 2156 void 2157 fxp_mdi_write(device_t self, int phy, int reg, int value) 2158 { 2159 struct fxp_softc *sc = device_private(self); 2160 int count = 10000; 2161 2162 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2163 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2164 (value & 0xffff)); 2165 2166 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2167 count--) 2168 DELAY(10); 2169 2170 if (count <= 0) 2171 log(LOG_WARNING, 2172 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2173 } 2174 2175 int 2176 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2177 { 2178 struct fxp_softc *sc = ifp->if_softc; 2179 struct ifreq *ifr = (struct ifreq *)data; 2180 int s, error; 2181 2182 s = splnet(); 2183 2184 switch (cmd) { 2185 case SIOCSIFMEDIA: 2186 case SIOCGIFMEDIA: 2187 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2188 break; 2189 2190 default: 2191 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2192 break; 2193 2194 error = 0; 2195 2196 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2197 ; 2198 else if (ifp->if_flags & IFF_RUNNING) { 2199 /* 2200 * Multicast list has changed; set the 2201 * hardware filter accordingly. 2202 */ 2203 while (sc->sc_txpending) { 2204 sc->sc_flags |= FXPF_WANTINIT; 2205 tsleep(sc, PSOCK, "fxp_init", 0); 2206 } 2207 error = fxp_init(ifp); 2208 } 2209 break; 2210 } 2211 2212 /* Try to get more packets going. */ 2213 if (sc->sc_enabled) 2214 fxp_start(ifp); 2215 2216 splx(s); 2217 return (error); 2218 } 2219 2220 /* 2221 * Program the multicast filter. 2222 * 2223 * This function must be called at splnet(). 2224 */ 2225 void 2226 fxp_mc_setup(struct fxp_softc *sc) 2227 { 2228 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2229 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2230 struct ethercom *ec = &sc->sc_ethercom; 2231 struct ether_multi *enm; 2232 struct ether_multistep step; 2233 int count, nmcasts; 2234 uint16_t status; 2235 2236 #ifdef DIAGNOSTIC 2237 if (sc->sc_txpending) 2238 panic("fxp_mc_setup: pending transmissions"); 2239 #endif 2240 2241 ifp->if_flags &= ~IFF_ALLMULTI; 2242 2243 /* 2244 * Initialize multicast setup descriptor. 2245 */ 2246 nmcasts = 0; 2247 ETHER_FIRST_MULTI(step, ec, enm); 2248 while (enm != NULL) { 2249 /* 2250 * Check for too many multicast addresses or if we're 2251 * listening to a range. Either way, we simply have 2252 * to accept all multicasts. 2253 */ 2254 if (nmcasts >= MAXMCADDR || 2255 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2256 ETHER_ADDR_LEN) != 0) { 2257 /* 2258 * Callers of this function must do the 2259 * right thing with this. If we're called 2260 * from outside fxp_init(), the caller must 2261 * detect if the state if IFF_ALLMULTI changes. 2262 * If it does, the caller must then call 2263 * fxp_init(), since allmulti is handled by 2264 * the config block. 2265 */ 2266 ifp->if_flags |= IFF_ALLMULTI; 2267 return; 2268 } 2269 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2270 ETHER_ADDR_LEN); 2271 nmcasts++; 2272 ETHER_NEXT_MULTI(step, enm); 2273 } 2274 2275 /* BIG_ENDIAN: no need to swap to store 0 */ 2276 mcsp->cb_status = 0; 2277 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2278 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2279 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2280 2281 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2282 2283 /* 2284 * Wait until the command unit is not active. This should never 2285 * happen since nothing is queued, but make sure anyway. 2286 */ 2287 count = 100; 2288 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2289 FXP_SCB_CUS_ACTIVE && --count) 2290 DELAY(1); 2291 if (count == 0) { 2292 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2293 device_xname(sc->sc_dev), __LINE__); 2294 return; 2295 } 2296 2297 /* 2298 * Start the multicast setup command/DMA. 2299 */ 2300 fxp_scb_wait(sc); 2301 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2302 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2303 2304 /* ...and wait for it to complete. */ 2305 for (count = 1000; count > 0; count--) { 2306 FXP_CDMCSSYNC(sc, 2307 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2308 status = le16toh(mcsp->cb_status); 2309 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2310 if ((status & FXP_CB_STATUS_C) != 0) 2311 break; 2312 DELAY(1); 2313 } 2314 if (count == 0) { 2315 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2316 device_xname(sc->sc_dev), __LINE__); 2317 return; 2318 } 2319 } 2320 2321 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2322 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2323 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2324 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2325 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2326 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2327 2328 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2329 2330 static const struct ucode { 2331 int32_t revision; 2332 const uint32_t *ucode; 2333 size_t length; 2334 uint16_t int_delay_offset; 2335 uint16_t bundle_max_offset; 2336 } ucode_table[] = { 2337 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2338 D101_CPUSAVER_DWORD, 0 }, 2339 2340 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2341 D101_CPUSAVER_DWORD, 0 }, 2342 2343 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2344 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2345 2346 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2347 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2348 2349 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2350 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2351 2352 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2353 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2354 2355 { 0, NULL, 0, 0, 0 } 2356 }; 2357 2358 void 2359 fxp_load_ucode(struct fxp_softc *sc) 2360 { 2361 const struct ucode *uc; 2362 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2363 int count, i; 2364 uint16_t status; 2365 2366 if (sc->sc_flags & FXPF_UCODE_LOADED) 2367 return; 2368 2369 /* 2370 * Only load the uCode if the user has requested that 2371 * we do so. 2372 */ 2373 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2374 sc->sc_int_delay = 0; 2375 sc->sc_bundle_max = 0; 2376 return; 2377 } 2378 2379 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2380 if (sc->sc_rev == uc->revision) 2381 break; 2382 } 2383 if (uc->ucode == NULL) 2384 return; 2385 2386 /* BIG ENDIAN: no need to swap to store 0 */ 2387 cbp->cb_status = 0; 2388 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2389 cbp->link_addr = 0xffffffff; /* (no) next command */ 2390 for (i = 0; i < uc->length; i++) 2391 cbp->ucode[i] = htole32(uc->ucode[i]); 2392 2393 if (uc->int_delay_offset) 2394 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2395 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2396 2397 if (uc->bundle_max_offset) 2398 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2399 htole16(fxp_bundle_max); 2400 2401 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2402 2403 /* 2404 * Download the uCode to the chip. 2405 */ 2406 fxp_scb_wait(sc); 2407 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2408 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2409 2410 /* ...and wait for it to complete. */ 2411 for (count = 10000; count > 0; count--) { 2412 FXP_CDUCODESYNC(sc, 2413 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2414 status = le16toh(cbp->cb_status); 2415 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2416 if ((status & FXP_CB_STATUS_C) != 0) 2417 break; 2418 DELAY(2); 2419 } 2420 if (count == 0) { 2421 sc->sc_int_delay = 0; 2422 sc->sc_bundle_max = 0; 2423 log(LOG_WARNING, "%s: timeout loading microcode\n", 2424 device_xname(sc->sc_dev)); 2425 return; 2426 } 2427 2428 if (sc->sc_int_delay != fxp_int_delay || 2429 sc->sc_bundle_max != fxp_bundle_max) { 2430 sc->sc_int_delay = fxp_int_delay; 2431 sc->sc_bundle_max = fxp_bundle_max; 2432 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2433 "max bundle: %d\n", device_xname(sc->sc_dev), 2434 sc->sc_int_delay, 2435 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2436 } 2437 2438 sc->sc_flags |= FXPF_UCODE_LOADED; 2439 } 2440 2441 int 2442 fxp_enable(struct fxp_softc *sc) 2443 { 2444 2445 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2446 if ((*sc->sc_enable)(sc) != 0) { 2447 log(LOG_ERR, "%s: device enable failed\n", 2448 device_xname(sc->sc_dev)); 2449 return (EIO); 2450 } 2451 } 2452 2453 sc->sc_enabled = 1; 2454 return (0); 2455 } 2456 2457 void 2458 fxp_disable(struct fxp_softc *sc) 2459 { 2460 2461 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2462 (*sc->sc_disable)(sc); 2463 sc->sc_enabled = 0; 2464 } 2465 } 2466 2467 /* 2468 * fxp_activate: 2469 * 2470 * Handle device activation/deactivation requests. 2471 */ 2472 int 2473 fxp_activate(device_t self, enum devact act) 2474 { 2475 struct fxp_softc *sc = device_private(self); 2476 2477 switch (act) { 2478 case DVACT_DEACTIVATE: 2479 if_deactivate(&sc->sc_ethercom.ec_if); 2480 return 0; 2481 default: 2482 return EOPNOTSUPP; 2483 } 2484 } 2485 2486 /* 2487 * fxp_detach: 2488 * 2489 * Detach an i82557 interface. 2490 */ 2491 int 2492 fxp_detach(struct fxp_softc *sc, int flags) 2493 { 2494 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2495 int i, s; 2496 2497 /* Succeed now if there's no work to do. */ 2498 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2499 return (0); 2500 2501 s = splnet(); 2502 /* Stop the interface. Callouts are stopped in it. */ 2503 fxp_stop(ifp, 1); 2504 splx(s); 2505 2506 /* Destroy our callout. */ 2507 callout_destroy(&sc->sc_callout); 2508 2509 if (sc->sc_flags & FXPF_MII) { 2510 /* Detach all PHYs */ 2511 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2512 } 2513 2514 /* Delete all remaining media. */ 2515 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2516 2517 #if NRND > 0 2518 rnd_detach_source(&sc->rnd_source); 2519 #endif 2520 ether_ifdetach(ifp); 2521 if_detach(ifp); 2522 2523 for (i = 0; i < FXP_NRFABUFS; i++) { 2524 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2525 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2526 } 2527 2528 for (i = 0; i < FXP_NTXCB; i++) { 2529 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2530 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2531 } 2532 2533 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2534 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2535 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2536 sizeof(struct fxp_control_data)); 2537 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2538 2539 return (0); 2540 } 2541
Indexes created Mon Sep 29 21:09:56 GMT 2025