i82557.c revision 1.148
1 /* $NetBSD: i82557.c,v 1.148 2017/09/26 07:42:06 knakahara Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.148 2017/09/26 07:42:06 knakahara Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/callout.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/ioctl.h> 79 #include <sys/errno.h> 80 #include <sys/device.h> 81 #include <sys/syslog.h> 82 #include <sys/proc.h> 83 84 #include <machine/endian.h> 85 86 #include <sys/rndsource.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 #include <net/if_ether.h> 92 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/ip.h> 96 #include <netinet/tcp.h> 97 #include <netinet/udp.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 104 #include <dev/mii/miivar.h> 105 106 #include <dev/ic/i82557reg.h> 107 #include <dev/ic/i82557var.h> 108 109 #include <dev/microcode/i8255x/rcvbundl.h> 110 111 /* 112 * NOTE! On the Alpha, we have an alignment constraint. The 113 * card DMAs the packet immediately following the RFA. However, 114 * the first thing in the packet is a 14-byte Ethernet header. 115 * This means that the packet is misaligned. To compensate, 116 * we actually offset the RFA 2 bytes into the cluster. This 117 * alignes the packet after the Ethernet header at a 32-bit 118 * boundary. HOWEVER! This means that the RFA is misaligned! 119 */ 120 #define RFA_ALIGNMENT_FUDGE 2 121 122 /* 123 * The configuration byte map has several undefined fields which 124 * must be one or must be zero. Set up a template for these bits 125 * only (assuming an i82557 chip), leaving the actual configuration 126 * for fxp_init(). 127 * 128 * See the definition of struct fxp_cb_config for the bit definitions. 129 */ 130 const uint8_t fxp_cb_config_template[] = { 131 0x0, 0x0, /* cb_status */ 132 0x0, 0x0, /* cb_command */ 133 0x0, 0x0, 0x0, 0x0, /* link_addr */ 134 0x0, /* 0 */ 135 0x0, /* 1 */ 136 0x0, /* 2 */ 137 0x0, /* 3 */ 138 0x0, /* 4 */ 139 0x0, /* 5 */ 140 0x32, /* 6 */ 141 0x0, /* 7 */ 142 0x0, /* 8 */ 143 0x0, /* 9 */ 144 0x6, /* 10 */ 145 0x0, /* 11 */ 146 0x0, /* 12 */ 147 0x0, /* 13 */ 148 0xf2, /* 14 */ 149 0x48, /* 15 */ 150 0x0, /* 16 */ 151 0x40, /* 17 */ 152 0xf0, /* 18 */ 153 0x0, /* 19 */ 154 0x3f, /* 20 */ 155 0x5, /* 21 */ 156 0x0, /* 22 */ 157 0x0, /* 23 */ 158 0x0, /* 24 */ 159 0x0, /* 25 */ 160 0x0, /* 26 */ 161 0x0, /* 27 */ 162 0x0, /* 28 */ 163 0x0, /* 29 */ 164 0x0, /* 30 */ 165 0x0, /* 31 */ 166 }; 167 168 void fxp_mii_initmedia(struct fxp_softc *); 169 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 170 171 void fxp_80c24_initmedia(struct fxp_softc *); 172 int fxp_80c24_mediachange(struct ifnet *); 173 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 174 175 void fxp_start(struct ifnet *); 176 int fxp_ioctl(struct ifnet *, u_long, void *); 177 void fxp_watchdog(struct ifnet *); 178 int fxp_init(struct ifnet *); 179 void fxp_stop(struct ifnet *, int); 180 181 void fxp_txintr(struct fxp_softc *); 182 int fxp_rxintr(struct fxp_softc *); 183 184 void fxp_rx_hwcksum(struct fxp_softc *,struct mbuf *, 185 const struct fxp_rfa *, u_int); 186 187 void fxp_rxdrain(struct fxp_softc *); 188 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 189 int fxp_mdi_read(device_t, int, int); 190 void fxp_statchg(struct ifnet *); 191 void fxp_mdi_write(device_t, int, int, int); 192 void fxp_autosize_eeprom(struct fxp_softc*); 193 void fxp_read_eeprom(struct fxp_softc *, uint16_t *, int, int); 194 void fxp_write_eeprom(struct fxp_softc *, uint16_t *, int, int); 195 void fxp_eeprom_update_cksum(struct fxp_softc *); 196 void fxp_get_info(struct fxp_softc *, uint8_t *); 197 void fxp_tick(void *); 198 void fxp_mc_setup(struct fxp_softc *); 199 void fxp_load_ucode(struct fxp_softc *); 200 201 int fxp_copy_small = 0; 202 203 /* 204 * Variables for interrupt mitigating microcode. 205 */ 206 int fxp_int_delay = 1000; /* usec */ 207 int fxp_bundle_max = 6; /* packets */ 208 209 struct fxp_phytype { 210 int fp_phy; /* type of PHY, -1 for MII at the end. */ 211 void (*fp_init)(struct fxp_softc *); 212 } fxp_phytype_table[] = { 213 { FXP_PHY_80C24, fxp_80c24_initmedia }, 214 { -1, fxp_mii_initmedia }, 215 }; 216 217 /* 218 * Set initial transmit threshold at 64 (512 bytes). This is 219 * increased by 64 (512 bytes) at a time, to maximum of 192 220 * (1536 bytes), if an underrun occurs. 221 */ 222 static int tx_threshold = 64; 223 224 /* 225 * Wait for the previous command to be accepted (but not necessarily 226 * completed). 227 */ 228 static inline void 229 fxp_scb_wait(struct fxp_softc *sc) 230 { 231 int i = 10000; 232 233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 234 delay(2); 235 if (i == 0) 236 log(LOG_WARNING, 237 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 238 } 239 240 /* 241 * Submit a command to the i82557. 242 */ 243 static inline void 244 fxp_scb_cmd(struct fxp_softc *sc, uint8_t cmd) 245 { 246 247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 248 } 249 250 /* 251 * Finish attaching an i82557 interface. Called by bus-specific front-end. 252 */ 253 void 254 fxp_attach(struct fxp_softc *sc) 255 { 256 uint8_t enaddr[ETHER_ADDR_LEN]; 257 struct ifnet *ifp; 258 bus_dma_segment_t seg; 259 int rseg, i, error; 260 struct fxp_phytype *fp; 261 262 callout_init(&sc->sc_callout, 0); 263 264 /* 265 * Enable use of extended RFDs and IPCBs for 82550 and later chips. 266 * Note: to use IPCB we need extended TXCB support too, and 267 * these feature flags should be set in each bus attachment. 268 */ 269 if (sc->sc_flags & FXPF_EXT_RFA) { 270 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 271 sc->sc_rfa_size = RFA_EXT_SIZE; 272 } else { 273 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 274 sc->sc_rfa_size = RFA_SIZE; 275 } 276 277 /* 278 * Allocate the control data structures, and create and load the 279 * DMA map for it. 280 */ 281 if ((error = bus_dmamem_alloc(sc->sc_dmat, 282 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 283 0)) != 0) { 284 aprint_error_dev(sc->sc_dev, 285 "unable to allocate control data, error = %d\n", 286 error); 287 goto fail_0; 288 } 289 290 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 291 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 292 BUS_DMA_COHERENT)) != 0) { 293 aprint_error_dev(sc->sc_dev, 294 "unable to map control data, error = %d\n", error); 295 goto fail_1; 296 } 297 sc->sc_cdseg = seg; 298 sc->sc_cdnseg = rseg; 299 300 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 301 302 if ((error = bus_dmamap_create(sc->sc_dmat, 303 sizeof(struct fxp_control_data), 1, 304 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 305 aprint_error_dev(sc->sc_dev, 306 "unable to create control data DMA map, error = %d\n", 307 error); 308 goto fail_2; 309 } 310 311 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 312 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 313 0)) != 0) { 314 aprint_error_dev(sc->sc_dev, 315 "can't load control data DMA map, error = %d\n", 316 error); 317 goto fail_3; 318 } 319 320 /* 321 * Create the transmit buffer DMA maps. 322 */ 323 for (i = 0; i < FXP_NTXCB; i++) { 324 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 325 (sc->sc_flags & FXPF_EXT_RFA) ? 326 FXP_IPCB_NTXSEG : FXP_NTXSEG, 327 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 328 aprint_error_dev(sc->sc_dev, 329 "unable to create tx DMA map %d, error = %d\n", 330 i, error); 331 goto fail_4; 332 } 333 } 334 335 /* 336 * Create the receive buffer DMA maps. 337 */ 338 for (i = 0; i < FXP_NRFABUFS; i++) { 339 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 340 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 341 aprint_error_dev(sc->sc_dev, 342 "unable to create rx DMA map %d, error = %d\n", 343 i, error); 344 goto fail_5; 345 } 346 } 347 348 /* Initialize MAC address and media structures. */ 349 fxp_get_info(sc, enaddr); 350 351 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 352 ether_sprintf(enaddr)); 353 354 ifp = &sc->sc_ethercom.ec_if; 355 356 /* 357 * Get info about our media interface, and initialize it. Note 358 * the table terminates itself with a phy of -1, indicating 359 * that we're using MII. 360 */ 361 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 362 if (fp->fp_phy == sc->phy_primary_device) 363 break; 364 (*fp->fp_init)(sc); 365 366 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = fxp_ioctl; 370 ifp->if_start = fxp_start; 371 ifp->if_watchdog = fxp_watchdog; 372 ifp->if_init = fxp_init; 373 ifp->if_stop = fxp_stop; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 if (sc->sc_flags & FXPF_EXT_RFA) { 377 /* 378 * Enable hardware cksum support by EXT_RFA and IPCB. 379 * 380 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 381 * at least, on i82550 rev.12. 382 * specifically, it doesn't set ipv4 checksum properly 383 * when sending UDP (and probably TCP) packets with 384 * 20 byte ipv4 header + 1 or 2 byte data, 385 * though ICMP packets seem working. 386 * FreeBSD driver has related comments. 387 * We've added a workaround to handle the bug by padding 388 * such packets manually. 389 */ 390 ifp->if_capabilities = 391 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 392 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 393 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 394 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 395 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 396 ifp->if_capabilities = 397 IFCAP_CSUM_TCPv4_Rx | 398 IFCAP_CSUM_UDPv4_Rx; 399 } 400 401 /* 402 * We can support 802.1Q VLAN-sized frames. 403 */ 404 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 405 406 /* 407 * Attach the interface. 408 */ 409 if_attach(ifp); 410 if_deferred_start_init(ifp, NULL); 411 ether_ifattach(ifp, enaddr); 412 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 413 RND_TYPE_NET, RND_FLAG_DEFAULT); 414 415 #ifdef FXP_EVENT_COUNTERS 416 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 417 NULL, device_xname(sc->sc_dev), "txstall"); 418 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 419 NULL, device_xname(sc->sc_dev), "txintr"); 420 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 421 NULL, device_xname(sc->sc_dev), "rxintr"); 422 if (sc->sc_flags & FXPF_FC) { 423 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 424 NULL, device_xname(sc->sc_dev), "txpause"); 425 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 426 NULL, device_xname(sc->sc_dev), "rxpause"); 427 } 428 #endif /* FXP_EVENT_COUNTERS */ 429 430 /* The attach is successful. */ 431 sc->sc_flags |= FXPF_ATTACHED; 432 433 return; 434 435 /* 436 * Free any resources we've allocated during the failed attach 437 * attempt. Do this in reverse order and fall though. 438 */ 439 fail_5: 440 for (i = 0; i < FXP_NRFABUFS; i++) { 441 if (sc->sc_rxmaps[i] != NULL) 442 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 443 } 444 fail_4: 445 for (i = 0; i < FXP_NTXCB; i++) { 446 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 447 bus_dmamap_destroy(sc->sc_dmat, 448 FXP_DSTX(sc, i)->txs_dmamap); 449 } 450 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 451 fail_3: 452 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 453 fail_2: 454 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 455 sizeof(struct fxp_control_data)); 456 fail_1: 457 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 458 fail_0: 459 return; 460 } 461 462 void 463 fxp_mii_initmedia(struct fxp_softc *sc) 464 { 465 int flags; 466 467 sc->sc_flags |= FXPF_MII; 468 469 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 470 sc->sc_mii.mii_readreg = fxp_mdi_read; 471 sc->sc_mii.mii_writereg = fxp_mdi_write; 472 sc->sc_mii.mii_statchg = fxp_statchg; 473 474 sc->sc_ethercom.ec_mii = &sc->sc_mii; 475 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 476 fxp_mii_mediastatus); 477 478 flags = MIIF_NOISOLATE; 479 if (sc->sc_flags & FXPF_FC) 480 flags |= MIIF_FORCEANEG|MIIF_DOPAUSE; 481 /* 482 * The i82557 wedges if all of its PHYs are isolated! 483 */ 484 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 485 MII_OFFSET_ANY, flags); 486 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 487 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 488 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 489 } else 490 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 491 } 492 493 void 494 fxp_80c24_initmedia(struct fxp_softc *sc) 495 { 496 497 /* 498 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 499 * doesn't have a programming interface of any sort. The 500 * media is sensed automatically based on how the link partner 501 * is configured. This is, in essence, manual configuration. 502 */ 503 aprint_normal_dev(sc->sc_dev, 504 "Seeq 80c24 AutoDUPLEX media interface present\n"); 505 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 506 fxp_80c24_mediastatus); 507 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 509 } 510 511 /* 512 * Initialize the interface media. 513 */ 514 void 515 fxp_get_info(struct fxp_softc *sc, uint8_t *enaddr) 516 { 517 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 518 519 /* 520 * Reset to a stable state. 521 */ 522 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 523 DELAY(100); 524 525 sc->sc_eeprom_size = 0; 526 fxp_autosize_eeprom(sc); 527 if (sc->sc_eeprom_size == 0) { 528 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 529 sc->sc_eeprom_size = 6; /* XXX panic here? */ 530 } 531 #ifdef DEBUG 532 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 533 1 << sc->sc_eeprom_size); 534 #endif 535 536 /* 537 * Get info about the primary PHY 538 */ 539 fxp_read_eeprom(sc, &data, 6, 1); 540 sc->phy_primary_device = 541 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 542 543 /* 544 * Read MAC address. 545 */ 546 fxp_read_eeprom(sc, myea, 0, 3); 547 enaddr[0] = myea[0] & 0xff; 548 enaddr[1] = myea[0] >> 8; 549 enaddr[2] = myea[1] & 0xff; 550 enaddr[3] = myea[1] >> 8; 551 enaddr[4] = myea[2] & 0xff; 552 enaddr[5] = myea[2] >> 8; 553 554 /* 555 * Systems based on the ICH2/ICH2-M chip from Intel, as well 556 * as some i82559 designs, have a defect where the chip can 557 * cause a PCI protocol violation if it receives a CU_RESUME 558 * command when it is entering the IDLE state. 559 * 560 * The work-around is to disable Dynamic Standby Mode, so that 561 * the chip never deasserts #CLKRUN, and always remains in the 562 * active state. 563 * 564 * Unfortunately, the only way to disable Dynamic Standby is 565 * to frob an EEPROM setting and reboot (the EEPROM setting 566 * is only consulted when the PCI bus comes out of reset). 567 * 568 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 569 */ 570 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 571 fxp_read_eeprom(sc, &data, 10, 1); 572 if (data & 0x02) { /* STB enable */ 573 aprint_error_dev(sc->sc_dev, "WARNING: " 574 "Disabling dynamic standby mode in EEPROM " 575 "to work around a\n"); 576 aprint_normal_dev(sc->sc_dev, 577 "WARNING: hardware bug. You must reset " 578 "the system before using this\n"); 579 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 580 data &= ~0x02; 581 fxp_write_eeprom(sc, &data, 10, 1); 582 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 583 data); 584 fxp_eeprom_update_cksum(sc); 585 } 586 } 587 588 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 589 /* Due to false positives we make it conditional on setting link1 */ 590 fxp_read_eeprom(sc, &data, 3, 1); 591 if ((data & 0x03) != 0x03) { 592 aprint_verbose_dev(sc->sc_dev, 593 "May need receiver lock-up workaround\n"); 594 } 595 } 596 597 static void 598 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 599 { 600 uint16_t reg; 601 int x; 602 603 for (x = 1 << (len - 1); x != 0; x >>= 1) { 604 DELAY(40); 605 if (data & x) 606 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 607 else 608 reg = FXP_EEPROM_EECS; 609 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 610 DELAY(40); 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 612 reg | FXP_EEPROM_EESK); 613 DELAY(40); 614 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 615 } 616 DELAY(40); 617 } 618 619 /* 620 * Figure out EEPROM size. 621 * 622 * 559's can have either 64-word or 256-word EEPROMs, the 558 623 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 624 * talks about the existence of 16 to 256 word EEPROMs. 625 * 626 * The only known sizes are 64 and 256, where the 256 version is used 627 * by CardBus cards to store CIS information. 628 * 629 * The address is shifted in msb-to-lsb, and after the last 630 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 631 * after which follows the actual data. We try to detect this zero, by 632 * probing the data-out bit in the EEPROM control register just after 633 * having shifted in a bit. If the bit is zero, we assume we've 634 * shifted enough address bits. The data-out should be tri-state, 635 * before this, which should translate to a logical one. 636 * 637 * Other ways to do this would be to try to read a register with known 638 * contents with a varying number of address bits, but no such 639 * register seem to be available. The high bits of register 10 are 01 640 * on the 558 and 559, but apparently not on the 557. 641 * 642 * The Linux driver computes a checksum on the EEPROM data, but the 643 * value of this checksum is not very well documented. 644 */ 645 646 void 647 fxp_autosize_eeprom(struct fxp_softc *sc) 648 { 649 int x; 650 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 652 DELAY(40); 653 654 /* Shift in read opcode. */ 655 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 656 657 /* 658 * Shift in address, wait for the dummy zero following a correct 659 * address shift. 660 */ 661 for (x = 1; x <= 8; x++) { 662 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 663 DELAY(40); 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 665 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 666 DELAY(40); 667 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 668 FXP_EEPROM_EEDO) == 0) 669 break; 670 DELAY(40); 671 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 672 DELAY(40); 673 } 674 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 675 DELAY(40); 676 if (x != 6 && x != 8) { 677 #ifdef DEBUG 678 printf("%s: strange EEPROM size (%d)\n", 679 device_xname(sc->sc_dev), 1 << x); 680 #endif 681 } else 682 sc->sc_eeprom_size = x; 683 } 684 685 /* 686 * Read from the serial EEPROM. Basically, you manually shift in 687 * the read opcode (one bit at a time) and then shift in the address, 688 * and then you shift out the data (all of this one bit at a time). 689 * The word size is 16 bits, so you have to provide the address for 690 * every 16 bits of data. 691 */ 692 void 693 fxp_read_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 694 { 695 uint16_t reg; 696 int i, x; 697 698 for (i = 0; i < words; i++) { 699 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 700 701 /* Shift in read opcode. */ 702 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 703 704 /* Shift in address. */ 705 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 706 707 reg = FXP_EEPROM_EECS; 708 data[i] = 0; 709 710 /* Shift out data. */ 711 for (x = 16; x > 0; x--) { 712 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 713 reg | FXP_EEPROM_EESK); 714 DELAY(40); 715 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 716 FXP_EEPROM_EEDO) 717 data[i] |= (1 << (x - 1)); 718 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 719 DELAY(40); 720 } 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 722 DELAY(40); 723 } 724 } 725 726 /* 727 * Write data to the serial EEPROM. 728 */ 729 void 730 fxp_write_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 731 { 732 int i, j; 733 734 for (i = 0; i < words; i++) { 735 /* Erase/write enable. */ 736 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 737 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 738 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 739 sc->sc_eeprom_size); 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 741 DELAY(4); 742 743 /* Shift in write opcode, address, data. */ 744 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 745 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 746 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 747 fxp_eeprom_shiftin(sc, data[i], 16); 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 749 DELAY(4); 750 751 /* Wait for the EEPROM to finish up. */ 752 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 753 DELAY(4); 754 for (j = 0; j < 1000; j++) { 755 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 756 FXP_EEPROM_EEDO) 757 break; 758 DELAY(50); 759 } 760 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 761 DELAY(4); 762 763 /* Erase/write disable. */ 764 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 765 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 766 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 767 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 768 DELAY(4); 769 } 770 } 771 772 /* 773 * Update the checksum of the EEPROM. 774 */ 775 void 776 fxp_eeprom_update_cksum(struct fxp_softc *sc) 777 { 778 int i; 779 uint16_t data, cksum; 780 781 cksum = 0; 782 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 783 fxp_read_eeprom(sc, &data, i, 1); 784 cksum += data; 785 } 786 i = (1 << sc->sc_eeprom_size) - 1; 787 cksum = 0xbaba - cksum; 788 fxp_read_eeprom(sc, &data, i, 1); 789 fxp_write_eeprom(sc, &cksum, i, 1); 790 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 791 device_xname(sc->sc_dev), i, data, cksum); 792 } 793 794 /* 795 * Start packet transmission on the interface. 796 */ 797 void 798 fxp_start(struct ifnet *ifp) 799 { 800 struct fxp_softc *sc = ifp->if_softc; 801 struct mbuf *m0, *m; 802 struct fxp_txdesc *txd; 803 struct fxp_txsoft *txs; 804 bus_dmamap_t dmamap; 805 int error, lasttx, nexttx, opending, seg, nsegs, len; 806 807 /* 808 * If we want a re-init, bail out now. 809 */ 810 if (sc->sc_flags & FXPF_WANTINIT) { 811 ifp->if_flags |= IFF_OACTIVE; 812 return; 813 } 814 815 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 816 return; 817 818 /* 819 * Remember the previous txpending and the current lasttx. 820 */ 821 opending = sc->sc_txpending; 822 lasttx = sc->sc_txlast; 823 824 /* 825 * Loop through the send queue, setting up transmit descriptors 826 * until we drain the queue, or use up all available transmit 827 * descriptors. 828 */ 829 for (;;) { 830 struct fxp_tbd *tbdp; 831 int csum_flags; 832 833 /* 834 * Grab a packet off the queue. 835 */ 836 IFQ_POLL(&ifp->if_snd, m0); 837 if (m0 == NULL) 838 break; 839 m = NULL; 840 841 if (sc->sc_txpending == FXP_NTXCB - 1) { 842 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 843 break; 844 } 845 846 /* 847 * Get the next available transmit descriptor. 848 */ 849 nexttx = FXP_NEXTTX(sc->sc_txlast); 850 txd = FXP_CDTX(sc, nexttx); 851 txs = FXP_DSTX(sc, nexttx); 852 dmamap = txs->txs_dmamap; 853 854 /* 855 * Load the DMA map. If this fails, the packet either 856 * didn't fit in the allotted number of frags, or we were 857 * short on resources. In this case, we'll copy and try 858 * again. 859 */ 860 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 861 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 862 MGETHDR(m, M_DONTWAIT, MT_DATA); 863 if (m == NULL) { 864 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 865 device_xname(sc->sc_dev)); 866 break; 867 } 868 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 869 if (m0->m_pkthdr.len > MHLEN) { 870 MCLGET(m, M_DONTWAIT); 871 if ((m->m_flags & M_EXT) == 0) { 872 log(LOG_ERR, "%s: unable to allocate " 873 "Tx cluster\n", 874 device_xname(sc->sc_dev)); 875 m_freem(m); 876 break; 877 } 878 } 879 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 880 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 881 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 882 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 883 if (error) { 884 log(LOG_ERR, "%s: unable to load Tx buffer, " 885 "error = %d\n", 886 device_xname(sc->sc_dev), error); 887 break; 888 } 889 } 890 891 IFQ_DEQUEUE(&ifp->if_snd, m0); 892 csum_flags = m0->m_pkthdr.csum_flags; 893 if (m != NULL) { 894 m_freem(m0); 895 m0 = m; 896 } 897 898 /* Initialize the fraglist. */ 899 tbdp = txd->txd_tbd; 900 len = m0->m_pkthdr.len; 901 nsegs = dmamap->dm_nsegs; 902 if (sc->sc_flags & FXPF_EXT_RFA) 903 tbdp++; 904 for (seg = 0; seg < nsegs; seg++) { 905 tbdp[seg].tb_addr = 906 htole32(dmamap->dm_segs[seg].ds_addr); 907 tbdp[seg].tb_size = 908 htole32(dmamap->dm_segs[seg].ds_len); 909 } 910 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 911 (csum_flags & M_CSUM_IPv4) != 0)) { 912 /* 913 * Pad short packets to avoid ip4csum-tx bug. 914 * 915 * XXX Should we still consider if such short 916 * (36 bytes or less) packets might already 917 * occupy FXP_IPCB_NTXSEG (15) fragments here? 918 */ 919 KASSERT(nsegs < FXP_IPCB_NTXSEG); 920 nsegs++; 921 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 922 tbdp[seg].tb_size = 923 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 924 } 925 926 /* Sync the DMA map. */ 927 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 928 BUS_DMASYNC_PREWRITE); 929 930 /* 931 * Store a pointer to the packet so we can free it later. 932 */ 933 txs->txs_mbuf = m0; 934 935 /* 936 * Initialize the transmit descriptor. 937 */ 938 /* BIG_ENDIAN: no need to swap to store 0 */ 939 txd->txd_txcb.cb_status = 0; 940 txd->txd_txcb.cb_command = 941 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 942 txd->txd_txcb.tx_threshold = tx_threshold; 943 txd->txd_txcb.tbd_number = nsegs; 944 945 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 946 if (sc->sc_flags & FXPF_EXT_RFA) { 947 struct fxp_ipcb *ipcb; 948 /* 949 * Deal with TCP/IP checksum offload. Note that 950 * in order for TCP checksum offload to work, 951 * the pseudo header checksum must have already 952 * been computed and stored in the checksum field 953 * in the TCP header. The stack should have 954 * already done this for us. 955 */ 956 ipcb = &txd->txd_u.txdu_ipcb; 957 memset(ipcb, 0, sizeof(*ipcb)); 958 /* 959 * always do hardware parsing. 960 */ 961 ipcb->ipcb_ip_activation_high = 962 FXP_IPCB_HARDWAREPARSING_ENABLE; 963 /* 964 * ip checksum offloading. 965 */ 966 if (csum_flags & M_CSUM_IPv4) { 967 ipcb->ipcb_ip_schedule |= 968 FXP_IPCB_IP_CHECKSUM_ENABLE; 969 } 970 /* 971 * TCP/UDP checksum offloading. 972 */ 973 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 974 ipcb->ipcb_ip_schedule |= 975 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 976 } 977 978 /* 979 * request VLAN tag insertion if needed. 980 */ 981 if (vlan_has_tag(m0)) { 982 ipcb->ipcb_vlan_id = htobe16(vlan_get_tag(m0)); 983 ipcb->ipcb_ip_activation_high |= 984 FXP_IPCB_INSERTVLAN_ENABLE; 985 } 986 } else { 987 KASSERT((csum_flags & 988 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 989 } 990 991 FXP_CDTXSYNC(sc, nexttx, 992 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 993 994 /* Advance the tx pointer. */ 995 sc->sc_txpending++; 996 sc->sc_txlast = nexttx; 997 998 /* 999 * Pass packet to bpf if there is a listener. 1000 */ 1001 bpf_mtap(ifp, m0); 1002 } 1003 1004 if (sc->sc_txpending == FXP_NTXCB - 1) { 1005 /* No more slots; notify upper layer. */ 1006 ifp->if_flags |= IFF_OACTIVE; 1007 } 1008 1009 if (sc->sc_txpending != opending) { 1010 /* 1011 * We enqueued packets. If the transmitter was idle, 1012 * reset the txdirty pointer. 1013 */ 1014 if (opending == 0) 1015 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1016 1017 /* 1018 * Cause the chip to interrupt and suspend command 1019 * processing once the last packet we've enqueued 1020 * has been transmitted. 1021 * 1022 * To avoid a race between updating status bits 1023 * by the fxp chip and clearing command bits 1024 * by this function on machines which don't have 1025 * atomic methods to clear/set bits in memory 1026 * smaller than 32bits (both cb_status and cb_command 1027 * members are uint16_t and in the same 32bit word), 1028 * we have to prepare a dummy TX descriptor which has 1029 * NOP command and just causes a TX completion interrupt. 1030 */ 1031 sc->sc_txpending++; 1032 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1033 txd = FXP_CDTX(sc, sc->sc_txlast); 1034 /* BIG_ENDIAN: no need to swap to store 0 */ 1035 txd->txd_txcb.cb_status = 0; 1036 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1037 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1038 FXP_CDTXSYNC(sc, sc->sc_txlast, 1039 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1040 1041 /* 1042 * The entire packet chain is set up. Clear the suspend bit 1043 * on the command prior to the first packet we set up. 1044 */ 1045 FXP_CDTXSYNC(sc, lasttx, 1046 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1047 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1048 htole16(~FXP_CB_COMMAND_S); 1049 FXP_CDTXSYNC(sc, lasttx, 1050 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1051 1052 /* 1053 * Issue a Resume command in case the chip was suspended. 1054 */ 1055 fxp_scb_wait(sc); 1056 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1057 1058 /* Set a watchdog timer in case the chip flakes out. */ 1059 ifp->if_timer = 5; 1060 } 1061 } 1062 1063 /* 1064 * Process interface interrupts. 1065 */ 1066 int 1067 fxp_intr(void *arg) 1068 { 1069 struct fxp_softc *sc = arg; 1070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1071 bus_dmamap_t rxmap; 1072 int claimed = 0, rnr; 1073 uint8_t statack; 1074 1075 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1076 return (0); 1077 /* 1078 * If the interface isn't running, don't try to 1079 * service the interrupt.. just ack it and bail. 1080 */ 1081 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1082 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1083 if (statack) { 1084 claimed = 1; 1085 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1086 } 1087 return (claimed); 1088 } 1089 1090 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1091 claimed = 1; 1092 1093 /* 1094 * First ACK all the interrupts in this pass. 1095 */ 1096 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1097 1098 /* 1099 * Process receiver interrupts. If a no-resource (RNR) 1100 * condition exists, get whatever packets we can and 1101 * re-start the receiver. 1102 */ 1103 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1104 1 : 0; 1105 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1106 FXP_SCB_STATACK_SWI)) { 1107 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1108 rnr |= fxp_rxintr(sc); 1109 } 1110 1111 /* 1112 * Free any finished transmit mbuf chains. 1113 */ 1114 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1115 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1116 fxp_txintr(sc); 1117 1118 /* 1119 * Try to get more packets going. 1120 */ 1121 if_schedule_deferred_start(ifp); 1122 1123 if (sc->sc_txpending == 0) { 1124 /* 1125 * Tell them that they can re-init now. 1126 */ 1127 if (sc->sc_flags & FXPF_WANTINIT) 1128 wakeup(sc); 1129 } 1130 } 1131 1132 if (rnr) { 1133 fxp_scb_wait(sc); 1134 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1135 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1136 fxp_scb_wait(sc); 1137 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1138 rxmap->dm_segs[0].ds_addr + 1139 RFA_ALIGNMENT_FUDGE); 1140 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1141 } 1142 } 1143 1144 if (claimed) 1145 rnd_add_uint32(&sc->rnd_source, statack); 1146 return (claimed); 1147 } 1148 1149 /* 1150 * Handle transmit completion interrupts. 1151 */ 1152 void 1153 fxp_txintr(struct fxp_softc *sc) 1154 { 1155 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1156 struct fxp_txdesc *txd; 1157 struct fxp_txsoft *txs; 1158 int i; 1159 uint16_t txstat; 1160 1161 ifp->if_flags &= ~IFF_OACTIVE; 1162 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1163 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1164 txd = FXP_CDTX(sc, i); 1165 txs = FXP_DSTX(sc, i); 1166 1167 FXP_CDTXSYNC(sc, i, 1168 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1169 1170 /* skip dummy NOP TX descriptor */ 1171 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1172 == FXP_CB_COMMAND_NOP) 1173 continue; 1174 1175 txstat = le16toh(txd->txd_txcb.cb_status); 1176 1177 if ((txstat & FXP_CB_STATUS_C) == 0) 1178 break; 1179 1180 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1181 0, txs->txs_dmamap->dm_mapsize, 1182 BUS_DMASYNC_POSTWRITE); 1183 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1184 m_freem(txs->txs_mbuf); 1185 txs->txs_mbuf = NULL; 1186 } 1187 1188 /* Update the dirty transmit buffer pointer. */ 1189 sc->sc_txdirty = i; 1190 1191 /* 1192 * Cancel the watchdog timer if there are no pending 1193 * transmissions. 1194 */ 1195 if (sc->sc_txpending == 0) 1196 ifp->if_timer = 0; 1197 } 1198 1199 /* 1200 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1201 */ 1202 1203 void 1204 fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1205 u_int len) 1206 { 1207 uint32_t csum_data; 1208 int csum_flags; 1209 1210 /* 1211 * check H/W Checksumming. 1212 */ 1213 1214 csum_flags = 0; 1215 csum_data = 0; 1216 1217 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1218 uint8_t csum_stat; 1219 1220 csum_stat = rfa->cksum_stat; 1221 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1222 goto out; 1223 1224 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1225 csum_flags = M_CSUM_IPv4; 1226 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1227 csum_flags |= M_CSUM_IPv4_BAD; 1228 } 1229 1230 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1231 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1232 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1233 csum_flags |= M_CSUM_TCP_UDP_BAD; 1234 } 1235 1236 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1237 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1238 struct ether_header *eh; 1239 struct ip *ip; 1240 struct udphdr *uh; 1241 u_int hlen, pktlen; 1242 1243 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1244 goto out; 1245 pktlen = len - ETHER_HDR_LEN; 1246 eh = mtod(m, struct ether_header *); 1247 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1248 goto out; 1249 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1250 if (ip->ip_v != IPVERSION) 1251 goto out; 1252 1253 hlen = ip->ip_hl << 2; 1254 if (hlen < sizeof(struct ip)) 1255 goto out; 1256 1257 /* 1258 * Bail if too short, has random trailing garbage, truncated, 1259 * fragment, or has ethernet pad. 1260 */ 1261 if (ntohs(ip->ip_len) < hlen || 1262 ntohs(ip->ip_len) != pktlen || 1263 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1264 goto out; 1265 1266 switch (ip->ip_p) { 1267 case IPPROTO_TCP: 1268 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1269 pktlen < (hlen + sizeof(struct tcphdr))) 1270 goto out; 1271 csum_flags = 1272 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1273 break; 1274 case IPPROTO_UDP: 1275 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1276 pktlen < (hlen + sizeof(struct udphdr))) 1277 goto out; 1278 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1279 if (uh->uh_sum == 0) 1280 goto out; /* no checksum */ 1281 csum_flags = 1282 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1283 break; 1284 default: 1285 goto out; 1286 } 1287 1288 /* Extract computed checksum. */ 1289 csum_data = be16dec(mtod(m, uint8_t *) + len); 1290 1291 /* 1292 * The computed checksum includes IP headers, 1293 * so we have to deduct them. 1294 */ 1295 #if 0 1296 /* 1297 * But in TCP/UDP layer we can assume the IP header is valid, 1298 * i.e. a sum of the whole IP header should be 0xffff, 1299 * so we don't have to bother to deduct it. 1300 */ 1301 if (hlen > 0) { 1302 uint32_t hsum; 1303 const uint16_t *iphdr; 1304 hsum = 0; 1305 iphdr = (uint16_t *)ip; 1306 1307 while (hlen > 1) { 1308 hsum += ntohs(*iphdr++); 1309 hlen -= sizeof(uint16_t); 1310 } 1311 while (hsum >> 16) 1312 hsum = (hsum >> 16) + (hsum & 0xffff); 1313 1314 csum_data += (uint16_t)~hsum; 1315 1316 while (csum_data >> 16) 1317 csum_data = 1318 (csum_data >> 16) + (csum_data & 0xffff); 1319 } 1320 #endif 1321 } 1322 out: 1323 m->m_pkthdr.csum_flags = csum_flags; 1324 m->m_pkthdr.csum_data = csum_data; 1325 } 1326 1327 /* 1328 * Handle receive interrupts. 1329 */ 1330 int 1331 fxp_rxintr(struct fxp_softc *sc) 1332 { 1333 struct ethercom *ec = &sc->sc_ethercom; 1334 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1335 struct mbuf *m, *m0; 1336 bus_dmamap_t rxmap; 1337 struct fxp_rfa *rfa; 1338 int rnr; 1339 uint16_t len, rxstat; 1340 1341 rnr = 0; 1342 1343 for (;;) { 1344 m = sc->sc_rxq.ifq_head; 1345 rfa = FXP_MTORFA(m); 1346 rxmap = M_GETCTX(m, bus_dmamap_t); 1347 1348 FXP_RFASYNC(sc, m, 1349 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1350 1351 rxstat = le16toh(rfa->rfa_status); 1352 1353 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1354 rnr = 1; 1355 1356 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1357 /* 1358 * We have processed all of the 1359 * receive buffers. 1360 */ 1361 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1362 return rnr; 1363 } 1364 1365 IF_DEQUEUE(&sc->sc_rxq, m); 1366 1367 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1368 1369 len = le16toh(rfa->actual_size) & 1370 (m->m_ext.ext_size - 1); 1371 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1372 /* Adjust for appended checksum bytes. */ 1373 len -= sizeof(uint16_t); 1374 } 1375 1376 if (len < sizeof(struct ether_header)) { 1377 /* 1378 * Runt packet; drop it now. 1379 */ 1380 FXP_INIT_RFABUF(sc, m); 1381 continue; 1382 } 1383 1384 /* 1385 * If support for 802.1Q VLAN sized frames is 1386 * enabled, we need to do some additional error 1387 * checking (as we are saving bad frames, in 1388 * order to receive the larger ones). 1389 */ 1390 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1391 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1392 FXP_RFA_STATUS_RNR| 1393 FXP_RFA_STATUS_ALIGN| 1394 FXP_RFA_STATUS_CRC)) != 0) { 1395 FXP_INIT_RFABUF(sc, m); 1396 continue; 1397 } 1398 1399 /* 1400 * check VLAN tag stripping. 1401 */ 1402 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1403 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) 1404 vlan_set_tag(m, be16toh(rfa->vlan_id)); 1405 1406 /* Do checksum checking. */ 1407 if ((ifp->if_csum_flags_rx & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 1408 fxp_rx_hwcksum(sc, m, rfa, len); 1409 1410 /* 1411 * If the packet is small enough to fit in a 1412 * single header mbuf, allocate one and copy 1413 * the data into it. This greatly reduces 1414 * memory consumption when we receive lots 1415 * of small packets. 1416 * 1417 * Otherwise, we add a new buffer to the receive 1418 * chain. If this fails, we drop the packet and 1419 * recycle the old buffer. 1420 */ 1421 if (fxp_copy_small != 0 && len <= MHLEN) { 1422 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1423 if (m0 == NULL) 1424 goto dropit; 1425 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1426 memcpy(mtod(m0, void *), 1427 mtod(m, void *), len); 1428 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1429 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1430 FXP_INIT_RFABUF(sc, m); 1431 m = m0; 1432 } else { 1433 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1434 dropit: 1435 ifp->if_ierrors++; 1436 FXP_INIT_RFABUF(sc, m); 1437 continue; 1438 } 1439 } 1440 1441 m_set_rcvif(m, ifp); 1442 m->m_pkthdr.len = m->m_len = len; 1443 1444 /* Pass it on. */ 1445 if_percpuq_enqueue(ifp->if_percpuq, m); 1446 } 1447 } 1448 1449 /* 1450 * Update packet in/out/collision statistics. The i82557 doesn't 1451 * allow you to access these counters without doing a fairly 1452 * expensive DMA to get _all_ of the statistics it maintains, so 1453 * we do this operation here only once per second. The statistics 1454 * counters in the kernel are updated from the previous dump-stats 1455 * DMA and then a new dump-stats DMA is started. The on-chip 1456 * counters are zeroed when the DMA completes. If we can't start 1457 * the DMA immediately, we don't wait - we just prepare to read 1458 * them again next time. 1459 */ 1460 void 1461 fxp_tick(void *arg) 1462 { 1463 struct fxp_softc *sc = arg; 1464 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1465 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1466 int s; 1467 1468 if (!device_is_active(sc->sc_dev)) 1469 return; 1470 1471 s = splnet(); 1472 1473 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1474 1475 ifp->if_opackets += le32toh(sp->tx_good); 1476 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1477 if (sp->rx_good) { 1478 ifp->if_ipackets += le32toh(sp->rx_good); 1479 sc->sc_rxidle = 0; 1480 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1481 sc->sc_rxidle++; 1482 } 1483 ifp->if_ierrors += 1484 le32toh(sp->rx_crc_errors) + 1485 le32toh(sp->rx_alignment_errors) + 1486 le32toh(sp->rx_rnr_errors) + 1487 le32toh(sp->rx_overrun_errors); 1488 /* 1489 * If any transmit underruns occurred, bump up the transmit 1490 * threshold by another 512 bytes (64 * 8). 1491 */ 1492 if (sp->tx_underruns) { 1493 ifp->if_oerrors += le32toh(sp->tx_underruns); 1494 if (tx_threshold < 192) 1495 tx_threshold += 64; 1496 } 1497 #ifdef FXP_EVENT_COUNTERS 1498 if (sc->sc_flags & FXPF_FC) { 1499 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1500 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1501 } 1502 #endif 1503 1504 /* 1505 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1506 * then assume the receiver has locked up and attempt to clear 1507 * the condition by reprogramming the multicast filter (actually, 1508 * resetting the interface). This is a work-around for a bug in 1509 * the 82557 where the receiver locks up if it gets certain types 1510 * of garbage in the synchronization bits prior to the packet header. 1511 * This bug is supposed to only occur in 10Mbps mode, but has been 1512 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1513 * speed transition). 1514 */ 1515 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1516 (void) fxp_init(ifp); 1517 splx(s); 1518 return; 1519 } 1520 /* 1521 * If there is no pending command, start another stats 1522 * dump. Otherwise punt for now. 1523 */ 1524 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1525 /* 1526 * Start another stats dump. 1527 */ 1528 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1529 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1530 } else { 1531 /* 1532 * A previous command is still waiting to be accepted. 1533 * Just zero our copy of the stats and wait for the 1534 * next timer event to update them. 1535 */ 1536 /* BIG_ENDIAN: no swap required to store 0 */ 1537 sp->tx_good = 0; 1538 sp->tx_underruns = 0; 1539 sp->tx_total_collisions = 0; 1540 1541 sp->rx_good = 0; 1542 sp->rx_crc_errors = 0; 1543 sp->rx_alignment_errors = 0; 1544 sp->rx_rnr_errors = 0; 1545 sp->rx_overrun_errors = 0; 1546 if (sc->sc_flags & FXPF_FC) { 1547 sp->tx_pauseframes = 0; 1548 sp->rx_pauseframes = 0; 1549 } 1550 } 1551 1552 if (sc->sc_flags & FXPF_MII) { 1553 /* Tick the MII clock. */ 1554 mii_tick(&sc->sc_mii); 1555 } 1556 1557 splx(s); 1558 1559 /* 1560 * Schedule another timeout one second from now. 1561 */ 1562 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1563 } 1564 1565 /* 1566 * Drain the receive queue. 1567 */ 1568 void 1569 fxp_rxdrain(struct fxp_softc *sc) 1570 { 1571 bus_dmamap_t rxmap; 1572 struct mbuf *m; 1573 1574 for (;;) { 1575 IF_DEQUEUE(&sc->sc_rxq, m); 1576 if (m == NULL) 1577 break; 1578 rxmap = M_GETCTX(m, bus_dmamap_t); 1579 bus_dmamap_unload(sc->sc_dmat, rxmap); 1580 FXP_RXMAP_PUT(sc, rxmap); 1581 m_freem(m); 1582 } 1583 } 1584 1585 /* 1586 * Stop the interface. Cancels the statistics updater and resets 1587 * the interface. 1588 */ 1589 void 1590 fxp_stop(struct ifnet *ifp, int disable) 1591 { 1592 struct fxp_softc *sc = ifp->if_softc; 1593 struct fxp_txsoft *txs; 1594 int i; 1595 1596 /* 1597 * Turn down interface (done early to avoid bad interactions 1598 * between panics, shutdown hooks, and the watchdog timer) 1599 */ 1600 ifp->if_timer = 0; 1601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1602 1603 /* 1604 * Cancel stats updater. 1605 */ 1606 callout_stop(&sc->sc_callout); 1607 if (sc->sc_flags & FXPF_MII) { 1608 /* Down the MII. */ 1609 mii_down(&sc->sc_mii); 1610 } 1611 1612 /* 1613 * Issue software reset. This unloads any microcode that 1614 * might already be loaded. 1615 */ 1616 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1617 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1618 DELAY(50); 1619 1620 /* 1621 * Release any xmit buffers. 1622 */ 1623 for (i = 0; i < FXP_NTXCB; i++) { 1624 txs = FXP_DSTX(sc, i); 1625 if (txs->txs_mbuf != NULL) { 1626 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1627 m_freem(txs->txs_mbuf); 1628 txs->txs_mbuf = NULL; 1629 } 1630 } 1631 sc->sc_txpending = 0; 1632 1633 if (disable) { 1634 fxp_rxdrain(sc); 1635 fxp_disable(sc); 1636 } 1637 1638 } 1639 1640 /* 1641 * Watchdog/transmission transmit timeout handler. Called when a 1642 * transmission is started on the interface, but no interrupt is 1643 * received before the timeout. This usually indicates that the 1644 * card has wedged for some reason. 1645 */ 1646 void 1647 fxp_watchdog(struct ifnet *ifp) 1648 { 1649 struct fxp_softc *sc = ifp->if_softc; 1650 1651 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1652 ifp->if_oerrors++; 1653 1654 (void) fxp_init(ifp); 1655 } 1656 1657 /* 1658 * Initialize the interface. Must be called at splnet(). 1659 */ 1660 int 1661 fxp_init(struct ifnet *ifp) 1662 { 1663 struct fxp_softc *sc = ifp->if_softc; 1664 struct fxp_cb_config *cbp; 1665 struct fxp_cb_ias *cb_ias; 1666 struct fxp_txdesc *txd; 1667 bus_dmamap_t rxmap; 1668 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1669 uint16_t status; 1670 1671 if ((error = fxp_enable(sc)) != 0) 1672 goto out; 1673 1674 /* 1675 * Cancel any pending I/O 1676 */ 1677 fxp_stop(ifp, 0); 1678 1679 /* 1680 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1681 * flag, and this prevents the MII from detaching resulting in 1682 * a panic. The flags field should perhaps be split in runtime 1683 * flags and more static information. For now, just clear the 1684 * only other flag set. 1685 */ 1686 1687 sc->sc_flags &= ~FXPF_WANTINIT; 1688 1689 /* 1690 * Initialize base of CBL and RFA memory. Loading with zero 1691 * sets it up for regular linear addressing. 1692 */ 1693 fxp_scb_wait(sc); 1694 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1695 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1696 1697 fxp_scb_wait(sc); 1698 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1699 1700 /* 1701 * Initialize the multicast filter. Do this now, since we might 1702 * have to setup the config block differently. 1703 */ 1704 fxp_mc_setup(sc); 1705 1706 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1707 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1708 1709 /* 1710 * In order to support receiving 802.1Q VLAN frames, we have to 1711 * enable "save bad frames", since they are 4 bytes larger than 1712 * the normal Ethernet maximum frame length. On i82558 and later, 1713 * we have a better mechanism for this. 1714 */ 1715 save_bf = 0; 1716 lrxen = 0; 1717 vlan_drop = 0; 1718 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1719 if (sc->sc_rev < FXP_REV_82558_A4) 1720 save_bf = 1; 1721 else 1722 lrxen = 1; 1723 if (sc->sc_rev >= FXP_REV_82550) 1724 vlan_drop = 1; 1725 } 1726 1727 /* 1728 * Initialize base of dump-stats buffer. 1729 */ 1730 fxp_scb_wait(sc); 1731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1732 sc->sc_cddma + FXP_CDSTATSOFF); 1733 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1734 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1735 1736 cbp = &sc->sc_control_data->fcd_configcb; 1737 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1738 1739 /* 1740 * Load microcode for this controller. 1741 */ 1742 fxp_load_ucode(sc); 1743 1744 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1745 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1746 else 1747 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1748 1749 /* 1750 * This copy is kind of disgusting, but there are a bunch of must be 1751 * zero and must be one bits in this structure and this is the easiest 1752 * way to initialize them all to proper values. 1753 */ 1754 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1755 1756 /* BIG_ENDIAN: no need to swap to store 0 */ 1757 cbp->cb_status = 0; 1758 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1759 FXP_CB_COMMAND_EL); 1760 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1761 cbp->link_addr = 0xffffffff; /* (no) next command */ 1762 /* bytes in config block */ 1763 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1764 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1765 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1766 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1767 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1768 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1769 cbp->type_enable = 0; /* actually reserved */ 1770 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1771 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1772 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1773 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1774 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1775 cbp->late_scb = 0; /* (don't) defer SCB update */ 1776 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1777 cbp->ci_int = 1; /* interrupt on CU idle */ 1778 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1779 cbp->ext_stats_dis = 1; /* disable extended counters */ 1780 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1781 cbp->save_bf = save_bf;/* save bad frames */ 1782 cbp->disc_short_rx = !prm; /* discard short packets */ 1783 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1784 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1785 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1786 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1787 /* interface mode */ 1788 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1789 cbp->csma_dis = 0; /* (don't) disable link */ 1790 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1791 /* (don't) enable RX checksum */ 1792 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1793 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1794 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1795 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1796 cbp->nsai = 1; /* (don't) disable source addr insert */ 1797 cbp->preamble_length = 2; /* (7 byte) preamble */ 1798 cbp->loopback = 0; /* (don't) loopback */ 1799 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1800 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1801 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1802 cbp->promiscuous = prm; /* promiscuous mode */ 1803 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1804 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1805 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1806 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1807 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1808 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1809 cbp->padding = 1; /* (do) pad short tx packets */ 1810 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1811 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1812 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1813 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1814 /* must set wake_en in PMCSR also */ 1815 cbp->force_fdx = 0; /* (don't) force full duplex */ 1816 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1817 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1818 cbp->mc_all = allm; /* accept all multicasts */ 1819 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1820 cbp->vlan_drop_en = vlan_drop; 1821 1822 if (!(sc->sc_flags & FXPF_FC)) { 1823 /* 1824 * The i82557 has no hardware flow control, the values 1825 * here are the defaults for the chip. 1826 */ 1827 cbp->fc_delay_lsb = 0; 1828 cbp->fc_delay_msb = 0x40; 1829 cbp->pri_fc_thresh = 3; 1830 cbp->tx_fc_dis = 0; 1831 cbp->rx_fc_restop = 0; 1832 cbp->rx_fc_restart = 0; 1833 cbp->fc_filter = 0; 1834 cbp->pri_fc_loc = 1; 1835 } else { 1836 cbp->fc_delay_lsb = 0x1f; 1837 cbp->fc_delay_msb = 0x01; 1838 cbp->pri_fc_thresh = 3; 1839 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1840 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1841 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1842 cbp->fc_filter = !prm; /* drop FC frames to host */ 1843 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1844 cbp->ext_stats_dis = 0; /* enable extended stats */ 1845 } 1846 1847 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1848 1849 /* 1850 * Start the config command/DMA. 1851 */ 1852 fxp_scb_wait(sc); 1853 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1854 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1855 /* ...and wait for it to complete. */ 1856 for (i = 1000; i > 0; i--) { 1857 FXP_CDCONFIGSYNC(sc, 1858 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1859 status = le16toh(cbp->cb_status); 1860 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1861 if ((status & FXP_CB_STATUS_C) != 0) 1862 break; 1863 DELAY(1); 1864 } 1865 if (i == 0) { 1866 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1867 device_xname(sc->sc_dev), __LINE__); 1868 return (ETIMEDOUT); 1869 } 1870 1871 /* 1872 * Initialize the station address. 1873 */ 1874 cb_ias = &sc->sc_control_data->fcd_iascb; 1875 /* BIG_ENDIAN: no need to swap to store 0 */ 1876 cb_ias->cb_status = 0; 1877 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1878 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1879 cb_ias->link_addr = 0xffffffff; 1880 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1881 1882 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1883 1884 /* 1885 * Start the IAS (Individual Address Setup) command/DMA. 1886 */ 1887 fxp_scb_wait(sc); 1888 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1889 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1890 /* ...and wait for it to complete. */ 1891 for (i = 1000; i > 0; i++) { 1892 FXP_CDIASSYNC(sc, 1893 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1894 status = le16toh(cb_ias->cb_status); 1895 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1896 if ((status & FXP_CB_STATUS_C) != 0) 1897 break; 1898 DELAY(1); 1899 } 1900 if (i == 0) { 1901 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1902 device_xname(sc->sc_dev), __LINE__); 1903 return (ETIMEDOUT); 1904 } 1905 1906 /* 1907 * Initialize the transmit descriptor ring. txlast is initialized 1908 * to the end of the list so that it will wrap around to the first 1909 * descriptor when the first packet is transmitted. 1910 */ 1911 for (i = 0; i < FXP_NTXCB; i++) { 1912 txd = FXP_CDTX(sc, i); 1913 memset(txd, 0, sizeof(*txd)); 1914 txd->txd_txcb.cb_command = 1915 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1916 txd->txd_txcb.link_addr = 1917 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1918 if (sc->sc_flags & FXPF_EXT_TXCB) 1919 txd->txd_txcb.tbd_array_addr = 1920 htole32(FXP_CDTBDADDR(sc, i) + 1921 (2 * sizeof(struct fxp_tbd))); 1922 else 1923 txd->txd_txcb.tbd_array_addr = 1924 htole32(FXP_CDTBDADDR(sc, i)); 1925 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1926 } 1927 sc->sc_txpending = 0; 1928 sc->sc_txdirty = 0; 1929 sc->sc_txlast = FXP_NTXCB - 1; 1930 1931 /* 1932 * Initialize the receive buffer list. 1933 */ 1934 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1935 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1936 rxmap = FXP_RXMAP_GET(sc); 1937 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1938 log(LOG_ERR, "%s: unable to allocate or map rx " 1939 "buffer %d, error = %d\n", 1940 device_xname(sc->sc_dev), 1941 sc->sc_rxq.ifq_len, error); 1942 /* 1943 * XXX Should attempt to run with fewer receive 1944 * XXX buffers instead of just failing. 1945 */ 1946 FXP_RXMAP_PUT(sc, rxmap); 1947 fxp_rxdrain(sc); 1948 goto out; 1949 } 1950 } 1951 sc->sc_rxidle = 0; 1952 1953 /* 1954 * Give the transmit ring to the chip. We do this by pointing 1955 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1956 * issuing a start command. It will execute the NOP and then 1957 * suspend, pointing at the first descriptor. 1958 */ 1959 fxp_scb_wait(sc); 1960 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1961 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1962 1963 /* 1964 * Initialize receiver buffer area - RFA. 1965 */ 1966 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1967 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1968 fxp_scb_wait(sc); 1969 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1970 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1971 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1972 #endif 1973 1974 if (sc->sc_flags & FXPF_MII) { 1975 /* 1976 * Set current media. 1977 */ 1978 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1979 goto out; 1980 } 1981 1982 /* 1983 * ...all done! 1984 */ 1985 ifp->if_flags |= IFF_RUNNING; 1986 ifp->if_flags &= ~IFF_OACTIVE; 1987 1988 /* 1989 * Request a software generated interrupt that will be used to 1990 * (re)start the RU processing. If we direct the chip to start 1991 * receiving from the start of queue now, instead of letting the 1992 * interrupt handler first process all received packets, we run 1993 * the risk of having it overwrite mbuf clusters while they are 1994 * being processed or after they have been returned to the pool. 1995 */ 1996 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 1997 1998 /* 1999 * Start the one second timer. 2000 */ 2001 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 2002 2003 /* 2004 * Attempt to start output on the interface. 2005 */ 2006 fxp_start(ifp); 2007 2008 out: 2009 if (error) { 2010 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2011 ifp->if_timer = 0; 2012 log(LOG_ERR, "%s: interface not running\n", 2013 device_xname(sc->sc_dev)); 2014 } 2015 return (error); 2016 } 2017 2018 /* 2019 * Notify the world which media we're using. 2020 */ 2021 void 2022 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2023 { 2024 struct fxp_softc *sc = ifp->if_softc; 2025 2026 if (sc->sc_enabled == 0) { 2027 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2028 ifmr->ifm_status = 0; 2029 return; 2030 } 2031 2032 ether_mediastatus(ifp, ifmr); 2033 } 2034 2035 int 2036 fxp_80c24_mediachange(struct ifnet *ifp) 2037 { 2038 2039 /* Nothing to do here. */ 2040 return (0); 2041 } 2042 2043 void 2044 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2045 { 2046 struct fxp_softc *sc = ifp->if_softc; 2047 2048 /* 2049 * Media is currently-selected media. We cannot determine 2050 * the link status. 2051 */ 2052 ifmr->ifm_status = 0; 2053 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2054 } 2055 2056 /* 2057 * Add a buffer to the end of the RFA buffer list. 2058 * Return 0 if successful, error code on failure. 2059 * 2060 * The RFA struct is stuck at the beginning of mbuf cluster and the 2061 * data pointer is fixed up to point just past it. 2062 */ 2063 int 2064 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2065 { 2066 struct mbuf *m; 2067 int error; 2068 2069 MGETHDR(m, M_DONTWAIT, MT_DATA); 2070 if (m == NULL) 2071 return (ENOBUFS); 2072 2073 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2074 MCLGET(m, M_DONTWAIT); 2075 if ((m->m_flags & M_EXT) == 0) { 2076 m_freem(m); 2077 return (ENOBUFS); 2078 } 2079 2080 if (unload) 2081 bus_dmamap_unload(sc->sc_dmat, rxmap); 2082 2083 M_SETCTX(m, rxmap); 2084 2085 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2086 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2087 BUS_DMA_READ|BUS_DMA_NOWAIT); 2088 if (error) { 2089 /* XXX XXX XXX */ 2090 aprint_error_dev(sc->sc_dev, 2091 "can't load rx DMA map %d, error = %d\n", 2092 sc->sc_rxq.ifq_len, error); 2093 panic("fxp_add_rfabuf"); 2094 } 2095 2096 FXP_INIT_RFABUF(sc, m); 2097 2098 return (0); 2099 } 2100 2101 int 2102 fxp_mdi_read(device_t self, int phy, int reg) 2103 { 2104 struct fxp_softc *sc = device_private(self); 2105 int count = 10000; 2106 int value; 2107 2108 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2109 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2110 2111 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2112 0x10000000) == 0 && count--) 2113 DELAY(10); 2114 2115 if (count <= 0) 2116 log(LOG_WARNING, 2117 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2118 2119 return (value & 0xffff); 2120 } 2121 2122 void 2123 fxp_statchg(struct ifnet *ifp) 2124 { 2125 2126 /* Nothing to do. */ 2127 } 2128 2129 void 2130 fxp_mdi_write(device_t self, int phy, int reg, int value) 2131 { 2132 struct fxp_softc *sc = device_private(self); 2133 int count = 10000; 2134 2135 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2136 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2137 (value & 0xffff)); 2138 2139 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2140 count--) 2141 DELAY(10); 2142 2143 if (count <= 0) 2144 log(LOG_WARNING, 2145 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2146 } 2147 2148 int 2149 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2150 { 2151 struct fxp_softc *sc = ifp->if_softc; 2152 struct ifreq *ifr = (struct ifreq *)data; 2153 int s, error; 2154 2155 s = splnet(); 2156 2157 switch (cmd) { 2158 case SIOCSIFMEDIA: 2159 case SIOCGIFMEDIA: 2160 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2161 break; 2162 2163 default: 2164 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2165 break; 2166 2167 error = 0; 2168 2169 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2170 ; 2171 else if (ifp->if_flags & IFF_RUNNING) { 2172 /* 2173 * Multicast list has changed; set the 2174 * hardware filter accordingly. 2175 */ 2176 while (sc->sc_txpending) { 2177 sc->sc_flags |= FXPF_WANTINIT; 2178 tsleep(sc, PSOCK, "fxp_init", 0); 2179 } 2180 error = fxp_init(ifp); 2181 } 2182 break; 2183 } 2184 2185 /* Try to get more packets going. */ 2186 if (sc->sc_enabled) 2187 fxp_start(ifp); 2188 2189 splx(s); 2190 return (error); 2191 } 2192 2193 /* 2194 * Program the multicast filter. 2195 * 2196 * This function must be called at splnet(). 2197 */ 2198 void 2199 fxp_mc_setup(struct fxp_softc *sc) 2200 { 2201 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2202 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2203 struct ethercom *ec = &sc->sc_ethercom; 2204 struct ether_multi *enm; 2205 struct ether_multistep step; 2206 int count, nmcasts; 2207 uint16_t status; 2208 2209 #ifdef DIAGNOSTIC 2210 if (sc->sc_txpending) 2211 panic("fxp_mc_setup: pending transmissions"); 2212 #endif 2213 2214 2215 if (ifp->if_flags & IFF_PROMISC) { 2216 ifp->if_flags |= IFF_ALLMULTI; 2217 return; 2218 } else { 2219 ifp->if_flags &= ~IFF_ALLMULTI; 2220 } 2221 2222 /* 2223 * Initialize multicast setup descriptor. 2224 */ 2225 nmcasts = 0; 2226 ETHER_FIRST_MULTI(step, ec, enm); 2227 while (enm != NULL) { 2228 /* 2229 * Check for too many multicast addresses or if we're 2230 * listening to a range. Either way, we simply have 2231 * to accept all multicasts. 2232 */ 2233 if (nmcasts >= MAXMCADDR || 2234 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2235 ETHER_ADDR_LEN) != 0) { 2236 /* 2237 * Callers of this function must do the 2238 * right thing with this. If we're called 2239 * from outside fxp_init(), the caller must 2240 * detect if the state if IFF_ALLMULTI changes. 2241 * If it does, the caller must then call 2242 * fxp_init(), since allmulti is handled by 2243 * the config block. 2244 */ 2245 ifp->if_flags |= IFF_ALLMULTI; 2246 return; 2247 } 2248 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2249 ETHER_ADDR_LEN); 2250 nmcasts++; 2251 ETHER_NEXT_MULTI(step, enm); 2252 } 2253 2254 /* BIG_ENDIAN: no need to swap to store 0 */ 2255 mcsp->cb_status = 0; 2256 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2257 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2258 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2259 2260 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2261 2262 /* 2263 * Wait until the command unit is not active. This should never 2264 * happen since nothing is queued, but make sure anyway. 2265 */ 2266 count = 100; 2267 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2268 FXP_SCB_CUS_ACTIVE && --count) 2269 DELAY(1); 2270 if (count == 0) { 2271 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2272 device_xname(sc->sc_dev), __LINE__); 2273 return; 2274 } 2275 2276 /* 2277 * Start the multicast setup command/DMA. 2278 */ 2279 fxp_scb_wait(sc); 2280 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2281 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2282 2283 /* ...and wait for it to complete. */ 2284 for (count = 1000; count > 0; count--) { 2285 FXP_CDMCSSYNC(sc, 2286 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2287 status = le16toh(mcsp->cb_status); 2288 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2289 if ((status & FXP_CB_STATUS_C) != 0) 2290 break; 2291 DELAY(1); 2292 } 2293 if (count == 0) { 2294 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2295 device_xname(sc->sc_dev), __LINE__); 2296 return; 2297 } 2298 } 2299 2300 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2301 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2302 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2303 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2304 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2305 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2306 static const uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2307 2308 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2309 2310 static const struct ucode { 2311 int32_t revision; 2312 const uint32_t *ucode; 2313 size_t length; 2314 uint16_t int_delay_offset; 2315 uint16_t bundle_max_offset; 2316 } ucode_table[] = { 2317 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2318 D101_CPUSAVER_DWORD, 0 }, 2319 2320 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2321 D101_CPUSAVER_DWORD, 0 }, 2322 2323 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2324 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2325 2326 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2327 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2328 2329 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2330 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2331 2332 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2333 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2334 2335 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2336 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2337 2338 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 2339 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2340 2341 { 0, NULL, 0, 0, 0 } 2342 }; 2343 2344 void 2345 fxp_load_ucode(struct fxp_softc *sc) 2346 { 2347 const struct ucode *uc; 2348 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2349 int count, i; 2350 uint16_t status; 2351 2352 if (sc->sc_flags & FXPF_UCODE_LOADED) 2353 return; 2354 2355 /* 2356 * Only load the uCode if the user has requested that 2357 * we do so. 2358 */ 2359 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2360 sc->sc_int_delay = 0; 2361 sc->sc_bundle_max = 0; 2362 return; 2363 } 2364 2365 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2366 if (sc->sc_rev == uc->revision) 2367 break; 2368 } 2369 if (uc->ucode == NULL) 2370 return; 2371 2372 /* BIG ENDIAN: no need to swap to store 0 */ 2373 cbp->cb_status = 0; 2374 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2375 cbp->link_addr = 0xffffffff; /* (no) next command */ 2376 for (i = 0; i < uc->length; i++) 2377 cbp->ucode[i] = htole32(uc->ucode[i]); 2378 2379 if (uc->int_delay_offset) 2380 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2381 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2382 2383 if (uc->bundle_max_offset) 2384 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2385 htole16(fxp_bundle_max); 2386 2387 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2388 2389 /* 2390 * Download the uCode to the chip. 2391 */ 2392 fxp_scb_wait(sc); 2393 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2394 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2395 2396 /* ...and wait for it to complete. */ 2397 for (count = 10000; count > 0; count--) { 2398 FXP_CDUCODESYNC(sc, 2399 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2400 status = le16toh(cbp->cb_status); 2401 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2402 if ((status & FXP_CB_STATUS_C) != 0) 2403 break; 2404 DELAY(2); 2405 } 2406 if (count == 0) { 2407 sc->sc_int_delay = 0; 2408 sc->sc_bundle_max = 0; 2409 log(LOG_WARNING, "%s: timeout loading microcode\n", 2410 device_xname(sc->sc_dev)); 2411 return; 2412 } 2413 2414 if (sc->sc_int_delay != fxp_int_delay || 2415 sc->sc_bundle_max != fxp_bundle_max) { 2416 sc->sc_int_delay = fxp_int_delay; 2417 sc->sc_bundle_max = fxp_bundle_max; 2418 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2419 "max bundle: %d\n", device_xname(sc->sc_dev), 2420 sc->sc_int_delay, 2421 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2422 } 2423 2424 sc->sc_flags |= FXPF_UCODE_LOADED; 2425 } 2426 2427 int 2428 fxp_enable(struct fxp_softc *sc) 2429 { 2430 2431 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2432 if ((*sc->sc_enable)(sc) != 0) { 2433 log(LOG_ERR, "%s: device enable failed\n", 2434 device_xname(sc->sc_dev)); 2435 return (EIO); 2436 } 2437 } 2438 2439 sc->sc_enabled = 1; 2440 return (0); 2441 } 2442 2443 void 2444 fxp_disable(struct fxp_softc *sc) 2445 { 2446 2447 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2448 (*sc->sc_disable)(sc); 2449 sc->sc_enabled = 0; 2450 } 2451 } 2452 2453 /* 2454 * fxp_activate: 2455 * 2456 * Handle device activation/deactivation requests. 2457 */ 2458 int 2459 fxp_activate(device_t self, enum devact act) 2460 { 2461 struct fxp_softc *sc = device_private(self); 2462 2463 switch (act) { 2464 case DVACT_DEACTIVATE: 2465 if_deactivate(&sc->sc_ethercom.ec_if); 2466 return 0; 2467 default: 2468 return EOPNOTSUPP; 2469 } 2470 } 2471 2472 /* 2473 * fxp_detach: 2474 * 2475 * Detach an i82557 interface. 2476 */ 2477 int 2478 fxp_detach(struct fxp_softc *sc, int flags) 2479 { 2480 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2481 int i, s; 2482 2483 /* Succeed now if there's no work to do. */ 2484 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2485 return (0); 2486 2487 s = splnet(); 2488 /* Stop the interface. Callouts are stopped in it. */ 2489 fxp_stop(ifp, 1); 2490 splx(s); 2491 2492 /* Destroy our callout. */ 2493 callout_destroy(&sc->sc_callout); 2494 2495 if (sc->sc_flags & FXPF_MII) { 2496 /* Detach all PHYs */ 2497 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2498 } 2499 2500 /* Delete all remaining media. */ 2501 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2502 2503 rnd_detach_source(&sc->rnd_source); 2504 ether_ifdetach(ifp); 2505 if_detach(ifp); 2506 2507 for (i = 0; i < FXP_NRFABUFS; i++) { 2508 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2509 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2510 } 2511 2512 for (i = 0; i < FXP_NTXCB; i++) { 2513 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2514 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2515 } 2516 2517 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2518 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2519 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2520 sizeof(struct fxp_control_data)); 2521 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2522 2523 return (0); 2524 } 2525
Indexes created Tue Sep 30 11:09:46 GMT 2025