i82557.c revision 1.149.2.3
1 /* $NetBSD: i82557.c,v 1.149.2.3 2020/04/13 08:04:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.149.2.3 2020/04/13 08:04:21 martin Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/callout.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/ioctl.h> 79 #include <sys/errno.h> 80 #include <sys/device.h> 81 #include <sys/syslog.h> 82 #include <sys/proc.h> 83 84 #include <machine/endian.h> 85 86 #include <sys/rndsource.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 #include <net/if_ether.h> 92 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/ip.h> 96 #include <netinet/tcp.h> 97 #include <netinet/udp.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 104 #include <dev/mii/miivar.h> 105 106 #include <dev/ic/i82557reg.h> 107 #include <dev/ic/i82557var.h> 108 109 #include <dev/microcode/i8255x/rcvbundl.h> 110 111 /* 112 * NOTE! On the Alpha, we have an alignment constraint. The 113 * card DMAs the packet immediately following the RFA. However, 114 * the first thing in the packet is a 14-byte Ethernet header. 115 * This means that the packet is misaligned. To compensate, 116 * we actually offset the RFA 2 bytes into the cluster. This 117 * alignes the packet after the Ethernet header at a 32-bit 118 * boundary. HOWEVER! This means that the RFA is misaligned! 119 */ 120 #define RFA_ALIGNMENT_FUDGE 2 121 122 /* 123 * The configuration byte map has several undefined fields which 124 * must be one or must be zero. Set up a template for these bits 125 * only (assuming an i82557 chip), leaving the actual configuration 126 * for fxp_init(). 127 * 128 * See the definition of struct fxp_cb_config for the bit definitions. 129 */ 130 const uint8_t fxp_cb_config_template[] = { 131 0x0, 0x0, /* cb_status */ 132 0x0, 0x0, /* cb_command */ 133 0x0, 0x0, 0x0, 0x0, /* link_addr */ 134 0x0, /* 0 */ 135 0x0, /* 1 */ 136 0x0, /* 2 */ 137 0x0, /* 3 */ 138 0x0, /* 4 */ 139 0x0, /* 5 */ 140 0x32, /* 6 */ 141 0x0, /* 7 */ 142 0x0, /* 8 */ 143 0x0, /* 9 */ 144 0x6, /* 10 */ 145 0x0, /* 11 */ 146 0x0, /* 12 */ 147 0x0, /* 13 */ 148 0xf2, /* 14 */ 149 0x48, /* 15 */ 150 0x0, /* 16 */ 151 0x40, /* 17 */ 152 0xf0, /* 18 */ 153 0x0, /* 19 */ 154 0x3f, /* 20 */ 155 0x5, /* 21 */ 156 0x0, /* 22 */ 157 0x0, /* 23 */ 158 0x0, /* 24 */ 159 0x0, /* 25 */ 160 0x0, /* 26 */ 161 0x0, /* 27 */ 162 0x0, /* 28 */ 163 0x0, /* 29 */ 164 0x0, /* 30 */ 165 0x0, /* 31 */ 166 }; 167 168 void fxp_mii_initmedia(struct fxp_softc *); 169 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 170 171 void fxp_80c24_initmedia(struct fxp_softc *); 172 int fxp_80c24_mediachange(struct ifnet *); 173 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 174 175 void fxp_start(struct ifnet *); 176 int fxp_ioctl(struct ifnet *, u_long, void *); 177 void fxp_watchdog(struct ifnet *); 178 int fxp_init(struct ifnet *); 179 void fxp_stop(struct ifnet *, int); 180 181 void fxp_txintr(struct fxp_softc *); 182 int fxp_rxintr(struct fxp_softc *); 183 184 void fxp_rx_hwcksum(struct fxp_softc *, struct mbuf *, 185 const struct fxp_rfa *, u_int); 186 187 void fxp_rxdrain(struct fxp_softc *); 188 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 189 int fxp_mdi_read(device_t, int, int, uint16_t *); 190 void fxp_statchg(struct ifnet *); 191 int fxp_mdi_write(device_t, int, int, uint16_t); 192 void fxp_autosize_eeprom(struct fxp_softc*); 193 void fxp_read_eeprom(struct fxp_softc *, uint16_t *, int, int); 194 void fxp_write_eeprom(struct fxp_softc *, uint16_t *, int, int); 195 void fxp_eeprom_update_cksum(struct fxp_softc *); 196 void fxp_get_info(struct fxp_softc *, uint8_t *); 197 void fxp_tick(void *); 198 void fxp_mc_setup(struct fxp_softc *); 199 void fxp_load_ucode(struct fxp_softc *); 200 201 int fxp_copy_small = 0; 202 203 /* 204 * Variables for interrupt mitigating microcode. 205 */ 206 int fxp_int_delay = 1000; /* usec */ 207 int fxp_bundle_max = 6; /* packets */ 208 209 struct fxp_phytype { 210 int fp_phy; /* type of PHY, -1 for MII at the end. */ 211 void (*fp_init)(struct fxp_softc *); 212 } fxp_phytype_table[] = { 213 { FXP_PHY_80C24, fxp_80c24_initmedia }, 214 { -1, fxp_mii_initmedia }, 215 }; 216 217 /* 218 * Set initial transmit threshold at 64 (512 bytes). This is 219 * increased by 64 (512 bytes) at a time, to maximum of 192 220 * (1536 bytes), if an underrun occurs. 221 */ 222 static int tx_threshold = 64; 223 224 /* 225 * Wait for the previous command to be accepted (but not necessarily 226 * completed). 227 */ 228 static inline void 229 fxp_scb_wait(struct fxp_softc *sc) 230 { 231 int i = 10000; 232 233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 234 delay(2); 235 if (i == 0) 236 log(LOG_WARNING, 237 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 238 } 239 240 /* 241 * Submit a command to the i82557. 242 */ 243 static inline void 244 fxp_scb_cmd(struct fxp_softc *sc, uint8_t cmd) 245 { 246 247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 248 } 249 250 /* 251 * Finish attaching an i82557 interface. Called by bus-specific front-end. 252 */ 253 void 254 fxp_attach(struct fxp_softc *sc) 255 { 256 uint8_t enaddr[ETHER_ADDR_LEN]; 257 struct ifnet *ifp; 258 bus_dma_segment_t seg; 259 int rseg, i, error; 260 struct fxp_phytype *fp; 261 262 callout_init(&sc->sc_callout, 0); 263 callout_setfunc(&sc->sc_callout, fxp_tick, sc); 264 265 /* 266 * Enable use of extended RFDs and IPCBs for 82550 and later chips. 267 * Note: to use IPCB we need extended TXCB support too, and 268 * these feature flags should be set in each bus attachment. 269 */ 270 if (sc->sc_flags & FXPF_EXT_RFA) { 271 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 272 sc->sc_rfa_size = RFA_EXT_SIZE; 273 } else { 274 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 275 sc->sc_rfa_size = RFA_SIZE; 276 } 277 278 /* 279 * Allocate the control data structures, and create and load the 280 * DMA map for it. 281 */ 282 if ((error = bus_dmamem_alloc(sc->sc_dmat, 283 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 284 0)) != 0) { 285 aprint_error_dev(sc->sc_dev, 286 "unable to allocate control data, error = %d\n", 287 error); 288 goto fail_0; 289 } 290 291 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 292 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 293 BUS_DMA_COHERENT)) != 0) { 294 aprint_error_dev(sc->sc_dev, 295 "unable to map control data, error = %d\n", error); 296 goto fail_1; 297 } 298 sc->sc_cdseg = seg; 299 sc->sc_cdnseg = rseg; 300 301 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 302 303 if ((error = bus_dmamap_create(sc->sc_dmat, 304 sizeof(struct fxp_control_data), 1, 305 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 306 aprint_error_dev(sc->sc_dev, 307 "unable to create control data DMA map, error = %d\n", 308 error); 309 goto fail_2; 310 } 311 312 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 313 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 314 0)) != 0) { 315 aprint_error_dev(sc->sc_dev, 316 "can't load control data DMA map, error = %d\n", 317 error); 318 goto fail_3; 319 } 320 321 /* 322 * Create the transmit buffer DMA maps. 323 */ 324 for (i = 0; i < FXP_NTXCB; i++) { 325 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 326 (sc->sc_flags & FXPF_EXT_RFA) ? 327 FXP_IPCB_NTXSEG : FXP_NTXSEG, 328 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 329 aprint_error_dev(sc->sc_dev, 330 "unable to create tx DMA map %d, error = %d\n", 331 i, error); 332 goto fail_4; 333 } 334 } 335 336 /* 337 * Create the receive buffer DMA maps. 338 */ 339 for (i = 0; i < FXP_NRFABUFS; i++) { 340 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 341 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 342 aprint_error_dev(sc->sc_dev, 343 "unable to create rx DMA map %d, error = %d\n", 344 i, error); 345 goto fail_5; 346 } 347 } 348 349 /* Initialize MAC address and media structures. */ 350 fxp_get_info(sc, enaddr); 351 352 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 353 ether_sprintf(enaddr)); 354 355 ifp = &sc->sc_ethercom.ec_if; 356 357 /* 358 * Get info about our media interface, and initialize it. Note 359 * the table terminates itself with a phy of -1, indicating 360 * that we're using MII. 361 */ 362 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 363 if (fp->fp_phy == sc->phy_primary_device) 364 break; 365 (*fp->fp_init)(sc); 366 367 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 368 ifp->if_softc = sc; 369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 370 ifp->if_ioctl = fxp_ioctl; 371 ifp->if_start = fxp_start; 372 ifp->if_watchdog = fxp_watchdog; 373 ifp->if_init = fxp_init; 374 ifp->if_stop = fxp_stop; 375 IFQ_SET_READY(&ifp->if_snd); 376 377 if (sc->sc_flags & FXPF_EXT_RFA) { 378 /* 379 * Enable hardware cksum support by EXT_RFA and IPCB. 380 * 381 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 382 * at least, on i82550 rev.12. 383 * specifically, it doesn't set ipv4 checksum properly 384 * when sending UDP (and probably TCP) packets with 385 * 20 byte ipv4 header + 1 or 2 byte data, 386 * though ICMP packets seem working. 387 * FreeBSD driver has related comments. 388 * We've added a workaround to handle the bug by padding 389 * such packets manually. 390 */ 391 ifp->if_capabilities = 392 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 393 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 394 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 395 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 396 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 397 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 398 ifp->if_capabilities = 399 IFCAP_CSUM_TCPv4_Rx | 400 IFCAP_CSUM_UDPv4_Rx; 401 } 402 403 /* 404 * We can support 802.1Q VLAN-sized frames. 405 */ 406 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 407 408 /* 409 * Attach the interface. 410 */ 411 if_attach(ifp); 412 if_deferred_start_init(ifp, NULL); 413 ether_ifattach(ifp, enaddr); 414 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 415 RND_TYPE_NET, RND_FLAG_DEFAULT); 416 417 #ifdef FXP_EVENT_COUNTERS 418 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 419 NULL, device_xname(sc->sc_dev), "txstall"); 420 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 421 NULL, device_xname(sc->sc_dev), "txintr"); 422 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 423 NULL, device_xname(sc->sc_dev), "rxintr"); 424 if (sc->sc_flags & FXPF_FC) { 425 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 426 NULL, device_xname(sc->sc_dev), "txpause"); 427 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 428 NULL, device_xname(sc->sc_dev), "rxpause"); 429 } 430 #endif /* FXP_EVENT_COUNTERS */ 431 432 /* The attach is successful. */ 433 sc->sc_flags |= FXPF_ATTACHED; 434 435 return; 436 437 /* 438 * Free any resources we've allocated during the failed attach 439 * attempt. Do this in reverse order and fall though. 440 */ 441 fail_5: 442 for (i = 0; i < FXP_NRFABUFS; i++) { 443 if (sc->sc_rxmaps[i] != NULL) 444 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 445 } 446 fail_4: 447 for (i = 0; i < FXP_NTXCB; i++) { 448 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 449 bus_dmamap_destroy(sc->sc_dmat, 450 FXP_DSTX(sc, i)->txs_dmamap); 451 } 452 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 453 fail_3: 454 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 455 fail_2: 456 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 457 sizeof(struct fxp_control_data)); 458 fail_1: 459 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 460 fail_0: 461 return; 462 } 463 464 void 465 fxp_mii_initmedia(struct fxp_softc *sc) 466 { 467 struct mii_data * const mii = &sc->sc_mii; 468 int flags; 469 470 sc->sc_flags |= FXPF_MII; 471 472 mii->mii_ifp = &sc->sc_ethercom.ec_if; 473 mii->mii_readreg = fxp_mdi_read; 474 mii->mii_writereg = fxp_mdi_write; 475 mii->mii_statchg = fxp_statchg; 476 477 sc->sc_ethercom.ec_mii = mii; 478 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 479 fxp_mii_mediastatus); 480 481 flags = MIIF_NOISOLATE; 482 if (sc->sc_flags & FXPF_FC) 483 flags |= MIIF_FORCEANEG | MIIF_DOPAUSE; 484 /* 485 * The i82557 wedges if all of its PHYs are isolated! 486 */ 487 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 488 MII_OFFSET_ANY, flags); 489 if (LIST_EMPTY(&mii->mii_phys)) { 490 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 491 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 492 } else 493 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 494 } 495 496 void 497 fxp_80c24_initmedia(struct fxp_softc *sc) 498 { 499 struct mii_data * const mii = &sc->sc_mii; 500 501 /* 502 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 503 * doesn't have a programming interface of any sort. The 504 * media is sensed automatically based on how the link partner 505 * is configured. This is, in essence, manual configuration. 506 */ 507 aprint_normal_dev(sc->sc_dev, 508 "Seeq 80c24 AutoDUPLEX media interface present\n"); 509 ifmedia_init(&mii->mii_media, 0, fxp_80c24_mediachange, 510 fxp_80c24_mediastatus); 511 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 512 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 513 } 514 515 /* 516 * Initialize the interface media. 517 */ 518 void 519 fxp_get_info(struct fxp_softc *sc, uint8_t *enaddr) 520 { 521 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 522 523 /* 524 * Reset to a stable state. 525 */ 526 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 527 DELAY(100); 528 529 sc->sc_eeprom_size = 0; 530 fxp_autosize_eeprom(sc); 531 if (sc->sc_eeprom_size == 0) { 532 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 533 sc->sc_eeprom_size = 6; /* XXX panic here? */ 534 } 535 #ifdef DEBUG 536 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 537 1 << sc->sc_eeprom_size); 538 #endif 539 540 /* 541 * Get info about the primary PHY 542 */ 543 fxp_read_eeprom(sc, &data, 6, 1); 544 sc->phy_primary_device = 545 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 546 547 /* 548 * Read MAC address. 549 */ 550 fxp_read_eeprom(sc, myea, 0, 3); 551 enaddr[0] = myea[0] & 0xff; 552 enaddr[1] = myea[0] >> 8; 553 enaddr[2] = myea[1] & 0xff; 554 enaddr[3] = myea[1] >> 8; 555 enaddr[4] = myea[2] & 0xff; 556 enaddr[5] = myea[2] >> 8; 557 558 /* 559 * Systems based on the ICH2/ICH2-M chip from Intel, as well 560 * as some i82559 designs, have a defect where the chip can 561 * cause a PCI protocol violation if it receives a CU_RESUME 562 * command when it is entering the IDLE state. 563 * 564 * The work-around is to disable Dynamic Standby Mode, so that 565 * the chip never deasserts #CLKRUN, and always remains in the 566 * active state. 567 * 568 * Unfortunately, the only way to disable Dynamic Standby is 569 * to frob an EEPROM setting and reboot (the EEPROM setting 570 * is only consulted when the PCI bus comes out of reset). 571 * 572 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 573 */ 574 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 575 fxp_read_eeprom(sc, &data, 10, 1); 576 if (data & 0x02) { /* STB enable */ 577 aprint_error_dev(sc->sc_dev, "WARNING: " 578 "Disabling dynamic standby mode in EEPROM " 579 "to work around a\n"); 580 aprint_normal_dev(sc->sc_dev, 581 "WARNING: hardware bug. You must reset " 582 "the system before using this\n"); 583 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 584 data &= ~0x02; 585 fxp_write_eeprom(sc, &data, 10, 1); 586 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 587 data); 588 fxp_eeprom_update_cksum(sc); 589 } 590 } 591 592 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 593 /* Due to false positives we make it conditional on setting link1 */ 594 fxp_read_eeprom(sc, &data, 3, 1); 595 if ((data & 0x03) != 0x03) { 596 aprint_verbose_dev(sc->sc_dev, 597 "May need receiver lock-up workaround\n"); 598 } 599 } 600 601 static void 602 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 603 { 604 uint16_t reg; 605 int x; 606 607 for (x = 1 << (len - 1); x != 0; x >>= 1) { 608 DELAY(40); 609 if (data & x) 610 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 611 else 612 reg = FXP_EEPROM_EECS; 613 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 614 DELAY(40); 615 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 616 reg | FXP_EEPROM_EESK); 617 DELAY(40); 618 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 619 } 620 DELAY(40); 621 } 622 623 /* 624 * Figure out EEPROM size. 625 * 626 * 559's can have either 64-word or 256-word EEPROMs, the 558 627 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 628 * talks about the existence of 16 to 256 word EEPROMs. 629 * 630 * The only known sizes are 64 and 256, where the 256 version is used 631 * by CardBus cards to store CIS information. 632 * 633 * The address is shifted in msb-to-lsb, and after the last 634 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 635 * after which follows the actual data. We try to detect this zero, by 636 * probing the data-out bit in the EEPROM control register just after 637 * having shifted in a bit. If the bit is zero, we assume we've 638 * shifted enough address bits. The data-out should be tri-state, 639 * before this, which should translate to a logical one. 640 * 641 * Other ways to do this would be to try to read a register with known 642 * contents with a varying number of address bits, but no such 643 * register seem to be available. The high bits of register 10 are 01 644 * on the 558 and 559, but apparently not on the 557. 645 * 646 * The Linux driver computes a checksum on the EEPROM data, but the 647 * value of this checksum is not very well documented. 648 */ 649 650 void 651 fxp_autosize_eeprom(struct fxp_softc *sc) 652 { 653 int x; 654 655 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 656 DELAY(40); 657 658 /* Shift in read opcode. */ 659 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 660 661 /* 662 * Shift in address, wait for the dummy zero following a correct 663 * address shift. 664 */ 665 for (x = 1; x <= 8; x++) { 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 667 DELAY(40); 668 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 669 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 670 DELAY(40); 671 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 672 FXP_EEPROM_EEDO) == 0) 673 break; 674 DELAY(40); 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 676 DELAY(40); 677 } 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 679 DELAY(40); 680 if (x != 6 && x != 8) { 681 #ifdef DEBUG 682 printf("%s: strange EEPROM size (%d)\n", 683 device_xname(sc->sc_dev), 1 << x); 684 #endif 685 } else 686 sc->sc_eeprom_size = x; 687 } 688 689 /* 690 * Read from the serial EEPROM. Basically, you manually shift in 691 * the read opcode (one bit at a time) and then shift in the address, 692 * and then you shift out the data (all of this one bit at a time). 693 * The word size is 16 bits, so you have to provide the address for 694 * every 16 bits of data. 695 */ 696 void 697 fxp_read_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 698 { 699 uint16_t reg; 700 int i, x; 701 702 for (i = 0; i < words; i++) { 703 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 704 705 /* Shift in read opcode. */ 706 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 707 708 /* Shift in address. */ 709 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 710 711 reg = FXP_EEPROM_EECS; 712 data[i] = 0; 713 714 /* Shift out data. */ 715 for (x = 16; x > 0; x--) { 716 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 717 reg | FXP_EEPROM_EESK); 718 DELAY(40); 719 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 720 FXP_EEPROM_EEDO) 721 data[i] |= (1 << (x - 1)); 722 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 723 DELAY(40); 724 } 725 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 726 DELAY(40); 727 } 728 } 729 730 /* 731 * Write data to the serial EEPROM. 732 */ 733 void 734 fxp_write_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 735 { 736 int i, j; 737 738 for (i = 0; i < words; i++) { 739 /* Erase/write enable. */ 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 741 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 742 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 743 sc->sc_eeprom_size); 744 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 745 DELAY(4); 746 747 /* Shift in write opcode, address, data. */ 748 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 749 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 750 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 751 fxp_eeprom_shiftin(sc, data[i], 16); 752 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 753 DELAY(4); 754 755 /* Wait for the EEPROM to finish up. */ 756 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 757 DELAY(4); 758 for (j = 0; j < 1000; j++) { 759 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 760 FXP_EEPROM_EEDO) 761 break; 762 DELAY(50); 763 } 764 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 765 DELAY(4); 766 767 /* Erase/write disable. */ 768 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 769 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 770 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 771 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 772 DELAY(4); 773 } 774 } 775 776 /* 777 * Update the checksum of the EEPROM. 778 */ 779 void 780 fxp_eeprom_update_cksum(struct fxp_softc *sc) 781 { 782 int i; 783 uint16_t data, cksum; 784 785 cksum = 0; 786 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 787 fxp_read_eeprom(sc, &data, i, 1); 788 cksum += data; 789 } 790 i = (1 << sc->sc_eeprom_size) - 1; 791 cksum = 0xbaba - cksum; 792 fxp_read_eeprom(sc, &data, i, 1); 793 fxp_write_eeprom(sc, &cksum, i, 1); 794 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 795 device_xname(sc->sc_dev), i, data, cksum); 796 } 797 798 /* 799 * Start packet transmission on the interface. 800 */ 801 void 802 fxp_start(struct ifnet *ifp) 803 { 804 struct fxp_softc *sc = ifp->if_softc; 805 struct mbuf *m0, *m; 806 struct fxp_txdesc *txd; 807 struct fxp_txsoft *txs; 808 bus_dmamap_t dmamap; 809 int error, lasttx, nexttx, opending, seg, nsegs, len; 810 811 /* 812 * If we want a re-init, bail out now. 813 */ 814 if (sc->sc_flags & FXPF_WANTINIT) { 815 ifp->if_flags |= IFF_OACTIVE; 816 return; 817 } 818 819 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 820 return; 821 822 /* 823 * Remember the previous txpending and the current lasttx. 824 */ 825 opending = sc->sc_txpending; 826 lasttx = sc->sc_txlast; 827 828 /* 829 * Loop through the send queue, setting up transmit descriptors 830 * until we drain the queue, or use up all available transmit 831 * descriptors. 832 */ 833 for (;;) { 834 struct fxp_tbd *tbdp; 835 int csum_flags; 836 837 /* 838 * Grab a packet off the queue. 839 */ 840 IFQ_POLL(&ifp->if_snd, m0); 841 if (m0 == NULL) 842 break; 843 m = NULL; 844 845 if (sc->sc_txpending == FXP_NTXCB - 1) { 846 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 847 break; 848 } 849 850 /* 851 * Get the next available transmit descriptor. 852 */ 853 nexttx = FXP_NEXTTX(sc->sc_txlast); 854 txd = FXP_CDTX(sc, nexttx); 855 txs = FXP_DSTX(sc, nexttx); 856 dmamap = txs->txs_dmamap; 857 858 /* 859 * Load the DMA map. If this fails, the packet either 860 * didn't fit in the allotted number of frags, or we were 861 * short on resources. In this case, we'll copy and try 862 * again. 863 */ 864 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 865 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 866 MGETHDR(m, M_DONTWAIT, MT_DATA); 867 if (m == NULL) { 868 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 869 device_xname(sc->sc_dev)); 870 break; 871 } 872 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 873 if (m0->m_pkthdr.len > MHLEN) { 874 MCLGET(m, M_DONTWAIT); 875 if ((m->m_flags & M_EXT) == 0) { 876 log(LOG_ERR, "%s: unable to allocate " 877 "Tx cluster\n", 878 device_xname(sc->sc_dev)); 879 m_freem(m); 880 break; 881 } 882 } 883 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 884 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 885 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 886 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 887 if (error) { 888 log(LOG_ERR, "%s: unable to load Tx buffer, " 889 "error = %d\n", 890 device_xname(sc->sc_dev), error); 891 break; 892 } 893 } 894 895 IFQ_DEQUEUE(&ifp->if_snd, m0); 896 csum_flags = m0->m_pkthdr.csum_flags; 897 if (m != NULL) { 898 m_freem(m0); 899 m0 = m; 900 } 901 902 /* Initialize the fraglist. */ 903 tbdp = txd->txd_tbd; 904 len = m0->m_pkthdr.len; 905 nsegs = dmamap->dm_nsegs; 906 if (sc->sc_flags & FXPF_EXT_RFA) 907 tbdp++; 908 for (seg = 0; seg < nsegs; seg++) { 909 tbdp[seg].tb_addr = 910 htole32(dmamap->dm_segs[seg].ds_addr); 911 tbdp[seg].tb_size = 912 htole32(dmamap->dm_segs[seg].ds_len); 913 } 914 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 915 (csum_flags & M_CSUM_IPv4) != 0)) { 916 /* 917 * Pad short packets to avoid ip4csum-tx bug. 918 * 919 * XXX Should we still consider if such short 920 * (36 bytes or less) packets might already 921 * occupy FXP_IPCB_NTXSEG (15) fragments here? 922 */ 923 KASSERT(nsegs < FXP_IPCB_NTXSEG); 924 nsegs++; 925 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 926 tbdp[seg].tb_size = 927 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 928 } 929 930 /* Sync the DMA map. */ 931 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 932 BUS_DMASYNC_PREWRITE); 933 934 /* 935 * Store a pointer to the packet so we can free it later. 936 */ 937 txs->txs_mbuf = m0; 938 939 /* 940 * Initialize the transmit descriptor. 941 */ 942 /* BIG_ENDIAN: no need to swap to store 0 */ 943 txd->txd_txcb.cb_status = 0; 944 txd->txd_txcb.cb_command = 945 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 946 txd->txd_txcb.tx_threshold = tx_threshold; 947 txd->txd_txcb.tbd_number = nsegs; 948 949 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 950 if (sc->sc_flags & FXPF_EXT_RFA) { 951 struct fxp_ipcb *ipcb; 952 /* 953 * Deal with TCP/IP checksum offload. Note that 954 * in order for TCP checksum offload to work, 955 * the pseudo header checksum must have already 956 * been computed and stored in the checksum field 957 * in the TCP header. The stack should have 958 * already done this for us. 959 */ 960 ipcb = &txd->txd_u.txdu_ipcb; 961 memset(ipcb, 0, sizeof(*ipcb)); 962 /* 963 * always do hardware parsing. 964 */ 965 ipcb->ipcb_ip_activation_high = 966 FXP_IPCB_HARDWAREPARSING_ENABLE; 967 /* 968 * ip checksum offloading. 969 */ 970 if (csum_flags & M_CSUM_IPv4) { 971 ipcb->ipcb_ip_schedule |= 972 FXP_IPCB_IP_CHECKSUM_ENABLE; 973 } 974 /* 975 * TCP/UDP checksum offloading. 976 */ 977 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 978 ipcb->ipcb_ip_schedule |= 979 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 980 } 981 982 /* 983 * request VLAN tag insertion if needed. 984 */ 985 if (vlan_has_tag(m0)) { 986 ipcb->ipcb_vlan_id = htobe16(vlan_get_tag(m0)); 987 ipcb->ipcb_ip_activation_high |= 988 FXP_IPCB_INSERTVLAN_ENABLE; 989 } 990 } else { 991 KASSERT((csum_flags & 992 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 993 } 994 995 FXP_CDTXSYNC(sc, nexttx, 996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 997 998 /* Advance the tx pointer. */ 999 sc->sc_txpending++; 1000 sc->sc_txlast = nexttx; 1001 1002 /* 1003 * Pass packet to bpf if there is a listener. 1004 */ 1005 bpf_mtap(ifp, m0, BPF_D_OUT); 1006 } 1007 1008 if (sc->sc_txpending == FXP_NTXCB - 1) { 1009 /* No more slots; notify upper layer. */ 1010 ifp->if_flags |= IFF_OACTIVE; 1011 } 1012 1013 if (sc->sc_txpending != opending) { 1014 /* 1015 * We enqueued packets. If the transmitter was idle, 1016 * reset the txdirty pointer. 1017 */ 1018 if (opending == 0) 1019 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1020 1021 /* 1022 * Cause the chip to interrupt and suspend command 1023 * processing once the last packet we've enqueued 1024 * has been transmitted. 1025 * 1026 * To avoid a race between updating status bits 1027 * by the fxp chip and clearing command bits 1028 * by this function on machines which don't have 1029 * atomic methods to clear/set bits in memory 1030 * smaller than 32bits (both cb_status and cb_command 1031 * members are uint16_t and in the same 32bit word), 1032 * we have to prepare a dummy TX descriptor which has 1033 * NOP command and just causes a TX completion interrupt. 1034 */ 1035 sc->sc_txpending++; 1036 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1037 txd = FXP_CDTX(sc, sc->sc_txlast); 1038 /* BIG_ENDIAN: no need to swap to store 0 */ 1039 txd->txd_txcb.cb_status = 0; 1040 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1041 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1042 FXP_CDTXSYNC(sc, sc->sc_txlast, 1043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1044 1045 /* 1046 * The entire packet chain is set up. Clear the suspend bit 1047 * on the command prior to the first packet we set up. 1048 */ 1049 FXP_CDTXSYNC(sc, lasttx, 1050 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1051 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1052 htole16(~FXP_CB_COMMAND_S); 1053 FXP_CDTXSYNC(sc, lasttx, 1054 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1055 1056 /* 1057 * Issue a Resume command in case the chip was suspended. 1058 */ 1059 fxp_scb_wait(sc); 1060 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1061 1062 /* Set a watchdog timer in case the chip flakes out. */ 1063 ifp->if_timer = 5; 1064 } 1065 } 1066 1067 /* 1068 * Process interface interrupts. 1069 */ 1070 int 1071 fxp_intr(void *arg) 1072 { 1073 struct fxp_softc *sc = arg; 1074 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1075 bus_dmamap_t rxmap; 1076 int claimed = 0, rnr; 1077 uint8_t statack; 1078 1079 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1080 return (0); 1081 /* 1082 * If the interface isn't running, don't try to 1083 * service the interrupt.. just ack it and bail. 1084 */ 1085 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1086 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1087 if (statack) { 1088 claimed = 1; 1089 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1090 } 1091 return (claimed); 1092 } 1093 1094 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1095 claimed = 1; 1096 1097 /* 1098 * First ACK all the interrupts in this pass. 1099 */ 1100 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1101 1102 /* 1103 * Process receiver interrupts. If a no-resource (RNR) 1104 * condition exists, get whatever packets we can and 1105 * re-start the receiver. 1106 */ 1107 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1108 1 : 0; 1109 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1110 FXP_SCB_STATACK_SWI)) { 1111 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1112 rnr |= fxp_rxintr(sc); 1113 } 1114 1115 /* 1116 * Free any finished transmit mbuf chains. 1117 */ 1118 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1119 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1120 fxp_txintr(sc); 1121 1122 /* 1123 * Try to get more packets going. 1124 */ 1125 if_schedule_deferred_start(ifp); 1126 1127 if (sc->sc_txpending == 0) { 1128 /* 1129 * Tell them that they can re-init now. 1130 */ 1131 if (sc->sc_flags & FXPF_WANTINIT) 1132 wakeup(sc); 1133 } 1134 } 1135 1136 if (rnr) { 1137 fxp_scb_wait(sc); 1138 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1139 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1140 fxp_scb_wait(sc); 1141 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1142 rxmap->dm_segs[0].ds_addr + 1143 RFA_ALIGNMENT_FUDGE); 1144 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1145 } 1146 } 1147 1148 if (claimed) 1149 rnd_add_uint32(&sc->rnd_source, statack); 1150 return (claimed); 1151 } 1152 1153 /* 1154 * Handle transmit completion interrupts. 1155 */ 1156 void 1157 fxp_txintr(struct fxp_softc *sc) 1158 { 1159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1160 struct fxp_txdesc *txd; 1161 struct fxp_txsoft *txs; 1162 int i; 1163 uint16_t txstat; 1164 1165 ifp->if_flags &= ~IFF_OACTIVE; 1166 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1167 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1168 txd = FXP_CDTX(sc, i); 1169 txs = FXP_DSTX(sc, i); 1170 1171 FXP_CDTXSYNC(sc, i, 1172 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1173 1174 /* skip dummy NOP TX descriptor */ 1175 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1176 == FXP_CB_COMMAND_NOP) 1177 continue; 1178 1179 txstat = le16toh(txd->txd_txcb.cb_status); 1180 1181 if ((txstat & FXP_CB_STATUS_C) == 0) 1182 break; 1183 1184 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1185 0, txs->txs_dmamap->dm_mapsize, 1186 BUS_DMASYNC_POSTWRITE); 1187 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1188 m_freem(txs->txs_mbuf); 1189 txs->txs_mbuf = NULL; 1190 } 1191 1192 /* Update the dirty transmit buffer pointer. */ 1193 sc->sc_txdirty = i; 1194 1195 /* 1196 * Cancel the watchdog timer if there are no pending 1197 * transmissions. 1198 */ 1199 if (sc->sc_txpending == 0) 1200 ifp->if_timer = 0; 1201 } 1202 1203 /* 1204 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1205 */ 1206 1207 void 1208 fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1209 u_int len) 1210 { 1211 uint32_t csum_data; 1212 int csum_flags; 1213 1214 /* 1215 * check H/W Checksumming. 1216 */ 1217 1218 csum_flags = 0; 1219 csum_data = 0; 1220 1221 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1222 uint8_t csum_stat; 1223 1224 csum_stat = rfa->cksum_stat; 1225 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1226 goto out; 1227 1228 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1229 csum_flags = M_CSUM_IPv4; 1230 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1231 csum_flags |= M_CSUM_IPv4_BAD; 1232 } 1233 1234 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1235 csum_flags |= (M_CSUM_TCPv4 | M_CSUM_UDPv4); /* XXX */ 1236 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1237 csum_flags |= M_CSUM_TCP_UDP_BAD; 1238 } 1239 1240 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1242 struct ether_header *eh; 1243 struct ip *ip; 1244 struct udphdr *uh; 1245 u_int hlen, pktlen; 1246 1247 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1248 goto out; 1249 pktlen = len - ETHER_HDR_LEN; 1250 eh = mtod(m, struct ether_header *); 1251 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1252 goto out; 1253 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1254 if (ip->ip_v != IPVERSION) 1255 goto out; 1256 1257 hlen = ip->ip_hl << 2; 1258 if (hlen < sizeof(struct ip)) 1259 goto out; 1260 1261 /* 1262 * Bail if too short, has random trailing garbage, truncated, 1263 * fragment, or has ethernet pad. 1264 */ 1265 if (ntohs(ip->ip_len) < hlen || 1266 ntohs(ip->ip_len) != pktlen || 1267 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1268 goto out; 1269 1270 switch (ip->ip_p) { 1271 case IPPROTO_TCP: 1272 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1273 pktlen < (hlen + sizeof(struct tcphdr))) 1274 goto out; 1275 csum_flags = 1276 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1277 break; 1278 case IPPROTO_UDP: 1279 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1280 pktlen < (hlen + sizeof(struct udphdr))) 1281 goto out; 1282 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1283 if (uh->uh_sum == 0) 1284 goto out; /* no checksum */ 1285 csum_flags = 1286 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1287 break; 1288 default: 1289 goto out; 1290 } 1291 1292 /* Extract computed checksum. */ 1293 csum_data = be16dec(mtod(m, uint8_t *) + len); 1294 1295 /* 1296 * The computed checksum includes IP headers, 1297 * so we have to deduct them. 1298 */ 1299 #if 0 1300 /* 1301 * But in TCP/UDP layer we can assume the IP header is valid, 1302 * i.e. a sum of the whole IP header should be 0xffff, 1303 * so we don't have to bother to deduct it. 1304 */ 1305 if (hlen > 0) { 1306 uint32_t hsum; 1307 const uint16_t *iphdr; 1308 hsum = 0; 1309 iphdr = (uint16_t *)ip; 1310 1311 while (hlen > 1) { 1312 hsum += ntohs(*iphdr++); 1313 hlen -= sizeof(uint16_t); 1314 } 1315 while (hsum >> 16) 1316 hsum = (hsum >> 16) + (hsum & 0xffff); 1317 1318 csum_data += (uint16_t)~hsum; 1319 1320 while (csum_data >> 16) 1321 csum_data = 1322 (csum_data >> 16) + (csum_data & 0xffff); 1323 } 1324 #endif 1325 } 1326 out: 1327 m->m_pkthdr.csum_flags = csum_flags; 1328 m->m_pkthdr.csum_data = csum_data; 1329 } 1330 1331 /* 1332 * Handle receive interrupts. 1333 */ 1334 int 1335 fxp_rxintr(struct fxp_softc *sc) 1336 { 1337 struct ethercom *ec = &sc->sc_ethercom; 1338 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1339 struct mbuf *m, *m0; 1340 bus_dmamap_t rxmap; 1341 struct fxp_rfa *rfa; 1342 int rnr; 1343 uint16_t len, rxstat; 1344 1345 rnr = 0; 1346 1347 for (;;) { 1348 m = sc->sc_rxq.ifq_head; 1349 rfa = FXP_MTORFA(m); 1350 rxmap = M_GETCTX(m, bus_dmamap_t); 1351 1352 FXP_RFASYNC(sc, m, 1353 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1354 1355 rxstat = le16toh(rfa->rfa_status); 1356 1357 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1358 rnr = 1; 1359 1360 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1361 /* 1362 * We have processed all of the 1363 * receive buffers. 1364 */ 1365 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1366 return rnr; 1367 } 1368 1369 IF_DEQUEUE(&sc->sc_rxq, m); 1370 1371 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1372 1373 len = le16toh(rfa->actual_size) & 1374 (m->m_ext.ext_size - 1); 1375 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1376 /* Adjust for appended checksum bytes. */ 1377 len -= sizeof(uint16_t); 1378 } 1379 1380 if (len < sizeof(struct ether_header)) { 1381 /* 1382 * Runt packet; drop it now. 1383 */ 1384 FXP_INIT_RFABUF(sc, m); 1385 continue; 1386 } 1387 1388 /* 1389 * If support for 802.1Q VLAN sized frames is 1390 * enabled, we need to do some additional error 1391 * checking (as we are saving bad frames, in 1392 * order to receive the larger ones). 1393 */ 1394 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1395 (rxstat & (FXP_RFA_STATUS_OVERRUN | 1396 FXP_RFA_STATUS_RNR | 1397 FXP_RFA_STATUS_ALIGN | 1398 FXP_RFA_STATUS_CRC)) != 0) { 1399 FXP_INIT_RFABUF(sc, m); 1400 continue; 1401 } 1402 1403 /* 1404 * check VLAN tag stripping. 1405 */ 1406 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1407 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) 1408 vlan_set_tag(m, be16toh(rfa->vlan_id)); 1409 1410 /* Do checksum checking. */ 1411 if ((ifp->if_csum_flags_rx & 1412 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) 1413 fxp_rx_hwcksum(sc, m, rfa, len); 1414 1415 /* 1416 * If the packet is small enough to fit in a 1417 * single header mbuf, allocate one and copy 1418 * the data into it. This greatly reduces 1419 * memory consumption when we receive lots 1420 * of small packets. 1421 * 1422 * Otherwise, we add a new buffer to the receive 1423 * chain. If this fails, we drop the packet and 1424 * recycle the old buffer. 1425 */ 1426 if (fxp_copy_small != 0 && len <= MHLEN) { 1427 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1428 if (m0 == NULL) 1429 goto dropit; 1430 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1431 memcpy(mtod(m0, void *), 1432 mtod(m, void *), len); 1433 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1434 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1435 FXP_INIT_RFABUF(sc, m); 1436 m = m0; 1437 } else { 1438 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1439 dropit: 1440 if_statinc(ifp, if_ierrors); 1441 FXP_INIT_RFABUF(sc, m); 1442 continue; 1443 } 1444 } 1445 1446 m_set_rcvif(m, ifp); 1447 m->m_pkthdr.len = m->m_len = len; 1448 1449 /* Pass it on. */ 1450 if_percpuq_enqueue(ifp->if_percpuq, m); 1451 } 1452 } 1453 1454 /* 1455 * Update packet in/out/collision statistics. The i82557 doesn't 1456 * allow you to access these counters without doing a fairly 1457 * expensive DMA to get _all_ of the statistics it maintains, so 1458 * we do this operation here only once per second. The statistics 1459 * counters in the kernel are updated from the previous dump-stats 1460 * DMA and then a new dump-stats DMA is started. The on-chip 1461 * counters are zeroed when the DMA completes. If we can't start 1462 * the DMA immediately, we don't wait - we just prepare to read 1463 * them again next time. 1464 */ 1465 void 1466 fxp_tick(void *arg) 1467 { 1468 struct fxp_softc *sc = arg; 1469 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1470 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1471 int s; 1472 1473 if (!device_is_active(sc->sc_dev)) 1474 return; 1475 1476 s = splnet(); 1477 1478 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1479 1480 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1481 1482 if_statadd_ref(nsr, if_opackets, le32toh(sp->tx_good)); 1483 if_statadd_ref(nsr, if_collisions, le32toh(sp->tx_total_collisions)); 1484 if (sp->rx_good) { 1485 sc->sc_rxidle = 0; 1486 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1487 sc->sc_rxidle++; 1488 } 1489 if_statadd_ref(nsr, if_ierrors, 1490 le32toh(sp->rx_crc_errors) + 1491 le32toh(sp->rx_alignment_errors) + 1492 le32toh(sp->rx_rnr_errors) + 1493 le32toh(sp->rx_overrun_errors)); 1494 /* 1495 * If any transmit underruns occurred, bump up the transmit 1496 * threshold by another 512 bytes (64 * 8). 1497 */ 1498 if (sp->tx_underruns) { 1499 if_statadd_ref(nsr, if_oerrors, le32toh(sp->tx_underruns)); 1500 if (tx_threshold < 192) 1501 tx_threshold += 64; 1502 } 1503 #ifdef FXP_EVENT_COUNTERS 1504 if (sc->sc_flags & FXPF_FC) { 1505 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1506 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1507 } 1508 #endif 1509 1510 IF_STAT_PUTREF(ifp); 1511 1512 /* 1513 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1514 * then assume the receiver has locked up and attempt to clear 1515 * the condition by reprogramming the multicast filter (actually, 1516 * resetting the interface). This is a work-around for a bug in 1517 * the 82557 where the receiver locks up if it gets certain types 1518 * of garbage in the synchronization bits prior to the packet header. 1519 * This bug is supposed to only occur in 10Mbps mode, but has been 1520 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1521 * speed transition). 1522 */ 1523 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1524 (void) fxp_init(ifp); 1525 splx(s); 1526 return; 1527 } 1528 /* 1529 * If there is no pending command, start another stats 1530 * dump. Otherwise punt for now. 1531 */ 1532 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1533 /* 1534 * Start another stats dump. 1535 */ 1536 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1537 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1538 } else { 1539 /* 1540 * A previous command is still waiting to be accepted. 1541 * Just zero our copy of the stats and wait for the 1542 * next timer event to update them. 1543 */ 1544 /* BIG_ENDIAN: no swap required to store 0 */ 1545 sp->tx_good = 0; 1546 sp->tx_underruns = 0; 1547 sp->tx_total_collisions = 0; 1548 1549 sp->rx_good = 0; 1550 sp->rx_crc_errors = 0; 1551 sp->rx_alignment_errors = 0; 1552 sp->rx_rnr_errors = 0; 1553 sp->rx_overrun_errors = 0; 1554 if (sc->sc_flags & FXPF_FC) { 1555 sp->tx_pauseframes = 0; 1556 sp->rx_pauseframes = 0; 1557 } 1558 } 1559 1560 if (sc->sc_flags & FXPF_MII) { 1561 /* Tick the MII clock. */ 1562 mii_tick(&sc->sc_mii); 1563 } 1564 1565 splx(s); 1566 1567 /* 1568 * Schedule another timeout one second from now. 1569 */ 1570 callout_schedule(&sc->sc_callout, hz); 1571 } 1572 1573 /* 1574 * Drain the receive queue. 1575 */ 1576 void 1577 fxp_rxdrain(struct fxp_softc *sc) 1578 { 1579 bus_dmamap_t rxmap; 1580 struct mbuf *m; 1581 1582 for (;;) { 1583 IF_DEQUEUE(&sc->sc_rxq, m); 1584 if (m == NULL) 1585 break; 1586 rxmap = M_GETCTX(m, bus_dmamap_t); 1587 bus_dmamap_unload(sc->sc_dmat, rxmap); 1588 FXP_RXMAP_PUT(sc, rxmap); 1589 m_freem(m); 1590 } 1591 } 1592 1593 /* 1594 * Stop the interface. Cancels the statistics updater and resets 1595 * the interface. 1596 */ 1597 void 1598 fxp_stop(struct ifnet *ifp, int disable) 1599 { 1600 struct fxp_softc *sc = ifp->if_softc; 1601 struct fxp_txsoft *txs; 1602 int i; 1603 1604 /* 1605 * Turn down interface (done early to avoid bad interactions 1606 * between panics, shutdown hooks, and the watchdog timer) 1607 */ 1608 ifp->if_timer = 0; 1609 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1610 1611 /* 1612 * Cancel stats updater. 1613 */ 1614 callout_stop(&sc->sc_callout); 1615 if (sc->sc_flags & FXPF_MII) { 1616 /* Down the MII. */ 1617 mii_down(&sc->sc_mii); 1618 } 1619 1620 /* 1621 * Issue software reset. This unloads any microcode that 1622 * might already be loaded. 1623 */ 1624 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1625 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1626 DELAY(50); 1627 1628 /* 1629 * Release any xmit buffers. 1630 */ 1631 for (i = 0; i < FXP_NTXCB; i++) { 1632 txs = FXP_DSTX(sc, i); 1633 if (txs->txs_mbuf != NULL) { 1634 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1635 m_freem(txs->txs_mbuf); 1636 txs->txs_mbuf = NULL; 1637 } 1638 } 1639 sc->sc_txpending = 0; 1640 1641 if (disable) { 1642 fxp_rxdrain(sc); 1643 fxp_disable(sc); 1644 } 1645 1646 } 1647 1648 /* 1649 * Watchdog/transmission transmit timeout handler. Called when a 1650 * transmission is started on the interface, but no interrupt is 1651 * received before the timeout. This usually indicates that the 1652 * card has wedged for some reason. 1653 */ 1654 void 1655 fxp_watchdog(struct ifnet *ifp) 1656 { 1657 struct fxp_softc *sc = ifp->if_softc; 1658 1659 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1660 if_statinc(ifp, if_oerrors); 1661 1662 (void) fxp_init(ifp); 1663 } 1664 1665 /* 1666 * Initialize the interface. Must be called at splnet(). 1667 */ 1668 int 1669 fxp_init(struct ifnet *ifp) 1670 { 1671 struct fxp_softc *sc = ifp->if_softc; 1672 struct fxp_cb_config *cbp; 1673 struct fxp_cb_ias *cb_ias; 1674 struct fxp_txdesc *txd; 1675 bus_dmamap_t rxmap; 1676 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1677 uint16_t status; 1678 1679 if ((error = fxp_enable(sc)) != 0) 1680 goto out; 1681 1682 /* 1683 * Cancel any pending I/O 1684 */ 1685 fxp_stop(ifp, 0); 1686 1687 /* 1688 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1689 * flag, and this prevents the MII from detaching resulting in 1690 * a panic. The flags field should perhaps be split in runtime 1691 * flags and more static information. For now, just clear the 1692 * only other flag set. 1693 */ 1694 1695 sc->sc_flags &= ~FXPF_WANTINIT; 1696 1697 /* 1698 * Initialize base of CBL and RFA memory. Loading with zero 1699 * sets it up for regular linear addressing. 1700 */ 1701 fxp_scb_wait(sc); 1702 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1703 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1704 1705 fxp_scb_wait(sc); 1706 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1707 1708 /* 1709 * Initialize the multicast filter. Do this now, since we might 1710 * have to setup the config block differently. 1711 */ 1712 fxp_mc_setup(sc); 1713 1714 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1715 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1716 1717 /* 1718 * In order to support receiving 802.1Q VLAN frames, we have to 1719 * enable "save bad frames", since they are 4 bytes larger than 1720 * the normal Ethernet maximum frame length. On i82558 and later, 1721 * we have a better mechanism for this. 1722 */ 1723 save_bf = 0; 1724 lrxen = 0; 1725 vlan_drop = 0; 1726 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1727 if (sc->sc_rev < FXP_REV_82558_A4) 1728 save_bf = 1; 1729 else 1730 lrxen = 1; 1731 if (sc->sc_rev >= FXP_REV_82550) 1732 vlan_drop = 1; 1733 } 1734 1735 /* 1736 * Initialize base of dump-stats buffer. 1737 */ 1738 fxp_scb_wait(sc); 1739 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1740 sc->sc_cddma + FXP_CDSTATSOFF); 1741 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1742 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1743 1744 cbp = &sc->sc_control_data->fcd_configcb; 1745 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1746 1747 /* 1748 * Load microcode for this controller. 1749 */ 1750 fxp_load_ucode(sc); 1751 1752 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1753 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1754 else 1755 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1756 1757 /* 1758 * This copy is kind of disgusting, but there are a bunch of must be 1759 * zero and must be one bits in this structure and this is the easiest 1760 * way to initialize them all to proper values. 1761 */ 1762 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1763 1764 /* BIG_ENDIAN: no need to swap to store 0 */ 1765 cbp->cb_status = 0; 1766 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1767 FXP_CB_COMMAND_EL); 1768 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1769 cbp->link_addr = 0xffffffff; /* (no) next command */ 1770 /* bytes in config block */ 1771 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1772 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1773 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1774 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1775 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1776 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1777 cbp->type_enable = 0; /* actually reserved */ 1778 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1779 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1780 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1781 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1782 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1783 cbp->late_scb = 0; /* (don't) defer SCB update */ 1784 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1785 cbp->ci_int = 1; /* interrupt on CU idle */ 1786 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1787 cbp->ext_stats_dis = 1; /* disable extended counters */ 1788 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1789 cbp->save_bf = save_bf;/* save bad frames */ 1790 cbp->disc_short_rx = !prm; /* discard short packets */ 1791 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1792 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1793 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1794 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1795 /* interface mode */ 1796 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1797 cbp->csma_dis = 0; /* (don't) disable link */ 1798 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1799 /* (don't) enable RX checksum */ 1800 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1801 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1802 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1803 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1804 cbp->nsai = 1; /* (don't) disable source addr insert */ 1805 cbp->preamble_length = 2; /* (7 byte) preamble */ 1806 cbp->loopback = 0; /* (don't) loopback */ 1807 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1808 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1809 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1810 cbp->promiscuous = prm; /* promiscuous mode */ 1811 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1812 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1813 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1814 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1815 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1816 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1817 cbp->padding = 1; /* (do) pad short tx packets */ 1818 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1819 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1820 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1821 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1822 /* must set wake_en in PMCSR also */ 1823 cbp->force_fdx = 0; /* (don't) force full duplex */ 1824 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1825 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1826 cbp->mc_all = allm; /* accept all multicasts */ 1827 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1828 cbp->vlan_drop_en = vlan_drop; 1829 1830 if (!(sc->sc_flags & FXPF_FC)) { 1831 /* 1832 * The i82557 has no hardware flow control, the values 1833 * here are the defaults for the chip. 1834 */ 1835 cbp->fc_delay_lsb = 0; 1836 cbp->fc_delay_msb = 0x40; 1837 cbp->pri_fc_thresh = 3; 1838 cbp->tx_fc_dis = 0; 1839 cbp->rx_fc_restop = 0; 1840 cbp->rx_fc_restart = 0; 1841 cbp->fc_filter = 0; 1842 cbp->pri_fc_loc = 1; 1843 } else { 1844 cbp->fc_delay_lsb = 0x1f; 1845 cbp->fc_delay_msb = 0x01; 1846 cbp->pri_fc_thresh = 3; 1847 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1848 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1849 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1850 cbp->fc_filter = !prm; /* drop FC frames to host */ 1851 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1852 cbp->ext_stats_dis = 0; /* enable extended stats */ 1853 } 1854 1855 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1856 1857 /* 1858 * Start the config command/DMA. 1859 */ 1860 fxp_scb_wait(sc); 1861 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1862 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1863 /* ...and wait for it to complete. */ 1864 for (i = 1000; i > 0; i--) { 1865 FXP_CDCONFIGSYNC(sc, 1866 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1867 status = le16toh(cbp->cb_status); 1868 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1869 if ((status & FXP_CB_STATUS_C) != 0) 1870 break; 1871 DELAY(1); 1872 } 1873 if (i == 0) { 1874 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1875 device_xname(sc->sc_dev), __LINE__); 1876 return (ETIMEDOUT); 1877 } 1878 1879 /* 1880 * Initialize the station address. 1881 */ 1882 cb_ias = &sc->sc_control_data->fcd_iascb; 1883 /* BIG_ENDIAN: no need to swap to store 0 */ 1884 cb_ias->cb_status = 0; 1885 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1886 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1887 cb_ias->link_addr = 0xffffffff; 1888 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1889 1890 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1891 1892 /* 1893 * Start the IAS (Individual Address Setup) command/DMA. 1894 */ 1895 fxp_scb_wait(sc); 1896 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1897 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1898 /* ...and wait for it to complete. */ 1899 for (i = 1000; i > 0; i--) { 1900 FXP_CDIASSYNC(sc, 1901 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1902 status = le16toh(cb_ias->cb_status); 1903 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1904 if ((status & FXP_CB_STATUS_C) != 0) 1905 break; 1906 DELAY(1); 1907 } 1908 if (i == 0) { 1909 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1910 device_xname(sc->sc_dev), __LINE__); 1911 return (ETIMEDOUT); 1912 } 1913 1914 /* 1915 * Initialize the transmit descriptor ring. txlast is initialized 1916 * to the end of the list so that it will wrap around to the first 1917 * descriptor when the first packet is transmitted. 1918 */ 1919 for (i = 0; i < FXP_NTXCB; i++) { 1920 txd = FXP_CDTX(sc, i); 1921 memset(txd, 0, sizeof(*txd)); 1922 txd->txd_txcb.cb_command = 1923 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1924 txd->txd_txcb.link_addr = 1925 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1926 if (sc->sc_flags & FXPF_EXT_TXCB) 1927 txd->txd_txcb.tbd_array_addr = 1928 htole32(FXP_CDTBDADDR(sc, i) + 1929 (2 * sizeof(struct fxp_tbd))); 1930 else 1931 txd->txd_txcb.tbd_array_addr = 1932 htole32(FXP_CDTBDADDR(sc, i)); 1933 FXP_CDTXSYNC(sc, i, 1934 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1935 } 1936 sc->sc_txpending = 0; 1937 sc->sc_txdirty = 0; 1938 sc->sc_txlast = FXP_NTXCB - 1; 1939 1940 /* 1941 * Initialize the receive buffer list. 1942 */ 1943 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1944 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1945 rxmap = FXP_RXMAP_GET(sc); 1946 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1947 log(LOG_ERR, "%s: unable to allocate or map rx " 1948 "buffer %d, error = %d\n", 1949 device_xname(sc->sc_dev), 1950 sc->sc_rxq.ifq_len, error); 1951 /* 1952 * XXX Should attempt to run with fewer receive 1953 * XXX buffers instead of just failing. 1954 */ 1955 FXP_RXMAP_PUT(sc, rxmap); 1956 fxp_rxdrain(sc); 1957 goto out; 1958 } 1959 } 1960 sc->sc_rxidle = 0; 1961 1962 /* 1963 * Give the transmit ring to the chip. We do this by pointing 1964 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1965 * issuing a start command. It will execute the NOP and then 1966 * suspend, pointing at the first descriptor. 1967 */ 1968 fxp_scb_wait(sc); 1969 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1970 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1971 1972 /* 1973 * Initialize receiver buffer area - RFA. 1974 */ 1975 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1976 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1977 fxp_scb_wait(sc); 1978 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1979 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1980 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1981 #endif 1982 1983 if (sc->sc_flags & FXPF_MII) { 1984 /* 1985 * Set current media. 1986 */ 1987 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1988 goto out; 1989 } 1990 1991 /* 1992 * ...all done! 1993 */ 1994 ifp->if_flags |= IFF_RUNNING; 1995 ifp->if_flags &= ~IFF_OACTIVE; 1996 1997 /* 1998 * Request a software generated interrupt that will be used to 1999 * (re)start the RU processing. If we direct the chip to start 2000 * receiving from the start of queue now, instead of letting the 2001 * interrupt handler first process all received packets, we run 2002 * the risk of having it overwrite mbuf clusters while they are 2003 * being processed or after they have been returned to the pool. 2004 */ 2005 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 2006 2007 /* 2008 * Start the one second timer. 2009 */ 2010 callout_schedule(&sc->sc_callout, hz); 2011 2012 /* 2013 * Attempt to start output on the interface. 2014 */ 2015 fxp_start(ifp); 2016 2017 out: 2018 if (error) { 2019 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2020 ifp->if_timer = 0; 2021 log(LOG_ERR, "%s: interface not running\n", 2022 device_xname(sc->sc_dev)); 2023 } 2024 return (error); 2025 } 2026 2027 /* 2028 * Notify the world which media we're using. 2029 */ 2030 void 2031 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2032 { 2033 struct fxp_softc *sc = ifp->if_softc; 2034 2035 if (sc->sc_enabled == 0) { 2036 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2037 ifmr->ifm_status = 0; 2038 return; 2039 } 2040 2041 ether_mediastatus(ifp, ifmr); 2042 } 2043 2044 int 2045 fxp_80c24_mediachange(struct ifnet *ifp) 2046 { 2047 2048 /* Nothing to do here. */ 2049 return (0); 2050 } 2051 2052 void 2053 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2054 { 2055 struct fxp_softc *sc = ifp->if_softc; 2056 2057 /* 2058 * Media is currently-selected media. We cannot determine 2059 * the link status. 2060 */ 2061 ifmr->ifm_status = 0; 2062 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2063 } 2064 2065 /* 2066 * Add a buffer to the end of the RFA buffer list. 2067 * Return 0 if successful, error code on failure. 2068 * 2069 * The RFA struct is stuck at the beginning of mbuf cluster and the 2070 * data pointer is fixed up to point just past it. 2071 */ 2072 int 2073 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2074 { 2075 struct mbuf *m; 2076 int error; 2077 2078 MGETHDR(m, M_DONTWAIT, MT_DATA); 2079 if (m == NULL) 2080 return (ENOBUFS); 2081 2082 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2083 MCLGET(m, M_DONTWAIT); 2084 if ((m->m_flags & M_EXT) == 0) { 2085 m_freem(m); 2086 return (ENOBUFS); 2087 } 2088 2089 if (unload) 2090 bus_dmamap_unload(sc->sc_dmat, rxmap); 2091 2092 M_SETCTX(m, rxmap); 2093 2094 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2095 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2096 BUS_DMA_READ | BUS_DMA_NOWAIT); 2097 if (error) { 2098 /* XXX XXX XXX */ 2099 aprint_error_dev(sc->sc_dev, 2100 "can't load rx DMA map %d, error = %d\n", 2101 sc->sc_rxq.ifq_len, error); 2102 panic("fxp_add_rfabuf"); 2103 } 2104 2105 FXP_INIT_RFABUF(sc, m); 2106 2107 return (0); 2108 } 2109 2110 int 2111 fxp_mdi_read(device_t self, int phy, int reg, uint16_t *value) 2112 { 2113 struct fxp_softc *sc = device_private(self); 2114 int count = 10000; 2115 uint32_t data; 2116 2117 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2118 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2119 2120 while (((data = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2121 0x10000000) == 0 && count--) 2122 DELAY(10); 2123 2124 if (count <= 0) { 2125 log(LOG_WARNING, 2126 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2127 return ETIMEDOUT; 2128 } 2129 2130 *value = data & 0xffff; 2131 return 0; 2132 } 2133 2134 void 2135 fxp_statchg(struct ifnet *ifp) 2136 { 2137 2138 /* Nothing to do. */ 2139 } 2140 2141 int 2142 fxp_mdi_write(device_t self, int phy, int reg, uint16_t value) 2143 { 2144 struct fxp_softc *sc = device_private(self); 2145 int count = 10000; 2146 2147 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2148 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | value); 2149 2150 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2151 count--) 2152 DELAY(10); 2153 2154 if (count <= 0) { 2155 log(LOG_WARNING, 2156 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2157 return ETIMEDOUT; 2158 } 2159 2160 return 0; 2161 } 2162 2163 int 2164 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2165 { 2166 struct fxp_softc *sc = ifp->if_softc; 2167 int s, error; 2168 2169 s = splnet(); 2170 2171 switch (cmd) { 2172 default: 2173 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2174 break; 2175 2176 error = 0; 2177 2178 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2179 ; 2180 else if (ifp->if_flags & IFF_RUNNING) { 2181 /* 2182 * Multicast list has changed; set the 2183 * hardware filter accordingly. 2184 */ 2185 while (sc->sc_txpending) { 2186 sc->sc_flags |= FXPF_WANTINIT; 2187 tsleep(sc, PSOCK, "fxp_init", 0); 2188 } 2189 error = fxp_init(ifp); 2190 } 2191 break; 2192 } 2193 2194 /* Try to get more packets going. */ 2195 if (sc->sc_enabled) 2196 fxp_start(ifp); 2197 2198 splx(s); 2199 return (error); 2200 } 2201 2202 /* 2203 * Program the multicast filter. 2204 * 2205 * This function must be called at splnet(). 2206 */ 2207 void 2208 fxp_mc_setup(struct fxp_softc *sc) 2209 { 2210 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2211 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2212 struct ethercom *ec = &sc->sc_ethercom; 2213 struct ether_multi *enm; 2214 struct ether_multistep step; 2215 int count, nmcasts; 2216 uint16_t status; 2217 2218 #ifdef DIAGNOSTIC 2219 if (sc->sc_txpending) 2220 panic("fxp_mc_setup: pending transmissions"); 2221 #endif 2222 2223 2224 if (ifp->if_flags & IFF_PROMISC) { 2225 ifp->if_flags |= IFF_ALLMULTI; 2226 return; 2227 } else { 2228 ifp->if_flags &= ~IFF_ALLMULTI; 2229 } 2230 2231 /* 2232 * Initialize multicast setup descriptor. 2233 */ 2234 nmcasts = 0; 2235 ETHER_LOCK(ec); 2236 ETHER_FIRST_MULTI(step, ec, enm); 2237 while (enm != NULL) { 2238 /* 2239 * Check for too many multicast addresses or if we're 2240 * listening to a range. Either way, we simply have 2241 * to accept all multicasts. 2242 */ 2243 if (nmcasts >= MAXMCADDR || 2244 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2245 ETHER_ADDR_LEN) != 0) { 2246 /* 2247 * Callers of this function must do the 2248 * right thing with this. If we're called 2249 * from outside fxp_init(), the caller must 2250 * detect if the state if IFF_ALLMULTI changes. 2251 * If it does, the caller must then call 2252 * fxp_init(), since allmulti is handled by 2253 * the config block. 2254 */ 2255 ifp->if_flags |= IFF_ALLMULTI; 2256 ETHER_UNLOCK(ec); 2257 return; 2258 } 2259 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2260 ETHER_ADDR_LEN); 2261 nmcasts++; 2262 ETHER_NEXT_MULTI(step, enm); 2263 } 2264 ETHER_UNLOCK(ec); 2265 2266 /* BIG_ENDIAN: no need to swap to store 0 */ 2267 mcsp->cb_status = 0; 2268 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2269 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2270 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2271 2272 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2273 2274 /* 2275 * Wait until the command unit is not active. This should never 2276 * happen since nothing is queued, but make sure anyway. 2277 */ 2278 count = 100; 2279 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2280 FXP_SCB_CUS_ACTIVE && --count) 2281 DELAY(1); 2282 if (count == 0) { 2283 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2284 device_xname(sc->sc_dev), __LINE__); 2285 return; 2286 } 2287 2288 /* 2289 * Start the multicast setup command/DMA. 2290 */ 2291 fxp_scb_wait(sc); 2292 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2293 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2294 2295 /* ...and wait for it to complete. */ 2296 for (count = 1000; count > 0; count--) { 2297 FXP_CDMCSSYNC(sc, 2298 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2299 status = le16toh(mcsp->cb_status); 2300 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2301 if ((status & FXP_CB_STATUS_C) != 0) 2302 break; 2303 DELAY(1); 2304 } 2305 if (count == 0) { 2306 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2307 device_xname(sc->sc_dev), __LINE__); 2308 return; 2309 } 2310 } 2311 2312 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2313 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2314 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2315 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2316 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2317 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2318 static const uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2319 2320 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2321 2322 static const struct ucode { 2323 int32_t revision; 2324 const uint32_t *ucode; 2325 size_t length; 2326 uint16_t int_delay_offset; 2327 uint16_t bundle_max_offset; 2328 } ucode_table[] = { 2329 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2330 D101_CPUSAVER_DWORD, 0 }, 2331 2332 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2333 D101_CPUSAVER_DWORD, 0 }, 2334 2335 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2336 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2337 2338 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2339 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2340 2341 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2342 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2343 2344 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2345 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2346 2347 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2348 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2349 2350 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 2351 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2352 2353 { 0, NULL, 0, 0, 0 } 2354 }; 2355 2356 void 2357 fxp_load_ucode(struct fxp_softc *sc) 2358 { 2359 const struct ucode *uc; 2360 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2361 int count, i; 2362 uint16_t status; 2363 2364 if (sc->sc_flags & FXPF_UCODE_LOADED) 2365 return; 2366 2367 /* 2368 * Only load the uCode if the user has requested that 2369 * we do so. 2370 */ 2371 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2372 sc->sc_int_delay = 0; 2373 sc->sc_bundle_max = 0; 2374 return; 2375 } 2376 2377 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2378 if (sc->sc_rev == uc->revision) 2379 break; 2380 } 2381 if (uc->ucode == NULL) 2382 return; 2383 2384 /* BIG ENDIAN: no need to swap to store 0 */ 2385 cbp->cb_status = 0; 2386 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2387 cbp->link_addr = 0xffffffff; /* (no) next command */ 2388 for (i = 0; i < uc->length; i++) 2389 cbp->ucode[i] = htole32(uc->ucode[i]); 2390 2391 if (uc->int_delay_offset) 2392 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2393 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2394 2395 if (uc->bundle_max_offset) 2396 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2397 htole16(fxp_bundle_max); 2398 2399 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2400 2401 /* 2402 * Download the uCode to the chip. 2403 */ 2404 fxp_scb_wait(sc); 2405 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2406 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2407 2408 /* ...and wait for it to complete. */ 2409 for (count = 10000; count > 0; count--) { 2410 FXP_CDUCODESYNC(sc, 2411 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2412 status = le16toh(cbp->cb_status); 2413 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2414 if ((status & FXP_CB_STATUS_C) != 0) 2415 break; 2416 DELAY(2); 2417 } 2418 if (count == 0) { 2419 sc->sc_int_delay = 0; 2420 sc->sc_bundle_max = 0; 2421 log(LOG_WARNING, "%s: timeout loading microcode\n", 2422 device_xname(sc->sc_dev)); 2423 return; 2424 } 2425 2426 if (sc->sc_int_delay != fxp_int_delay || 2427 sc->sc_bundle_max != fxp_bundle_max) { 2428 sc->sc_int_delay = fxp_int_delay; 2429 sc->sc_bundle_max = fxp_bundle_max; 2430 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2431 "max bundle: %d\n", device_xname(sc->sc_dev), 2432 sc->sc_int_delay, 2433 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2434 } 2435 2436 sc->sc_flags |= FXPF_UCODE_LOADED; 2437 } 2438 2439 int 2440 fxp_enable(struct fxp_softc *sc) 2441 { 2442 2443 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2444 if ((*sc->sc_enable)(sc) != 0) { 2445 log(LOG_ERR, "%s: device enable failed\n", 2446 device_xname(sc->sc_dev)); 2447 return (EIO); 2448 } 2449 } 2450 2451 sc->sc_enabled = 1; 2452 return (0); 2453 } 2454 2455 void 2456 fxp_disable(struct fxp_softc *sc) 2457 { 2458 2459 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2460 (*sc->sc_disable)(sc); 2461 sc->sc_enabled = 0; 2462 } 2463 } 2464 2465 /* 2466 * fxp_activate: 2467 * 2468 * Handle device activation/deactivation requests. 2469 */ 2470 int 2471 fxp_activate(device_t self, enum devact act) 2472 { 2473 struct fxp_softc *sc = device_private(self); 2474 2475 switch (act) { 2476 case DVACT_DEACTIVATE: 2477 if_deactivate(&sc->sc_ethercom.ec_if); 2478 return 0; 2479 default: 2480 return EOPNOTSUPP; 2481 } 2482 } 2483 2484 /* 2485 * fxp_detach: 2486 * 2487 * Detach an i82557 interface. 2488 */ 2489 int 2490 fxp_detach(struct fxp_softc *sc, int flags) 2491 { 2492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2493 int i, s; 2494 2495 /* Succeed now if there's no work to do. */ 2496 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2497 return (0); 2498 2499 s = splnet(); 2500 /* Stop the interface. Callouts are stopped in it. */ 2501 fxp_stop(ifp, 1); 2502 splx(s); 2503 2504 /* Destroy our callout. */ 2505 callout_destroy(&sc->sc_callout); 2506 2507 if (sc->sc_flags & FXPF_MII) { 2508 /* Detach all PHYs */ 2509 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2510 } 2511 2512 rnd_detach_source(&sc->rnd_source); 2513 ether_ifdetach(ifp); 2514 if_detach(ifp); 2515 2516 /* Delete all remaining media. */ 2517 ifmedia_fini(&sc->sc_mii.mii_media); 2518 2519 for (i = 0; i < FXP_NRFABUFS; i++) { 2520 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2521 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2522 } 2523 2524 for (i = 0; i < FXP_NTXCB; i++) { 2525 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2526 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2527 } 2528 2529 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2530 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2531 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2532 sizeof(struct fxp_control_data)); 2533 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2534 2535 return (0); 2536 } 2537
Indexes created Sat Oct 25 10:09:55 GMT 2025