i82557.c revision 1.155
1 /* $NetBSD: i82557.c,v 1.155 2019/09/20 09:00:50 maxv Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, David Greenman 35 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice unmodified, this list of conditions, and the following 43 * disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 61 */ 62 63 /* 64 * Device driver for the Intel i82557 fast Ethernet controller, 65 * and its successors, the i82558 and i82559. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.155 2019/09/20 09:00:50 maxv Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/callout.h> 74 #include <sys/mbuf.h> 75 #include <sys/malloc.h> 76 #include <sys/kernel.h> 77 #include <sys/socket.h> 78 #include <sys/ioctl.h> 79 #include <sys/errno.h> 80 #include <sys/device.h> 81 #include <sys/syslog.h> 82 #include <sys/proc.h> 83 84 #include <machine/endian.h> 85 86 #include <sys/rndsource.h> 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 #include <net/if_ether.h> 92 93 #include <netinet/in.h> 94 #include <netinet/in_systm.h> 95 #include <netinet/ip.h> 96 #include <netinet/tcp.h> 97 #include <netinet/udp.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 104 #include <dev/mii/miivar.h> 105 106 #include <dev/ic/i82557reg.h> 107 #include <dev/ic/i82557var.h> 108 109 #include <dev/microcode/i8255x/rcvbundl.h> 110 111 /* 112 * NOTE! On the Alpha, we have an alignment constraint. The 113 * card DMAs the packet immediately following the RFA. However, 114 * the first thing in the packet is a 14-byte Ethernet header. 115 * This means that the packet is misaligned. To compensate, 116 * we actually offset the RFA 2 bytes into the cluster. This 117 * alignes the packet after the Ethernet header at a 32-bit 118 * boundary. HOWEVER! This means that the RFA is misaligned! 119 */ 120 #define RFA_ALIGNMENT_FUDGE 2 121 122 /* 123 * The configuration byte map has several undefined fields which 124 * must be one or must be zero. Set up a template for these bits 125 * only (assuming an i82557 chip), leaving the actual configuration 126 * for fxp_init(). 127 * 128 * See the definition of struct fxp_cb_config for the bit definitions. 129 */ 130 const uint8_t fxp_cb_config_template[] = { 131 0x0, 0x0, /* cb_status */ 132 0x0, 0x0, /* cb_command */ 133 0x0, 0x0, 0x0, 0x0, /* link_addr */ 134 0x0, /* 0 */ 135 0x0, /* 1 */ 136 0x0, /* 2 */ 137 0x0, /* 3 */ 138 0x0, /* 4 */ 139 0x0, /* 5 */ 140 0x32, /* 6 */ 141 0x0, /* 7 */ 142 0x0, /* 8 */ 143 0x0, /* 9 */ 144 0x6, /* 10 */ 145 0x0, /* 11 */ 146 0x0, /* 12 */ 147 0x0, /* 13 */ 148 0xf2, /* 14 */ 149 0x48, /* 15 */ 150 0x0, /* 16 */ 151 0x40, /* 17 */ 152 0xf0, /* 18 */ 153 0x0, /* 19 */ 154 0x3f, /* 20 */ 155 0x5, /* 21 */ 156 0x0, /* 22 */ 157 0x0, /* 23 */ 158 0x0, /* 24 */ 159 0x0, /* 25 */ 160 0x0, /* 26 */ 161 0x0, /* 27 */ 162 0x0, /* 28 */ 163 0x0, /* 29 */ 164 0x0, /* 30 */ 165 0x0, /* 31 */ 166 }; 167 168 void fxp_mii_initmedia(struct fxp_softc *); 169 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 170 171 void fxp_80c24_initmedia(struct fxp_softc *); 172 int fxp_80c24_mediachange(struct ifnet *); 173 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 174 175 void fxp_start(struct ifnet *); 176 int fxp_ioctl(struct ifnet *, u_long, void *); 177 void fxp_watchdog(struct ifnet *); 178 int fxp_init(struct ifnet *); 179 void fxp_stop(struct ifnet *, int); 180 181 void fxp_txintr(struct fxp_softc *); 182 int fxp_rxintr(struct fxp_softc *); 183 184 void fxp_rx_hwcksum(struct fxp_softc *, struct mbuf *, 185 const struct fxp_rfa *, u_int); 186 187 void fxp_rxdrain(struct fxp_softc *); 188 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 189 int fxp_mdi_read(device_t, int, int, uint16_t *); 190 void fxp_statchg(struct ifnet *); 191 int fxp_mdi_write(device_t, int, int, uint16_t); 192 void fxp_autosize_eeprom(struct fxp_softc*); 193 void fxp_read_eeprom(struct fxp_softc *, uint16_t *, int, int); 194 void fxp_write_eeprom(struct fxp_softc *, uint16_t *, int, int); 195 void fxp_eeprom_update_cksum(struct fxp_softc *); 196 void fxp_get_info(struct fxp_softc *, uint8_t *); 197 void fxp_tick(void *); 198 void fxp_mc_setup(struct fxp_softc *); 199 void fxp_load_ucode(struct fxp_softc *); 200 201 int fxp_copy_small = 0; 202 203 /* 204 * Variables for interrupt mitigating microcode. 205 */ 206 int fxp_int_delay = 1000; /* usec */ 207 int fxp_bundle_max = 6; /* packets */ 208 209 struct fxp_phytype { 210 int fp_phy; /* type of PHY, -1 for MII at the end. */ 211 void (*fp_init)(struct fxp_softc *); 212 } fxp_phytype_table[] = { 213 { FXP_PHY_80C24, fxp_80c24_initmedia }, 214 { -1, fxp_mii_initmedia }, 215 }; 216 217 /* 218 * Set initial transmit threshold at 64 (512 bytes). This is 219 * increased by 64 (512 bytes) at a time, to maximum of 192 220 * (1536 bytes), if an underrun occurs. 221 */ 222 static int tx_threshold = 64; 223 224 /* 225 * Wait for the previous command to be accepted (but not necessarily 226 * completed). 227 */ 228 static inline void 229 fxp_scb_wait(struct fxp_softc *sc) 230 { 231 int i = 10000; 232 233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 234 delay(2); 235 if (i == 0) 236 log(LOG_WARNING, 237 "%s: WARNING: SCB timed out!\n", device_xname(sc->sc_dev)); 238 } 239 240 /* 241 * Submit a command to the i82557. 242 */ 243 static inline void 244 fxp_scb_cmd(struct fxp_softc *sc, uint8_t cmd) 245 { 246 247 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 248 } 249 250 /* 251 * Finish attaching an i82557 interface. Called by bus-specific front-end. 252 */ 253 void 254 fxp_attach(struct fxp_softc *sc) 255 { 256 uint8_t enaddr[ETHER_ADDR_LEN]; 257 struct ifnet *ifp; 258 bus_dma_segment_t seg; 259 int rseg, i, error; 260 struct fxp_phytype *fp; 261 262 callout_init(&sc->sc_callout, 0); 263 264 /* 265 * Enable use of extended RFDs and IPCBs for 82550 and later chips. 266 * Note: to use IPCB we need extended TXCB support too, and 267 * these feature flags should be set in each bus attachment. 268 */ 269 if (sc->sc_flags & FXPF_EXT_RFA) { 270 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 271 sc->sc_rfa_size = RFA_EXT_SIZE; 272 } else { 273 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 274 sc->sc_rfa_size = RFA_SIZE; 275 } 276 277 /* 278 * Allocate the control data structures, and create and load the 279 * DMA map for it. 280 */ 281 if ((error = bus_dmamem_alloc(sc->sc_dmat, 282 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 283 0)) != 0) { 284 aprint_error_dev(sc->sc_dev, 285 "unable to allocate control data, error = %d\n", 286 error); 287 goto fail_0; 288 } 289 290 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 291 sizeof(struct fxp_control_data), (void **)&sc->sc_control_data, 292 BUS_DMA_COHERENT)) != 0) { 293 aprint_error_dev(sc->sc_dev, 294 "unable to map control data, error = %d\n", error); 295 goto fail_1; 296 } 297 sc->sc_cdseg = seg; 298 sc->sc_cdnseg = rseg; 299 300 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 301 302 if ((error = bus_dmamap_create(sc->sc_dmat, 303 sizeof(struct fxp_control_data), 1, 304 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 305 aprint_error_dev(sc->sc_dev, 306 "unable to create control data DMA map, error = %d\n", 307 error); 308 goto fail_2; 309 } 310 311 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 312 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 313 0)) != 0) { 314 aprint_error_dev(sc->sc_dev, 315 "can't load control data DMA map, error = %d\n", 316 error); 317 goto fail_3; 318 } 319 320 /* 321 * Create the transmit buffer DMA maps. 322 */ 323 for (i = 0; i < FXP_NTXCB; i++) { 324 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 325 (sc->sc_flags & FXPF_EXT_RFA) ? 326 FXP_IPCB_NTXSEG : FXP_NTXSEG, 327 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 328 aprint_error_dev(sc->sc_dev, 329 "unable to create tx DMA map %d, error = %d\n", 330 i, error); 331 goto fail_4; 332 } 333 } 334 335 /* 336 * Create the receive buffer DMA maps. 337 */ 338 for (i = 0; i < FXP_NRFABUFS; i++) { 339 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 340 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 341 aprint_error_dev(sc->sc_dev, 342 "unable to create rx DMA map %d, error = %d\n", 343 i, error); 344 goto fail_5; 345 } 346 } 347 348 /* Initialize MAC address and media structures. */ 349 fxp_get_info(sc, enaddr); 350 351 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 352 ether_sprintf(enaddr)); 353 354 ifp = &sc->sc_ethercom.ec_if; 355 356 /* 357 * Get info about our media interface, and initialize it. Note 358 * the table terminates itself with a phy of -1, indicating 359 * that we're using MII. 360 */ 361 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 362 if (fp->fp_phy == sc->phy_primary_device) 363 break; 364 (*fp->fp_init)(sc); 365 366 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = fxp_ioctl; 370 ifp->if_start = fxp_start; 371 ifp->if_watchdog = fxp_watchdog; 372 ifp->if_init = fxp_init; 373 ifp->if_stop = fxp_stop; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 if (sc->sc_flags & FXPF_EXT_RFA) { 377 /* 378 * Enable hardware cksum support by EXT_RFA and IPCB. 379 * 380 * IFCAP_CSUM_IPv4_Tx seems to have a problem, 381 * at least, on i82550 rev.12. 382 * specifically, it doesn't set ipv4 checksum properly 383 * when sending UDP (and probably TCP) packets with 384 * 20 byte ipv4 header + 1 or 2 byte data, 385 * though ICMP packets seem working. 386 * FreeBSD driver has related comments. 387 * We've added a workaround to handle the bug by padding 388 * such packets manually. 389 */ 390 ifp->if_capabilities = 391 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 392 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 393 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 394 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 395 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 396 } else if (sc->sc_flags & FXPF_82559_RXCSUM) { 397 ifp->if_capabilities = 398 IFCAP_CSUM_TCPv4_Rx | 399 IFCAP_CSUM_UDPv4_Rx; 400 } 401 402 /* 403 * We can support 802.1Q VLAN-sized frames. 404 */ 405 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 406 407 /* 408 * Attach the interface. 409 */ 410 if_attach(ifp); 411 if_deferred_start_init(ifp, NULL); 412 ether_ifattach(ifp, enaddr); 413 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 414 RND_TYPE_NET, RND_FLAG_DEFAULT); 415 416 #ifdef FXP_EVENT_COUNTERS 417 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 418 NULL, device_xname(sc->sc_dev), "txstall"); 419 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 420 NULL, device_xname(sc->sc_dev), "txintr"); 421 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 422 NULL, device_xname(sc->sc_dev), "rxintr"); 423 if (sc->sc_flags & FXPF_FC) { 424 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 425 NULL, device_xname(sc->sc_dev), "txpause"); 426 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 427 NULL, device_xname(sc->sc_dev), "rxpause"); 428 } 429 #endif /* FXP_EVENT_COUNTERS */ 430 431 /* The attach is successful. */ 432 sc->sc_flags |= FXPF_ATTACHED; 433 434 return; 435 436 /* 437 * Free any resources we've allocated during the failed attach 438 * attempt. Do this in reverse order and fall though. 439 */ 440 fail_5: 441 for (i = 0; i < FXP_NRFABUFS; i++) { 442 if (sc->sc_rxmaps[i] != NULL) 443 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 444 } 445 fail_4: 446 for (i = 0; i < FXP_NTXCB; i++) { 447 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 448 bus_dmamap_destroy(sc->sc_dmat, 449 FXP_DSTX(sc, i)->txs_dmamap); 450 } 451 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 452 fail_3: 453 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 454 fail_2: 455 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 456 sizeof(struct fxp_control_data)); 457 fail_1: 458 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 459 fail_0: 460 return; 461 } 462 463 void 464 fxp_mii_initmedia(struct fxp_softc *sc) 465 { 466 struct mii_data * const mii = &sc->sc_mii; 467 int flags; 468 469 sc->sc_flags |= FXPF_MII; 470 471 mii->mii_ifp = &sc->sc_ethercom.ec_if; 472 mii->mii_readreg = fxp_mdi_read; 473 mii->mii_writereg = fxp_mdi_write; 474 mii->mii_statchg = fxp_statchg; 475 476 sc->sc_ethercom.ec_mii = mii; 477 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 478 fxp_mii_mediastatus); 479 480 flags = MIIF_NOISOLATE; 481 if (sc->sc_flags & FXPF_FC) 482 flags |= MIIF_FORCEANEG | MIIF_DOPAUSE; 483 /* 484 * The i82557 wedges if all of its PHYs are isolated! 485 */ 486 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 487 MII_OFFSET_ANY, flags); 488 if (LIST_EMPTY(&mii->mii_phys)) { 489 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 490 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 491 } else 492 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 493 } 494 495 void 496 fxp_80c24_initmedia(struct fxp_softc *sc) 497 { 498 struct mii_data * const mii = &sc->sc_mii; 499 500 /* 501 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 502 * doesn't have a programming interface of any sort. The 503 * media is sensed automatically based on how the link partner 504 * is configured. This is, in essence, manual configuration. 505 */ 506 aprint_normal_dev(sc->sc_dev, 507 "Seeq 80c24 AutoDUPLEX media interface present\n"); 508 ifmedia_init(&mii->mii_media, 0, fxp_80c24_mediachange, 509 fxp_80c24_mediastatus); 510 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 511 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 512 } 513 514 /* 515 * Initialize the interface media. 516 */ 517 void 518 fxp_get_info(struct fxp_softc *sc, uint8_t *enaddr) 519 { 520 uint16_t data, myea[ETHER_ADDR_LEN / 2]; 521 522 /* 523 * Reset to a stable state. 524 */ 525 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 526 DELAY(100); 527 528 sc->sc_eeprom_size = 0; 529 fxp_autosize_eeprom(sc); 530 if (sc->sc_eeprom_size == 0) { 531 aprint_error_dev(sc->sc_dev, "failed to detect EEPROM size\n"); 532 sc->sc_eeprom_size = 6; /* XXX panic here? */ 533 } 534 #ifdef DEBUG 535 aprint_debug_dev(sc->sc_dev, "detected %d word EEPROM\n", 536 1 << sc->sc_eeprom_size); 537 #endif 538 539 /* 540 * Get info about the primary PHY 541 */ 542 fxp_read_eeprom(sc, &data, 6, 1); 543 sc->phy_primary_device = 544 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 545 546 /* 547 * Read MAC address. 548 */ 549 fxp_read_eeprom(sc, myea, 0, 3); 550 enaddr[0] = myea[0] & 0xff; 551 enaddr[1] = myea[0] >> 8; 552 enaddr[2] = myea[1] & 0xff; 553 enaddr[3] = myea[1] >> 8; 554 enaddr[4] = myea[2] & 0xff; 555 enaddr[5] = myea[2] >> 8; 556 557 /* 558 * Systems based on the ICH2/ICH2-M chip from Intel, as well 559 * as some i82559 designs, have a defect where the chip can 560 * cause a PCI protocol violation if it receives a CU_RESUME 561 * command when it is entering the IDLE state. 562 * 563 * The work-around is to disable Dynamic Standby Mode, so that 564 * the chip never deasserts #CLKRUN, and always remains in the 565 * active state. 566 * 567 * Unfortunately, the only way to disable Dynamic Standby is 568 * to frob an EEPROM setting and reboot (the EEPROM setting 569 * is only consulted when the PCI bus comes out of reset). 570 * 571 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 572 */ 573 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 574 fxp_read_eeprom(sc, &data, 10, 1); 575 if (data & 0x02) { /* STB enable */ 576 aprint_error_dev(sc->sc_dev, "WARNING: " 577 "Disabling dynamic standby mode in EEPROM " 578 "to work around a\n"); 579 aprint_normal_dev(sc->sc_dev, 580 "WARNING: hardware bug. You must reset " 581 "the system before using this\n"); 582 aprint_normal_dev(sc->sc_dev, "WARNING: interface.\n"); 583 data &= ~0x02; 584 fxp_write_eeprom(sc, &data, 10, 1); 585 aprint_normal_dev(sc->sc_dev, "new EEPROM ID: 0x%04x\n", 586 data); 587 fxp_eeprom_update_cksum(sc); 588 } 589 } 590 591 /* Receiver lock-up workaround detection. (FXPF_RECV_WORKAROUND) */ 592 /* Due to false positives we make it conditional on setting link1 */ 593 fxp_read_eeprom(sc, &data, 3, 1); 594 if ((data & 0x03) != 0x03) { 595 aprint_verbose_dev(sc->sc_dev, 596 "May need receiver lock-up workaround\n"); 597 } 598 } 599 600 static void 601 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 602 { 603 uint16_t reg; 604 int x; 605 606 for (x = 1 << (len - 1); x != 0; x >>= 1) { 607 DELAY(40); 608 if (data & x) 609 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 610 else 611 reg = FXP_EEPROM_EECS; 612 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 613 DELAY(40); 614 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 615 reg | FXP_EEPROM_EESK); 616 DELAY(40); 617 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 618 } 619 DELAY(40); 620 } 621 622 /* 623 * Figure out EEPROM size. 624 * 625 * 559's can have either 64-word or 256-word EEPROMs, the 558 626 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 627 * talks about the existence of 16 to 256 word EEPROMs. 628 * 629 * The only known sizes are 64 and 256, where the 256 version is used 630 * by CardBus cards to store CIS information. 631 * 632 * The address is shifted in msb-to-lsb, and after the last 633 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 634 * after which follows the actual data. We try to detect this zero, by 635 * probing the data-out bit in the EEPROM control register just after 636 * having shifted in a bit. If the bit is zero, we assume we've 637 * shifted enough address bits. The data-out should be tri-state, 638 * before this, which should translate to a logical one. 639 * 640 * Other ways to do this would be to try to read a register with known 641 * contents with a varying number of address bits, but no such 642 * register seem to be available. The high bits of register 10 are 01 643 * on the 558 and 559, but apparently not on the 557. 644 * 645 * The Linux driver computes a checksum on the EEPROM data, but the 646 * value of this checksum is not very well documented. 647 */ 648 649 void 650 fxp_autosize_eeprom(struct fxp_softc *sc) 651 { 652 int x; 653 654 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 655 DELAY(40); 656 657 /* Shift in read opcode. */ 658 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 659 660 /* 661 * Shift in address, wait for the dummy zero following a correct 662 * address shift. 663 */ 664 for (x = 1; x <= 8; x++) { 665 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 666 DELAY(40); 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 668 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 669 DELAY(40); 670 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 671 FXP_EEPROM_EEDO) == 0) 672 break; 673 DELAY(40); 674 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 675 DELAY(40); 676 } 677 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 678 DELAY(40); 679 if (x != 6 && x != 8) { 680 #ifdef DEBUG 681 printf("%s: strange EEPROM size (%d)\n", 682 device_xname(sc->sc_dev), 1 << x); 683 #endif 684 } else 685 sc->sc_eeprom_size = x; 686 } 687 688 /* 689 * Read from the serial EEPROM. Basically, you manually shift in 690 * the read opcode (one bit at a time) and then shift in the address, 691 * and then you shift out the data (all of this one bit at a time). 692 * The word size is 16 bits, so you have to provide the address for 693 * every 16 bits of data. 694 */ 695 void 696 fxp_read_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 697 { 698 uint16_t reg; 699 int i, x; 700 701 for (i = 0; i < words; i++) { 702 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 703 704 /* Shift in read opcode. */ 705 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 706 707 /* Shift in address. */ 708 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 709 710 reg = FXP_EEPROM_EECS; 711 data[i] = 0; 712 713 /* Shift out data. */ 714 for (x = 16; x > 0; x--) { 715 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 716 reg | FXP_EEPROM_EESK); 717 DELAY(40); 718 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 719 FXP_EEPROM_EEDO) 720 data[i] |= (1 << (x - 1)); 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 722 DELAY(40); 723 } 724 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 725 DELAY(40); 726 } 727 } 728 729 /* 730 * Write data to the serial EEPROM. 731 */ 732 void 733 fxp_write_eeprom(struct fxp_softc *sc, uint16_t *data, int offset, int words) 734 { 735 int i, j; 736 737 for (i = 0; i < words; i++) { 738 /* Erase/write enable. */ 739 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 740 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 741 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 742 sc->sc_eeprom_size); 743 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 744 DELAY(4); 745 746 /* Shift in write opcode, address, data. */ 747 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 748 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 749 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 750 fxp_eeprom_shiftin(sc, data[i], 16); 751 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 752 DELAY(4); 753 754 /* Wait for the EEPROM to finish up. */ 755 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 756 DELAY(4); 757 for (j = 0; j < 1000; j++) { 758 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 759 FXP_EEPROM_EEDO) 760 break; 761 DELAY(50); 762 } 763 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 764 DELAY(4); 765 766 /* Erase/write disable. */ 767 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 768 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 769 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 771 DELAY(4); 772 } 773 } 774 775 /* 776 * Update the checksum of the EEPROM. 777 */ 778 void 779 fxp_eeprom_update_cksum(struct fxp_softc *sc) 780 { 781 int i; 782 uint16_t data, cksum; 783 784 cksum = 0; 785 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 786 fxp_read_eeprom(sc, &data, i, 1); 787 cksum += data; 788 } 789 i = (1 << sc->sc_eeprom_size) - 1; 790 cksum = 0xbaba - cksum; 791 fxp_read_eeprom(sc, &data, i, 1); 792 fxp_write_eeprom(sc, &cksum, i, 1); 793 log(LOG_INFO, "%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 794 device_xname(sc->sc_dev), i, data, cksum); 795 } 796 797 /* 798 * Start packet transmission on the interface. 799 */ 800 void 801 fxp_start(struct ifnet *ifp) 802 { 803 struct fxp_softc *sc = ifp->if_softc; 804 struct mbuf *m0, *m; 805 struct fxp_txdesc *txd; 806 struct fxp_txsoft *txs; 807 bus_dmamap_t dmamap; 808 int error, lasttx, nexttx, opending, seg, nsegs, len; 809 810 /* 811 * If we want a re-init, bail out now. 812 */ 813 if (sc->sc_flags & FXPF_WANTINIT) { 814 ifp->if_flags |= IFF_OACTIVE; 815 return; 816 } 817 818 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 819 return; 820 821 /* 822 * Remember the previous txpending and the current lasttx. 823 */ 824 opending = sc->sc_txpending; 825 lasttx = sc->sc_txlast; 826 827 /* 828 * Loop through the send queue, setting up transmit descriptors 829 * until we drain the queue, or use up all available transmit 830 * descriptors. 831 */ 832 for (;;) { 833 struct fxp_tbd *tbdp; 834 int csum_flags; 835 836 /* 837 * Grab a packet off the queue. 838 */ 839 IFQ_POLL(&ifp->if_snd, m0); 840 if (m0 == NULL) 841 break; 842 m = NULL; 843 844 if (sc->sc_txpending == FXP_NTXCB - 1) { 845 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 846 break; 847 } 848 849 /* 850 * Get the next available transmit descriptor. 851 */ 852 nexttx = FXP_NEXTTX(sc->sc_txlast); 853 txd = FXP_CDTX(sc, nexttx); 854 txs = FXP_DSTX(sc, nexttx); 855 dmamap = txs->txs_dmamap; 856 857 /* 858 * Load the DMA map. If this fails, the packet either 859 * didn't fit in the allotted number of frags, or we were 860 * short on resources. In this case, we'll copy and try 861 * again. 862 */ 863 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 864 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 865 MGETHDR(m, M_DONTWAIT, MT_DATA); 866 if (m == NULL) { 867 log(LOG_ERR, "%s: unable to allocate Tx mbuf\n", 868 device_xname(sc->sc_dev)); 869 break; 870 } 871 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 872 if (m0->m_pkthdr.len > MHLEN) { 873 MCLGET(m, M_DONTWAIT); 874 if ((m->m_flags & M_EXT) == 0) { 875 log(LOG_ERR, "%s: unable to allocate " 876 "Tx cluster\n", 877 device_xname(sc->sc_dev)); 878 m_freem(m); 879 break; 880 } 881 } 882 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 883 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 884 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 885 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 886 if (error) { 887 log(LOG_ERR, "%s: unable to load Tx buffer, " 888 "error = %d\n", 889 device_xname(sc->sc_dev), error); 890 break; 891 } 892 } 893 894 IFQ_DEQUEUE(&ifp->if_snd, m0); 895 csum_flags = m0->m_pkthdr.csum_flags; 896 if (m != NULL) { 897 m_freem(m0); 898 m0 = m; 899 } 900 901 /* Initialize the fraglist. */ 902 tbdp = txd->txd_tbd; 903 len = m0->m_pkthdr.len; 904 nsegs = dmamap->dm_nsegs; 905 if (sc->sc_flags & FXPF_EXT_RFA) 906 tbdp++; 907 for (seg = 0; seg < nsegs; seg++) { 908 tbdp[seg].tb_addr = 909 htole32(dmamap->dm_segs[seg].ds_addr); 910 tbdp[seg].tb_size = 911 htole32(dmamap->dm_segs[seg].ds_len); 912 } 913 if (__predict_false(len <= FXP_IP4CSUMTX_PADLEN && 914 (csum_flags & M_CSUM_IPv4) != 0)) { 915 /* 916 * Pad short packets to avoid ip4csum-tx bug. 917 * 918 * XXX Should we still consider if such short 919 * (36 bytes or less) packets might already 920 * occupy FXP_IPCB_NTXSEG (15) fragments here? 921 */ 922 KASSERT(nsegs < FXP_IPCB_NTXSEG); 923 nsegs++; 924 tbdp[seg].tb_addr = htole32(FXP_CDTXPADADDR(sc)); 925 tbdp[seg].tb_size = 926 htole32(FXP_IP4CSUMTX_PADLEN + 1 - len); 927 } 928 929 /* Sync the DMA map. */ 930 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 931 BUS_DMASYNC_PREWRITE); 932 933 /* 934 * Store a pointer to the packet so we can free it later. 935 */ 936 txs->txs_mbuf = m0; 937 938 /* 939 * Initialize the transmit descriptor. 940 */ 941 /* BIG_ENDIAN: no need to swap to store 0 */ 942 txd->txd_txcb.cb_status = 0; 943 txd->txd_txcb.cb_command = 944 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 945 txd->txd_txcb.tx_threshold = tx_threshold; 946 txd->txd_txcb.tbd_number = nsegs; 947 948 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 949 if (sc->sc_flags & FXPF_EXT_RFA) { 950 struct fxp_ipcb *ipcb; 951 /* 952 * Deal with TCP/IP checksum offload. Note that 953 * in order for TCP checksum offload to work, 954 * the pseudo header checksum must have already 955 * been computed and stored in the checksum field 956 * in the TCP header. The stack should have 957 * already done this for us. 958 */ 959 ipcb = &txd->txd_u.txdu_ipcb; 960 memset(ipcb, 0, sizeof(*ipcb)); 961 /* 962 * always do hardware parsing. 963 */ 964 ipcb->ipcb_ip_activation_high = 965 FXP_IPCB_HARDWAREPARSING_ENABLE; 966 /* 967 * ip checksum offloading. 968 */ 969 if (csum_flags & M_CSUM_IPv4) { 970 ipcb->ipcb_ip_schedule |= 971 FXP_IPCB_IP_CHECKSUM_ENABLE; 972 } 973 /* 974 * TCP/UDP checksum offloading. 975 */ 976 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 977 ipcb->ipcb_ip_schedule |= 978 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 979 } 980 981 /* 982 * request VLAN tag insertion if needed. 983 */ 984 if (vlan_has_tag(m0)) { 985 ipcb->ipcb_vlan_id = htobe16(vlan_get_tag(m0)); 986 ipcb->ipcb_ip_activation_high |= 987 FXP_IPCB_INSERTVLAN_ENABLE; 988 } 989 } else { 990 KASSERT((csum_flags & 991 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 992 } 993 994 FXP_CDTXSYNC(sc, nexttx, 995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 996 997 /* Advance the tx pointer. */ 998 sc->sc_txpending++; 999 sc->sc_txlast = nexttx; 1000 1001 /* 1002 * Pass packet to bpf if there is a listener. 1003 */ 1004 bpf_mtap(ifp, m0, BPF_D_OUT); 1005 } 1006 1007 if (sc->sc_txpending == FXP_NTXCB - 1) { 1008 /* No more slots; notify upper layer. */ 1009 ifp->if_flags |= IFF_OACTIVE; 1010 } 1011 1012 if (sc->sc_txpending != opending) { 1013 /* 1014 * We enqueued packets. If the transmitter was idle, 1015 * reset the txdirty pointer. 1016 */ 1017 if (opending == 0) 1018 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1019 1020 /* 1021 * Cause the chip to interrupt and suspend command 1022 * processing once the last packet we've enqueued 1023 * has been transmitted. 1024 * 1025 * To avoid a race between updating status bits 1026 * by the fxp chip and clearing command bits 1027 * by this function on machines which don't have 1028 * atomic methods to clear/set bits in memory 1029 * smaller than 32bits (both cb_status and cb_command 1030 * members are uint16_t and in the same 32bit word), 1031 * we have to prepare a dummy TX descriptor which has 1032 * NOP command and just causes a TX completion interrupt. 1033 */ 1034 sc->sc_txpending++; 1035 sc->sc_txlast = FXP_NEXTTX(sc->sc_txlast); 1036 txd = FXP_CDTX(sc, sc->sc_txlast); 1037 /* BIG_ENDIAN: no need to swap to store 0 */ 1038 txd->txd_txcb.cb_status = 0; 1039 txd->txd_txcb.cb_command = htole16(FXP_CB_COMMAND_NOP | 1040 FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1041 FXP_CDTXSYNC(sc, sc->sc_txlast, 1042 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1043 1044 /* 1045 * The entire packet chain is set up. Clear the suspend bit 1046 * on the command prior to the first packet we set up. 1047 */ 1048 FXP_CDTXSYNC(sc, lasttx, 1049 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1050 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1051 htole16(~FXP_CB_COMMAND_S); 1052 FXP_CDTXSYNC(sc, lasttx, 1053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1054 1055 /* 1056 * Issue a Resume command in case the chip was suspended. 1057 */ 1058 fxp_scb_wait(sc); 1059 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1060 1061 /* Set a watchdog timer in case the chip flakes out. */ 1062 ifp->if_timer = 5; 1063 } 1064 } 1065 1066 /* 1067 * Process interface interrupts. 1068 */ 1069 int 1070 fxp_intr(void *arg) 1071 { 1072 struct fxp_softc *sc = arg; 1073 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1074 bus_dmamap_t rxmap; 1075 int claimed = 0, rnr; 1076 uint8_t statack; 1077 1078 if (!device_is_active(sc->sc_dev) || sc->sc_enabled == 0) 1079 return (0); 1080 /* 1081 * If the interface isn't running, don't try to 1082 * service the interrupt.. just ack it and bail. 1083 */ 1084 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1085 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1086 if (statack) { 1087 claimed = 1; 1088 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1089 } 1090 return (claimed); 1091 } 1092 1093 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1094 claimed = 1; 1095 1096 /* 1097 * First ACK all the interrupts in this pass. 1098 */ 1099 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1100 1101 /* 1102 * Process receiver interrupts. If a no-resource (RNR) 1103 * condition exists, get whatever packets we can and 1104 * re-start the receiver. 1105 */ 1106 rnr = (statack & (FXP_SCB_STATACK_RNR | FXP_SCB_STATACK_SWI)) ? 1107 1 : 0; 1108 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR | 1109 FXP_SCB_STATACK_SWI)) { 1110 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1111 rnr |= fxp_rxintr(sc); 1112 } 1113 1114 /* 1115 * Free any finished transmit mbuf chains. 1116 */ 1117 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1118 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1119 fxp_txintr(sc); 1120 1121 /* 1122 * Try to get more packets going. 1123 */ 1124 if_schedule_deferred_start(ifp); 1125 1126 if (sc->sc_txpending == 0) { 1127 /* 1128 * Tell them that they can re-init now. 1129 */ 1130 if (sc->sc_flags & FXPF_WANTINIT) 1131 wakeup(sc); 1132 } 1133 } 1134 1135 if (rnr) { 1136 fxp_scb_wait(sc); 1137 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_ABORT); 1138 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1139 fxp_scb_wait(sc); 1140 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1141 rxmap->dm_segs[0].ds_addr + 1142 RFA_ALIGNMENT_FUDGE); 1143 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1144 } 1145 } 1146 1147 if (claimed) 1148 rnd_add_uint32(&sc->rnd_source, statack); 1149 return (claimed); 1150 } 1151 1152 /* 1153 * Handle transmit completion interrupts. 1154 */ 1155 void 1156 fxp_txintr(struct fxp_softc *sc) 1157 { 1158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1159 struct fxp_txdesc *txd; 1160 struct fxp_txsoft *txs; 1161 int i; 1162 uint16_t txstat; 1163 1164 ifp->if_flags &= ~IFF_OACTIVE; 1165 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1166 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1167 txd = FXP_CDTX(sc, i); 1168 txs = FXP_DSTX(sc, i); 1169 1170 FXP_CDTXSYNC(sc, i, 1171 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1172 1173 /* skip dummy NOP TX descriptor */ 1174 if ((le16toh(txd->txd_txcb.cb_command) & FXP_CB_COMMAND_CMD) 1175 == FXP_CB_COMMAND_NOP) 1176 continue; 1177 1178 txstat = le16toh(txd->txd_txcb.cb_status); 1179 1180 if ((txstat & FXP_CB_STATUS_C) == 0) 1181 break; 1182 1183 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1184 0, txs->txs_dmamap->dm_mapsize, 1185 BUS_DMASYNC_POSTWRITE); 1186 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1187 m_freem(txs->txs_mbuf); 1188 txs->txs_mbuf = NULL; 1189 } 1190 1191 /* Update the dirty transmit buffer pointer. */ 1192 sc->sc_txdirty = i; 1193 1194 /* 1195 * Cancel the watchdog timer if there are no pending 1196 * transmissions. 1197 */ 1198 if (sc->sc_txpending == 0) 1199 ifp->if_timer = 0; 1200 } 1201 1202 /* 1203 * fxp_rx_hwcksum: check status of H/W offloading for received packets. 1204 */ 1205 1206 void 1207 fxp_rx_hwcksum(struct fxp_softc *sc, struct mbuf *m, const struct fxp_rfa *rfa, 1208 u_int len) 1209 { 1210 uint32_t csum_data; 1211 int csum_flags; 1212 1213 /* 1214 * check H/W Checksumming. 1215 */ 1216 1217 csum_flags = 0; 1218 csum_data = 0; 1219 1220 if ((sc->sc_flags & FXPF_EXT_RFA) != 0) { 1221 uint8_t csum_stat; 1222 1223 csum_stat = rfa->cksum_stat; 1224 if ((rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE)) == 0) 1225 goto out; 1226 1227 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1228 csum_flags = M_CSUM_IPv4; 1229 if ((csum_stat & FXP_RFDX_CS_IP_CSUM_VALID) == 0) 1230 csum_flags |= M_CSUM_IPv4_BAD; 1231 } 1232 1233 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1234 csum_flags |= (M_CSUM_TCPv4 | M_CSUM_UDPv4); /* XXX */ 1235 if ((csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID) == 0) 1236 csum_flags |= M_CSUM_TCP_UDP_BAD; 1237 } 1238 1239 } else if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1240 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1241 struct ether_header *eh; 1242 struct ip *ip; 1243 struct udphdr *uh; 1244 u_int hlen, pktlen; 1245 1246 if (len < ETHER_HDR_LEN + sizeof(struct ip)) 1247 goto out; 1248 pktlen = len - ETHER_HDR_LEN; 1249 eh = mtod(m, struct ether_header *); 1250 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1251 goto out; 1252 ip = (struct ip *)((uint8_t *)eh + ETHER_HDR_LEN); 1253 if (ip->ip_v != IPVERSION) 1254 goto out; 1255 1256 hlen = ip->ip_hl << 2; 1257 if (hlen < sizeof(struct ip)) 1258 goto out; 1259 1260 /* 1261 * Bail if too short, has random trailing garbage, truncated, 1262 * fragment, or has ethernet pad. 1263 */ 1264 if (ntohs(ip->ip_len) < hlen || 1265 ntohs(ip->ip_len) != pktlen || 1266 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 1267 goto out; 1268 1269 switch (ip->ip_p) { 1270 case IPPROTO_TCP: 1271 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0 || 1272 pktlen < (hlen + sizeof(struct tcphdr))) 1273 goto out; 1274 csum_flags = 1275 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1276 break; 1277 case IPPROTO_UDP: 1278 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0 || 1279 pktlen < (hlen + sizeof(struct udphdr))) 1280 goto out; 1281 uh = (struct udphdr *)((uint8_t *)ip + hlen); 1282 if (uh->uh_sum == 0) 1283 goto out; /* no checksum */ 1284 csum_flags = 1285 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 1286 break; 1287 default: 1288 goto out; 1289 } 1290 1291 /* Extract computed checksum. */ 1292 csum_data = be16dec(mtod(m, uint8_t *) + len); 1293 1294 /* 1295 * The computed checksum includes IP headers, 1296 * so we have to deduct them. 1297 */ 1298 #if 0 1299 /* 1300 * But in TCP/UDP layer we can assume the IP header is valid, 1301 * i.e. a sum of the whole IP header should be 0xffff, 1302 * so we don't have to bother to deduct it. 1303 */ 1304 if (hlen > 0) { 1305 uint32_t hsum; 1306 const uint16_t *iphdr; 1307 hsum = 0; 1308 iphdr = (uint16_t *)ip; 1309 1310 while (hlen > 1) { 1311 hsum += ntohs(*iphdr++); 1312 hlen -= sizeof(uint16_t); 1313 } 1314 while (hsum >> 16) 1315 hsum = (hsum >> 16) + (hsum & 0xffff); 1316 1317 csum_data += (uint16_t)~hsum; 1318 1319 while (csum_data >> 16) 1320 csum_data = 1321 (csum_data >> 16) + (csum_data & 0xffff); 1322 } 1323 #endif 1324 } 1325 out: 1326 m->m_pkthdr.csum_flags = csum_flags; 1327 m->m_pkthdr.csum_data = csum_data; 1328 } 1329 1330 /* 1331 * Handle receive interrupts. 1332 */ 1333 int 1334 fxp_rxintr(struct fxp_softc *sc) 1335 { 1336 struct ethercom *ec = &sc->sc_ethercom; 1337 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1338 struct mbuf *m, *m0; 1339 bus_dmamap_t rxmap; 1340 struct fxp_rfa *rfa; 1341 int rnr; 1342 uint16_t len, rxstat; 1343 1344 rnr = 0; 1345 1346 for (;;) { 1347 m = sc->sc_rxq.ifq_head; 1348 rfa = FXP_MTORFA(m); 1349 rxmap = M_GETCTX(m, bus_dmamap_t); 1350 1351 FXP_RFASYNC(sc, m, 1352 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1353 1354 rxstat = le16toh(rfa->rfa_status); 1355 1356 if ((rxstat & FXP_RFA_STATUS_RNR) != 0) 1357 rnr = 1; 1358 1359 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1360 /* 1361 * We have processed all of the 1362 * receive buffers. 1363 */ 1364 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1365 return rnr; 1366 } 1367 1368 IF_DEQUEUE(&sc->sc_rxq, m); 1369 1370 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1371 1372 len = le16toh(rfa->actual_size) & 1373 (m->m_ext.ext_size - 1); 1374 if ((sc->sc_flags & FXPF_82559_RXCSUM) != 0) { 1375 /* Adjust for appended checksum bytes. */ 1376 len -= sizeof(uint16_t); 1377 } 1378 1379 if (len < sizeof(struct ether_header)) { 1380 /* 1381 * Runt packet; drop it now. 1382 */ 1383 FXP_INIT_RFABUF(sc, m); 1384 continue; 1385 } 1386 1387 /* 1388 * If support for 802.1Q VLAN sized frames is 1389 * enabled, we need to do some additional error 1390 * checking (as we are saving bad frames, in 1391 * order to receive the larger ones). 1392 */ 1393 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1394 (rxstat & (FXP_RFA_STATUS_OVERRUN | 1395 FXP_RFA_STATUS_RNR | 1396 FXP_RFA_STATUS_ALIGN | 1397 FXP_RFA_STATUS_CRC)) != 0) { 1398 FXP_INIT_RFABUF(sc, m); 1399 continue; 1400 } 1401 1402 /* 1403 * check VLAN tag stripping. 1404 */ 1405 if ((sc->sc_flags & FXPF_EXT_RFA) != 0 && 1406 (rfa->rfa_status & htole16(FXP_RFA_STATUS_VLAN)) != 0) 1407 vlan_set_tag(m, be16toh(rfa->vlan_id)); 1408 1409 /* Do checksum checking. */ 1410 if ((ifp->if_csum_flags_rx & 1411 (M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) 1412 fxp_rx_hwcksum(sc, m, rfa, len); 1413 1414 /* 1415 * If the packet is small enough to fit in a 1416 * single header mbuf, allocate one and copy 1417 * the data into it. This greatly reduces 1418 * memory consumption when we receive lots 1419 * of small packets. 1420 * 1421 * Otherwise, we add a new buffer to the receive 1422 * chain. If this fails, we drop the packet and 1423 * recycle the old buffer. 1424 */ 1425 if (fxp_copy_small != 0 && len <= MHLEN) { 1426 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1427 if (m0 == NULL) 1428 goto dropit; 1429 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1430 memcpy(mtod(m0, void *), 1431 mtod(m, void *), len); 1432 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1433 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1434 FXP_INIT_RFABUF(sc, m); 1435 m = m0; 1436 } else { 1437 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1438 dropit: 1439 ifp->if_ierrors++; 1440 FXP_INIT_RFABUF(sc, m); 1441 continue; 1442 } 1443 } 1444 1445 m_set_rcvif(m, ifp); 1446 m->m_pkthdr.len = m->m_len = len; 1447 1448 /* Pass it on. */ 1449 if_percpuq_enqueue(ifp->if_percpuq, m); 1450 } 1451 } 1452 1453 /* 1454 * Update packet in/out/collision statistics. The i82557 doesn't 1455 * allow you to access these counters without doing a fairly 1456 * expensive DMA to get _all_ of the statistics it maintains, so 1457 * we do this operation here only once per second. The statistics 1458 * counters in the kernel are updated from the previous dump-stats 1459 * DMA and then a new dump-stats DMA is started. The on-chip 1460 * counters are zeroed when the DMA completes. If we can't start 1461 * the DMA immediately, we don't wait - we just prepare to read 1462 * them again next time. 1463 */ 1464 void 1465 fxp_tick(void *arg) 1466 { 1467 struct fxp_softc *sc = arg; 1468 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1469 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1470 int s; 1471 1472 if (!device_is_active(sc->sc_dev)) 1473 return; 1474 1475 s = splnet(); 1476 1477 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1478 1479 ifp->if_opackets += le32toh(sp->tx_good); 1480 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1481 if (sp->rx_good) { 1482 ifp->if_ipackets += le32toh(sp->rx_good); 1483 sc->sc_rxidle = 0; 1484 } else if (sc->sc_flags & FXPF_RECV_WORKAROUND) { 1485 sc->sc_rxidle++; 1486 } 1487 ifp->if_ierrors += 1488 le32toh(sp->rx_crc_errors) + 1489 le32toh(sp->rx_alignment_errors) + 1490 le32toh(sp->rx_rnr_errors) + 1491 le32toh(sp->rx_overrun_errors); 1492 /* 1493 * If any transmit underruns occurred, bump up the transmit 1494 * threshold by another 512 bytes (64 * 8). 1495 */ 1496 if (sp->tx_underruns) { 1497 ifp->if_oerrors += le32toh(sp->tx_underruns); 1498 if (tx_threshold < 192) 1499 tx_threshold += 64; 1500 } 1501 #ifdef FXP_EVENT_COUNTERS 1502 if (sc->sc_flags & FXPF_FC) { 1503 sc->sc_ev_txpause.ev_count += sp->tx_pauseframes; 1504 sc->sc_ev_rxpause.ev_count += sp->rx_pauseframes; 1505 } 1506 #endif 1507 1508 /* 1509 * If we haven't received any packets in FXP_MAX_RX_IDLE seconds, 1510 * then assume the receiver has locked up and attempt to clear 1511 * the condition by reprogramming the multicast filter (actually, 1512 * resetting the interface). This is a work-around for a bug in 1513 * the 82557 where the receiver locks up if it gets certain types 1514 * of garbage in the synchronization bits prior to the packet header. 1515 * This bug is supposed to only occur in 10Mbps mode, but has been 1516 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1517 * speed transition). 1518 */ 1519 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1520 (void) fxp_init(ifp); 1521 splx(s); 1522 return; 1523 } 1524 /* 1525 * If there is no pending command, start another stats 1526 * dump. Otherwise punt for now. 1527 */ 1528 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1529 /* 1530 * Start another stats dump. 1531 */ 1532 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1533 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1534 } else { 1535 /* 1536 * A previous command is still waiting to be accepted. 1537 * Just zero our copy of the stats and wait for the 1538 * next timer event to update them. 1539 */ 1540 /* BIG_ENDIAN: no swap required to store 0 */ 1541 sp->tx_good = 0; 1542 sp->tx_underruns = 0; 1543 sp->tx_total_collisions = 0; 1544 1545 sp->rx_good = 0; 1546 sp->rx_crc_errors = 0; 1547 sp->rx_alignment_errors = 0; 1548 sp->rx_rnr_errors = 0; 1549 sp->rx_overrun_errors = 0; 1550 if (sc->sc_flags & FXPF_FC) { 1551 sp->tx_pauseframes = 0; 1552 sp->rx_pauseframes = 0; 1553 } 1554 } 1555 1556 if (sc->sc_flags & FXPF_MII) { 1557 /* Tick the MII clock. */ 1558 mii_tick(&sc->sc_mii); 1559 } 1560 1561 splx(s); 1562 1563 /* 1564 * Schedule another timeout one second from now. 1565 */ 1566 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1567 } 1568 1569 /* 1570 * Drain the receive queue. 1571 */ 1572 void 1573 fxp_rxdrain(struct fxp_softc *sc) 1574 { 1575 bus_dmamap_t rxmap; 1576 struct mbuf *m; 1577 1578 for (;;) { 1579 IF_DEQUEUE(&sc->sc_rxq, m); 1580 if (m == NULL) 1581 break; 1582 rxmap = M_GETCTX(m, bus_dmamap_t); 1583 bus_dmamap_unload(sc->sc_dmat, rxmap); 1584 FXP_RXMAP_PUT(sc, rxmap); 1585 m_freem(m); 1586 } 1587 } 1588 1589 /* 1590 * Stop the interface. Cancels the statistics updater and resets 1591 * the interface. 1592 */ 1593 void 1594 fxp_stop(struct ifnet *ifp, int disable) 1595 { 1596 struct fxp_softc *sc = ifp->if_softc; 1597 struct fxp_txsoft *txs; 1598 int i; 1599 1600 /* 1601 * Turn down interface (done early to avoid bad interactions 1602 * between panics, shutdown hooks, and the watchdog timer) 1603 */ 1604 ifp->if_timer = 0; 1605 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1606 1607 /* 1608 * Cancel stats updater. 1609 */ 1610 callout_stop(&sc->sc_callout); 1611 if (sc->sc_flags & FXPF_MII) { 1612 /* Down the MII. */ 1613 mii_down(&sc->sc_mii); 1614 } 1615 1616 /* 1617 * Issue software reset. This unloads any microcode that 1618 * might already be loaded. 1619 */ 1620 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1621 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1622 DELAY(50); 1623 1624 /* 1625 * Release any xmit buffers. 1626 */ 1627 for (i = 0; i < FXP_NTXCB; i++) { 1628 txs = FXP_DSTX(sc, i); 1629 if (txs->txs_mbuf != NULL) { 1630 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1631 m_freem(txs->txs_mbuf); 1632 txs->txs_mbuf = NULL; 1633 } 1634 } 1635 sc->sc_txpending = 0; 1636 1637 if (disable) { 1638 fxp_rxdrain(sc); 1639 fxp_disable(sc); 1640 } 1641 1642 } 1643 1644 /* 1645 * Watchdog/transmission transmit timeout handler. Called when a 1646 * transmission is started on the interface, but no interrupt is 1647 * received before the timeout. This usually indicates that the 1648 * card has wedged for some reason. 1649 */ 1650 void 1651 fxp_watchdog(struct ifnet *ifp) 1652 { 1653 struct fxp_softc *sc = ifp->if_softc; 1654 1655 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1656 ifp->if_oerrors++; 1657 1658 (void) fxp_init(ifp); 1659 } 1660 1661 /* 1662 * Initialize the interface. Must be called at splnet(). 1663 */ 1664 int 1665 fxp_init(struct ifnet *ifp) 1666 { 1667 struct fxp_softc *sc = ifp->if_softc; 1668 struct fxp_cb_config *cbp; 1669 struct fxp_cb_ias *cb_ias; 1670 struct fxp_txdesc *txd; 1671 bus_dmamap_t rxmap; 1672 int i, prm, save_bf, lrxen, vlan_drop, allm, error = 0; 1673 uint16_t status; 1674 1675 if ((error = fxp_enable(sc)) != 0) 1676 goto out; 1677 1678 /* 1679 * Cancel any pending I/O 1680 */ 1681 fxp_stop(ifp, 0); 1682 1683 /* 1684 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1685 * flag, and this prevents the MII from detaching resulting in 1686 * a panic. The flags field should perhaps be split in runtime 1687 * flags and more static information. For now, just clear the 1688 * only other flag set. 1689 */ 1690 1691 sc->sc_flags &= ~FXPF_WANTINIT; 1692 1693 /* 1694 * Initialize base of CBL and RFA memory. Loading with zero 1695 * sets it up for regular linear addressing. 1696 */ 1697 fxp_scb_wait(sc); 1698 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1699 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1700 1701 fxp_scb_wait(sc); 1702 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1703 1704 /* 1705 * Initialize the multicast filter. Do this now, since we might 1706 * have to setup the config block differently. 1707 */ 1708 fxp_mc_setup(sc); 1709 1710 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1711 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1712 1713 /* 1714 * In order to support receiving 802.1Q VLAN frames, we have to 1715 * enable "save bad frames", since they are 4 bytes larger than 1716 * the normal Ethernet maximum frame length. On i82558 and later, 1717 * we have a better mechanism for this. 1718 */ 1719 save_bf = 0; 1720 lrxen = 0; 1721 vlan_drop = 0; 1722 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1723 if (sc->sc_rev < FXP_REV_82558_A4) 1724 save_bf = 1; 1725 else 1726 lrxen = 1; 1727 if (sc->sc_rev >= FXP_REV_82550) 1728 vlan_drop = 1; 1729 } 1730 1731 /* 1732 * Initialize base of dump-stats buffer. 1733 */ 1734 fxp_scb_wait(sc); 1735 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1736 sc->sc_cddma + FXP_CDSTATSOFF); 1737 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1738 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1739 1740 cbp = &sc->sc_control_data->fcd_configcb; 1741 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1742 1743 /* 1744 * Load microcode for this controller. 1745 */ 1746 fxp_load_ucode(sc); 1747 1748 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK1)) 1749 sc->sc_flags |= FXPF_RECV_WORKAROUND; 1750 else 1751 sc->sc_flags &= ~FXPF_RECV_WORKAROUND; 1752 1753 /* 1754 * This copy is kind of disgusting, but there are a bunch of must be 1755 * zero and must be one bits in this structure and this is the easiest 1756 * way to initialize them all to proper values. 1757 */ 1758 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1759 1760 /* BIG_ENDIAN: no need to swap to store 0 */ 1761 cbp->cb_status = 0; 1762 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1763 FXP_CB_COMMAND_EL); 1764 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1765 cbp->link_addr = 0xffffffff; /* (no) next command */ 1766 /* bytes in config block */ 1767 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1768 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1769 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1770 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1771 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1772 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1773 cbp->type_enable = 0; /* actually reserved */ 1774 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1775 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1776 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1777 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1778 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1779 cbp->late_scb = 0; /* (don't) defer SCB update */ 1780 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1781 cbp->ci_int = 1; /* interrupt on CU idle */ 1782 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1783 cbp->ext_stats_dis = 1; /* disable extended counters */ 1784 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1785 cbp->save_bf = save_bf;/* save bad frames */ 1786 cbp->disc_short_rx = !prm; /* discard short packets */ 1787 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1788 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1789 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1790 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1791 /* interface mode */ 1792 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1793 cbp->csma_dis = 0; /* (don't) disable link */ 1794 cbp->tcp_udp_cksum = (sc->sc_flags & FXPF_82559_RXCSUM) ? 1 : 0; 1795 /* (don't) enable RX checksum */ 1796 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1797 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1798 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1799 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1800 cbp->nsai = 1; /* (don't) disable source addr insert */ 1801 cbp->preamble_length = 2; /* (7 byte) preamble */ 1802 cbp->loopback = 0; /* (don't) loopback */ 1803 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1804 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1805 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1806 cbp->promiscuous = prm; /* promiscuous mode */ 1807 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1808 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1809 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1810 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1811 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1812 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1813 cbp->padding = 1; /* (do) pad short tx packets */ 1814 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1815 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1816 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1817 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1818 /* must set wake_en in PMCSR also */ 1819 cbp->force_fdx = 0; /* (don't) force full duplex */ 1820 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1821 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1822 cbp->mc_all = allm; /* accept all multicasts */ 1823 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1824 cbp->vlan_drop_en = vlan_drop; 1825 1826 if (!(sc->sc_flags & FXPF_FC)) { 1827 /* 1828 * The i82557 has no hardware flow control, the values 1829 * here are the defaults for the chip. 1830 */ 1831 cbp->fc_delay_lsb = 0; 1832 cbp->fc_delay_msb = 0x40; 1833 cbp->pri_fc_thresh = 3; 1834 cbp->tx_fc_dis = 0; 1835 cbp->rx_fc_restop = 0; 1836 cbp->rx_fc_restart = 0; 1837 cbp->fc_filter = 0; 1838 cbp->pri_fc_loc = 1; 1839 } else { 1840 cbp->fc_delay_lsb = 0x1f; 1841 cbp->fc_delay_msb = 0x01; 1842 cbp->pri_fc_thresh = 3; 1843 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1844 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1845 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1846 cbp->fc_filter = !prm; /* drop FC frames to host */ 1847 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1848 cbp->ext_stats_dis = 0; /* enable extended stats */ 1849 } 1850 1851 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1852 1853 /* 1854 * Start the config command/DMA. 1855 */ 1856 fxp_scb_wait(sc); 1857 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1858 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1859 /* ...and wait for it to complete. */ 1860 for (i = 1000; i > 0; i--) { 1861 FXP_CDCONFIGSYNC(sc, 1862 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1863 status = le16toh(cbp->cb_status); 1864 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD); 1865 if ((status & FXP_CB_STATUS_C) != 0) 1866 break; 1867 DELAY(1); 1868 } 1869 if (i == 0) { 1870 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1871 device_xname(sc->sc_dev), __LINE__); 1872 return (ETIMEDOUT); 1873 } 1874 1875 /* 1876 * Initialize the station address. 1877 */ 1878 cb_ias = &sc->sc_control_data->fcd_iascb; 1879 /* BIG_ENDIAN: no need to swap to store 0 */ 1880 cb_ias->cb_status = 0; 1881 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1882 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1883 cb_ias->link_addr = 0xffffffff; 1884 memcpy(cb_ias->macaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1885 1886 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1887 1888 /* 1889 * Start the IAS (Individual Address Setup) command/DMA. 1890 */ 1891 fxp_scb_wait(sc); 1892 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1893 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1894 /* ...and wait for it to complete. */ 1895 for (i = 1000; i > 0; i--) { 1896 FXP_CDIASSYNC(sc, 1897 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1898 status = le16toh(cb_ias->cb_status); 1899 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD); 1900 if ((status & FXP_CB_STATUS_C) != 0) 1901 break; 1902 DELAY(1); 1903 } 1904 if (i == 0) { 1905 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 1906 device_xname(sc->sc_dev), __LINE__); 1907 return (ETIMEDOUT); 1908 } 1909 1910 /* 1911 * Initialize the transmit descriptor ring. txlast is initialized 1912 * to the end of the list so that it will wrap around to the first 1913 * descriptor when the first packet is transmitted. 1914 */ 1915 for (i = 0; i < FXP_NTXCB; i++) { 1916 txd = FXP_CDTX(sc, i); 1917 memset(txd, 0, sizeof(*txd)); 1918 txd->txd_txcb.cb_command = 1919 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1920 txd->txd_txcb.link_addr = 1921 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1922 if (sc->sc_flags & FXPF_EXT_TXCB) 1923 txd->txd_txcb.tbd_array_addr = 1924 htole32(FXP_CDTBDADDR(sc, i) + 1925 (2 * sizeof(struct fxp_tbd))); 1926 else 1927 txd->txd_txcb.tbd_array_addr = 1928 htole32(FXP_CDTBDADDR(sc, i)); 1929 FXP_CDTXSYNC(sc, i, 1930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1931 } 1932 sc->sc_txpending = 0; 1933 sc->sc_txdirty = 0; 1934 sc->sc_txlast = FXP_NTXCB - 1; 1935 1936 /* 1937 * Initialize the receive buffer list. 1938 */ 1939 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1940 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1941 rxmap = FXP_RXMAP_GET(sc); 1942 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1943 log(LOG_ERR, "%s: unable to allocate or map rx " 1944 "buffer %d, error = %d\n", 1945 device_xname(sc->sc_dev), 1946 sc->sc_rxq.ifq_len, error); 1947 /* 1948 * XXX Should attempt to run with fewer receive 1949 * XXX buffers instead of just failing. 1950 */ 1951 FXP_RXMAP_PUT(sc, rxmap); 1952 fxp_rxdrain(sc); 1953 goto out; 1954 } 1955 } 1956 sc->sc_rxidle = 0; 1957 1958 /* 1959 * Give the transmit ring to the chip. We do this by pointing 1960 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1961 * issuing a start command. It will execute the NOP and then 1962 * suspend, pointing at the first descriptor. 1963 */ 1964 fxp_scb_wait(sc); 1965 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1966 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1967 1968 /* 1969 * Initialize receiver buffer area - RFA. 1970 */ 1971 #if 0 /* initialization will be done by FXP_SCB_INTRCNTL_REQUEST_SWI later */ 1972 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1973 fxp_scb_wait(sc); 1974 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1975 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1976 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1977 #endif 1978 1979 if (sc->sc_flags & FXPF_MII) { 1980 /* 1981 * Set current media. 1982 */ 1983 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1984 goto out; 1985 } 1986 1987 /* 1988 * ...all done! 1989 */ 1990 ifp->if_flags |= IFF_RUNNING; 1991 ifp->if_flags &= ~IFF_OACTIVE; 1992 1993 /* 1994 * Request a software generated interrupt that will be used to 1995 * (re)start the RU processing. If we direct the chip to start 1996 * receiving from the start of queue now, instead of letting the 1997 * interrupt handler first process all received packets, we run 1998 * the risk of having it overwrite mbuf clusters while they are 1999 * being processed or after they have been returned to the pool. 2000 */ 2001 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTRCNTL_REQUEST_SWI); 2002 2003 /* 2004 * Start the one second timer. 2005 */ 2006 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 2007 2008 /* 2009 * Attempt to start output on the interface. 2010 */ 2011 fxp_start(ifp); 2012 2013 out: 2014 if (error) { 2015 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2016 ifp->if_timer = 0; 2017 log(LOG_ERR, "%s: interface not running\n", 2018 device_xname(sc->sc_dev)); 2019 } 2020 return (error); 2021 } 2022 2023 /* 2024 * Notify the world which media we're using. 2025 */ 2026 void 2027 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2028 { 2029 struct fxp_softc *sc = ifp->if_softc; 2030 2031 if (sc->sc_enabled == 0) { 2032 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 2033 ifmr->ifm_status = 0; 2034 return; 2035 } 2036 2037 ether_mediastatus(ifp, ifmr); 2038 } 2039 2040 int 2041 fxp_80c24_mediachange(struct ifnet *ifp) 2042 { 2043 2044 /* Nothing to do here. */ 2045 return (0); 2046 } 2047 2048 void 2049 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2050 { 2051 struct fxp_softc *sc = ifp->if_softc; 2052 2053 /* 2054 * Media is currently-selected media. We cannot determine 2055 * the link status. 2056 */ 2057 ifmr->ifm_status = 0; 2058 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 2059 } 2060 2061 /* 2062 * Add a buffer to the end of the RFA buffer list. 2063 * Return 0 if successful, error code on failure. 2064 * 2065 * The RFA struct is stuck at the beginning of mbuf cluster and the 2066 * data pointer is fixed up to point just past it. 2067 */ 2068 int 2069 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 2070 { 2071 struct mbuf *m; 2072 int error; 2073 2074 MGETHDR(m, M_DONTWAIT, MT_DATA); 2075 if (m == NULL) 2076 return (ENOBUFS); 2077 2078 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2079 MCLGET(m, M_DONTWAIT); 2080 if ((m->m_flags & M_EXT) == 0) { 2081 m_freem(m); 2082 return (ENOBUFS); 2083 } 2084 2085 if (unload) 2086 bus_dmamap_unload(sc->sc_dmat, rxmap); 2087 2088 M_SETCTX(m, rxmap); 2089 2090 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 2091 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 2092 BUS_DMA_READ | BUS_DMA_NOWAIT); 2093 if (error) { 2094 /* XXX XXX XXX */ 2095 aprint_error_dev(sc->sc_dev, 2096 "can't load rx DMA map %d, error = %d\n", 2097 sc->sc_rxq.ifq_len, error); 2098 panic("fxp_add_rfabuf"); 2099 } 2100 2101 FXP_INIT_RFABUF(sc, m); 2102 2103 return (0); 2104 } 2105 2106 int 2107 fxp_mdi_read(device_t self, int phy, int reg, uint16_t *value) 2108 { 2109 struct fxp_softc *sc = device_private(self); 2110 int count = 10000; 2111 uint32_t data; 2112 2113 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2114 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 2115 2116 while (((data = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 2117 0x10000000) == 0 && count--) 2118 DELAY(10); 2119 2120 if (count <= 0) { 2121 log(LOG_WARNING, 2122 "%s: fxp_mdi_read: timed out\n", device_xname(self)); 2123 return ETIMEDOUT; 2124 } 2125 2126 *value = data & 0xffff; 2127 return 0; 2128 } 2129 2130 void 2131 fxp_statchg(struct ifnet *ifp) 2132 { 2133 2134 /* Nothing to do. */ 2135 } 2136 2137 int 2138 fxp_mdi_write(device_t self, int phy, int reg, uint16_t value) 2139 { 2140 struct fxp_softc *sc = device_private(self); 2141 int count = 10000; 2142 2143 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2144 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | value); 2145 2146 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2147 count--) 2148 DELAY(10); 2149 2150 if (count <= 0) { 2151 log(LOG_WARNING, 2152 "%s: fxp_mdi_write: timed out\n", device_xname(self)); 2153 return ETIMEDOUT; 2154 } 2155 2156 return 0; 2157 } 2158 2159 int 2160 fxp_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2161 { 2162 struct fxp_softc *sc = ifp->if_softc; 2163 int s, error; 2164 2165 s = splnet(); 2166 2167 switch (cmd) { 2168 default: 2169 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2170 break; 2171 2172 error = 0; 2173 2174 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2175 ; 2176 else if (ifp->if_flags & IFF_RUNNING) { 2177 /* 2178 * Multicast list has changed; set the 2179 * hardware filter accordingly. 2180 */ 2181 while (sc->sc_txpending) { 2182 sc->sc_flags |= FXPF_WANTINIT; 2183 tsleep(sc, PSOCK, "fxp_init", 0); 2184 } 2185 error = fxp_init(ifp); 2186 } 2187 break; 2188 } 2189 2190 /* Try to get more packets going. */ 2191 if (sc->sc_enabled) 2192 fxp_start(ifp); 2193 2194 splx(s); 2195 return (error); 2196 } 2197 2198 /* 2199 * Program the multicast filter. 2200 * 2201 * This function must be called at splnet(). 2202 */ 2203 void 2204 fxp_mc_setup(struct fxp_softc *sc) 2205 { 2206 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2207 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2208 struct ethercom *ec = &sc->sc_ethercom; 2209 struct ether_multi *enm; 2210 struct ether_multistep step; 2211 int count, nmcasts; 2212 uint16_t status; 2213 2214 #ifdef DIAGNOSTIC 2215 if (sc->sc_txpending) 2216 panic("fxp_mc_setup: pending transmissions"); 2217 #endif 2218 2219 2220 if (ifp->if_flags & IFF_PROMISC) { 2221 ifp->if_flags |= IFF_ALLMULTI; 2222 return; 2223 } else { 2224 ifp->if_flags &= ~IFF_ALLMULTI; 2225 } 2226 2227 /* 2228 * Initialize multicast setup descriptor. 2229 */ 2230 nmcasts = 0; 2231 ETHER_LOCK(ec); 2232 ETHER_FIRST_MULTI(step, ec, enm); 2233 while (enm != NULL) { 2234 /* 2235 * Check for too many multicast addresses or if we're 2236 * listening to a range. Either way, we simply have 2237 * to accept all multicasts. 2238 */ 2239 if (nmcasts >= MAXMCADDR || 2240 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2241 ETHER_ADDR_LEN) != 0) { 2242 /* 2243 * Callers of this function must do the 2244 * right thing with this. If we're called 2245 * from outside fxp_init(), the caller must 2246 * detect if the state if IFF_ALLMULTI changes. 2247 * If it does, the caller must then call 2248 * fxp_init(), since allmulti is handled by 2249 * the config block. 2250 */ 2251 ifp->if_flags |= IFF_ALLMULTI; 2252 ETHER_UNLOCK(ec); 2253 return; 2254 } 2255 memcpy(&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2256 ETHER_ADDR_LEN); 2257 nmcasts++; 2258 ETHER_NEXT_MULTI(step, enm); 2259 } 2260 ETHER_UNLOCK(ec); 2261 2262 /* BIG_ENDIAN: no need to swap to store 0 */ 2263 mcsp->cb_status = 0; 2264 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2265 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2266 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2267 2268 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2269 2270 /* 2271 * Wait until the command unit is not active. This should never 2272 * happen since nothing is queued, but make sure anyway. 2273 */ 2274 count = 100; 2275 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2276 FXP_SCB_CUS_ACTIVE && --count) 2277 DELAY(1); 2278 if (count == 0) { 2279 log(LOG_WARNING, "%s: line %d: command queue timeout\n", 2280 device_xname(sc->sc_dev), __LINE__); 2281 return; 2282 } 2283 2284 /* 2285 * Start the multicast setup command/DMA. 2286 */ 2287 fxp_scb_wait(sc); 2288 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2289 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2290 2291 /* ...and wait for it to complete. */ 2292 for (count = 1000; count > 0; count--) { 2293 FXP_CDMCSSYNC(sc, 2294 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2295 status = le16toh(mcsp->cb_status); 2296 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD); 2297 if ((status & FXP_CB_STATUS_C) != 0) 2298 break; 2299 DELAY(1); 2300 } 2301 if (count == 0) { 2302 log(LOG_WARNING, "%s: line %d: dmasync timeout\n", 2303 device_xname(sc->sc_dev), __LINE__); 2304 return; 2305 } 2306 } 2307 2308 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2309 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2310 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2311 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2312 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2313 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2314 static const uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE; 2315 2316 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t) 2317 2318 static const struct ucode { 2319 int32_t revision; 2320 const uint32_t *ucode; 2321 size_t length; 2322 uint16_t int_delay_offset; 2323 uint16_t bundle_max_offset; 2324 } ucode_table[] = { 2325 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2326 D101_CPUSAVER_DWORD, 0 }, 2327 2328 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2329 D101_CPUSAVER_DWORD, 0 }, 2330 2331 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2332 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2333 2334 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2335 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2336 2337 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2338 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2339 2340 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2341 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2342 2343 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e), 2344 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2345 2346 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e), 2347 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD }, 2348 2349 { 0, NULL, 0, 0, 0 } 2350 }; 2351 2352 void 2353 fxp_load_ucode(struct fxp_softc *sc) 2354 { 2355 const struct ucode *uc; 2356 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2357 int count, i; 2358 uint16_t status; 2359 2360 if (sc->sc_flags & FXPF_UCODE_LOADED) 2361 return; 2362 2363 /* 2364 * Only load the uCode if the user has requested that 2365 * we do so. 2366 */ 2367 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2368 sc->sc_int_delay = 0; 2369 sc->sc_bundle_max = 0; 2370 return; 2371 } 2372 2373 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2374 if (sc->sc_rev == uc->revision) 2375 break; 2376 } 2377 if (uc->ucode == NULL) 2378 return; 2379 2380 /* BIG ENDIAN: no need to swap to store 0 */ 2381 cbp->cb_status = 0; 2382 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2383 cbp->link_addr = 0xffffffff; /* (no) next command */ 2384 for (i = 0; i < uc->length; i++) 2385 cbp->ucode[i] = htole32(uc->ucode[i]); 2386 2387 if (uc->int_delay_offset) 2388 *(volatile uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2389 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2390 2391 if (uc->bundle_max_offset) 2392 *(volatile uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2393 htole16(fxp_bundle_max); 2394 2395 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2396 2397 /* 2398 * Download the uCode to the chip. 2399 */ 2400 fxp_scb_wait(sc); 2401 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2402 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2403 2404 /* ...and wait for it to complete. */ 2405 for (count = 10000; count > 0; count--) { 2406 FXP_CDUCODESYNC(sc, 2407 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2408 status = le16toh(cbp->cb_status); 2409 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD); 2410 if ((status & FXP_CB_STATUS_C) != 0) 2411 break; 2412 DELAY(2); 2413 } 2414 if (count == 0) { 2415 sc->sc_int_delay = 0; 2416 sc->sc_bundle_max = 0; 2417 log(LOG_WARNING, "%s: timeout loading microcode\n", 2418 device_xname(sc->sc_dev)); 2419 return; 2420 } 2421 2422 if (sc->sc_int_delay != fxp_int_delay || 2423 sc->sc_bundle_max != fxp_bundle_max) { 2424 sc->sc_int_delay = fxp_int_delay; 2425 sc->sc_bundle_max = fxp_bundle_max; 2426 log(LOG_INFO, "%s: Microcode loaded: int delay: %d usec, " 2427 "max bundle: %d\n", device_xname(sc->sc_dev), 2428 sc->sc_int_delay, 2429 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2430 } 2431 2432 sc->sc_flags |= FXPF_UCODE_LOADED; 2433 } 2434 2435 int 2436 fxp_enable(struct fxp_softc *sc) 2437 { 2438 2439 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2440 if ((*sc->sc_enable)(sc) != 0) { 2441 log(LOG_ERR, "%s: device enable failed\n", 2442 device_xname(sc->sc_dev)); 2443 return (EIO); 2444 } 2445 } 2446 2447 sc->sc_enabled = 1; 2448 return (0); 2449 } 2450 2451 void 2452 fxp_disable(struct fxp_softc *sc) 2453 { 2454 2455 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2456 (*sc->sc_disable)(sc); 2457 sc->sc_enabled = 0; 2458 } 2459 } 2460 2461 /* 2462 * fxp_activate: 2463 * 2464 * Handle device activation/deactivation requests. 2465 */ 2466 int 2467 fxp_activate(device_t self, enum devact act) 2468 { 2469 struct fxp_softc *sc = device_private(self); 2470 2471 switch (act) { 2472 case DVACT_DEACTIVATE: 2473 if_deactivate(&sc->sc_ethercom.ec_if); 2474 return 0; 2475 default: 2476 return EOPNOTSUPP; 2477 } 2478 } 2479 2480 /* 2481 * fxp_detach: 2482 * 2483 * Detach an i82557 interface. 2484 */ 2485 int 2486 fxp_detach(struct fxp_softc *sc, int flags) 2487 { 2488 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2489 int i, s; 2490 2491 /* Succeed now if there's no work to do. */ 2492 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2493 return (0); 2494 2495 s = splnet(); 2496 /* Stop the interface. Callouts are stopped in it. */ 2497 fxp_stop(ifp, 1); 2498 splx(s); 2499 2500 /* Destroy our callout. */ 2501 callout_destroy(&sc->sc_callout); 2502 2503 if (sc->sc_flags & FXPF_MII) { 2504 /* Detach all PHYs */ 2505 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2506 } 2507 2508 /* Delete all remaining media. */ 2509 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2510 2511 rnd_detach_source(&sc->rnd_source); 2512 ether_ifdetach(ifp); 2513 if_detach(ifp); 2514 2515 for (i = 0; i < FXP_NRFABUFS; i++) { 2516 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2517 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2518 } 2519 2520 for (i = 0; i < FXP_NTXCB; i++) { 2521 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2522 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2523 } 2524 2525 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2526 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2527 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 2528 sizeof(struct fxp_control_data)); 2529 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2530 2531 return (0); 2532 } 2533
Indexes created Thu Sep 25 16:09:42 GMT 2025