i82557.c revision 1.18
1 /* $NetBSD: i82557.c,v 1.18 2000/02/09 22:15:57 joda Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 89 #include <machine/endian.h> 90 91 #include <vm/vm.h> /* for PAGE_SIZE */ 92 93 #if NRND > 0 94 #include <sys/rnd.h> 95 #endif 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #if NBPFILTER > 0 103 #include <net/bpf.h> 104 #endif 105 106 #ifdef INET 107 #include <netinet/in.h> 108 #include <netinet/if_inarp.h> 109 #endif 110 111 #ifdef NS 112 #include <netns/ns.h> 113 #include <netns/ns_if.h> 114 #endif 115 116 #include <machine/bus.h> 117 #include <machine/intr.h> 118 119 #include <dev/mii/miivar.h> 120 121 #include <dev/ic/i82557reg.h> 122 #include <dev/ic/i82557var.h> 123 124 /* 125 * NOTE! On the Alpha, we have an alignment constraint. The 126 * card DMAs the packet immediately following the RFA. However, 127 * the first thing in the packet is a 14-byte Ethernet header. 128 * This means that the packet is misaligned. To compensate, 129 * we actually offset the RFA 2 bytes into the cluster. This 130 * alignes the packet after the Ethernet header at a 32-bit 131 * boundary. HOWEVER! This means that the RFA is misaligned! 132 */ 133 #define RFA_ALIGNMENT_FUDGE 2 134 135 /* 136 * Template for default configuration parameters. 137 * See struct fxp_cb_config for the bit definitions. 138 */ 139 u_int8_t fxp_cb_config_template[] = { 140 0x0, 0x0, /* cb_status */ 141 0x80, 0x2, /* cb_command */ 142 0xff, 0xff, 0xff, 0xff, /* link_addr */ 143 0x16, /* 0 */ 144 0x8, /* 1 */ 145 0x0, /* 2 */ 146 0x0, /* 3 */ 147 0x0, /* 4 */ 148 0x80, /* 5 */ 149 0xb2, /* 6 */ 150 0x3, /* 7 */ 151 0x1, /* 8 */ 152 0x0, /* 9 */ 153 0x26, /* 10 */ 154 0x0, /* 11 */ 155 0x60, /* 12 */ 156 0x0, /* 13 */ 157 0xf2, /* 14 */ 158 0x48, /* 15 */ 159 0x0, /* 16 */ 160 0x40, /* 17 */ 161 0xf3, /* 18 */ 162 0x0, /* 19 */ 163 0x3f, /* 20 */ 164 0x5 /* 21 */ 165 }; 166 167 void fxp_mii_initmedia __P((struct fxp_softc *)); 168 int fxp_mii_mediachange __P((struct ifnet *)); 169 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 170 171 void fxp_80c24_initmedia __P((struct fxp_softc *)); 172 int fxp_80c24_mediachange __P((struct ifnet *)); 173 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 174 175 inline void fxp_scb_wait __P((struct fxp_softc *)); 176 177 void fxp_start __P((struct ifnet *)); 178 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 179 int fxp_init __P((struct fxp_softc *)); 180 void fxp_rxdrain __P((struct fxp_softc *)); 181 void fxp_stop __P((struct fxp_softc *, int)); 182 void fxp_watchdog __P((struct ifnet *)); 183 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 184 int fxp_mdi_read __P((struct device *, int, int)); 185 void fxp_statchg __P((struct device *)); 186 void fxp_mdi_write __P((struct device *, int, int, int)); 187 void fxp_autosize_eeprom __P((struct fxp_softc*)); 188 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 189 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 190 void fxp_tick __P((void *)); 191 void fxp_mc_setup __P((struct fxp_softc *)); 192 193 void fxp_shutdown __P((void *)); 194 void fxp_power __P((int, void *)); 195 196 int fxp_copy_small = 0; 197 198 int fxp_enable __P((struct fxp_softc*)); 199 void fxp_disable __P((struct fxp_softc*)); 200 201 struct fxp_phytype { 202 int fp_phy; /* type of PHY, -1 for MII at the end. */ 203 void (*fp_init) __P((struct fxp_softc *)); 204 } fxp_phytype_table[] = { 205 { FXP_PHY_80C24, fxp_80c24_initmedia }, 206 { -1, fxp_mii_initmedia }, 207 }; 208 209 /* 210 * Set initial transmit threshold at 64 (512 bytes). This is 211 * increased by 64 (512 bytes) at a time, to maximum of 192 212 * (1536 bytes), if an underrun occurs. 213 */ 214 static int tx_threshold = 64; 215 216 /* 217 * Wait for the previous command to be accepted (but not necessarily 218 * completed). 219 */ 220 inline void 221 fxp_scb_wait(sc) 222 struct fxp_softc *sc; 223 { 224 int i = 10000; 225 226 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 227 delay(2); 228 if (i == 0) 229 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 230 } 231 232 /* 233 * Finish attaching an i82557 interface. Called by bus-specific front-end. 234 */ 235 void 236 fxp_attach(sc) 237 struct fxp_softc *sc; 238 { 239 u_int8_t enaddr[6]; 240 struct ifnet *ifp; 241 bus_dma_segment_t seg; 242 int rseg, i, error; 243 struct fxp_phytype *fp; 244 245 /* 246 * Allocate the control data structures, and create and load the 247 * DMA map for it. 248 */ 249 if ((error = bus_dmamem_alloc(sc->sc_dmat, 250 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 251 0)) != 0) { 252 printf("%s: unable to allocate control data, error = %d\n", 253 sc->sc_dev.dv_xname, error); 254 goto fail_0; 255 } 256 257 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 258 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 259 BUS_DMA_COHERENT)) != 0) { 260 printf("%s: unable to map control data, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 goto fail_1; 263 } 264 sc->sc_cdseg = seg; 265 sc->sc_cdnseg = rseg; 266 267 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 268 269 if ((error = bus_dmamap_create(sc->sc_dmat, 270 sizeof(struct fxp_control_data), 1, 271 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 272 printf("%s: unable to create control data DMA map, " 273 "error = %d\n", sc->sc_dev.dv_xname, error); 274 goto fail_2; 275 } 276 277 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 278 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 279 0)) != 0) { 280 printf("%s: can't load control data DMA map, error = %d\n", 281 sc->sc_dev.dv_xname, error); 282 goto fail_3; 283 } 284 285 /* 286 * Create the transmit buffer DMA maps. 287 */ 288 for (i = 0; i < FXP_NTXCB; i++) { 289 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 290 FXP_NTXSEG, MCLBYTES, 0, 0, 291 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 292 printf("%s: unable to create tx DMA map %d, " 293 "error = %d\n", sc->sc_dev.dv_xname, i, error); 294 goto fail_4; 295 } 296 } 297 298 /* 299 * Create the receive buffer DMA maps. 300 */ 301 for (i = 0; i < FXP_NRFABUFS; i++) { 302 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 303 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 304 printf("%s: unable to create rx DMA map %d, " 305 "error = %d\n", sc->sc_dev.dv_xname, i, error); 306 goto fail_5; 307 } 308 } 309 310 /* Initialize MAC address and media structures. */ 311 fxp_get_info(sc, enaddr); 312 313 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 314 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 315 316 ifp = &sc->sc_ethercom.ec_if; 317 318 /* 319 * Get info about our media interface, and initialize it. Note 320 * the table terminates itself with a phy of -1, indicating 321 * that we're using MII. 322 */ 323 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 324 if (fp->fp_phy == sc->phy_primary_device) 325 break; 326 (*fp->fp_init)(sc); 327 328 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 329 ifp->if_softc = sc; 330 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 331 ifp->if_ioctl = fxp_ioctl; 332 ifp->if_start = fxp_start; 333 ifp->if_watchdog = fxp_watchdog; 334 335 /* 336 * Attach the interface. 337 */ 338 if_attach(ifp); 339 ether_ifattach(ifp, enaddr); 340 #if NBPFILTER > 0 341 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 342 sizeof(struct ether_header)); 343 #endif 344 #if NRND > 0 345 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 346 RND_TYPE_NET, 0); 347 #endif 348 349 /* 350 * Add shutdown hook so that DMA is disabled prior to reboot. Not 351 * doing do could allow DMA to corrupt kernel memory during the 352 * reboot before the driver initializes. 353 */ 354 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 355 if (sc->sc_sdhook == NULL) 356 printf("%s: WARNING: unable to establish shutdown hook\n", 357 sc->sc_dev.dv_xname); 358 /* 359 * Add suspend hook, for similar reasons.. 360 */ 361 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 362 if (sc->sc_powerhook == NULL) 363 printf("%s: WARNING: unable to establish power hook\n", 364 sc->sc_dev.dv_xname); 365 return; 366 367 /* 368 * Free any resources we've allocated during the failed attach 369 * attempt. Do this in reverse order and fall though. 370 */ 371 fail_5: 372 for (i = 0; i < FXP_NRFABUFS; i++) { 373 if (sc->sc_rxmaps[i] != NULL) 374 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 375 } 376 fail_4: 377 for (i = 0; i < FXP_NTXCB; i++) { 378 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 379 bus_dmamap_destroy(sc->sc_dmat, 380 FXP_DSTX(sc, i)->txs_dmamap); 381 } 382 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 383 fail_3: 384 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 385 fail_2: 386 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 387 sizeof(struct fxp_control_data)); 388 fail_1: 389 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 390 fail_0: 391 return; 392 } 393 394 void 395 fxp_mii_initmedia(sc) 396 struct fxp_softc *sc; 397 { 398 399 sc->sc_flags |= FXPF_MII; 400 401 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 402 sc->sc_mii.mii_readreg = fxp_mdi_read; 403 sc->sc_mii.mii_writereg = fxp_mdi_write; 404 sc->sc_mii.mii_statchg = fxp_statchg; 405 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 406 fxp_mii_mediastatus); 407 /* 408 * The i82557 wedges if all of its PHYs are isolated! 409 */ 410 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 411 MII_OFFSET_ANY, MIIF_NOISOLATE); 412 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 413 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 414 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 415 } else 416 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 417 } 418 419 void 420 fxp_80c24_initmedia(sc) 421 struct fxp_softc *sc; 422 { 423 424 /* 425 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 426 * doesn't have a programming interface of any sort. The 427 * media is sensed automatically based on how the link partner 428 * is configured. This is, in essence, manual configuration. 429 */ 430 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 431 sc->sc_dev.dv_xname); 432 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 433 fxp_80c24_mediastatus); 434 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 435 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 436 } 437 438 /* 439 * Device shutdown routine. Called at system shutdown after sync. The 440 * main purpose of this routine is to shut off receiver DMA so that 441 * kernel memory doesn't get clobbered during warmboot. 442 */ 443 void 444 fxp_shutdown(arg) 445 void *arg; 446 { 447 struct fxp_softc *sc = arg; 448 449 /* 450 * Since the system's going to halt shortly, don't bother 451 * freeing mbufs. 452 */ 453 fxp_stop(sc, 0); 454 } 455 /* 456 * Power handler routine. Called when the system is transitioning 457 * into/out of power save modes. As with fxp_shutdown, the main 458 * purpose of this routine is to shut off receiver DMA so it doesn't 459 * clobber kernel memory at the wrong time. 460 */ 461 void 462 fxp_power(why, arg) 463 int why; 464 void *arg; 465 { 466 struct fxp_softc *sc = arg; 467 struct ifnet *ifp; 468 int s; 469 470 s = splnet(); 471 if (why != PWR_RESUME) 472 fxp_stop(sc, 0); 473 else { 474 ifp = &sc->sc_ethercom.ec_if; 475 if (ifp->if_flags & IFF_UP) 476 fxp_init(sc); 477 } 478 splx(s); 479 } 480 481 /* 482 * Initialize the interface media. 483 */ 484 void 485 fxp_get_info(sc, enaddr) 486 struct fxp_softc *sc; 487 u_int8_t *enaddr; 488 { 489 u_int16_t data, myea[3]; 490 491 /* 492 * Reset to a stable state. 493 */ 494 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 495 DELAY(10); 496 497 sc->sc_eeprom_size = 0; 498 fxp_autosize_eeprom(sc); 499 if(sc->sc_eeprom_size == 0) { 500 printf("%s: failed to detect EEPROM size", sc->sc_dev.dv_xname); 501 sc->sc_eeprom_size = 6; /* XXX panic here? */ 502 } 503 #ifdef DEBUG 504 printf("%s: detected %d word EEPROM\n", 505 sc->sc_dev.dv_xname, 506 1 << sc->sc_eeprom_size); 507 #endif 508 509 /* 510 * Get info about the primary PHY 511 */ 512 fxp_read_eeprom(sc, &data, 6, 1); 513 sc->phy_primary_addr = data & 0xff; 514 sc->phy_primary_device = (data >> 8) & 0x3f; 515 sc->phy_10Mbps_only = data >> 15; 516 517 /* 518 * Read MAC address. 519 */ 520 fxp_read_eeprom(sc, myea, 0, 3); 521 bcopy(myea, enaddr, ETHER_ADDR_LEN); 522 } 523 524 /* 525 * Figure out EEPROM size. 526 * 527 * 559's can have either 64-word or 256-word EEPROMs, the 558 528 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 529 * talks about the existance of 16 to 256 word EEPROMs. 530 * 531 * The only known sizes are 64 and 256, where the 256 version is used 532 * by CardBus cards to store CIS information. 533 * 534 * The address is shifted in msb-to-lsb, and after the last 535 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 536 * after which follows the actual data. We try to detect this zero, by 537 * probing the data-out bit in the EEPROM control register just after 538 * having shifted in a bit. If the bit is zero, we assume we've 539 * shifted enough address bits. The data-out should be tri-state, 540 * before this, which should translate to a logical one. 541 * 542 * Other ways to do this would be to try to read a register with known 543 * contents with a varying number of address bits, but no such 544 * register seem to be available. The high bits of register 10 are 01 545 * on the 558 and 559, but apparently not on the 557. 546 * 547 * The Linux driver computes a checksum on the EEPROM data, but the 548 * value of this checksum is not very well documented. 549 */ 550 551 void 552 fxp_autosize_eeprom(sc) 553 struct fxp_softc *sc; 554 { 555 u_int16_t reg; 556 int x; 557 558 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 559 /* 560 * Shift in read opcode. 561 */ 562 for (x = 3; x > 0; x--) { 563 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 564 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 565 } else { 566 reg = FXP_EEPROM_EECS; 567 } 568 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 569 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 570 reg | FXP_EEPROM_EESK); 571 DELAY(1); 572 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 573 DELAY(1); 574 } 575 /* 576 * Shift in address, wait for the dummy zero following a correct 577 * address shift. 578 */ 579 for (x = 1; x <= 8; x++) { 580 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 581 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 582 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 583 DELAY(1); 584 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 585 FXP_EEPROM_EEDO) == 0) 586 break; 587 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 588 DELAY(1); 589 } 590 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 591 DELAY(1); 592 if(x != 6 && x != 8) { 593 #ifdef DEBUG 594 printf("%s: strange EEPROM size (%d)\n", 595 sc->sc_dev.dv_xname, 1 << x); 596 #endif 597 } else 598 sc->sc_eeprom_size = x; 599 } 600 601 /* 602 * Read from the serial EEPROM. Basically, you manually shift in 603 * the read opcode (one bit at a time) and then shift in the address, 604 * and then you shift out the data (all of this one bit at a time). 605 * The word size is 16 bits, so you have to provide the address for 606 * every 16 bits of data. 607 */ 608 void 609 fxp_read_eeprom(sc, data, offset, words) 610 struct fxp_softc *sc; 611 u_int16_t *data; 612 int offset; 613 int words; 614 { 615 u_int16_t reg; 616 int i, x; 617 618 for (i = 0; i < words; i++) { 619 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 620 /* 621 * Shift in read opcode. 622 */ 623 for (x = 3; x > 0; x--) { 624 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 625 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 626 } else { 627 reg = FXP_EEPROM_EECS; 628 } 629 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 630 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 631 reg | FXP_EEPROM_EESK); 632 DELAY(1); 633 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 634 DELAY(1); 635 } 636 /* 637 * Shift in address. 638 */ 639 for (x = sc->sc_eeprom_size; x > 0; x--) { 640 if ((i + offset) & (1 << (x - 1))) { 641 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 642 } else { 643 reg = FXP_EEPROM_EECS; 644 } 645 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 646 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 647 reg | FXP_EEPROM_EESK); 648 DELAY(1); 649 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 650 DELAY(1); 651 } 652 reg = FXP_EEPROM_EECS; 653 data[i] = 0; 654 /* 655 * Shift out data. 656 */ 657 for (x = 16; x > 0; x--) { 658 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 659 reg | FXP_EEPROM_EESK); 660 DELAY(1); 661 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 662 FXP_EEPROM_EEDO) 663 data[i] |= (1 << (x - 1)); 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 665 DELAY(1); 666 } 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 668 DELAY(1); 669 } 670 } 671 672 /* 673 * Start packet transmission on the interface. 674 */ 675 void 676 fxp_start(ifp) 677 struct ifnet *ifp; 678 { 679 struct fxp_softc *sc = ifp->if_softc; 680 struct mbuf *m0, *m; 681 struct fxp_cb_tx *txd; 682 struct fxp_txsoft *txs; 683 struct fxp_tbdlist *tbd; 684 bus_dmamap_t dmamap; 685 int error, lasttx, nexttx, opending, seg; 686 687 /* 688 * If we want a re-init, bail out now. 689 */ 690 if (sc->sc_flags & FXPF_WANTINIT) { 691 ifp->if_flags |= IFF_OACTIVE; 692 return; 693 } 694 695 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 696 return; 697 698 /* 699 * Remember the previous txpending and the current lasttx. 700 */ 701 opending = sc->sc_txpending; 702 lasttx = sc->sc_txlast; 703 704 /* 705 * Loop through the send queue, setting up transmit descriptors 706 * until we drain the queue, or use up all available transmit 707 * descriptors. 708 */ 709 while (sc->sc_txpending < FXP_NTXCB) { 710 /* 711 * Grab a packet off the queue. 712 */ 713 IF_DEQUEUE(&ifp->if_snd, m0); 714 if (m0 == NULL) 715 break; 716 717 /* 718 * Get the next available transmit descriptor. 719 */ 720 nexttx = FXP_NEXTTX(sc->sc_txlast); 721 txd = FXP_CDTX(sc, nexttx); 722 tbd = FXP_CDTBD(sc, nexttx); 723 txs = FXP_DSTX(sc, nexttx); 724 dmamap = txs->txs_dmamap; 725 726 /* 727 * Load the DMA map. If this fails, the packet either 728 * didn't fit in the allotted number of frags, or we were 729 * short on resources. In this case, we'll copy and try 730 * again. 731 */ 732 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 733 BUS_DMA_NOWAIT) != 0) { 734 MGETHDR(m, M_DONTWAIT, MT_DATA); 735 if (m == NULL) { 736 printf("%s: unable to allocate Tx mbuf\n", 737 sc->sc_dev.dv_xname); 738 IF_PREPEND(&ifp->if_snd, m0); 739 break; 740 } 741 if (m0->m_pkthdr.len > MHLEN) { 742 MCLGET(m, M_DONTWAIT); 743 if ((m->m_flags & M_EXT) == 0) { 744 printf("%s: unable to allocate Tx " 745 "cluster\n", sc->sc_dev.dv_xname); 746 m_freem(m); 747 IF_PREPEND(&ifp->if_snd, m0); 748 break; 749 } 750 } 751 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 752 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 753 m_freem(m0); 754 m0 = m; 755 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 756 m0, BUS_DMA_NOWAIT); 757 if (error) { 758 printf("%s: unable to load Tx buffer, " 759 "error = %d\n", sc->sc_dev.dv_xname, error); 760 IF_PREPEND(&ifp->if_snd, m0); 761 break; 762 } 763 } 764 765 /* Initialize the fraglist. */ 766 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 767 tbd->tbd_d[seg].tb_addr = 768 htole32(dmamap->dm_segs[seg].ds_addr); 769 tbd->tbd_d[seg].tb_size = 770 htole32(dmamap->dm_segs[seg].ds_len); 771 } 772 773 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 774 775 /* Sync the DMA map. */ 776 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 777 BUS_DMASYNC_PREWRITE); 778 779 /* 780 * Store a pointer to the packet so we can free it later. 781 */ 782 txs->txs_mbuf = m0; 783 784 /* 785 * Initialize the transmit descriptor. 786 */ 787 /* BIG_ENDIAN: no need to swap to store 0 */ 788 txd->cb_status = 0; 789 txd->cb_command = 790 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 791 txd->tx_threshold = tx_threshold; 792 txd->tbd_number = dmamap->dm_nsegs; 793 794 FXP_CDTXSYNC(sc, nexttx, 795 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 796 797 /* Advance the tx pointer. */ 798 sc->sc_txpending++; 799 sc->sc_txlast = nexttx; 800 801 #if NBPFILTER > 0 802 /* 803 * Pass packet to bpf if there is a listener. 804 */ 805 if (ifp->if_bpf) 806 bpf_mtap(ifp->if_bpf, m0); 807 #endif 808 } 809 810 if (sc->sc_txpending == FXP_NTXCB) { 811 /* No more slots; notify upper layer. */ 812 ifp->if_flags |= IFF_OACTIVE; 813 } 814 815 if (sc->sc_txpending != opending) { 816 /* 817 * We enqueued packets. If the transmitter was idle, 818 * reset the txdirty pointer. 819 */ 820 if (opending == 0) 821 sc->sc_txdirty = FXP_NEXTTX(lasttx); 822 823 /* 824 * Cause the chip to interrupt and suspend command 825 * processing once the last packet we've enqueued 826 * has been transmitted. 827 */ 828 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 829 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 830 FXP_CDTXSYNC(sc, sc->sc_txlast, 831 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 832 833 /* 834 * The entire packet chain is set up. Clear the suspend bit 835 * on the command prior to the first packet we set up. 836 */ 837 FXP_CDTXSYNC(sc, lasttx, 838 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 839 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 840 FXP_CDTXSYNC(sc, lasttx, 841 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 842 843 /* 844 * Issue a Resume command in case the chip was suspended. 845 */ 846 fxp_scb_wait(sc); 847 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 848 849 /* Set a watchdog timer in case the chip flakes out. */ 850 ifp->if_timer = 5; 851 } 852 } 853 854 /* 855 * Process interface interrupts. 856 */ 857 int 858 fxp_intr(arg) 859 void *arg; 860 { 861 struct fxp_softc *sc = arg; 862 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 863 struct fxp_cb_tx *txd; 864 struct fxp_txsoft *txs; 865 struct mbuf *m, *m0; 866 bus_dmamap_t rxmap; 867 struct fxp_rfa *rfa; 868 struct ether_header *eh; 869 int i, claimed = 0; 870 u_int16_t len, rxstat, txstat; 871 u_int8_t statack; 872 873 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 874 return 0; 875 /* 876 * If the interface isn't running, don't try to 877 * service the interrupt.. just ack it and bail. 878 */ 879 if ((ifp->if_flags & IFF_RUNNING) == 0) { 880 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 881 if (statack) { 882 claimed = 1; 883 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 884 } 885 return claimed; 886 } 887 888 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 889 claimed = 1; 890 891 /* 892 * First ACK all the interrupts in this pass. 893 */ 894 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 895 896 /* 897 * Process receiver interrupts. If a no-resource (RNR) 898 * condition exists, get whatever packets we can and 899 * re-start the receiver. 900 */ 901 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 902 rcvloop: 903 m = sc->sc_rxq.ifq_head; 904 rfa = FXP_MTORFA(m); 905 rxmap = M_GETCTX(m, bus_dmamap_t); 906 907 FXP_RFASYNC(sc, m, 908 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 909 910 rxstat = le16toh(rfa->rfa_status); 911 912 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 913 /* 914 * We have processed all of the 915 * receive buffers. 916 */ 917 goto do_transmit; 918 } 919 920 IF_DEQUEUE(&sc->sc_rxq, m); 921 922 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 923 924 len = le16toh(rfa->actual_size) & 925 (m->m_ext.ext_size - 1); 926 927 if (len < sizeof(struct ether_header)) { 928 /* 929 * Runt packet; drop it now. 930 */ 931 FXP_INIT_RFABUF(sc, m); 932 goto rcvloop; 933 } 934 935 /* 936 * If the packet is small enough to fit in a 937 * single header mbuf, allocate one and copy 938 * the data into it. This greatly reduces 939 * memory consumption when we receive lots 940 * of small packets. 941 * 942 * Otherwise, we add a new buffer to the receive 943 * chain. If this fails, we drop the packet and 944 * recycle the old buffer. 945 */ 946 if (fxp_copy_small != 0 && len <= MHLEN) { 947 MGETHDR(m0, M_DONTWAIT, MT_DATA); 948 if (m == NULL) 949 goto dropit; 950 memcpy(mtod(m0, caddr_t), 951 mtod(m, caddr_t), len); 952 FXP_INIT_RFABUF(sc, m); 953 m = m0; 954 } else { 955 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 956 dropit: 957 ifp->if_ierrors++; 958 FXP_INIT_RFABUF(sc, m); 959 goto rcvloop; 960 } 961 } 962 963 m->m_pkthdr.rcvif = ifp; 964 m->m_pkthdr.len = m->m_len = len; 965 eh = mtod(m, struct ether_header *); 966 967 #if NBPFILTER > 0 968 /* 969 * Pass this up to any BPF listeners, but only 970 * pass it up the stack it its for us. 971 */ 972 if (ifp->if_bpf) { 973 bpf_mtap(ifp->if_bpf, m); 974 975 if ((ifp->if_flags & IFF_PROMISC) != 0 && 976 (rxstat & FXP_RFA_STATUS_IAMATCH) != 0 && 977 (eh->ether_dhost[0] & 1) == 0) { 978 m_freem(m); 979 goto rcvloop; 980 } 981 } 982 #endif /* NBPFILTER > 0 */ 983 984 /* Pass it on. */ 985 (*ifp->if_input)(ifp, m); 986 goto rcvloop; 987 } 988 989 do_transmit: 990 if (statack & FXP_SCB_STATACK_RNR) { 991 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 992 fxp_scb_wait(sc); 993 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 994 rxmap->dm_segs[0].ds_addr + 995 RFA_ALIGNMENT_FUDGE); 996 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 997 FXP_SCB_COMMAND_RU_START); 998 } 999 1000 /* 1001 * Free any finished transmit mbuf chains. 1002 */ 1003 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1004 ifp->if_flags &= ~IFF_OACTIVE; 1005 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1006 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1007 txd = FXP_CDTX(sc, i); 1008 txs = FXP_DSTX(sc, i); 1009 1010 FXP_CDTXSYNC(sc, i, 1011 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1012 1013 txstat = le16toh(txd->cb_status); 1014 1015 if ((txstat & FXP_CB_STATUS_C) == 0) 1016 break; 1017 1018 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1019 1020 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1021 0, txs->txs_dmamap->dm_mapsize, 1022 BUS_DMASYNC_POSTWRITE); 1023 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1024 m_freem(txs->txs_mbuf); 1025 txs->txs_mbuf = NULL; 1026 } 1027 1028 /* Update the dirty transmit buffer pointer. */ 1029 sc->sc_txdirty = i; 1030 1031 /* 1032 * Cancel the watchdog timer if there are no pending 1033 * transmissions. 1034 */ 1035 if (sc->sc_txpending == 0) { 1036 ifp->if_timer = 0; 1037 1038 /* 1039 * If we want a re-init, do that now. 1040 */ 1041 if (sc->sc_flags & FXPF_WANTINIT) 1042 (void) fxp_init(sc); 1043 } 1044 1045 /* 1046 * Try to get more packets going. 1047 */ 1048 fxp_start(ifp); 1049 } 1050 } 1051 1052 #if NRND > 0 1053 if (claimed) 1054 rnd_add_uint32(&sc->rnd_source, statack); 1055 #endif 1056 return (claimed); 1057 } 1058 1059 /* 1060 * Update packet in/out/collision statistics. The i82557 doesn't 1061 * allow you to access these counters without doing a fairly 1062 * expensive DMA to get _all_ of the statistics it maintains, so 1063 * we do this operation here only once per second. The statistics 1064 * counters in the kernel are updated from the previous dump-stats 1065 * DMA and then a new dump-stats DMA is started. The on-chip 1066 * counters are zeroed when the DMA completes. If we can't start 1067 * the DMA immediately, we don't wait - we just prepare to read 1068 * them again next time. 1069 */ 1070 void 1071 fxp_tick(arg) 1072 void *arg; 1073 { 1074 struct fxp_softc *sc = arg; 1075 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1076 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1077 int s; 1078 1079 s = splnet(); 1080 1081 ifp->if_opackets += le32toh(sp->tx_good); 1082 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1083 if (sp->rx_good) { 1084 ifp->if_ipackets += le32toh(sp->rx_good); 1085 sc->sc_rxidle = 0; 1086 } else { 1087 sc->sc_rxidle++; 1088 } 1089 ifp->if_ierrors += 1090 le32toh(sp->rx_crc_errors) + 1091 le32toh(sp->rx_alignment_errors) + 1092 le32toh(sp->rx_rnr_errors) + 1093 le32toh(sp->rx_overrun_errors); 1094 /* 1095 * If any transmit underruns occured, bump up the transmit 1096 * threshold by another 512 bytes (64 * 8). 1097 */ 1098 if (sp->tx_underruns) { 1099 ifp->if_oerrors += le32toh(sp->tx_underruns); 1100 if (tx_threshold < 192) 1101 tx_threshold += 64; 1102 } 1103 1104 /* 1105 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1106 * then assume the receiver has locked up and attempt to clear 1107 * the condition by reprogramming the multicast filter (actually, 1108 * resetting the interface). This is a work-around for a bug in 1109 * the 82557 where the receiver locks up if it gets certain types 1110 * of garbage in the syncronization bits prior to the packet header. 1111 * This bug is supposed to only occur in 10Mbps mode, but has been 1112 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1113 * speed transition). 1114 */ 1115 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1116 (void) fxp_init(sc); 1117 splx(s); 1118 return; 1119 } 1120 /* 1121 * If there is no pending command, start another stats 1122 * dump. Otherwise punt for now. 1123 */ 1124 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1125 /* 1126 * Start another stats dump. 1127 */ 1128 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1129 FXP_SCB_COMMAND_CU_DUMPRESET); 1130 } else { 1131 /* 1132 * A previous command is still waiting to be accepted. 1133 * Just zero our copy of the stats and wait for the 1134 * next timer event to update them. 1135 */ 1136 /* BIG_ENDIAN: no swap required to store 0 */ 1137 sp->tx_good = 0; 1138 sp->tx_underruns = 0; 1139 sp->tx_total_collisions = 0; 1140 1141 sp->rx_good = 0; 1142 sp->rx_crc_errors = 0; 1143 sp->rx_alignment_errors = 0; 1144 sp->rx_rnr_errors = 0; 1145 sp->rx_overrun_errors = 0; 1146 } 1147 1148 if (sc->sc_flags & FXPF_MII) { 1149 /* Tick the MII clock. */ 1150 mii_tick(&sc->sc_mii); 1151 } 1152 1153 splx(s); 1154 1155 /* 1156 * Schedule another timeout one second from now. 1157 */ 1158 timeout(fxp_tick, sc, hz); 1159 } 1160 1161 /* 1162 * Drain the receive queue. 1163 */ 1164 void 1165 fxp_rxdrain(sc) 1166 struct fxp_softc *sc; 1167 { 1168 bus_dmamap_t rxmap; 1169 struct mbuf *m; 1170 1171 for (;;) { 1172 IF_DEQUEUE(&sc->sc_rxq, m); 1173 if (m == NULL) 1174 break; 1175 rxmap = M_GETCTX(m, bus_dmamap_t); 1176 bus_dmamap_unload(sc->sc_dmat, rxmap); 1177 FXP_RXMAP_PUT(sc, rxmap); 1178 m_freem(m); 1179 } 1180 } 1181 1182 /* 1183 * Stop the interface. Cancels the statistics updater and resets 1184 * the interface. 1185 */ 1186 void 1187 fxp_stop(sc, drain) 1188 struct fxp_softc *sc; 1189 int drain; 1190 { 1191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1192 struct fxp_txsoft *txs; 1193 int i; 1194 1195 /* 1196 * Turn down interface (done early to avoid bad interactions 1197 * between panics, shutdown hooks, and the watchdog timer) 1198 */ 1199 ifp->if_timer = 0; 1200 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1201 1202 /* 1203 * Cancel stats updater. 1204 */ 1205 untimeout(fxp_tick, sc); 1206 if (sc->sc_flags & FXPF_MII) { 1207 /* Down the MII. */ 1208 mii_down(&sc->sc_mii); 1209 } 1210 1211 /* 1212 * Issue software reset 1213 */ 1214 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1215 DELAY(10); 1216 1217 /* 1218 * Release any xmit buffers. 1219 */ 1220 for (i = 0; i < FXP_NTXCB; i++) { 1221 txs = FXP_DSTX(sc, i); 1222 if (txs->txs_mbuf != NULL) { 1223 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1224 m_freem(txs->txs_mbuf); 1225 txs->txs_mbuf = NULL; 1226 } 1227 } 1228 sc->sc_txpending = 0; 1229 1230 if (drain) { 1231 /* 1232 * Release the receive buffers. 1233 */ 1234 fxp_rxdrain(sc); 1235 } 1236 1237 } 1238 1239 /* 1240 * Watchdog/transmission transmit timeout handler. Called when a 1241 * transmission is started on the interface, but no interrupt is 1242 * received before the timeout. This usually indicates that the 1243 * card has wedged for some reason. 1244 */ 1245 void 1246 fxp_watchdog(ifp) 1247 struct ifnet *ifp; 1248 { 1249 struct fxp_softc *sc = ifp->if_softc; 1250 1251 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1252 ifp->if_oerrors++; 1253 1254 (void) fxp_init(sc); 1255 } 1256 1257 /* 1258 * Initialize the interface. Must be called at splnet(). 1259 */ 1260 int 1261 fxp_init(sc) 1262 struct fxp_softc *sc; 1263 { 1264 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1265 struct fxp_cb_config *cbp; 1266 struct fxp_cb_ias *cb_ias; 1267 struct fxp_cb_tx *txd; 1268 bus_dmamap_t rxmap; 1269 int i, prm, allm, error = 0; 1270 1271 /* 1272 * Cancel any pending I/O 1273 */ 1274 fxp_stop(sc, 0); 1275 1276 sc->sc_flags = 0; 1277 1278 /* 1279 * Initialize base of CBL and RFA memory. Loading with zero 1280 * sets it up for regular linear addressing. 1281 */ 1282 fxp_scb_wait(sc); 1283 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1284 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1285 1286 fxp_scb_wait(sc); 1287 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1288 1289 /* 1290 * Initialize the multicast filter. Do this now, since we might 1291 * have to setup the config block differently. 1292 */ 1293 fxp_mc_setup(sc); 1294 1295 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1296 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1297 1298 /* 1299 * Initialize base of dump-stats buffer. 1300 */ 1301 fxp_scb_wait(sc); 1302 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1303 sc->sc_cddma + FXP_CDSTATSOFF); 1304 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1305 1306 cbp = &sc->sc_control_data->fcd_configcb; 1307 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1308 1309 /* 1310 * This copy is kind of disgusting, but there are a bunch of must be 1311 * zero and must be one bits in this structure and this is the easiest 1312 * way to initialize them all to proper values. 1313 */ 1314 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1315 1316 /* BIG_ENDIAN: no need to swap to store 0 */ 1317 cbp->cb_status = 0; 1318 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1319 FXP_CB_COMMAND_EL); 1320 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1321 cbp->link_addr = 0xffffffff; /* (no) next command */ 1322 cbp->byte_count = 22; /* (22) bytes to config */ 1323 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1324 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1325 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1326 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1327 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1328 cbp->dma_bce = 0; /* (disable) dma max counters */ 1329 cbp->late_scb = 0; /* (don't) defer SCB update */ 1330 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1331 cbp->ci_int = 1; /* interrupt on CU idle */ 1332 cbp->save_bf = prm; /* save bad frames */ 1333 cbp->disc_short_rx = !prm; /* discard short packets */ 1334 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1335 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1336 cbp->nsai = 1; /* (don't) disable source addr insert */ 1337 cbp->preamble_length = 2; /* (7 byte) preamble */ 1338 cbp->loopback = 0; /* (don't) loopback */ 1339 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1340 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1341 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1342 cbp->promiscuous = prm; /* promiscuous mode */ 1343 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1344 cbp->crscdt = 0; /* (CRS only) */ 1345 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1346 cbp->padding = 1; /* (do) pad short tx packets */ 1347 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1348 cbp->force_fdx = 0; /* (don't) force full duplex */ 1349 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1350 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1351 cbp->mc_all = allm; /* accept all multicasts */ 1352 1353 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1354 1355 /* 1356 * Start the config command/DMA. 1357 */ 1358 fxp_scb_wait(sc); 1359 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1360 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1361 /* ...and wait for it to complete. */ 1362 do { 1363 FXP_CDCONFIGSYNC(sc, 1364 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1365 } while ((cbp->cb_status & FXP_CB_STATUS_C) == 0); 1366 1367 /* 1368 * Initialize the station address. 1369 */ 1370 cb_ias = &sc->sc_control_data->fcd_iascb; 1371 /* BIG_ENDIAN: no need to swap to store 0 */ 1372 cb_ias->cb_status = 0; 1373 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1374 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1375 cb_ias->link_addr = 0xffffffff; 1376 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1377 1378 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1379 1380 /* 1381 * Start the IAS (Individual Address Setup) command/DMA. 1382 */ 1383 fxp_scb_wait(sc); 1384 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1385 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1386 /* ...and wait for it to complete. */ 1387 do { 1388 FXP_CDIASSYNC(sc, 1389 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1390 } while ((cb_ias->cb_status & FXP_CB_STATUS_C) == 0); 1391 1392 /* 1393 * Initialize the transmit descriptor ring. txlast is initialized 1394 * to the end of the list so that it will wrap around to the first 1395 * descriptor when the first packet is transmitted. 1396 */ 1397 for (i = 0; i < FXP_NTXCB; i++) { 1398 txd = FXP_CDTX(sc, i); 1399 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1400 txd->cb_command = 1401 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1402 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1403 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1404 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1405 } 1406 sc->sc_txpending = 0; 1407 sc->sc_txdirty = 0; 1408 sc->sc_txlast = FXP_NTXCB - 1; 1409 1410 /* 1411 * Initialize the receive buffer list. 1412 */ 1413 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1414 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1415 rxmap = FXP_RXMAP_GET(sc); 1416 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1417 printf("%s: unable to allocate or map rx " 1418 "buffer %d, error = %d\n", 1419 sc->sc_dev.dv_xname, 1420 sc->sc_rxq.ifq_len, error); 1421 /* 1422 * XXX Should attempt to run with fewer receive 1423 * XXX buffers instead of just failing. 1424 */ 1425 FXP_RXMAP_PUT(sc, rxmap); 1426 fxp_rxdrain(sc); 1427 goto out; 1428 } 1429 } 1430 sc->sc_rxidle = 0; 1431 1432 /* 1433 * Give the transmit ring to the chip. We do this by pointing 1434 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1435 * issuing a start command. It will execute the NOP and then 1436 * suspend, pointing at the first descriptor. 1437 */ 1438 fxp_scb_wait(sc); 1439 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1440 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1441 1442 /* 1443 * Initialize receiver buffer area - RFA. 1444 */ 1445 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1446 fxp_scb_wait(sc); 1447 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1448 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1449 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1450 1451 if (sc->sc_flags & FXPF_MII) { 1452 /* 1453 * Set current media. 1454 */ 1455 mii_mediachg(&sc->sc_mii); 1456 } 1457 1458 /* 1459 * ...all done! 1460 */ 1461 ifp->if_flags |= IFF_RUNNING; 1462 ifp->if_flags &= ~IFF_OACTIVE; 1463 1464 /* 1465 * Start the one second timer. 1466 */ 1467 timeout(fxp_tick, sc, hz); 1468 1469 /* 1470 * Attempt to start output on the interface. 1471 */ 1472 fxp_start(ifp); 1473 1474 out: 1475 if (error) 1476 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1477 return (error); 1478 } 1479 1480 /* 1481 * Change media according to request. 1482 */ 1483 int 1484 fxp_mii_mediachange(ifp) 1485 struct ifnet *ifp; 1486 { 1487 struct fxp_softc *sc = ifp->if_softc; 1488 1489 if (ifp->if_flags & IFF_UP) 1490 mii_mediachg(&sc->sc_mii); 1491 return (0); 1492 } 1493 1494 /* 1495 * Notify the world which media we're using. 1496 */ 1497 void 1498 fxp_mii_mediastatus(ifp, ifmr) 1499 struct ifnet *ifp; 1500 struct ifmediareq *ifmr; 1501 { 1502 struct fxp_softc *sc = ifp->if_softc; 1503 1504 if(sc->sc_enabled == 0) { 1505 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1506 ifmr->ifm_status = 0; 1507 return; 1508 } 1509 1510 mii_pollstat(&sc->sc_mii); 1511 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1512 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1513 } 1514 1515 int 1516 fxp_80c24_mediachange(ifp) 1517 struct ifnet *ifp; 1518 { 1519 1520 /* Nothing to do here. */ 1521 return (0); 1522 } 1523 1524 void 1525 fxp_80c24_mediastatus(ifp, ifmr) 1526 struct ifnet *ifp; 1527 struct ifmediareq *ifmr; 1528 { 1529 struct fxp_softc *sc = ifp->if_softc; 1530 1531 /* 1532 * Media is currently-selected media. We cannot determine 1533 * the link status. 1534 */ 1535 ifmr->ifm_status = 0; 1536 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1537 } 1538 1539 /* 1540 * Add a buffer to the end of the RFA buffer list. 1541 * Return 0 if successful, error code on failure. 1542 * 1543 * The RFA struct is stuck at the beginning of mbuf cluster and the 1544 * data pointer is fixed up to point just past it. 1545 */ 1546 int 1547 fxp_add_rfabuf(sc, rxmap, unload) 1548 struct fxp_softc *sc; 1549 bus_dmamap_t rxmap; 1550 int unload; 1551 { 1552 struct mbuf *m; 1553 int error; 1554 1555 MGETHDR(m, M_DONTWAIT, MT_DATA); 1556 if (m == NULL) 1557 return (ENOBUFS); 1558 1559 MCLGET(m, M_DONTWAIT); 1560 if ((m->m_flags & M_EXT) == 0) { 1561 m_freem(m); 1562 return (ENOBUFS); 1563 } 1564 1565 if (unload) 1566 bus_dmamap_unload(sc->sc_dmat, rxmap); 1567 1568 M_SETCTX(m, rxmap); 1569 1570 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1571 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1572 if (error) { 1573 printf("%s: can't load rx DMA map %d, error = %d\n", 1574 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1575 panic("fxp_add_rfabuf"); /* XXX */ 1576 } 1577 1578 FXP_INIT_RFABUF(sc, m); 1579 1580 return (0); 1581 } 1582 1583 volatile int 1584 fxp_mdi_read(self, phy, reg) 1585 struct device *self; 1586 int phy; 1587 int reg; 1588 { 1589 struct fxp_softc *sc = (struct fxp_softc *)self; 1590 int count = 10000; 1591 int value; 1592 1593 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1594 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1595 1596 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1597 && count--) 1598 DELAY(10); 1599 1600 if (count <= 0) 1601 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1602 1603 return (value & 0xffff); 1604 } 1605 1606 void 1607 fxp_statchg(self) 1608 struct device *self; 1609 { 1610 1611 /* XXX Update ifp->if_baudrate */ 1612 } 1613 1614 void 1615 fxp_mdi_write(self, phy, reg, value) 1616 struct device *self; 1617 int phy; 1618 int reg; 1619 int value; 1620 { 1621 struct fxp_softc *sc = (struct fxp_softc *)self; 1622 int count = 10000; 1623 1624 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1625 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1626 (value & 0xffff)); 1627 1628 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1629 count--) 1630 DELAY(10); 1631 1632 if (count <= 0) 1633 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1634 } 1635 1636 int 1637 fxp_ioctl(ifp, command, data) 1638 struct ifnet *ifp; 1639 u_long command; 1640 caddr_t data; 1641 { 1642 struct fxp_softc *sc = ifp->if_softc; 1643 struct ifreq *ifr = (struct ifreq *)data; 1644 struct ifaddr *ifa = (struct ifaddr *)data; 1645 int s, error = 0; 1646 1647 s = splnet(); 1648 1649 switch (command) { 1650 case SIOCSIFADDR: 1651 if ((error = fxp_enable(sc)) != 0) 1652 break; 1653 ifp->if_flags |= IFF_UP; 1654 1655 switch (ifa->ifa_addr->sa_family) { 1656 #ifdef INET 1657 case AF_INET: 1658 if ((error = fxp_init(sc)) != 0) 1659 break; 1660 arp_ifinit(ifp, ifa); 1661 break; 1662 #endif /* INET */ 1663 #ifdef NS 1664 case AF_NS: 1665 { 1666 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1667 1668 if (ns_nullhost(*ina)) 1669 ina->x_host = *(union ns_host *) 1670 LLADDR(ifp->if_sadl); 1671 else 1672 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1673 ifp->if_addrlen); 1674 /* Set new address. */ 1675 error = fxp_init(sc); 1676 break; 1677 } 1678 #endif /* NS */ 1679 default: 1680 error = fxp_init(sc); 1681 break; 1682 } 1683 break; 1684 1685 case SIOCSIFMTU: 1686 if (ifr->ifr_mtu > ETHERMTU) 1687 error = EINVAL; 1688 else 1689 ifp->if_mtu = ifr->ifr_mtu; 1690 break; 1691 1692 case SIOCSIFFLAGS: 1693 if ((ifp->if_flags & IFF_UP) == 0 && 1694 (ifp->if_flags & IFF_RUNNING) != 0) { 1695 /* 1696 * If interface is marked down and it is running, then 1697 * stop it. 1698 */ 1699 fxp_stop(sc, 1); 1700 fxp_disable(sc); 1701 } else if ((ifp->if_flags & IFF_UP) != 0 && 1702 (ifp->if_flags & IFF_RUNNING) == 0) { 1703 /* 1704 * If interface is marked up and it is stopped, then 1705 * start it. 1706 */ 1707 if((error = fxp_enable(sc)) != 0) 1708 break; 1709 error = fxp_init(sc); 1710 } else if ((ifp->if_flags & IFF_UP) != 0) { 1711 /* 1712 * Reset the interface to pick up change in any other 1713 * flags that affect the hardware state. 1714 */ 1715 if((error = fxp_enable(sc)) != 0) 1716 break; 1717 error = fxp_init(sc); 1718 } 1719 break; 1720 1721 case SIOCADDMULTI: 1722 case SIOCDELMULTI: 1723 if(sc->sc_enabled == 0) { 1724 error = EIO; 1725 break; 1726 } 1727 error = (command == SIOCADDMULTI) ? 1728 ether_addmulti(ifr, &sc->sc_ethercom) : 1729 ether_delmulti(ifr, &sc->sc_ethercom); 1730 1731 if (error == ENETRESET) { 1732 /* 1733 * Multicast list has changed; set the hardware 1734 * filter accordingly. 1735 */ 1736 if (sc->sc_txpending) { 1737 sc->sc_flags |= FXPF_WANTINIT; 1738 error = 0; 1739 } else 1740 error = fxp_init(sc); 1741 } 1742 break; 1743 1744 case SIOCSIFMEDIA: 1745 case SIOCGIFMEDIA: 1746 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1747 break; 1748 1749 default: 1750 error = EINVAL; 1751 break; 1752 } 1753 1754 splx(s); 1755 return (error); 1756 } 1757 1758 /* 1759 * Program the multicast filter. 1760 * 1761 * This function must be called at splnet(). 1762 */ 1763 void 1764 fxp_mc_setup(sc) 1765 struct fxp_softc *sc; 1766 { 1767 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1768 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1769 struct ethercom *ec = &sc->sc_ethercom; 1770 struct ether_multi *enm; 1771 struct ether_multistep step; 1772 int nmcasts; 1773 1774 #ifdef DIAGNOSTIC 1775 if (sc->sc_txpending) 1776 panic("fxp_mc_setup: pending transmissions"); 1777 #endif 1778 1779 ifp->if_flags &= ~IFF_ALLMULTI; 1780 1781 /* 1782 * Initialize multicast setup descriptor. 1783 */ 1784 nmcasts = 0; 1785 ETHER_FIRST_MULTI(step, ec, enm); 1786 while (enm != NULL) { 1787 /* 1788 * Check for too many multicast addresses or if we're 1789 * listening to a range. Either way, we simply have 1790 * to accept all multicasts. 1791 */ 1792 if (nmcasts >= MAXMCADDR || 1793 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1794 ETHER_ADDR_LEN) != 0) { 1795 /* 1796 * Callers of this function must do the 1797 * right thing with this. If we're called 1798 * from outside fxp_init(), the caller must 1799 * detect if the state if IFF_ALLMULTI changes. 1800 * If it does, the caller must then call 1801 * fxp_init(), since allmulti is handled by 1802 * the config block. 1803 */ 1804 ifp->if_flags |= IFF_ALLMULTI; 1805 return; 1806 } 1807 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1808 ETHER_ADDR_LEN); 1809 nmcasts++; 1810 ETHER_NEXT_MULTI(step, enm); 1811 } 1812 1813 /* BIG_ENDIAN: no need to swap to store 0 */ 1814 mcsp->cb_status = 0; 1815 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1816 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1817 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1818 1819 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1820 1821 /* 1822 * Wait until the command unit is not active. This should never 1823 * happen since nothing is queued, but make sure anyway. 1824 */ 1825 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1826 FXP_SCB_CUS_ACTIVE) 1827 /* nothing */ ; 1828 1829 /* 1830 * Start the multicast setup command/DMA. 1831 */ 1832 fxp_scb_wait(sc); 1833 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1834 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1835 1836 /* ...and wait for it to complete. */ 1837 do { 1838 FXP_CDMCSSYNC(sc, 1839 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1840 } while ((mcsp->cb_status & FXP_CB_STATUS_C) == 0); 1841 } 1842 1843 int 1844 fxp_enable(sc) 1845 struct fxp_softc *sc; 1846 { 1847 1848 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1849 if ((*sc->sc_enable)(sc) != 0) { 1850 printf("%s: device enable failed\n", 1851 sc->sc_dev.dv_xname); 1852 return (EIO); 1853 } 1854 } 1855 1856 sc->sc_enabled = 1; 1857 1858 return 0; 1859 } 1860 1861 void 1862 fxp_disable(sc) 1863 struct fxp_softc *sc; 1864 { 1865 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1866 (*sc->sc_disable)(sc); 1867 sc->sc_enabled = 0; 1868 } 1869 } 1870 1871 1872 1873 int 1874 fxp_detach(sc) 1875 struct fxp_softc *sc; 1876 { 1877 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1878 int i; 1879 1880 /* Unhook our tick handler. */ 1881 untimeout(fxp_tick, sc); 1882 1883 if (sc->sc_flags & FXPF_MII) { 1884 /* Detach all PHYs */ 1885 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1886 } 1887 1888 /* Delete all remaining media. */ 1889 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1890 1891 #if NRND > 0 1892 rnd_detach_source(&sc->rnd_source); 1893 #endif 1894 #if NBPFILTER > 0 1895 bpfdetach(ifp); 1896 #endif 1897 ether_ifdetach(ifp); 1898 if_detach(ifp); 1899 1900 for (i = 0; i < FXP_NRFABUFS; i++) { 1901 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1902 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1903 } 1904 1905 for (i = 0; i < FXP_NTXCB; i++) { 1906 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1907 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1908 } 1909 1910 1911 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1912 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1913 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1914 sizeof(struct fxp_control_data)); 1915 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1916 1917 shutdownhook_disestablish(sc->sc_sdhook); 1918 1919 return (0); 1920 } 1921
Indexes created Mon Sep 29 21:09:56 GMT 2025