i82557.c revision 1.24
1 /* $NetBSD: i82557.c,v 1.24 2000/03/23 07:01:31 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <vm/vm.h> /* for PAGE_SIZE */ 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia __P((struct fxp_softc *)); 169 int fxp_mii_mediachange __P((struct ifnet *)); 170 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 void fxp_80c24_initmedia __P((struct fxp_softc *)); 173 int fxp_80c24_mediachange __P((struct ifnet *)); 174 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176 inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178 void fxp_start __P((struct ifnet *)); 179 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180 int fxp_init __P((struct fxp_softc *)); 181 void fxp_rxdrain __P((struct fxp_softc *)); 182 void fxp_stop __P((struct fxp_softc *, int)); 183 void fxp_watchdog __P((struct ifnet *)); 184 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 185 int fxp_mdi_read __P((struct device *, int, int)); 186 void fxp_statchg __P((struct device *)); 187 void fxp_mdi_write __P((struct device *, int, int, int)); 188 void fxp_autosize_eeprom __P((struct fxp_softc*)); 189 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 190 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 191 void fxp_tick __P((void *)); 192 void fxp_mc_setup __P((struct fxp_softc *)); 193 194 void fxp_shutdown __P((void *)); 195 void fxp_power __P((int, void *)); 196 197 int fxp_copy_small = 0; 198 199 int fxp_enable __P((struct fxp_softc*)); 200 void fxp_disable __P((struct fxp_softc*)); 201 202 struct fxp_phytype { 203 int fp_phy; /* type of PHY, -1 for MII at the end. */ 204 void (*fp_init) __P((struct fxp_softc *)); 205 } fxp_phytype_table[] = { 206 { FXP_PHY_80C24, fxp_80c24_initmedia }, 207 { -1, fxp_mii_initmedia }, 208 }; 209 210 /* 211 * Set initial transmit threshold at 64 (512 bytes). This is 212 * increased by 64 (512 bytes) at a time, to maximum of 192 213 * (1536 bytes), if an underrun occurs. 214 */ 215 static int tx_threshold = 64; 216 217 /* 218 * Wait for the previous command to be accepted (but not necessarily 219 * completed). 220 */ 221 inline void 222 fxp_scb_wait(sc) 223 struct fxp_softc *sc; 224 { 225 int i = 10000; 226 227 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 228 delay(2); 229 if (i == 0) 230 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 231 } 232 233 /* 234 * Finish attaching an i82557 interface. Called by bus-specific front-end. 235 */ 236 void 237 fxp_attach(sc) 238 struct fxp_softc *sc; 239 { 240 u_int8_t enaddr[6]; 241 struct ifnet *ifp; 242 bus_dma_segment_t seg; 243 int rseg, i, error; 244 struct fxp_phytype *fp; 245 246 callout_init(&sc->sc_callout); 247 248 /* 249 * Allocate the control data structures, and create and load the 250 * DMA map for it. 251 */ 252 if ((error = bus_dmamem_alloc(sc->sc_dmat, 253 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 254 0)) != 0) { 255 printf("%s: unable to allocate control data, error = %d\n", 256 sc->sc_dev.dv_xname, error); 257 goto fail_0; 258 } 259 260 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 261 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 262 BUS_DMA_COHERENT)) != 0) { 263 printf("%s: unable to map control data, error = %d\n", 264 sc->sc_dev.dv_xname, error); 265 goto fail_1; 266 } 267 sc->sc_cdseg = seg; 268 sc->sc_cdnseg = rseg; 269 270 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 271 272 if ((error = bus_dmamap_create(sc->sc_dmat, 273 sizeof(struct fxp_control_data), 1, 274 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 275 printf("%s: unable to create control data DMA map, " 276 "error = %d\n", sc->sc_dev.dv_xname, error); 277 goto fail_2; 278 } 279 280 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 281 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 282 0)) != 0) { 283 printf("%s: can't load control data DMA map, error = %d\n", 284 sc->sc_dev.dv_xname, error); 285 goto fail_3; 286 } 287 288 /* 289 * Create the transmit buffer DMA maps. 290 */ 291 for (i = 0; i < FXP_NTXCB; i++) { 292 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 293 FXP_NTXSEG, MCLBYTES, 0, 0, 294 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 295 printf("%s: unable to create tx DMA map %d, " 296 "error = %d\n", sc->sc_dev.dv_xname, i, error); 297 goto fail_4; 298 } 299 } 300 301 /* 302 * Create the receive buffer DMA maps. 303 */ 304 for (i = 0; i < FXP_NRFABUFS; i++) { 305 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 306 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 307 printf("%s: unable to create rx DMA map %d, " 308 "error = %d\n", sc->sc_dev.dv_xname, i, error); 309 goto fail_5; 310 } 311 } 312 313 /* Initialize MAC address and media structures. */ 314 fxp_get_info(sc, enaddr); 315 316 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 317 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 318 319 ifp = &sc->sc_ethercom.ec_if; 320 321 /* 322 * Get info about our media interface, and initialize it. Note 323 * the table terminates itself with a phy of -1, indicating 324 * that we're using MII. 325 */ 326 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 327 if (fp->fp_phy == sc->phy_primary_device) 328 break; 329 (*fp->fp_init)(sc); 330 331 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 332 ifp->if_softc = sc; 333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 334 ifp->if_ioctl = fxp_ioctl; 335 ifp->if_start = fxp_start; 336 ifp->if_watchdog = fxp_watchdog; 337 338 /* 339 * Attach the interface. 340 */ 341 if_attach(ifp); 342 ether_ifattach(ifp, enaddr); 343 #if NBPFILTER > 0 344 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 345 sizeof(struct ether_header)); 346 #endif 347 #if NRND > 0 348 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 349 RND_TYPE_NET, 0); 350 #endif 351 352 /* 353 * Add shutdown hook so that DMA is disabled prior to reboot. Not 354 * doing do could allow DMA to corrupt kernel memory during the 355 * reboot before the driver initializes. 356 */ 357 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 358 if (sc->sc_sdhook == NULL) 359 printf("%s: WARNING: unable to establish shutdown hook\n", 360 sc->sc_dev.dv_xname); 361 /* 362 * Add suspend hook, for similar reasons.. 363 */ 364 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 365 if (sc->sc_powerhook == NULL) 366 printf("%s: WARNING: unable to establish power hook\n", 367 sc->sc_dev.dv_xname); 368 return; 369 370 /* 371 * Free any resources we've allocated during the failed attach 372 * attempt. Do this in reverse order and fall though. 373 */ 374 fail_5: 375 for (i = 0; i < FXP_NRFABUFS; i++) { 376 if (sc->sc_rxmaps[i] != NULL) 377 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 378 } 379 fail_4: 380 for (i = 0; i < FXP_NTXCB; i++) { 381 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 382 bus_dmamap_destroy(sc->sc_dmat, 383 FXP_DSTX(sc, i)->txs_dmamap); 384 } 385 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 386 fail_3: 387 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 388 fail_2: 389 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 390 sizeof(struct fxp_control_data)); 391 fail_1: 392 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 393 fail_0: 394 return; 395 } 396 397 void 398 fxp_mii_initmedia(sc) 399 struct fxp_softc *sc; 400 { 401 402 sc->sc_flags |= FXPF_MII; 403 404 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 405 sc->sc_mii.mii_readreg = fxp_mdi_read; 406 sc->sc_mii.mii_writereg = fxp_mdi_write; 407 sc->sc_mii.mii_statchg = fxp_statchg; 408 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 409 fxp_mii_mediastatus); 410 /* 411 * The i82557 wedges if all of its PHYs are isolated! 412 */ 413 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 414 MII_OFFSET_ANY, MIIF_NOISOLATE); 415 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 416 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 417 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 418 } else 419 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 420 } 421 422 void 423 fxp_80c24_initmedia(sc) 424 struct fxp_softc *sc; 425 { 426 427 /* 428 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 429 * doesn't have a programming interface of any sort. The 430 * media is sensed automatically based on how the link partner 431 * is configured. This is, in essence, manual configuration. 432 */ 433 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 434 sc->sc_dev.dv_xname); 435 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 436 fxp_80c24_mediastatus); 437 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 438 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 439 } 440 441 /* 442 * Device shutdown routine. Called at system shutdown after sync. The 443 * main purpose of this routine is to shut off receiver DMA so that 444 * kernel memory doesn't get clobbered during warmboot. 445 */ 446 void 447 fxp_shutdown(arg) 448 void *arg; 449 { 450 struct fxp_softc *sc = arg; 451 452 /* 453 * Since the system's going to halt shortly, don't bother 454 * freeing mbufs. 455 */ 456 fxp_stop(sc, 0); 457 } 458 /* 459 * Power handler routine. Called when the system is transitioning 460 * into/out of power save modes. As with fxp_shutdown, the main 461 * purpose of this routine is to shut off receiver DMA so it doesn't 462 * clobber kernel memory at the wrong time. 463 */ 464 void 465 fxp_power(why, arg) 466 int why; 467 void *arg; 468 { 469 struct fxp_softc *sc = arg; 470 struct ifnet *ifp; 471 int s; 472 473 s = splnet(); 474 if (why != PWR_RESUME) 475 fxp_stop(sc, 0); 476 else { 477 ifp = &sc->sc_ethercom.ec_if; 478 if (ifp->if_flags & IFF_UP) 479 fxp_init(sc); 480 } 481 splx(s); 482 } 483 484 /* 485 * Initialize the interface media. 486 */ 487 void 488 fxp_get_info(sc, enaddr) 489 struct fxp_softc *sc; 490 u_int8_t *enaddr; 491 { 492 u_int16_t data, myea[3]; 493 494 /* 495 * Reset to a stable state. 496 */ 497 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 498 DELAY(10); 499 500 sc->sc_eeprom_size = 0; 501 fxp_autosize_eeprom(sc); 502 if(sc->sc_eeprom_size == 0) { 503 printf("%s: failed to detect EEPROM size", sc->sc_dev.dv_xname); 504 sc->sc_eeprom_size = 6; /* XXX panic here? */ 505 } 506 #ifdef DEBUG 507 printf("%s: detected %d word EEPROM\n", 508 sc->sc_dev.dv_xname, 509 1 << sc->sc_eeprom_size); 510 #endif 511 512 /* 513 * Get info about the primary PHY 514 */ 515 fxp_read_eeprom(sc, &data, 6, 1); 516 sc->phy_primary_addr = data & 0xff; 517 sc->phy_primary_device = (data >> 8) & 0x3f; 518 sc->phy_10Mbps_only = data >> 15; 519 520 /* 521 * Read MAC address. 522 */ 523 fxp_read_eeprom(sc, myea, 0, 3); 524 bcopy(myea, enaddr, ETHER_ADDR_LEN); 525 } 526 527 /* 528 * Figure out EEPROM size. 529 * 530 * 559's can have either 64-word or 256-word EEPROMs, the 558 531 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 532 * talks about the existance of 16 to 256 word EEPROMs. 533 * 534 * The only known sizes are 64 and 256, where the 256 version is used 535 * by CardBus cards to store CIS information. 536 * 537 * The address is shifted in msb-to-lsb, and after the last 538 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 539 * after which follows the actual data. We try to detect this zero, by 540 * probing the data-out bit in the EEPROM control register just after 541 * having shifted in a bit. If the bit is zero, we assume we've 542 * shifted enough address bits. The data-out should be tri-state, 543 * before this, which should translate to a logical one. 544 * 545 * Other ways to do this would be to try to read a register with known 546 * contents with a varying number of address bits, but no such 547 * register seem to be available. The high bits of register 10 are 01 548 * on the 558 and 559, but apparently not on the 557. 549 * 550 * The Linux driver computes a checksum on the EEPROM data, but the 551 * value of this checksum is not very well documented. 552 */ 553 554 void 555 fxp_autosize_eeprom(sc) 556 struct fxp_softc *sc; 557 { 558 u_int16_t reg; 559 int x; 560 561 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 562 /* 563 * Shift in read opcode. 564 */ 565 for (x = 3; x > 0; x--) { 566 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 567 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 568 } else { 569 reg = FXP_EEPROM_EECS; 570 } 571 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 572 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 573 reg | FXP_EEPROM_EESK); 574 DELAY(1); 575 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 576 DELAY(1); 577 } 578 /* 579 * Shift in address, wait for the dummy zero following a correct 580 * address shift. 581 */ 582 for (x = 1; x <= 8; x++) { 583 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 584 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 585 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 586 DELAY(1); 587 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 588 FXP_EEPROM_EEDO) == 0) 589 break; 590 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 591 DELAY(1); 592 } 593 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 594 DELAY(1); 595 if(x != 6 && x != 8) { 596 #ifdef DEBUG 597 printf("%s: strange EEPROM size (%d)\n", 598 sc->sc_dev.dv_xname, 1 << x); 599 #endif 600 } else 601 sc->sc_eeprom_size = x; 602 } 603 604 /* 605 * Read from the serial EEPROM. Basically, you manually shift in 606 * the read opcode (one bit at a time) and then shift in the address, 607 * and then you shift out the data (all of this one bit at a time). 608 * The word size is 16 bits, so you have to provide the address for 609 * every 16 bits of data. 610 */ 611 void 612 fxp_read_eeprom(sc, data, offset, words) 613 struct fxp_softc *sc; 614 u_int16_t *data; 615 int offset; 616 int words; 617 { 618 u_int16_t reg; 619 int i, x; 620 621 for (i = 0; i < words; i++) { 622 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 623 /* 624 * Shift in read opcode. 625 */ 626 for (x = 3; x > 0; x--) { 627 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 628 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 629 } else { 630 reg = FXP_EEPROM_EECS; 631 } 632 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 633 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 634 reg | FXP_EEPROM_EESK); 635 DELAY(1); 636 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 637 DELAY(1); 638 } 639 /* 640 * Shift in address. 641 */ 642 for (x = sc->sc_eeprom_size; x > 0; x--) { 643 if ((i + offset) & (1 << (x - 1))) { 644 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 645 } else { 646 reg = FXP_EEPROM_EECS; 647 } 648 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 649 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 650 reg | FXP_EEPROM_EESK); 651 DELAY(1); 652 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 653 DELAY(1); 654 } 655 reg = FXP_EEPROM_EECS; 656 data[i] = 0; 657 /* 658 * Shift out data. 659 */ 660 for (x = 16; x > 0; x--) { 661 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 662 reg | FXP_EEPROM_EESK); 663 DELAY(1); 664 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 665 FXP_EEPROM_EEDO) 666 data[i] |= (1 << (x - 1)); 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 668 DELAY(1); 669 } 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 671 DELAY(1); 672 } 673 } 674 675 /* 676 * Start packet transmission on the interface. 677 */ 678 void 679 fxp_start(ifp) 680 struct ifnet *ifp; 681 { 682 struct fxp_softc *sc = ifp->if_softc; 683 struct mbuf *m0, *m; 684 struct fxp_cb_tx *txd; 685 struct fxp_txsoft *txs; 686 struct fxp_tbdlist *tbd; 687 bus_dmamap_t dmamap; 688 int error, lasttx, nexttx, opending, seg; 689 690 /* 691 * If we want a re-init, bail out now. 692 */ 693 if (sc->sc_flags & FXPF_WANTINIT) { 694 ifp->if_flags |= IFF_OACTIVE; 695 return; 696 } 697 698 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 699 return; 700 701 /* 702 * Remember the previous txpending and the current lasttx. 703 */ 704 opending = sc->sc_txpending; 705 lasttx = sc->sc_txlast; 706 707 /* 708 * Loop through the send queue, setting up transmit descriptors 709 * until we drain the queue, or use up all available transmit 710 * descriptors. 711 */ 712 while (sc->sc_txpending < FXP_NTXCB) { 713 /* 714 * Grab a packet off the queue. 715 */ 716 IF_DEQUEUE(&ifp->if_snd, m0); 717 if (m0 == NULL) 718 break; 719 720 /* 721 * Get the next available transmit descriptor. 722 */ 723 nexttx = FXP_NEXTTX(sc->sc_txlast); 724 txd = FXP_CDTX(sc, nexttx); 725 tbd = FXP_CDTBD(sc, nexttx); 726 txs = FXP_DSTX(sc, nexttx); 727 dmamap = txs->txs_dmamap; 728 729 /* 730 * Load the DMA map. If this fails, the packet either 731 * didn't fit in the allotted number of frags, or we were 732 * short on resources. In this case, we'll copy and try 733 * again. 734 */ 735 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 736 BUS_DMA_NOWAIT) != 0) { 737 MGETHDR(m, M_DONTWAIT, MT_DATA); 738 if (m == NULL) { 739 printf("%s: unable to allocate Tx mbuf\n", 740 sc->sc_dev.dv_xname); 741 IF_PREPEND(&ifp->if_snd, m0); 742 break; 743 } 744 if (m0->m_pkthdr.len > MHLEN) { 745 MCLGET(m, M_DONTWAIT); 746 if ((m->m_flags & M_EXT) == 0) { 747 printf("%s: unable to allocate Tx " 748 "cluster\n", sc->sc_dev.dv_xname); 749 m_freem(m); 750 IF_PREPEND(&ifp->if_snd, m0); 751 break; 752 } 753 } 754 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 755 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 756 m_freem(m0); 757 m0 = m; 758 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 759 m0, BUS_DMA_NOWAIT); 760 if (error) { 761 printf("%s: unable to load Tx buffer, " 762 "error = %d\n", sc->sc_dev.dv_xname, error); 763 IF_PREPEND(&ifp->if_snd, m0); 764 break; 765 } 766 } 767 768 /* Initialize the fraglist. */ 769 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 770 tbd->tbd_d[seg].tb_addr = 771 htole32(dmamap->dm_segs[seg].ds_addr); 772 tbd->tbd_d[seg].tb_size = 773 htole32(dmamap->dm_segs[seg].ds_len); 774 } 775 776 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 777 778 /* Sync the DMA map. */ 779 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 780 BUS_DMASYNC_PREWRITE); 781 782 /* 783 * Store a pointer to the packet so we can free it later. 784 */ 785 txs->txs_mbuf = m0; 786 787 /* 788 * Initialize the transmit descriptor. 789 */ 790 /* BIG_ENDIAN: no need to swap to store 0 */ 791 txd->cb_status = 0; 792 txd->cb_command = 793 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 794 txd->tx_threshold = tx_threshold; 795 txd->tbd_number = dmamap->dm_nsegs; 796 797 FXP_CDTXSYNC(sc, nexttx, 798 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 799 800 /* Advance the tx pointer. */ 801 sc->sc_txpending++; 802 sc->sc_txlast = nexttx; 803 804 #if NBPFILTER > 0 805 /* 806 * Pass packet to bpf if there is a listener. 807 */ 808 if (ifp->if_bpf) 809 bpf_mtap(ifp->if_bpf, m0); 810 #endif 811 } 812 813 if (sc->sc_txpending == FXP_NTXCB) { 814 /* No more slots; notify upper layer. */ 815 ifp->if_flags |= IFF_OACTIVE; 816 } 817 818 if (sc->sc_txpending != opending) { 819 /* 820 * We enqueued packets. If the transmitter was idle, 821 * reset the txdirty pointer. 822 */ 823 if (opending == 0) 824 sc->sc_txdirty = FXP_NEXTTX(lasttx); 825 826 /* 827 * Cause the chip to interrupt and suspend command 828 * processing once the last packet we've enqueued 829 * has been transmitted. 830 */ 831 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 832 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 833 FXP_CDTXSYNC(sc, sc->sc_txlast, 834 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 835 836 /* 837 * The entire packet chain is set up. Clear the suspend bit 838 * on the command prior to the first packet we set up. 839 */ 840 FXP_CDTXSYNC(sc, lasttx, 841 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 842 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 843 FXP_CDTXSYNC(sc, lasttx, 844 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 845 846 /* 847 * Issue a Resume command in case the chip was suspended. 848 */ 849 fxp_scb_wait(sc); 850 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 851 852 /* Set a watchdog timer in case the chip flakes out. */ 853 ifp->if_timer = 5; 854 } 855 } 856 857 /* 858 * Process interface interrupts. 859 */ 860 int 861 fxp_intr(arg) 862 void *arg; 863 { 864 struct fxp_softc *sc = arg; 865 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 866 struct fxp_cb_tx *txd; 867 struct fxp_txsoft *txs; 868 struct mbuf *m, *m0; 869 bus_dmamap_t rxmap; 870 struct fxp_rfa *rfa; 871 struct ether_header *eh; 872 int i, claimed = 0; 873 u_int16_t len, rxstat, txstat; 874 u_int8_t statack; 875 876 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 877 return (0); 878 /* 879 * If the interface isn't running, don't try to 880 * service the interrupt.. just ack it and bail. 881 */ 882 if ((ifp->if_flags & IFF_RUNNING) == 0) { 883 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 884 if (statack) { 885 claimed = 1; 886 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 887 } 888 return (claimed); 889 } 890 891 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 892 claimed = 1; 893 894 /* 895 * First ACK all the interrupts in this pass. 896 */ 897 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 898 899 /* 900 * Process receiver interrupts. If a no-resource (RNR) 901 * condition exists, get whatever packets we can and 902 * re-start the receiver. 903 */ 904 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 905 rcvloop: 906 m = sc->sc_rxq.ifq_head; 907 rfa = FXP_MTORFA(m); 908 rxmap = M_GETCTX(m, bus_dmamap_t); 909 910 FXP_RFASYNC(sc, m, 911 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 912 913 rxstat = le16toh(rfa->rfa_status); 914 915 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 916 /* 917 * We have processed all of the 918 * receive buffers. 919 */ 920 goto do_transmit; 921 } 922 923 IF_DEQUEUE(&sc->sc_rxq, m); 924 925 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 926 927 len = le16toh(rfa->actual_size) & 928 (m->m_ext.ext_size - 1); 929 930 if (len < sizeof(struct ether_header)) { 931 /* 932 * Runt packet; drop it now. 933 */ 934 FXP_INIT_RFABUF(sc, m); 935 goto rcvloop; 936 } 937 938 /* 939 * If the packet is small enough to fit in a 940 * single header mbuf, allocate one and copy 941 * the data into it. This greatly reduces 942 * memory consumption when we receive lots 943 * of small packets. 944 * 945 * Otherwise, we add a new buffer to the receive 946 * chain. If this fails, we drop the packet and 947 * recycle the old buffer. 948 */ 949 if (fxp_copy_small != 0 && len <= MHLEN) { 950 MGETHDR(m0, M_DONTWAIT, MT_DATA); 951 if (m == NULL) 952 goto dropit; 953 memcpy(mtod(m0, caddr_t), 954 mtod(m, caddr_t), len); 955 FXP_INIT_RFABUF(sc, m); 956 m = m0; 957 } else { 958 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 959 dropit: 960 ifp->if_ierrors++; 961 FXP_INIT_RFABUF(sc, m); 962 goto rcvloop; 963 } 964 } 965 966 m->m_pkthdr.rcvif = ifp; 967 m->m_pkthdr.len = m->m_len = len; 968 eh = mtod(m, struct ether_header *); 969 970 #if NBPFILTER > 0 971 /* 972 * Pass this up to any BPF listeners, but only 973 * pass it up the stack it its for us. 974 */ 975 if (ifp->if_bpf) { 976 bpf_mtap(ifp->if_bpf, m); 977 978 if ((ifp->if_flags & IFF_PROMISC) != 0 && 979 (rxstat & FXP_RFA_STATUS_IAMATCH) != 0 && 980 (eh->ether_dhost[0] & 1) == 0) { 981 m_freem(m); 982 goto rcvloop; 983 } 984 } 985 #endif /* NBPFILTER > 0 */ 986 987 /* Pass it on. */ 988 (*ifp->if_input)(ifp, m); 989 goto rcvloop; 990 } 991 992 do_transmit: 993 if (statack & FXP_SCB_STATACK_RNR) { 994 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 995 fxp_scb_wait(sc); 996 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 997 rxmap->dm_segs[0].ds_addr + 998 RFA_ALIGNMENT_FUDGE); 999 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1000 FXP_SCB_COMMAND_RU_START); 1001 } 1002 1003 /* 1004 * Free any finished transmit mbuf chains. 1005 */ 1006 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1007 ifp->if_flags &= ~IFF_OACTIVE; 1008 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1009 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1010 txd = FXP_CDTX(sc, i); 1011 txs = FXP_DSTX(sc, i); 1012 1013 FXP_CDTXSYNC(sc, i, 1014 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1015 1016 txstat = le16toh(txd->cb_status); 1017 1018 if ((txstat & FXP_CB_STATUS_C) == 0) 1019 break; 1020 1021 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1022 1023 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1024 0, txs->txs_dmamap->dm_mapsize, 1025 BUS_DMASYNC_POSTWRITE); 1026 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1027 m_freem(txs->txs_mbuf); 1028 txs->txs_mbuf = NULL; 1029 } 1030 1031 /* Update the dirty transmit buffer pointer. */ 1032 sc->sc_txdirty = i; 1033 1034 /* 1035 * Cancel the watchdog timer if there are no pending 1036 * transmissions. 1037 */ 1038 if (sc->sc_txpending == 0) { 1039 ifp->if_timer = 0; 1040 1041 /* 1042 * If we want a re-init, do that now. 1043 */ 1044 if (sc->sc_flags & FXPF_WANTINIT) 1045 (void) fxp_init(sc); 1046 } 1047 1048 /* 1049 * Try to get more packets going. 1050 */ 1051 fxp_start(ifp); 1052 } 1053 } 1054 1055 #if NRND > 0 1056 if (claimed) 1057 rnd_add_uint32(&sc->rnd_source, statack); 1058 #endif 1059 return (claimed); 1060 } 1061 1062 /* 1063 * Update packet in/out/collision statistics. The i82557 doesn't 1064 * allow you to access these counters without doing a fairly 1065 * expensive DMA to get _all_ of the statistics it maintains, so 1066 * we do this operation here only once per second. The statistics 1067 * counters in the kernel are updated from the previous dump-stats 1068 * DMA and then a new dump-stats DMA is started. The on-chip 1069 * counters are zeroed when the DMA completes. If we can't start 1070 * the DMA immediately, we don't wait - we just prepare to read 1071 * them again next time. 1072 */ 1073 void 1074 fxp_tick(arg) 1075 void *arg; 1076 { 1077 struct fxp_softc *sc = arg; 1078 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1079 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1080 int s; 1081 1082 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1083 return; 1084 1085 s = splnet(); 1086 1087 ifp->if_opackets += le32toh(sp->tx_good); 1088 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1089 if (sp->rx_good) { 1090 ifp->if_ipackets += le32toh(sp->rx_good); 1091 sc->sc_rxidle = 0; 1092 } else { 1093 sc->sc_rxidle++; 1094 } 1095 ifp->if_ierrors += 1096 le32toh(sp->rx_crc_errors) + 1097 le32toh(sp->rx_alignment_errors) + 1098 le32toh(sp->rx_rnr_errors) + 1099 le32toh(sp->rx_overrun_errors); 1100 /* 1101 * If any transmit underruns occured, bump up the transmit 1102 * threshold by another 512 bytes (64 * 8). 1103 */ 1104 if (sp->tx_underruns) { 1105 ifp->if_oerrors += le32toh(sp->tx_underruns); 1106 if (tx_threshold < 192) 1107 tx_threshold += 64; 1108 } 1109 1110 /* 1111 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1112 * then assume the receiver has locked up and attempt to clear 1113 * the condition by reprogramming the multicast filter (actually, 1114 * resetting the interface). This is a work-around for a bug in 1115 * the 82557 where the receiver locks up if it gets certain types 1116 * of garbage in the syncronization bits prior to the packet header. 1117 * This bug is supposed to only occur in 10Mbps mode, but has been 1118 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1119 * speed transition). 1120 */ 1121 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1122 (void) fxp_init(sc); 1123 splx(s); 1124 return; 1125 } 1126 /* 1127 * If there is no pending command, start another stats 1128 * dump. Otherwise punt for now. 1129 */ 1130 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1131 /* 1132 * Start another stats dump. 1133 */ 1134 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1135 FXP_SCB_COMMAND_CU_DUMPRESET); 1136 } else { 1137 /* 1138 * A previous command is still waiting to be accepted. 1139 * Just zero our copy of the stats and wait for the 1140 * next timer event to update them. 1141 */ 1142 /* BIG_ENDIAN: no swap required to store 0 */ 1143 sp->tx_good = 0; 1144 sp->tx_underruns = 0; 1145 sp->tx_total_collisions = 0; 1146 1147 sp->rx_good = 0; 1148 sp->rx_crc_errors = 0; 1149 sp->rx_alignment_errors = 0; 1150 sp->rx_rnr_errors = 0; 1151 sp->rx_overrun_errors = 0; 1152 } 1153 1154 if (sc->sc_flags & FXPF_MII) { 1155 /* Tick the MII clock. */ 1156 mii_tick(&sc->sc_mii); 1157 } 1158 1159 splx(s); 1160 1161 /* 1162 * Schedule another timeout one second from now. 1163 */ 1164 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1165 } 1166 1167 /* 1168 * Drain the receive queue. 1169 */ 1170 void 1171 fxp_rxdrain(sc) 1172 struct fxp_softc *sc; 1173 { 1174 bus_dmamap_t rxmap; 1175 struct mbuf *m; 1176 1177 for (;;) { 1178 IF_DEQUEUE(&sc->sc_rxq, m); 1179 if (m == NULL) 1180 break; 1181 rxmap = M_GETCTX(m, bus_dmamap_t); 1182 bus_dmamap_unload(sc->sc_dmat, rxmap); 1183 FXP_RXMAP_PUT(sc, rxmap); 1184 m_freem(m); 1185 } 1186 } 1187 1188 /* 1189 * Stop the interface. Cancels the statistics updater and resets 1190 * the interface. 1191 */ 1192 void 1193 fxp_stop(sc, drain) 1194 struct fxp_softc *sc; 1195 int drain; 1196 { 1197 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1198 struct fxp_txsoft *txs; 1199 int i; 1200 1201 /* 1202 * Turn down interface (done early to avoid bad interactions 1203 * between panics, shutdown hooks, and the watchdog timer) 1204 */ 1205 ifp->if_timer = 0; 1206 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1207 1208 /* 1209 * Cancel stats updater. 1210 */ 1211 callout_stop(&sc->sc_callout); 1212 if (sc->sc_flags & FXPF_MII) { 1213 /* Down the MII. */ 1214 mii_down(&sc->sc_mii); 1215 } 1216 1217 /* 1218 * Issue software reset 1219 */ 1220 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1221 DELAY(10); 1222 1223 /* 1224 * Release any xmit buffers. 1225 */ 1226 for (i = 0; i < FXP_NTXCB; i++) { 1227 txs = FXP_DSTX(sc, i); 1228 if (txs->txs_mbuf != NULL) { 1229 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1230 m_freem(txs->txs_mbuf); 1231 txs->txs_mbuf = NULL; 1232 } 1233 } 1234 sc->sc_txpending = 0; 1235 1236 if (drain) { 1237 /* 1238 * Release the receive buffers. 1239 */ 1240 fxp_rxdrain(sc); 1241 } 1242 1243 } 1244 1245 /* 1246 * Watchdog/transmission transmit timeout handler. Called when a 1247 * transmission is started on the interface, but no interrupt is 1248 * received before the timeout. This usually indicates that the 1249 * card has wedged for some reason. 1250 */ 1251 void 1252 fxp_watchdog(ifp) 1253 struct ifnet *ifp; 1254 { 1255 struct fxp_softc *sc = ifp->if_softc; 1256 1257 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1258 ifp->if_oerrors++; 1259 1260 (void) fxp_init(sc); 1261 } 1262 1263 /* 1264 * Initialize the interface. Must be called at splnet(). 1265 */ 1266 int 1267 fxp_init(sc) 1268 struct fxp_softc *sc; 1269 { 1270 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1271 struct fxp_cb_config *cbp; 1272 struct fxp_cb_ias *cb_ias; 1273 struct fxp_cb_tx *txd; 1274 bus_dmamap_t rxmap; 1275 int i, prm, allm, error = 0; 1276 1277 /* 1278 * Cancel any pending I/O 1279 */ 1280 fxp_stop(sc, 0); 1281 1282 /* 1283 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1284 * flag, and this prevents the MII from detaching resulting in 1285 * a panic. The flags field should perhaps be split in runtime 1286 * flags and more static information. For now, just clear the 1287 * only other flag set. 1288 */ 1289 1290 sc->sc_flags &= ~FXPF_WANTINIT; 1291 1292 /* 1293 * Initialize base of CBL and RFA memory. Loading with zero 1294 * sets it up for regular linear addressing. 1295 */ 1296 fxp_scb_wait(sc); 1297 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1298 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1299 1300 fxp_scb_wait(sc); 1301 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1302 1303 /* 1304 * Initialize the multicast filter. Do this now, since we might 1305 * have to setup the config block differently. 1306 */ 1307 fxp_mc_setup(sc); 1308 1309 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1310 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1311 1312 /* 1313 * Initialize base of dump-stats buffer. 1314 */ 1315 fxp_scb_wait(sc); 1316 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1317 sc->sc_cddma + FXP_CDSTATSOFF); 1318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1319 1320 cbp = &sc->sc_control_data->fcd_configcb; 1321 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1322 1323 /* 1324 * This copy is kind of disgusting, but there are a bunch of must be 1325 * zero and must be one bits in this structure and this is the easiest 1326 * way to initialize them all to proper values. 1327 */ 1328 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1329 1330 /* BIG_ENDIAN: no need to swap to store 0 */ 1331 cbp->cb_status = 0; 1332 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1333 FXP_CB_COMMAND_EL); 1334 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1335 cbp->link_addr = 0xffffffff; /* (no) next command */ 1336 cbp->byte_count = 22; /* (22) bytes to config */ 1337 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1338 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1339 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1340 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1341 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1342 cbp->dma_bce = 0; /* (disable) dma max counters */ 1343 cbp->late_scb = 0; /* (don't) defer SCB update */ 1344 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1345 cbp->ci_int = 1; /* interrupt on CU idle */ 1346 cbp->save_bf = prm; /* save bad frames */ 1347 cbp->disc_short_rx = !prm; /* discard short packets */ 1348 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1349 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1350 cbp->nsai = 1; /* (don't) disable source addr insert */ 1351 cbp->preamble_length = 2; /* (7 byte) preamble */ 1352 cbp->loopback = 0; /* (don't) loopback */ 1353 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1354 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1355 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1356 cbp->promiscuous = prm; /* promiscuous mode */ 1357 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1358 cbp->crscdt = 0; /* (CRS only) */ 1359 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1360 cbp->padding = 1; /* (do) pad short tx packets */ 1361 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1362 cbp->force_fdx = 0; /* (don't) force full duplex */ 1363 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1364 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1365 cbp->mc_all = allm; /* accept all multicasts */ 1366 1367 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1368 1369 /* 1370 * Start the config command/DMA. 1371 */ 1372 fxp_scb_wait(sc); 1373 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1374 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1375 /* ...and wait for it to complete. */ 1376 do { 1377 FXP_CDCONFIGSYNC(sc, 1378 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1379 } while ((cbp->cb_status & FXP_CB_STATUS_C) == 0); 1380 1381 /* 1382 * Initialize the station address. 1383 */ 1384 cb_ias = &sc->sc_control_data->fcd_iascb; 1385 /* BIG_ENDIAN: no need to swap to store 0 */ 1386 cb_ias->cb_status = 0; 1387 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1388 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1389 cb_ias->link_addr = 0xffffffff; 1390 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1391 1392 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1393 1394 /* 1395 * Start the IAS (Individual Address Setup) command/DMA. 1396 */ 1397 fxp_scb_wait(sc); 1398 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1399 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1400 /* ...and wait for it to complete. */ 1401 do { 1402 FXP_CDIASSYNC(sc, 1403 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1404 } while ((cb_ias->cb_status & FXP_CB_STATUS_C) == 0); 1405 1406 /* 1407 * Initialize the transmit descriptor ring. txlast is initialized 1408 * to the end of the list so that it will wrap around to the first 1409 * descriptor when the first packet is transmitted. 1410 */ 1411 for (i = 0; i < FXP_NTXCB; i++) { 1412 txd = FXP_CDTX(sc, i); 1413 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1414 txd->cb_command = 1415 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1416 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1417 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1418 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1419 } 1420 sc->sc_txpending = 0; 1421 sc->sc_txdirty = 0; 1422 sc->sc_txlast = FXP_NTXCB - 1; 1423 1424 /* 1425 * Initialize the receive buffer list. 1426 */ 1427 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1428 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1429 rxmap = FXP_RXMAP_GET(sc); 1430 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1431 printf("%s: unable to allocate or map rx " 1432 "buffer %d, error = %d\n", 1433 sc->sc_dev.dv_xname, 1434 sc->sc_rxq.ifq_len, error); 1435 /* 1436 * XXX Should attempt to run with fewer receive 1437 * XXX buffers instead of just failing. 1438 */ 1439 FXP_RXMAP_PUT(sc, rxmap); 1440 fxp_rxdrain(sc); 1441 goto out; 1442 } 1443 } 1444 sc->sc_rxidle = 0; 1445 1446 /* 1447 * Give the transmit ring to the chip. We do this by pointing 1448 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1449 * issuing a start command. It will execute the NOP and then 1450 * suspend, pointing at the first descriptor. 1451 */ 1452 fxp_scb_wait(sc); 1453 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1454 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1455 1456 /* 1457 * Initialize receiver buffer area - RFA. 1458 */ 1459 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1460 fxp_scb_wait(sc); 1461 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1462 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1463 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1464 1465 if (sc->sc_flags & FXPF_MII) { 1466 /* 1467 * Set current media. 1468 */ 1469 mii_mediachg(&sc->sc_mii); 1470 } 1471 1472 /* 1473 * ...all done! 1474 */ 1475 ifp->if_flags |= IFF_RUNNING; 1476 ifp->if_flags &= ~IFF_OACTIVE; 1477 1478 /* 1479 * Start the one second timer. 1480 */ 1481 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1482 1483 /* 1484 * Attempt to start output on the interface. 1485 */ 1486 fxp_start(ifp); 1487 1488 out: 1489 if (error) 1490 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1491 return (error); 1492 } 1493 1494 /* 1495 * Change media according to request. 1496 */ 1497 int 1498 fxp_mii_mediachange(ifp) 1499 struct ifnet *ifp; 1500 { 1501 struct fxp_softc *sc = ifp->if_softc; 1502 1503 if (ifp->if_flags & IFF_UP) 1504 mii_mediachg(&sc->sc_mii); 1505 return (0); 1506 } 1507 1508 /* 1509 * Notify the world which media we're using. 1510 */ 1511 void 1512 fxp_mii_mediastatus(ifp, ifmr) 1513 struct ifnet *ifp; 1514 struct ifmediareq *ifmr; 1515 { 1516 struct fxp_softc *sc = ifp->if_softc; 1517 1518 if(sc->sc_enabled == 0) { 1519 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1520 ifmr->ifm_status = 0; 1521 return; 1522 } 1523 1524 mii_pollstat(&sc->sc_mii); 1525 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1526 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1527 } 1528 1529 int 1530 fxp_80c24_mediachange(ifp) 1531 struct ifnet *ifp; 1532 { 1533 1534 /* Nothing to do here. */ 1535 return (0); 1536 } 1537 1538 void 1539 fxp_80c24_mediastatus(ifp, ifmr) 1540 struct ifnet *ifp; 1541 struct ifmediareq *ifmr; 1542 { 1543 struct fxp_softc *sc = ifp->if_softc; 1544 1545 /* 1546 * Media is currently-selected media. We cannot determine 1547 * the link status. 1548 */ 1549 ifmr->ifm_status = 0; 1550 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1551 } 1552 1553 /* 1554 * Add a buffer to the end of the RFA buffer list. 1555 * Return 0 if successful, error code on failure. 1556 * 1557 * The RFA struct is stuck at the beginning of mbuf cluster and the 1558 * data pointer is fixed up to point just past it. 1559 */ 1560 int 1561 fxp_add_rfabuf(sc, rxmap, unload) 1562 struct fxp_softc *sc; 1563 bus_dmamap_t rxmap; 1564 int unload; 1565 { 1566 struct mbuf *m; 1567 int error; 1568 1569 MGETHDR(m, M_DONTWAIT, MT_DATA); 1570 if (m == NULL) 1571 return (ENOBUFS); 1572 1573 MCLGET(m, M_DONTWAIT); 1574 if ((m->m_flags & M_EXT) == 0) { 1575 m_freem(m); 1576 return (ENOBUFS); 1577 } 1578 1579 if (unload) 1580 bus_dmamap_unload(sc->sc_dmat, rxmap); 1581 1582 M_SETCTX(m, rxmap); 1583 1584 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1585 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1586 if (error) { 1587 printf("%s: can't load rx DMA map %d, error = %d\n", 1588 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1589 panic("fxp_add_rfabuf"); /* XXX */ 1590 } 1591 1592 FXP_INIT_RFABUF(sc, m); 1593 1594 return (0); 1595 } 1596 1597 volatile int 1598 fxp_mdi_read(self, phy, reg) 1599 struct device *self; 1600 int phy; 1601 int reg; 1602 { 1603 struct fxp_softc *sc = (struct fxp_softc *)self; 1604 int count = 10000; 1605 int value; 1606 1607 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1608 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1609 1610 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1611 && count--) 1612 DELAY(10); 1613 1614 if (count <= 0) 1615 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1616 1617 return (value & 0xffff); 1618 } 1619 1620 void 1621 fxp_statchg(self) 1622 struct device *self; 1623 { 1624 1625 /* Nothing to do. */ 1626 } 1627 1628 void 1629 fxp_mdi_write(self, phy, reg, value) 1630 struct device *self; 1631 int phy; 1632 int reg; 1633 int value; 1634 { 1635 struct fxp_softc *sc = (struct fxp_softc *)self; 1636 int count = 10000; 1637 1638 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1639 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1640 (value & 0xffff)); 1641 1642 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1643 count--) 1644 DELAY(10); 1645 1646 if (count <= 0) 1647 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1648 } 1649 1650 int 1651 fxp_ioctl(ifp, command, data) 1652 struct ifnet *ifp; 1653 u_long command; 1654 caddr_t data; 1655 { 1656 struct fxp_softc *sc = ifp->if_softc; 1657 struct ifreq *ifr = (struct ifreq *)data; 1658 struct ifaddr *ifa = (struct ifaddr *)data; 1659 int s, error = 0; 1660 1661 s = splnet(); 1662 1663 switch (command) { 1664 case SIOCSIFADDR: 1665 if ((error = fxp_enable(sc)) != 0) 1666 break; 1667 ifp->if_flags |= IFF_UP; 1668 1669 switch (ifa->ifa_addr->sa_family) { 1670 #ifdef INET 1671 case AF_INET: 1672 if ((error = fxp_init(sc)) != 0) 1673 break; 1674 arp_ifinit(ifp, ifa); 1675 break; 1676 #endif /* INET */ 1677 #ifdef NS 1678 case AF_NS: 1679 { 1680 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1681 1682 if (ns_nullhost(*ina)) 1683 ina->x_host = *(union ns_host *) 1684 LLADDR(ifp->if_sadl); 1685 else 1686 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1687 ifp->if_addrlen); 1688 /* Set new address. */ 1689 error = fxp_init(sc); 1690 break; 1691 } 1692 #endif /* NS */ 1693 default: 1694 error = fxp_init(sc); 1695 break; 1696 } 1697 break; 1698 1699 case SIOCSIFMTU: 1700 if (ifr->ifr_mtu > ETHERMTU) 1701 error = EINVAL; 1702 else 1703 ifp->if_mtu = ifr->ifr_mtu; 1704 break; 1705 1706 case SIOCSIFFLAGS: 1707 if ((ifp->if_flags & IFF_UP) == 0 && 1708 (ifp->if_flags & IFF_RUNNING) != 0) { 1709 /* 1710 * If interface is marked down and it is running, then 1711 * stop it. 1712 */ 1713 fxp_stop(sc, 1); 1714 fxp_disable(sc); 1715 } else if ((ifp->if_flags & IFF_UP) != 0 && 1716 (ifp->if_flags & IFF_RUNNING) == 0) { 1717 /* 1718 * If interface is marked up and it is stopped, then 1719 * start it. 1720 */ 1721 if((error = fxp_enable(sc)) != 0) 1722 break; 1723 error = fxp_init(sc); 1724 } else if ((ifp->if_flags & IFF_UP) != 0) { 1725 /* 1726 * Reset the interface to pick up change in any other 1727 * flags that affect the hardware state. 1728 */ 1729 if((error = fxp_enable(sc)) != 0) 1730 break; 1731 error = fxp_init(sc); 1732 } 1733 break; 1734 1735 case SIOCADDMULTI: 1736 case SIOCDELMULTI: 1737 if(sc->sc_enabled == 0) { 1738 error = EIO; 1739 break; 1740 } 1741 error = (command == SIOCADDMULTI) ? 1742 ether_addmulti(ifr, &sc->sc_ethercom) : 1743 ether_delmulti(ifr, &sc->sc_ethercom); 1744 1745 if (error == ENETRESET) { 1746 /* 1747 * Multicast list has changed; set the hardware 1748 * filter accordingly. 1749 */ 1750 if (sc->sc_txpending) { 1751 sc->sc_flags |= FXPF_WANTINIT; 1752 error = 0; 1753 } else 1754 error = fxp_init(sc); 1755 } 1756 break; 1757 1758 case SIOCSIFMEDIA: 1759 case SIOCGIFMEDIA: 1760 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1761 break; 1762 1763 default: 1764 error = EINVAL; 1765 break; 1766 } 1767 1768 splx(s); 1769 return (error); 1770 } 1771 1772 /* 1773 * Program the multicast filter. 1774 * 1775 * This function must be called at splnet(). 1776 */ 1777 void 1778 fxp_mc_setup(sc) 1779 struct fxp_softc *sc; 1780 { 1781 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1782 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1783 struct ethercom *ec = &sc->sc_ethercom; 1784 struct ether_multi *enm; 1785 struct ether_multistep step; 1786 int nmcasts; 1787 1788 #ifdef DIAGNOSTIC 1789 if (sc->sc_txpending) 1790 panic("fxp_mc_setup: pending transmissions"); 1791 #endif 1792 1793 ifp->if_flags &= ~IFF_ALLMULTI; 1794 1795 /* 1796 * Initialize multicast setup descriptor. 1797 */ 1798 nmcasts = 0; 1799 ETHER_FIRST_MULTI(step, ec, enm); 1800 while (enm != NULL) { 1801 /* 1802 * Check for too many multicast addresses or if we're 1803 * listening to a range. Either way, we simply have 1804 * to accept all multicasts. 1805 */ 1806 if (nmcasts >= MAXMCADDR || 1807 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1808 ETHER_ADDR_LEN) != 0) { 1809 /* 1810 * Callers of this function must do the 1811 * right thing with this. If we're called 1812 * from outside fxp_init(), the caller must 1813 * detect if the state if IFF_ALLMULTI changes. 1814 * If it does, the caller must then call 1815 * fxp_init(), since allmulti is handled by 1816 * the config block. 1817 */ 1818 ifp->if_flags |= IFF_ALLMULTI; 1819 return; 1820 } 1821 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1822 ETHER_ADDR_LEN); 1823 nmcasts++; 1824 ETHER_NEXT_MULTI(step, enm); 1825 } 1826 1827 /* BIG_ENDIAN: no need to swap to store 0 */ 1828 mcsp->cb_status = 0; 1829 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1830 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1831 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1832 1833 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1834 1835 /* 1836 * Wait until the command unit is not active. This should never 1837 * happen since nothing is queued, but make sure anyway. 1838 */ 1839 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1840 FXP_SCB_CUS_ACTIVE) 1841 /* nothing */ ; 1842 1843 /* 1844 * Start the multicast setup command/DMA. 1845 */ 1846 fxp_scb_wait(sc); 1847 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1848 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1849 1850 /* ...and wait for it to complete. */ 1851 do { 1852 FXP_CDMCSSYNC(sc, 1853 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1854 } while ((mcsp->cb_status & FXP_CB_STATUS_C) == 0); 1855 } 1856 1857 int 1858 fxp_enable(sc) 1859 struct fxp_softc *sc; 1860 { 1861 1862 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1863 if ((*sc->sc_enable)(sc) != 0) { 1864 printf("%s: device enable failed\n", 1865 sc->sc_dev.dv_xname); 1866 return (EIO); 1867 } 1868 } 1869 1870 sc->sc_enabled = 1; 1871 return (0); 1872 } 1873 1874 void 1875 fxp_disable(sc) 1876 struct fxp_softc *sc; 1877 { 1878 1879 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1880 (*sc->sc_disable)(sc); 1881 sc->sc_enabled = 0; 1882 } 1883 } 1884 1885 /* 1886 * fxp_activate: 1887 * 1888 * Handle device activation/deactivation requests. 1889 */ 1890 int 1891 fxp_activate(self, act) 1892 struct device *self; 1893 enum devact act; 1894 { 1895 struct fxp_softc *sc = (void *) self; 1896 int s, error = 0; 1897 1898 s = splnet(); 1899 switch (act) { 1900 case DVACT_ACTIVATE: 1901 error = EOPNOTSUPP; 1902 break; 1903 1904 case DVACT_DEACTIVATE: 1905 if (sc->sc_flags & FXPF_MII) 1906 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1907 MII_OFFSET_ANY); 1908 if_deactivate(&sc->sc_ethercom.ec_if); 1909 break; 1910 } 1911 splx(s); 1912 1913 return (error); 1914 } 1915 1916 /* 1917 * fxp_detach: 1918 * 1919 * Detach an i82557 interface. 1920 */ 1921 int 1922 fxp_detach(sc) 1923 struct fxp_softc *sc; 1924 { 1925 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1926 int i; 1927 1928 /* Unhook our tick handler. */ 1929 callout_stop(&sc->sc_callout); 1930 1931 if (sc->sc_flags & FXPF_MII) { 1932 /* Detach all PHYs */ 1933 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1934 } 1935 1936 /* Delete all remaining media. */ 1937 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1938 1939 #if NRND > 0 1940 rnd_detach_source(&sc->rnd_source); 1941 #endif 1942 #if NBPFILTER > 0 1943 bpfdetach(ifp); 1944 #endif 1945 ether_ifdetach(ifp); 1946 if_detach(ifp); 1947 1948 for (i = 0; i < FXP_NRFABUFS; i++) { 1949 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1950 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1951 } 1952 1953 for (i = 0; i < FXP_NTXCB; i++) { 1954 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1955 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1956 } 1957 1958 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1959 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1960 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1961 sizeof(struct fxp_control_data)); 1962 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1963 1964 shutdownhook_disestablish(sc->sc_sdhook); 1965 powerhook_disestablish(sc->sc_powerhook); 1966 1967 return (0); 1968 } 1969
Indexes created Mon Sep 29 21:09:56 GMT 2025