i82557.c revision 1.34.2.3
1 /* $NetBSD: i82557.c,v 1.34.2.3 2001/05/06 15:04:55 he Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <vm/vm.h> /* for PAGE_SIZE */ 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia __P((struct fxp_softc *)); 169 int fxp_mii_mediachange __P((struct ifnet *)); 170 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 void fxp_80c24_initmedia __P((struct fxp_softc *)); 173 int fxp_80c24_mediachange __P((struct ifnet *)); 174 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176 inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178 void fxp_start __P((struct ifnet *)); 179 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180 int fxp_init __P((struct fxp_softc *)); 181 void fxp_rxdrain __P((struct fxp_softc *)); 182 void fxp_stop __P((struct fxp_softc *, int)); 183 void fxp_watchdog __P((struct ifnet *)); 184 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 185 int fxp_mdi_read __P((struct device *, int, int)); 186 void fxp_statchg __P((struct device *)); 187 void fxp_mdi_write __P((struct device *, int, int, int)); 188 void fxp_autosize_eeprom __P((struct fxp_softc*)); 189 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 190 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 191 void fxp_tick __P((void *)); 192 void fxp_mc_setup __P((struct fxp_softc *)); 193 194 void fxp_shutdown __P((void *)); 195 void fxp_power __P((int, void *)); 196 197 int fxp_copy_small = 0; 198 199 struct fxp_phytype { 200 int fp_phy; /* type of PHY, -1 for MII at the end. */ 201 void (*fp_init) __P((struct fxp_softc *)); 202 } fxp_phytype_table[] = { 203 { FXP_PHY_80C24, fxp_80c24_initmedia }, 204 { -1, fxp_mii_initmedia }, 205 }; 206 207 /* 208 * Set initial transmit threshold at 64 (512 bytes). This is 209 * increased by 64 (512 bytes) at a time, to maximum of 192 210 * (1536 bytes), if an underrun occurs. 211 */ 212 static int tx_threshold = 64; 213 214 /* 215 * Wait for the previous command to be accepted (but not necessarily 216 * completed). 217 */ 218 inline void 219 fxp_scb_wait(sc) 220 struct fxp_softc *sc; 221 { 222 int i = 10000; 223 224 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 225 delay(2); 226 if (i == 0) 227 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 228 } 229 230 /* 231 * Finish attaching an i82557 interface. Called by bus-specific front-end. 232 */ 233 void 234 fxp_attach(sc) 235 struct fxp_softc *sc; 236 { 237 u_int8_t enaddr[6]; 238 struct ifnet *ifp; 239 bus_dma_segment_t seg; 240 int rseg, i, error; 241 struct fxp_phytype *fp; 242 243 callout_init(&sc->sc_callout); 244 245 /* 246 * Allocate the control data structures, and create and load the 247 * DMA map for it. 248 */ 249 if ((error = bus_dmamem_alloc(sc->sc_dmat, 250 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 251 0)) != 0) { 252 printf("%s: unable to allocate control data, error = %d\n", 253 sc->sc_dev.dv_xname, error); 254 goto fail_0; 255 } 256 257 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 258 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 259 BUS_DMA_COHERENT)) != 0) { 260 printf("%s: unable to map control data, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 goto fail_1; 263 } 264 sc->sc_cdseg = seg; 265 sc->sc_cdnseg = rseg; 266 267 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 268 269 if ((error = bus_dmamap_create(sc->sc_dmat, 270 sizeof(struct fxp_control_data), 1, 271 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 272 printf("%s: unable to create control data DMA map, " 273 "error = %d\n", sc->sc_dev.dv_xname, error); 274 goto fail_2; 275 } 276 277 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 278 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 279 0)) != 0) { 280 printf("%s: can't load control data DMA map, error = %d\n", 281 sc->sc_dev.dv_xname, error); 282 goto fail_3; 283 } 284 285 /* 286 * Create the transmit buffer DMA maps. 287 */ 288 for (i = 0; i < FXP_NTXCB; i++) { 289 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 290 FXP_NTXSEG, MCLBYTES, 0, 0, 291 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 292 printf("%s: unable to create tx DMA map %d, " 293 "error = %d\n", sc->sc_dev.dv_xname, i, error); 294 goto fail_4; 295 } 296 } 297 298 /* 299 * Create the receive buffer DMA maps. 300 */ 301 for (i = 0; i < FXP_NRFABUFS; i++) { 302 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 303 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 304 printf("%s: unable to create rx DMA map %d, " 305 "error = %d\n", sc->sc_dev.dv_xname, i, error); 306 goto fail_5; 307 } 308 } 309 310 /* Initialize MAC address and media structures. */ 311 fxp_get_info(sc, enaddr); 312 313 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 314 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 315 316 ifp = &sc->sc_ethercom.ec_if; 317 318 /* 319 * Get info about our media interface, and initialize it. Note 320 * the table terminates itself with a phy of -1, indicating 321 * that we're using MII. 322 */ 323 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 324 if (fp->fp_phy == sc->phy_primary_device) 325 break; 326 (*fp->fp_init)(sc); 327 328 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 329 ifp->if_softc = sc; 330 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 331 ifp->if_ioctl = fxp_ioctl; 332 ifp->if_start = fxp_start; 333 ifp->if_watchdog = fxp_watchdog; 334 335 /* 336 * We can support 802.1Q VLAN-sized frames. 337 */ 338 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 339 340 /* 341 * Attach the interface. 342 */ 343 if_attach(ifp); 344 ether_ifattach(ifp, enaddr); 345 #if NBPFILTER > 0 346 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 347 sizeof(struct ether_header)); 348 #endif 349 #if NRND > 0 350 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 351 RND_TYPE_NET, 0); 352 #endif 353 354 /* 355 * Add shutdown hook so that DMA is disabled prior to reboot. Not 356 * doing do could allow DMA to corrupt kernel memory during the 357 * reboot before the driver initializes. 358 */ 359 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 360 if (sc->sc_sdhook == NULL) 361 printf("%s: WARNING: unable to establish shutdown hook\n", 362 sc->sc_dev.dv_xname); 363 /* 364 * Add suspend hook, for similar reasons.. 365 */ 366 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 367 if (sc->sc_powerhook == NULL) 368 printf("%s: WARNING: unable to establish power hook\n", 369 sc->sc_dev.dv_xname); 370 371 /* The attach is successful. */ 372 sc->sc_flags |= FXPF_ATTACHED; 373 374 return; 375 376 /* 377 * Free any resources we've allocated during the failed attach 378 * attempt. Do this in reverse order and fall though. 379 */ 380 fail_5: 381 for (i = 0; i < FXP_NRFABUFS; i++) { 382 if (sc->sc_rxmaps[i] != NULL) 383 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 384 } 385 fail_4: 386 for (i = 0; i < FXP_NTXCB; i++) { 387 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 388 bus_dmamap_destroy(sc->sc_dmat, 389 FXP_DSTX(sc, i)->txs_dmamap); 390 } 391 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 392 fail_3: 393 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 394 fail_2: 395 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 396 sizeof(struct fxp_control_data)); 397 fail_1: 398 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 399 fail_0: 400 return; 401 } 402 403 void 404 fxp_mii_initmedia(sc) 405 struct fxp_softc *sc; 406 { 407 408 sc->sc_flags |= FXPF_MII; 409 410 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 411 sc->sc_mii.mii_readreg = fxp_mdi_read; 412 sc->sc_mii.mii_writereg = fxp_mdi_write; 413 sc->sc_mii.mii_statchg = fxp_statchg; 414 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 415 fxp_mii_mediastatus); 416 /* 417 * The i82557 wedges if all of its PHYs are isolated! 418 */ 419 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 420 MII_OFFSET_ANY, MIIF_NOISOLATE); 421 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 422 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 423 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 424 } else 425 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 426 } 427 428 void 429 fxp_80c24_initmedia(sc) 430 struct fxp_softc *sc; 431 { 432 433 /* 434 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 435 * doesn't have a programming interface of any sort. The 436 * media is sensed automatically based on how the link partner 437 * is configured. This is, in essence, manual configuration. 438 */ 439 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 440 sc->sc_dev.dv_xname); 441 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 442 fxp_80c24_mediastatus); 443 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 444 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 445 } 446 447 /* 448 * Device shutdown routine. Called at system shutdown after sync. The 449 * main purpose of this routine is to shut off receiver DMA so that 450 * kernel memory doesn't get clobbered during warmboot. 451 */ 452 void 453 fxp_shutdown(arg) 454 void *arg; 455 { 456 struct fxp_softc *sc = arg; 457 458 /* 459 * Since the system's going to halt shortly, don't bother 460 * freeing mbufs. 461 */ 462 fxp_stop(sc, 0); 463 } 464 /* 465 * Power handler routine. Called when the system is transitioning 466 * into/out of power save modes. As with fxp_shutdown, the main 467 * purpose of this routine is to shut off receiver DMA so it doesn't 468 * clobber kernel memory at the wrong time. 469 */ 470 void 471 fxp_power(why, arg) 472 int why; 473 void *arg; 474 { 475 struct fxp_softc *sc = arg; 476 struct ifnet *ifp; 477 int s; 478 479 s = splnet(); 480 switch (why) { 481 case PWR_SUSPEND: 482 case PWR_STANDBY: 483 fxp_stop(sc, 0); 484 break; 485 case PWR_RESUME: 486 ifp = &sc->sc_ethercom.ec_if; 487 if (ifp->if_flags & IFF_UP) 488 fxp_init(sc); 489 break; 490 case PWR_SOFTSUSPEND: 491 case PWR_SOFTSTANDBY: 492 case PWR_SOFTRESUME: 493 break; 494 } 495 splx(s); 496 } 497 498 /* 499 * Initialize the interface media. 500 */ 501 void 502 fxp_get_info(sc, enaddr) 503 struct fxp_softc *sc; 504 u_int8_t *enaddr; 505 { 506 u_int16_t data, myea[3]; 507 508 /* 509 * Reset to a stable state. 510 */ 511 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 512 DELAY(10); 513 514 sc->sc_eeprom_size = 0; 515 fxp_autosize_eeprom(sc); 516 if(sc->sc_eeprom_size == 0) { 517 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 518 sc->sc_eeprom_size = 6; /* XXX panic here? */ 519 } 520 #ifdef DEBUG 521 printf("%s: detected %d word EEPROM\n", 522 sc->sc_dev.dv_xname, 523 1 << sc->sc_eeprom_size); 524 #endif 525 526 /* 527 * Get info about the primary PHY 528 */ 529 fxp_read_eeprom(sc, &data, 6, 1); 530 sc->phy_primary_addr = data & 0xff; 531 sc->phy_primary_device = (data >> 8) & 0x3f; 532 sc->phy_10Mbps_only = data >> 15; 533 534 /* 535 * Read MAC address. 536 */ 537 fxp_read_eeprom(sc, myea, 0, 3); 538 enaddr[0] = myea[0] & 0xff; 539 enaddr[1] = myea[0] >> 8; 540 enaddr[2] = myea[1] & 0xff; 541 enaddr[3] = myea[1] >> 8; 542 enaddr[4] = myea[2] & 0xff; 543 enaddr[5] = myea[2] >> 8; 544 } 545 546 /* 547 * Figure out EEPROM size. 548 * 549 * 559's can have either 64-word or 256-word EEPROMs, the 558 550 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 551 * talks about the existance of 16 to 256 word EEPROMs. 552 * 553 * The only known sizes are 64 and 256, where the 256 version is used 554 * by CardBus cards to store CIS information. 555 * 556 * The address is shifted in msb-to-lsb, and after the last 557 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 558 * after which follows the actual data. We try to detect this zero, by 559 * probing the data-out bit in the EEPROM control register just after 560 * having shifted in a bit. If the bit is zero, we assume we've 561 * shifted enough address bits. The data-out should be tri-state, 562 * before this, which should translate to a logical one. 563 * 564 * Other ways to do this would be to try to read a register with known 565 * contents with a varying number of address bits, but no such 566 * register seem to be available. The high bits of register 10 are 01 567 * on the 558 and 559, but apparently not on the 557. 568 * 569 * The Linux driver computes a checksum on the EEPROM data, but the 570 * value of this checksum is not very well documented. 571 */ 572 573 void 574 fxp_autosize_eeprom(sc) 575 struct fxp_softc *sc; 576 { 577 u_int16_t reg; 578 int x; 579 580 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 581 /* 582 * Shift in read opcode. 583 */ 584 for (x = 3; x > 0; x--) { 585 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 586 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 587 } else { 588 reg = FXP_EEPROM_EECS; 589 } 590 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 591 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 592 reg | FXP_EEPROM_EESK); 593 DELAY(4); 594 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 595 DELAY(4); 596 } 597 /* 598 * Shift in address, wait for the dummy zero following a correct 599 * address shift. 600 */ 601 for (x = 1; x <= 8; x++) { 602 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 603 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 604 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 605 DELAY(4); 606 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 607 FXP_EEPROM_EEDO) == 0) 608 break; 609 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 610 DELAY(4); 611 } 612 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 613 DELAY(4); 614 if(x != 6 && x != 8) { 615 #ifdef DEBUG 616 printf("%s: strange EEPROM size (%d)\n", 617 sc->sc_dev.dv_xname, 1 << x); 618 #endif 619 } else 620 sc->sc_eeprom_size = x; 621 } 622 623 /* 624 * Read from the serial EEPROM. Basically, you manually shift in 625 * the read opcode (one bit at a time) and then shift in the address, 626 * and then you shift out the data (all of this one bit at a time). 627 * The word size is 16 bits, so you have to provide the address for 628 * every 16 bits of data. 629 */ 630 void 631 fxp_read_eeprom(sc, data, offset, words) 632 struct fxp_softc *sc; 633 u_int16_t *data; 634 int offset; 635 int words; 636 { 637 u_int16_t reg; 638 int i, x; 639 640 for (i = 0; i < words; i++) { 641 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 642 /* 643 * Shift in read opcode. 644 */ 645 for (x = 3; x > 0; x--) { 646 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 647 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 648 } else { 649 reg = FXP_EEPROM_EECS; 650 } 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 652 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 653 reg | FXP_EEPROM_EESK); 654 DELAY(4); 655 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 656 DELAY(4); 657 } 658 /* 659 * Shift in address. 660 */ 661 for (x = sc->sc_eeprom_size; x > 0; x--) { 662 if ((i + offset) & (1 << (x - 1))) { 663 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 664 } else { 665 reg = FXP_EEPROM_EECS; 666 } 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 668 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 669 reg | FXP_EEPROM_EESK); 670 DELAY(4); 671 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 672 DELAY(4); 673 } 674 reg = FXP_EEPROM_EECS; 675 data[i] = 0; 676 /* 677 * Shift out data. 678 */ 679 for (x = 16; x > 0; x--) { 680 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 681 reg | FXP_EEPROM_EESK); 682 DELAY(4); 683 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 684 FXP_EEPROM_EEDO) 685 data[i] |= (1 << (x - 1)); 686 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 687 DELAY(4); 688 } 689 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 690 DELAY(4); 691 } 692 } 693 694 /* 695 * Start packet transmission on the interface. 696 */ 697 void 698 fxp_start(ifp) 699 struct ifnet *ifp; 700 { 701 struct fxp_softc *sc = ifp->if_softc; 702 struct mbuf *m0, *m; 703 struct fxp_cb_tx *txd; 704 struct fxp_txsoft *txs; 705 struct fxp_tbdlist *tbd; 706 bus_dmamap_t dmamap; 707 int error, lasttx, nexttx, opending, seg; 708 709 /* 710 * If we want a re-init, bail out now. 711 */ 712 if (sc->sc_flags & FXPF_WANTINIT) { 713 ifp->if_flags |= IFF_OACTIVE; 714 return; 715 } 716 717 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 718 return; 719 720 /* 721 * Remember the previous txpending and the current lasttx. 722 */ 723 opending = sc->sc_txpending; 724 lasttx = sc->sc_txlast; 725 726 /* 727 * Loop through the send queue, setting up transmit descriptors 728 * until we drain the queue, or use up all available transmit 729 * descriptors. 730 */ 731 while (sc->sc_txpending < FXP_NTXCB) { 732 /* 733 * Grab a packet off the queue. 734 */ 735 IF_DEQUEUE(&ifp->if_snd, m0); 736 if (m0 == NULL) 737 break; 738 739 /* 740 * Get the next available transmit descriptor. 741 */ 742 nexttx = FXP_NEXTTX(sc->sc_txlast); 743 txd = FXP_CDTX(sc, nexttx); 744 tbd = FXP_CDTBD(sc, nexttx); 745 txs = FXP_DSTX(sc, nexttx); 746 dmamap = txs->txs_dmamap; 747 748 /* 749 * Load the DMA map. If this fails, the packet either 750 * didn't fit in the allotted number of frags, or we were 751 * short on resources. In this case, we'll copy and try 752 * again. 753 */ 754 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 755 BUS_DMA_NOWAIT) != 0) { 756 MGETHDR(m, M_DONTWAIT, MT_DATA); 757 if (m == NULL) { 758 printf("%s: unable to allocate Tx mbuf\n", 759 sc->sc_dev.dv_xname); 760 IF_PREPEND(&ifp->if_snd, m0); 761 break; 762 } 763 if (m0->m_pkthdr.len > MHLEN) { 764 MCLGET(m, M_DONTWAIT); 765 if ((m->m_flags & M_EXT) == 0) { 766 printf("%s: unable to allocate Tx " 767 "cluster\n", sc->sc_dev.dv_xname); 768 m_freem(m); 769 IF_PREPEND(&ifp->if_snd, m0); 770 break; 771 } 772 } 773 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 774 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 775 m_freem(m0); 776 m0 = m; 777 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 778 m0, BUS_DMA_NOWAIT); 779 if (error) { 780 printf("%s: unable to load Tx buffer, " 781 "error = %d\n", sc->sc_dev.dv_xname, error); 782 IF_PREPEND(&ifp->if_snd, m0); 783 break; 784 } 785 } 786 787 /* Initialize the fraglist. */ 788 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 789 tbd->tbd_d[seg].tb_addr = 790 htole32(dmamap->dm_segs[seg].ds_addr); 791 tbd->tbd_d[seg].tb_size = 792 htole32(dmamap->dm_segs[seg].ds_len); 793 } 794 795 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 796 797 /* Sync the DMA map. */ 798 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 799 BUS_DMASYNC_PREWRITE); 800 801 /* 802 * Store a pointer to the packet so we can free it later. 803 */ 804 txs->txs_mbuf = m0; 805 806 /* 807 * Initialize the transmit descriptor. 808 */ 809 /* BIG_ENDIAN: no need to swap to store 0 */ 810 txd->cb_status = 0; 811 txd->cb_command = 812 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 813 txd->tx_threshold = tx_threshold; 814 txd->tbd_number = dmamap->dm_nsegs; 815 816 FXP_CDTXSYNC(sc, nexttx, 817 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 818 819 /* Advance the tx pointer. */ 820 sc->sc_txpending++; 821 sc->sc_txlast = nexttx; 822 823 #if NBPFILTER > 0 824 /* 825 * Pass packet to bpf if there is a listener. 826 */ 827 if (ifp->if_bpf) 828 bpf_mtap(ifp->if_bpf, m0); 829 #endif 830 } 831 832 if (sc->sc_txpending == FXP_NTXCB) { 833 /* No more slots; notify upper layer. */ 834 ifp->if_flags |= IFF_OACTIVE; 835 } 836 837 if (sc->sc_txpending != opending) { 838 /* 839 * We enqueued packets. If the transmitter was idle, 840 * reset the txdirty pointer. 841 */ 842 if (opending == 0) 843 sc->sc_txdirty = FXP_NEXTTX(lasttx); 844 845 /* 846 * Cause the chip to interrupt and suspend command 847 * processing once the last packet we've enqueued 848 * has been transmitted. 849 */ 850 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 851 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 852 FXP_CDTXSYNC(sc, sc->sc_txlast, 853 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 854 855 /* 856 * The entire packet chain is set up. Clear the suspend bit 857 * on the command prior to the first packet we set up. 858 */ 859 FXP_CDTXSYNC(sc, lasttx, 860 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 861 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 862 FXP_CDTXSYNC(sc, lasttx, 863 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 864 865 /* 866 * Issue a Resume command in case the chip was suspended. 867 */ 868 fxp_scb_wait(sc); 869 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 870 871 /* Set a watchdog timer in case the chip flakes out. */ 872 ifp->if_timer = 5; 873 } 874 } 875 876 /* 877 * Process interface interrupts. 878 */ 879 int 880 fxp_intr(arg) 881 void *arg; 882 { 883 struct fxp_softc *sc = arg; 884 struct ethercom *ec = &sc->sc_ethercom; 885 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 886 struct fxp_cb_tx *txd; 887 struct fxp_txsoft *txs; 888 struct mbuf *m, *m0; 889 bus_dmamap_t rxmap; 890 struct fxp_rfa *rfa; 891 struct ether_header *eh; 892 int i, claimed = 0; 893 u_int16_t len, rxstat, txstat; 894 u_int8_t statack; 895 896 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 897 return (0); 898 /* 899 * If the interface isn't running, don't try to 900 * service the interrupt.. just ack it and bail. 901 */ 902 if ((ifp->if_flags & IFF_RUNNING) == 0) { 903 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 904 if (statack) { 905 claimed = 1; 906 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 907 } 908 return (claimed); 909 } 910 911 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 912 claimed = 1; 913 914 /* 915 * First ACK all the interrupts in this pass. 916 */ 917 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 918 919 /* 920 * Process receiver interrupts. If a no-resource (RNR) 921 * condition exists, get whatever packets we can and 922 * re-start the receiver. 923 */ 924 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 925 rcvloop: 926 m = sc->sc_rxq.ifq_head; 927 rfa = FXP_MTORFA(m); 928 rxmap = M_GETCTX(m, bus_dmamap_t); 929 930 FXP_RFASYNC(sc, m, 931 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 932 933 rxstat = le16toh(rfa->rfa_status); 934 935 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 936 /* 937 * We have processed all of the 938 * receive buffers. 939 */ 940 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 941 goto do_transmit; 942 } 943 944 IF_DEQUEUE(&sc->sc_rxq, m); 945 946 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 947 948 len = le16toh(rfa->actual_size) & 949 (m->m_ext.ext_size - 1); 950 951 if (len < sizeof(struct ether_header)) { 952 /* 953 * Runt packet; drop it now. 954 */ 955 FXP_INIT_RFABUF(sc, m); 956 goto rcvloop; 957 } 958 959 /* 960 * If support for 802.1Q VLAN sized frames is 961 * enabled, we need to do some additional error 962 * checking (as we are saving bad frames, in 963 * order to receive the larger ones). 964 */ 965 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 966 (rxstat & (FXP_RFA_STATUS_OVERRUN| 967 FXP_RFA_STATUS_RNR| 968 FXP_RFA_STATUS_ALIGN| 969 FXP_RFA_STATUS_CRC)) != 0) { 970 FXP_INIT_RFABUF(sc, m); 971 goto rcvloop; 972 } 973 974 /* 975 * If the packet is small enough to fit in a 976 * single header mbuf, allocate one and copy 977 * the data into it. This greatly reduces 978 * memory consumption when we receive lots 979 * of small packets. 980 * 981 * Otherwise, we add a new buffer to the receive 982 * chain. If this fails, we drop the packet and 983 * recycle the old buffer. 984 */ 985 if (fxp_copy_small != 0 && len <= MHLEN) { 986 MGETHDR(m0, M_DONTWAIT, MT_DATA); 987 if (m == NULL) 988 goto dropit; 989 memcpy(mtod(m0, caddr_t), 990 mtod(m, caddr_t), len); 991 FXP_INIT_RFABUF(sc, m); 992 m = m0; 993 } else { 994 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 995 dropit: 996 ifp->if_ierrors++; 997 FXP_INIT_RFABUF(sc, m); 998 goto rcvloop; 999 } 1000 } 1001 1002 m->m_pkthdr.rcvif = ifp; 1003 m->m_pkthdr.len = m->m_len = len; 1004 eh = mtod(m, struct ether_header *); 1005 1006 #if NBPFILTER > 0 1007 /* 1008 * Pass this up to any BPF listeners, but only 1009 * pass it up the stack it its for us. 1010 */ 1011 if (ifp->if_bpf) { 1012 bpf_mtap(ifp->if_bpf, m); 1013 1014 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1015 (rxstat & FXP_RFA_STATUS_IAMATCH) != 0 && 1016 (eh->ether_dhost[0] & 1) == 0) { 1017 m_freem(m); 1018 goto rcvloop; 1019 } 1020 } 1021 #endif /* NBPFILTER > 0 */ 1022 1023 /* Pass it on. */ 1024 (*ifp->if_input)(ifp, m); 1025 goto rcvloop; 1026 } 1027 1028 do_transmit: 1029 if (statack & FXP_SCB_STATACK_RNR) { 1030 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1031 fxp_scb_wait(sc); 1032 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1033 rxmap->dm_segs[0].ds_addr + 1034 RFA_ALIGNMENT_FUDGE); 1035 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1036 FXP_SCB_COMMAND_RU_START); 1037 } 1038 1039 /* 1040 * Free any finished transmit mbuf chains. 1041 */ 1042 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1043 ifp->if_flags &= ~IFF_OACTIVE; 1044 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1045 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1046 txd = FXP_CDTX(sc, i); 1047 txs = FXP_DSTX(sc, i); 1048 1049 FXP_CDTXSYNC(sc, i, 1050 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1051 1052 txstat = le16toh(txd->cb_status); 1053 1054 if ((txstat & FXP_CB_STATUS_C) == 0) 1055 break; 1056 1057 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1058 1059 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1060 0, txs->txs_dmamap->dm_mapsize, 1061 BUS_DMASYNC_POSTWRITE); 1062 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1063 m_freem(txs->txs_mbuf); 1064 txs->txs_mbuf = NULL; 1065 } 1066 1067 /* Update the dirty transmit buffer pointer. */ 1068 sc->sc_txdirty = i; 1069 1070 /* 1071 * Cancel the watchdog timer if there are no pending 1072 * transmissions. 1073 */ 1074 if (sc->sc_txpending == 0) { 1075 ifp->if_timer = 0; 1076 1077 /* 1078 * If we want a re-init, do that now. 1079 */ 1080 if (sc->sc_flags & FXPF_WANTINIT) 1081 (void) fxp_init(sc); 1082 } 1083 1084 /* 1085 * Try to get more packets going. 1086 */ 1087 fxp_start(ifp); 1088 } 1089 } 1090 1091 #if NRND > 0 1092 if (claimed) 1093 rnd_add_uint32(&sc->rnd_source, statack); 1094 #endif 1095 return (claimed); 1096 } 1097 1098 /* 1099 * Update packet in/out/collision statistics. The i82557 doesn't 1100 * allow you to access these counters without doing a fairly 1101 * expensive DMA to get _all_ of the statistics it maintains, so 1102 * we do this operation here only once per second. The statistics 1103 * counters in the kernel are updated from the previous dump-stats 1104 * DMA and then a new dump-stats DMA is started. The on-chip 1105 * counters are zeroed when the DMA completes. If we can't start 1106 * the DMA immediately, we don't wait - we just prepare to read 1107 * them again next time. 1108 */ 1109 void 1110 fxp_tick(arg) 1111 void *arg; 1112 { 1113 struct fxp_softc *sc = arg; 1114 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1115 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1116 int s; 1117 1118 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1119 return; 1120 1121 s = splnet(); 1122 1123 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1124 1125 ifp->if_opackets += le32toh(sp->tx_good); 1126 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1127 if (sp->rx_good) { 1128 ifp->if_ipackets += le32toh(sp->rx_good); 1129 sc->sc_rxidle = 0; 1130 } else { 1131 sc->sc_rxidle++; 1132 } 1133 ifp->if_ierrors += 1134 le32toh(sp->rx_crc_errors) + 1135 le32toh(sp->rx_alignment_errors) + 1136 le32toh(sp->rx_rnr_errors) + 1137 le32toh(sp->rx_overrun_errors); 1138 /* 1139 * If any transmit underruns occured, bump up the transmit 1140 * threshold by another 512 bytes (64 * 8). 1141 */ 1142 if (sp->tx_underruns) { 1143 ifp->if_oerrors += le32toh(sp->tx_underruns); 1144 if (tx_threshold < 192) 1145 tx_threshold += 64; 1146 } 1147 1148 /* 1149 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1150 * then assume the receiver has locked up and attempt to clear 1151 * the condition by reprogramming the multicast filter (actually, 1152 * resetting the interface). This is a work-around for a bug in 1153 * the 82557 where the receiver locks up if it gets certain types 1154 * of garbage in the syncronization bits prior to the packet header. 1155 * This bug is supposed to only occur in 10Mbps mode, but has been 1156 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1157 * speed transition). 1158 */ 1159 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1160 (void) fxp_init(sc); 1161 splx(s); 1162 return; 1163 } 1164 /* 1165 * If there is no pending command, start another stats 1166 * dump. Otherwise punt for now. 1167 */ 1168 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1169 /* 1170 * Start another stats dump. 1171 */ 1172 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1173 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1174 FXP_SCB_COMMAND_CU_DUMPRESET); 1175 } else { 1176 /* 1177 * A previous command is still waiting to be accepted. 1178 * Just zero our copy of the stats and wait for the 1179 * next timer event to update them. 1180 */ 1181 /* BIG_ENDIAN: no swap required to store 0 */ 1182 sp->tx_good = 0; 1183 sp->tx_underruns = 0; 1184 sp->tx_total_collisions = 0; 1185 1186 sp->rx_good = 0; 1187 sp->rx_crc_errors = 0; 1188 sp->rx_alignment_errors = 0; 1189 sp->rx_rnr_errors = 0; 1190 sp->rx_overrun_errors = 0; 1191 } 1192 1193 if (sc->sc_flags & FXPF_MII) { 1194 /* Tick the MII clock. */ 1195 mii_tick(&sc->sc_mii); 1196 } 1197 1198 splx(s); 1199 1200 /* 1201 * Schedule another timeout one second from now. 1202 */ 1203 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1204 } 1205 1206 /* 1207 * Drain the receive queue. 1208 */ 1209 void 1210 fxp_rxdrain(sc) 1211 struct fxp_softc *sc; 1212 { 1213 bus_dmamap_t rxmap; 1214 struct mbuf *m; 1215 1216 for (;;) { 1217 IF_DEQUEUE(&sc->sc_rxq, m); 1218 if (m == NULL) 1219 break; 1220 rxmap = M_GETCTX(m, bus_dmamap_t); 1221 bus_dmamap_unload(sc->sc_dmat, rxmap); 1222 FXP_RXMAP_PUT(sc, rxmap); 1223 m_freem(m); 1224 } 1225 } 1226 1227 /* 1228 * Stop the interface. Cancels the statistics updater and resets 1229 * the interface. 1230 */ 1231 void 1232 fxp_stop(sc, drain) 1233 struct fxp_softc *sc; 1234 int drain; 1235 { 1236 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1237 struct fxp_txsoft *txs; 1238 int i; 1239 1240 /* 1241 * Turn down interface (done early to avoid bad interactions 1242 * between panics, shutdown hooks, and the watchdog timer) 1243 */ 1244 ifp->if_timer = 0; 1245 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1246 1247 /* 1248 * Cancel stats updater. 1249 */ 1250 callout_stop(&sc->sc_callout); 1251 if (sc->sc_flags & FXPF_MII) { 1252 /* Down the MII. */ 1253 mii_down(&sc->sc_mii); 1254 } 1255 1256 /* 1257 * Issue software reset 1258 */ 1259 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1260 DELAY(10); 1261 1262 /* 1263 * Release any xmit buffers. 1264 */ 1265 for (i = 0; i < FXP_NTXCB; i++) { 1266 txs = FXP_DSTX(sc, i); 1267 if (txs->txs_mbuf != NULL) { 1268 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1269 m_freem(txs->txs_mbuf); 1270 txs->txs_mbuf = NULL; 1271 } 1272 } 1273 sc->sc_txpending = 0; 1274 1275 if (drain) { 1276 /* 1277 * Release the receive buffers. 1278 */ 1279 fxp_rxdrain(sc); 1280 } 1281 1282 } 1283 1284 /* 1285 * Watchdog/transmission transmit timeout handler. Called when a 1286 * transmission is started on the interface, but no interrupt is 1287 * received before the timeout. This usually indicates that the 1288 * card has wedged for some reason. 1289 */ 1290 void 1291 fxp_watchdog(ifp) 1292 struct ifnet *ifp; 1293 { 1294 struct fxp_softc *sc = ifp->if_softc; 1295 1296 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1297 ifp->if_oerrors++; 1298 1299 (void) fxp_init(sc); 1300 } 1301 1302 /* 1303 * Initialize the interface. Must be called at splnet(). 1304 */ 1305 int 1306 fxp_init(sc) 1307 struct fxp_softc *sc; 1308 { 1309 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1310 struct fxp_cb_config *cbp; 1311 struct fxp_cb_ias *cb_ias; 1312 struct fxp_cb_tx *txd; 1313 bus_dmamap_t rxmap; 1314 int i, prm, save_bf, allm, error = 0; 1315 1316 /* 1317 * Cancel any pending I/O 1318 */ 1319 fxp_stop(sc, 0); 1320 1321 /* 1322 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1323 * flag, and this prevents the MII from detaching resulting in 1324 * a panic. The flags field should perhaps be split in runtime 1325 * flags and more static information. For now, just clear the 1326 * only other flag set. 1327 */ 1328 1329 sc->sc_flags &= ~FXPF_WANTINIT; 1330 1331 /* 1332 * Initialize base of CBL and RFA memory. Loading with zero 1333 * sets it up for regular linear addressing. 1334 */ 1335 fxp_scb_wait(sc); 1336 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1337 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1338 1339 fxp_scb_wait(sc); 1340 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1341 1342 /* 1343 * Initialize the multicast filter. Do this now, since we might 1344 * have to setup the config block differently. 1345 */ 1346 fxp_mc_setup(sc); 1347 1348 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1349 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1350 1351 /* 1352 * In order to support receiving 802.1Q VLAN frames, we have to 1353 * enable "save bad frames", since they are 4 bytes larger than 1354 * the normal Ethernet maximum frame length. 1355 */ 1356 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1357 1358 /* 1359 * Initialize base of dump-stats buffer. 1360 */ 1361 fxp_scb_wait(sc); 1362 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1363 sc->sc_cddma + FXP_CDSTATSOFF); 1364 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1365 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1366 1367 cbp = &sc->sc_control_data->fcd_configcb; 1368 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1369 1370 /* 1371 * This copy is kind of disgusting, but there are a bunch of must be 1372 * zero and must be one bits in this structure and this is the easiest 1373 * way to initialize them all to proper values. 1374 */ 1375 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1376 1377 /* BIG_ENDIAN: no need to swap to store 0 */ 1378 cbp->cb_status = 0; 1379 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1380 FXP_CB_COMMAND_EL); 1381 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1382 cbp->link_addr = 0xffffffff; /* (no) next command */ 1383 cbp->byte_count = 22; /* (22) bytes to config */ 1384 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1385 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1386 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1387 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1388 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1389 cbp->dma_bce = 0; /* (disable) dma max counters */ 1390 cbp->late_scb = 0; /* (don't) defer SCB update */ 1391 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1392 cbp->ci_int = 1; /* interrupt on CU idle */ 1393 cbp->save_bf = save_bf;/* save bad frames */ 1394 cbp->disc_short_rx = !prm; /* discard short packets */ 1395 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1396 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1397 cbp->nsai = 1; /* (don't) disable source addr insert */ 1398 cbp->preamble_length = 2; /* (7 byte) preamble */ 1399 cbp->loopback = 0; /* (don't) loopback */ 1400 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1401 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1402 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1403 cbp->promiscuous = prm; /* promiscuous mode */ 1404 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1405 cbp->crscdt = 0; /* (CRS only) */ 1406 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1407 cbp->padding = 1; /* (do) pad short tx packets */ 1408 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1409 cbp->force_fdx = 0; /* (don't) force full duplex */ 1410 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1411 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1412 cbp->mc_all = allm; /* accept all multicasts */ 1413 1414 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1415 1416 /* 1417 * Start the config command/DMA. 1418 */ 1419 fxp_scb_wait(sc); 1420 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1421 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1422 /* ...and wait for it to complete. */ 1423 i = 1000; 1424 do { 1425 FXP_CDCONFIGSYNC(sc, 1426 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1427 DELAY(1); 1428 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1429 if (i == 0) { 1430 printf("%s at line %d: dmasync timeout\n", 1431 sc->sc_dev.dv_xname, __LINE__); 1432 return ETIMEDOUT; 1433 } 1434 1435 /* 1436 * Initialize the station address. 1437 */ 1438 cb_ias = &sc->sc_control_data->fcd_iascb; 1439 /* BIG_ENDIAN: no need to swap to store 0 */ 1440 cb_ias->cb_status = 0; 1441 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1442 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1443 cb_ias->link_addr = 0xffffffff; 1444 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1445 1446 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1447 1448 /* 1449 * Start the IAS (Individual Address Setup) command/DMA. 1450 */ 1451 fxp_scb_wait(sc); 1452 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1453 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1454 /* ...and wait for it to complete. */ 1455 i = 1000; 1456 do { 1457 FXP_CDIASSYNC(sc, 1458 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1459 DELAY(1); 1460 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1461 if (i == 0) { 1462 printf("%s at line %d: dmasync timeout\n", 1463 sc->sc_dev.dv_xname, __LINE__); 1464 return ETIMEDOUT; 1465 } 1466 1467 /* 1468 * Initialize the transmit descriptor ring. txlast is initialized 1469 * to the end of the list so that it will wrap around to the first 1470 * descriptor when the first packet is transmitted. 1471 */ 1472 for (i = 0; i < FXP_NTXCB; i++) { 1473 txd = FXP_CDTX(sc, i); 1474 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1475 txd->cb_command = 1476 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1477 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1478 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1479 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1480 } 1481 sc->sc_txpending = 0; 1482 sc->sc_txdirty = 0; 1483 sc->sc_txlast = FXP_NTXCB - 1; 1484 1485 /* 1486 * Initialize the receive buffer list. 1487 */ 1488 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1489 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1490 rxmap = FXP_RXMAP_GET(sc); 1491 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1492 printf("%s: unable to allocate or map rx " 1493 "buffer %d, error = %d\n", 1494 sc->sc_dev.dv_xname, 1495 sc->sc_rxq.ifq_len, error); 1496 /* 1497 * XXX Should attempt to run with fewer receive 1498 * XXX buffers instead of just failing. 1499 */ 1500 FXP_RXMAP_PUT(sc, rxmap); 1501 fxp_rxdrain(sc); 1502 goto out; 1503 } 1504 } 1505 sc->sc_rxidle = 0; 1506 1507 /* 1508 * Give the transmit ring to the chip. We do this by pointing 1509 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1510 * issuing a start command. It will execute the NOP and then 1511 * suspend, pointing at the first descriptor. 1512 */ 1513 fxp_scb_wait(sc); 1514 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1515 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1516 1517 /* 1518 * Initialize receiver buffer area - RFA. 1519 */ 1520 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1521 fxp_scb_wait(sc); 1522 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1523 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1524 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1525 1526 if (sc->sc_flags & FXPF_MII) { 1527 /* 1528 * Set current media. 1529 */ 1530 mii_mediachg(&sc->sc_mii); 1531 } 1532 1533 /* 1534 * ...all done! 1535 */ 1536 ifp->if_flags |= IFF_RUNNING; 1537 ifp->if_flags &= ~IFF_OACTIVE; 1538 1539 /* 1540 * Start the one second timer. 1541 */ 1542 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1543 1544 /* 1545 * Attempt to start output on the interface. 1546 */ 1547 fxp_start(ifp); 1548 1549 out: 1550 if (error) 1551 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1552 return (error); 1553 } 1554 1555 /* 1556 * Change media according to request. 1557 */ 1558 int 1559 fxp_mii_mediachange(ifp) 1560 struct ifnet *ifp; 1561 { 1562 struct fxp_softc *sc = ifp->if_softc; 1563 1564 if (ifp->if_flags & IFF_UP) 1565 mii_mediachg(&sc->sc_mii); 1566 return (0); 1567 } 1568 1569 /* 1570 * Notify the world which media we're using. 1571 */ 1572 void 1573 fxp_mii_mediastatus(ifp, ifmr) 1574 struct ifnet *ifp; 1575 struct ifmediareq *ifmr; 1576 { 1577 struct fxp_softc *sc = ifp->if_softc; 1578 1579 if(sc->sc_enabled == 0) { 1580 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1581 ifmr->ifm_status = 0; 1582 return; 1583 } 1584 1585 mii_pollstat(&sc->sc_mii); 1586 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1587 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1588 } 1589 1590 int 1591 fxp_80c24_mediachange(ifp) 1592 struct ifnet *ifp; 1593 { 1594 1595 /* Nothing to do here. */ 1596 return (0); 1597 } 1598 1599 void 1600 fxp_80c24_mediastatus(ifp, ifmr) 1601 struct ifnet *ifp; 1602 struct ifmediareq *ifmr; 1603 { 1604 struct fxp_softc *sc = ifp->if_softc; 1605 1606 /* 1607 * Media is currently-selected media. We cannot determine 1608 * the link status. 1609 */ 1610 ifmr->ifm_status = 0; 1611 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1612 } 1613 1614 /* 1615 * Add a buffer to the end of the RFA buffer list. 1616 * Return 0 if successful, error code on failure. 1617 * 1618 * The RFA struct is stuck at the beginning of mbuf cluster and the 1619 * data pointer is fixed up to point just past it. 1620 */ 1621 int 1622 fxp_add_rfabuf(sc, rxmap, unload) 1623 struct fxp_softc *sc; 1624 bus_dmamap_t rxmap; 1625 int unload; 1626 { 1627 struct mbuf *m; 1628 int error; 1629 1630 MGETHDR(m, M_DONTWAIT, MT_DATA); 1631 if (m == NULL) 1632 return (ENOBUFS); 1633 1634 MCLGET(m, M_DONTWAIT); 1635 if ((m->m_flags & M_EXT) == 0) { 1636 m_freem(m); 1637 return (ENOBUFS); 1638 } 1639 1640 if (unload) 1641 bus_dmamap_unload(sc->sc_dmat, rxmap); 1642 1643 M_SETCTX(m, rxmap); 1644 1645 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1646 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1647 if (error) { 1648 printf("%s: can't load rx DMA map %d, error = %d\n", 1649 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1650 panic("fxp_add_rfabuf"); /* XXX */ 1651 } 1652 1653 FXP_INIT_RFABUF(sc, m); 1654 1655 return (0); 1656 } 1657 1658 volatile int 1659 fxp_mdi_read(self, phy, reg) 1660 struct device *self; 1661 int phy; 1662 int reg; 1663 { 1664 struct fxp_softc *sc = (struct fxp_softc *)self; 1665 int count = 10000; 1666 int value; 1667 1668 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1669 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1670 1671 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1672 && count--) 1673 DELAY(10); 1674 1675 if (count <= 0) 1676 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1677 1678 return (value & 0xffff); 1679 } 1680 1681 void 1682 fxp_statchg(self) 1683 struct device *self; 1684 { 1685 1686 /* Nothing to do. */ 1687 } 1688 1689 void 1690 fxp_mdi_write(self, phy, reg, value) 1691 struct device *self; 1692 int phy; 1693 int reg; 1694 int value; 1695 { 1696 struct fxp_softc *sc = (struct fxp_softc *)self; 1697 int count = 10000; 1698 1699 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1700 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1701 (value & 0xffff)); 1702 1703 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1704 count--) 1705 DELAY(10); 1706 1707 if (count <= 0) 1708 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1709 } 1710 1711 int 1712 fxp_ioctl(ifp, command, data) 1713 struct ifnet *ifp; 1714 u_long command; 1715 caddr_t data; 1716 { 1717 struct fxp_softc *sc = ifp->if_softc; 1718 struct ifreq *ifr = (struct ifreq *)data; 1719 struct ifaddr *ifa = (struct ifaddr *)data; 1720 int s, error = 0; 1721 1722 s = splnet(); 1723 1724 switch (command) { 1725 case SIOCSIFADDR: 1726 if ((error = fxp_enable(sc)) != 0) 1727 break; 1728 ifp->if_flags |= IFF_UP; 1729 1730 switch (ifa->ifa_addr->sa_family) { 1731 #ifdef INET 1732 case AF_INET: 1733 if ((error = fxp_init(sc)) != 0) 1734 break; 1735 arp_ifinit(ifp, ifa); 1736 break; 1737 #endif /* INET */ 1738 #ifdef NS 1739 case AF_NS: 1740 { 1741 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1742 1743 if (ns_nullhost(*ina)) 1744 ina->x_host = *(union ns_host *) 1745 LLADDR(ifp->if_sadl); 1746 else 1747 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1748 ifp->if_addrlen); 1749 /* Set new address. */ 1750 error = fxp_init(sc); 1751 break; 1752 } 1753 #endif /* NS */ 1754 default: 1755 error = fxp_init(sc); 1756 break; 1757 } 1758 break; 1759 1760 case SIOCSIFMTU: 1761 if (ifr->ifr_mtu > ETHERMTU) 1762 error = EINVAL; 1763 else 1764 ifp->if_mtu = ifr->ifr_mtu; 1765 break; 1766 1767 case SIOCSIFFLAGS: 1768 if ((ifp->if_flags & IFF_UP) == 0 && 1769 (ifp->if_flags & IFF_RUNNING) != 0) { 1770 /* 1771 * If interface is marked down and it is running, then 1772 * stop it. 1773 */ 1774 fxp_stop(sc, 1); 1775 fxp_disable(sc); 1776 } else if ((ifp->if_flags & IFF_UP) != 0 && 1777 (ifp->if_flags & IFF_RUNNING) == 0) { 1778 /* 1779 * If interface is marked up and it is stopped, then 1780 * start it. 1781 */ 1782 if((error = fxp_enable(sc)) != 0) 1783 break; 1784 error = fxp_init(sc); 1785 } else if ((ifp->if_flags & IFF_UP) != 0) { 1786 /* 1787 * Reset the interface to pick up change in any other 1788 * flags that affect the hardware state. 1789 */ 1790 if((error = fxp_enable(sc)) != 0) 1791 break; 1792 error = fxp_init(sc); 1793 } 1794 break; 1795 1796 case SIOCADDMULTI: 1797 case SIOCDELMULTI: 1798 if(sc->sc_enabled == 0) { 1799 error = EIO; 1800 break; 1801 } 1802 error = (command == SIOCADDMULTI) ? 1803 ether_addmulti(ifr, &sc->sc_ethercom) : 1804 ether_delmulti(ifr, &sc->sc_ethercom); 1805 1806 if (error == ENETRESET) { 1807 /* 1808 * Multicast list has changed; set the hardware 1809 * filter accordingly. 1810 */ 1811 if (sc->sc_txpending) { 1812 sc->sc_flags |= FXPF_WANTINIT; 1813 error = 0; 1814 } else 1815 error = fxp_init(sc); 1816 } 1817 break; 1818 1819 case SIOCSIFMEDIA: 1820 case SIOCGIFMEDIA: 1821 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1822 break; 1823 1824 default: 1825 error = EINVAL; 1826 break; 1827 } 1828 1829 splx(s); 1830 return (error); 1831 } 1832 1833 /* 1834 * Program the multicast filter. 1835 * 1836 * This function must be called at splnet(). 1837 */ 1838 void 1839 fxp_mc_setup(sc) 1840 struct fxp_softc *sc; 1841 { 1842 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1843 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1844 struct ethercom *ec = &sc->sc_ethercom; 1845 struct ether_multi *enm; 1846 struct ether_multistep step; 1847 int count, nmcasts; 1848 1849 #ifdef DIAGNOSTIC 1850 if (sc->sc_txpending) 1851 panic("fxp_mc_setup: pending transmissions"); 1852 #endif 1853 1854 ifp->if_flags &= ~IFF_ALLMULTI; 1855 1856 /* 1857 * Initialize multicast setup descriptor. 1858 */ 1859 nmcasts = 0; 1860 ETHER_FIRST_MULTI(step, ec, enm); 1861 while (enm != NULL) { 1862 /* 1863 * Check for too many multicast addresses or if we're 1864 * listening to a range. Either way, we simply have 1865 * to accept all multicasts. 1866 */ 1867 if (nmcasts >= MAXMCADDR || 1868 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1869 ETHER_ADDR_LEN) != 0) { 1870 /* 1871 * Callers of this function must do the 1872 * right thing with this. If we're called 1873 * from outside fxp_init(), the caller must 1874 * detect if the state if IFF_ALLMULTI changes. 1875 * If it does, the caller must then call 1876 * fxp_init(), since allmulti is handled by 1877 * the config block. 1878 */ 1879 ifp->if_flags |= IFF_ALLMULTI; 1880 return; 1881 } 1882 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1883 ETHER_ADDR_LEN); 1884 nmcasts++; 1885 ETHER_NEXT_MULTI(step, enm); 1886 } 1887 1888 /* BIG_ENDIAN: no need to swap to store 0 */ 1889 mcsp->cb_status = 0; 1890 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1891 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1892 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1893 1894 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1895 1896 /* 1897 * Wait until the command unit is not active. This should never 1898 * happen since nothing is queued, but make sure anyway. 1899 */ 1900 count = 100; 1901 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1902 FXP_SCB_CUS_ACTIVE && --count) 1903 DELAY(1); 1904 if (count == 0) { 1905 printf("%s at line %d: command queue timeout\n", 1906 sc->sc_dev.dv_xname, __LINE__); 1907 return; 1908 } 1909 1910 /* 1911 * Start the multicast setup command/DMA. 1912 */ 1913 fxp_scb_wait(sc); 1914 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1915 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1916 1917 /* ...and wait for it to complete. */ 1918 count = 1000; 1919 do { 1920 FXP_CDMCSSYNC(sc, 1921 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1922 DELAY(1); 1923 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1924 if (count == 0) { 1925 printf("%s at line %d: dmasync timeout\n", 1926 sc->sc_dev.dv_xname, __LINE__); 1927 return; 1928 } 1929 } 1930 1931 int 1932 fxp_enable(sc) 1933 struct fxp_softc *sc; 1934 { 1935 1936 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1937 if ((*sc->sc_enable)(sc) != 0) { 1938 printf("%s: device enable failed\n", 1939 sc->sc_dev.dv_xname); 1940 return (EIO); 1941 } 1942 } 1943 1944 sc->sc_enabled = 1; 1945 return (0); 1946 } 1947 1948 void 1949 fxp_disable(sc) 1950 struct fxp_softc *sc; 1951 { 1952 1953 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1954 (*sc->sc_disable)(sc); 1955 sc->sc_enabled = 0; 1956 } 1957 } 1958 1959 /* 1960 * fxp_activate: 1961 * 1962 * Handle device activation/deactivation requests. 1963 */ 1964 int 1965 fxp_activate(self, act) 1966 struct device *self; 1967 enum devact act; 1968 { 1969 struct fxp_softc *sc = (void *) self; 1970 int s, error = 0; 1971 1972 s = splnet(); 1973 switch (act) { 1974 case DVACT_ACTIVATE: 1975 error = EOPNOTSUPP; 1976 break; 1977 1978 case DVACT_DEACTIVATE: 1979 if (sc->sc_flags & FXPF_MII) 1980 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1981 MII_OFFSET_ANY); 1982 if_deactivate(&sc->sc_ethercom.ec_if); 1983 break; 1984 } 1985 splx(s); 1986 1987 return (error); 1988 } 1989 1990 /* 1991 * fxp_detach: 1992 * 1993 * Detach an i82557 interface. 1994 */ 1995 int 1996 fxp_detach(sc) 1997 struct fxp_softc *sc; 1998 { 1999 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2000 int i; 2001 2002 /* Succeed now if there's no work to do. */ 2003 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2004 return (0); 2005 2006 /* Unhook our tick handler. */ 2007 callout_stop(&sc->sc_callout); 2008 2009 if (sc->sc_flags & FXPF_MII) { 2010 /* Detach all PHYs */ 2011 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2012 } 2013 2014 /* Delete all remaining media. */ 2015 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2016 2017 #if NRND > 0 2018 rnd_detach_source(&sc->rnd_source); 2019 #endif 2020 #if NBPFILTER > 0 2021 bpfdetach(ifp); 2022 #endif 2023 ether_ifdetach(ifp); 2024 if_detach(ifp); 2025 2026 for (i = 0; i < FXP_NRFABUFS; i++) { 2027 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2028 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2029 } 2030 2031 for (i = 0; i < FXP_NTXCB; i++) { 2032 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2033 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2034 } 2035 2036 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2037 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2038 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2039 sizeof(struct fxp_control_data)); 2040 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2041 2042 shutdownhook_disestablish(sc->sc_sdhook); 2043 powerhook_disestablish(sc->sc_powerhook); 2044 2045 return (0); 2046 } 2047
Indexes created Sat Oct 25 16:10:12 GMT 2025