i82557.c revision 1.34.2.4
1 /* $NetBSD: i82557.c,v 1.34.2.4 2002/06/06 19:41:07 he Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include "opt_inet.h" 76 #include "opt_ns.h" 77 #include "bpfilter.h" 78 #include "rnd.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 91 #include <machine/endian.h> 92 93 #include <vm/vm.h> /* for PAGE_SIZE */ 94 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NBPFILTER > 0 105 #include <net/bpf.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 113 #ifdef NS 114 #include <netns/ns.h> 115 #include <netns/ns_if.h> 116 #endif 117 118 #include <machine/bus.h> 119 #include <machine/intr.h> 120 121 #include <dev/mii/miivar.h> 122 123 #include <dev/ic/i82557reg.h> 124 #include <dev/ic/i82557var.h> 125 126 /* 127 * NOTE! On the Alpha, we have an alignment constraint. The 128 * card DMAs the packet immediately following the RFA. However, 129 * the first thing in the packet is a 14-byte Ethernet header. 130 * This means that the packet is misaligned. To compensate, 131 * we actually offset the RFA 2 bytes into the cluster. This 132 * alignes the packet after the Ethernet header at a 32-bit 133 * boundary. HOWEVER! This means that the RFA is misaligned! 134 */ 135 #define RFA_ALIGNMENT_FUDGE 2 136 137 /* 138 * The configuration byte map has several undefined fields which 139 * must be one or must be zero. Set up a template for these bits 140 * only (assuming an i82557 chip), leaving the actual configuration 141 * for fxp_init(). 142 * 143 * See the definition of struct fxp_cb_config for the bit definitions. 144 */ 145 const u_int8_t fxp_cb_config_template[] = { 146 0x0, 0x0, /* cb_status */ 147 0x0, 0x0, /* cb_command */ 148 0x0, 0x0, 0x0, 0x0, /* link_addr */ 149 0x0, /* 0 */ 150 0x0, /* 1 */ 151 0x0, /* 2 */ 152 0x0, /* 3 */ 153 0x0, /* 4 */ 154 0x0, /* 5 */ 155 0x32, /* 6 */ 156 0x0, /* 7 */ 157 0x0, /* 8 */ 158 0x0, /* 9 */ 159 0x6, /* 10 */ 160 0x0, /* 11 */ 161 0x0, /* 12 */ 162 0x0, /* 13 */ 163 0xf2, /* 14 */ 164 0x48, /* 15 */ 165 0x0, /* 16 */ 166 0x40, /* 17 */ 167 0xf0, /* 18 */ 168 0x0, /* 19 */ 169 0x3f, /* 20 */ 170 0x5, /* 21 */ 171 0x0, /* 22 */ 172 0x0, /* 23 */ 173 0x0, /* 24 */ 174 0x0, /* 25 */ 175 0x0, /* 26 */ 176 0x0, /* 27 */ 177 0x0, /* 28 */ 178 0x0, /* 29 */ 179 0x0, /* 30 */ 180 0x0, /* 31 */ 181 }; 182 183 void fxp_mii_initmedia(struct fxp_softc *); 184 int fxp_mii_mediachange(struct ifnet *); 185 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 186 187 void fxp_80c24_initmedia(struct fxp_softc *); 188 int fxp_80c24_mediachange(struct ifnet *); 189 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 190 191 void fxp_start(struct ifnet *); 192 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 193 void fxp_watchdog(struct ifnet *); 194 int fxp_init(struct fxp_softc *); 195 void fxp_stop(struct fxp_softc *, int); 196 197 void fxp_txintr(struct fxp_softc *); 198 void fxp_rxintr(struct fxp_softc *); 199 200 void fxp_rxdrain(struct fxp_softc *); 201 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 202 int fxp_mdi_read(struct device *, int, int); 203 void fxp_statchg(struct device *); 204 void fxp_mdi_write(struct device *, int, int, int); 205 void fxp_autosize_eeprom(struct fxp_softc*); 206 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 207 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 208 void fxp_eeprom_update_cksum(struct fxp_softc *); 209 void fxp_get_info(struct fxp_softc *, u_int8_t *); 210 void fxp_tick(void *); 211 void fxp_mc_setup(struct fxp_softc *); 212 213 void fxp_shutdown(void *); 214 void fxp_power(int, void *); 215 216 int fxp_copy_small = 0; 217 218 struct fxp_phytype { 219 int fp_phy; /* type of PHY, -1 for MII at the end. */ 220 void (*fp_init)(struct fxp_softc *); 221 } fxp_phytype_table[] = { 222 { FXP_PHY_80C24, fxp_80c24_initmedia }, 223 { -1, fxp_mii_initmedia }, 224 }; 225 226 /* 227 * Set initial transmit threshold at 64 (512 bytes). This is 228 * increased by 64 (512 bytes) at a time, to maximum of 192 229 * (1536 bytes), if an underrun occurs. 230 */ 231 static int tx_threshold = 64; 232 233 /* 234 * Wait for the previous command to be accepted (but not necessarily 235 * completed). 236 */ 237 static __inline void 238 fxp_scb_wait(struct fxp_softc *sc) 239 { 240 int i = 10000; 241 242 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 243 delay(2); 244 if (i == 0) 245 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 246 } 247 248 /* 249 * Submit a command to the i82557. 250 */ 251 static __inline void 252 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253 { 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256 } 257 258 /* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261 void 262 fxp_attach(struct fxp_softc *sc) 263 { 264 u_int8_t enaddr[6]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout); 271 272 /* Start out using the standard RFA. */ 273 sc->sc_rfa_size = RFA_SIZE; 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Allocate the control data structures, and create and load the 285 * DMA map for it. 286 */ 287 if ((error = bus_dmamem_alloc(sc->sc_dmat, 288 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 289 0)) != 0) { 290 printf("%s: unable to allocate control data, error = %d\n", 291 sc->sc_dev.dv_xname, error); 292 goto fail_0; 293 } 294 295 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 296 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 297 BUS_DMA_COHERENT)) != 0) { 298 printf("%s: unable to map control data, error = %d\n", 299 sc->sc_dev.dv_xname, error); 300 goto fail_1; 301 } 302 sc->sc_cdseg = seg; 303 sc->sc_cdnseg = rseg; 304 305 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 306 307 if ((error = bus_dmamap_create(sc->sc_dmat, 308 sizeof(struct fxp_control_data), 1, 309 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 310 printf("%s: unable to create control data DMA map, " 311 "error = %d\n", sc->sc_dev.dv_xname, error); 312 goto fail_2; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 316 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 317 0)) != 0) { 318 printf("%s: can't load control data DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail_3; 321 } 322 323 /* 324 * Create the transmit buffer DMA maps. 325 */ 326 for (i = 0; i < FXP_NTXCB; i++) { 327 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 328 FXP_NTXSEG, MCLBYTES, 0, 0, 329 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 330 printf("%s: unable to create tx DMA map %d, " 331 "error = %d\n", sc->sc_dev.dv_xname, i, error); 332 goto fail_4; 333 } 334 } 335 336 /* 337 * Create the receive buffer DMA maps. 338 */ 339 for (i = 0; i < FXP_NRFABUFS; i++) { 340 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 341 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 342 printf("%s: unable to create rx DMA map %d, " 343 "error = %d\n", sc->sc_dev.dv_xname, i, error); 344 goto fail_5; 345 } 346 } 347 348 /* Initialize MAC address and media structures. */ 349 fxp_get_info(sc, enaddr); 350 351 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 352 ether_sprintf(enaddr)); 353 354 ifp = &sc->sc_ethercom.ec_if; 355 356 /* 357 * Get info about our media interface, and initialize it. Note 358 * the table terminates itself with a phy of -1, indicating 359 * that we're using MII. 360 */ 361 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 362 if (fp->fp_phy == sc->phy_primary_device) 363 break; 364 (*fp->fp_init)(sc); 365 366 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = fxp_ioctl; 370 ifp->if_start = fxp_start; 371 ifp->if_watchdog = fxp_watchdog; 372 373 /* 374 * We can support 802.1Q VLAN-sized frames. 375 */ 376 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 377 378 /* 379 * Attach the interface. 380 */ 381 if_attach(ifp); 382 ether_ifattach(ifp, enaddr); 383 #if NBPFILTER > 0 384 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 385 sizeof(struct ether_header)); 386 #endif 387 #if NRND > 0 388 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 389 RND_TYPE_NET, 0); 390 #endif 391 392 #ifdef FXP_EVENT_COUNTERS 393 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 394 NULL, sc->sc_dev.dv_xname, "txstall"); 395 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 396 NULL, sc->sc_dev.dv_xname, "txintr"); 397 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 398 NULL, sc->sc_dev.dv_xname, "rxintr"); 399 #endif /* FXP_EVENT_COUNTERS */ 400 401 /* 402 * Add shutdown hook so that DMA is disabled prior to reboot. Not 403 * doing do could allow DMA to corrupt kernel memory during the 404 * reboot before the driver initializes. 405 */ 406 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 407 if (sc->sc_sdhook == NULL) 408 printf("%s: WARNING: unable to establish shutdown hook\n", 409 sc->sc_dev.dv_xname); 410 /* 411 * Add suspend hook, for similar reasons.. 412 */ 413 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 414 if (sc->sc_powerhook == NULL) 415 printf("%s: WARNING: unable to establish power hook\n", 416 sc->sc_dev.dv_xname); 417 418 /* The attach is successful. */ 419 sc->sc_flags |= FXPF_ATTACHED; 420 421 return; 422 423 /* 424 * Free any resources we've allocated during the failed attach 425 * attempt. Do this in reverse order and fall though. 426 */ 427 fail_5: 428 for (i = 0; i < FXP_NRFABUFS; i++) { 429 if (sc->sc_rxmaps[i] != NULL) 430 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 431 } 432 fail_4: 433 for (i = 0; i < FXP_NTXCB; i++) { 434 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 435 bus_dmamap_destroy(sc->sc_dmat, 436 FXP_DSTX(sc, i)->txs_dmamap); 437 } 438 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 439 fail_3: 440 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 441 fail_2: 442 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 443 sizeof(struct fxp_control_data)); 444 fail_1: 445 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 446 fail_0: 447 return; 448 } 449 450 void 451 fxp_mii_initmedia(struct fxp_softc *sc) 452 { 453 454 sc->sc_flags |= FXPF_MII; 455 456 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 457 sc->sc_mii.mii_readreg = fxp_mdi_read; 458 sc->sc_mii.mii_writereg = fxp_mdi_write; 459 sc->sc_mii.mii_statchg = fxp_statchg; 460 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 461 fxp_mii_mediastatus); 462 /* 463 * The i82557 wedges if all of its PHYs are isolated! 464 */ 465 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 466 MII_OFFSET_ANY, MIIF_NOISOLATE); 467 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 468 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 469 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 470 } else 471 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 472 } 473 474 void 475 fxp_80c24_initmedia(struct fxp_softc *sc) 476 { 477 478 /* 479 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 480 * doesn't have a programming interface of any sort. The 481 * media is sensed automatically based on how the link partner 482 * is configured. This is, in essence, manual configuration. 483 */ 484 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 485 sc->sc_dev.dv_xname); 486 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 487 fxp_80c24_mediastatus); 488 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 489 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 490 } 491 492 /* 493 * Device shutdown routine. Called at system shutdown after sync. The 494 * main purpose of this routine is to shut off receiver DMA so that 495 * kernel memory doesn't get clobbered during warmboot. 496 */ 497 void 498 fxp_shutdown(void *arg) 499 { 500 struct fxp_softc *sc = arg; 501 502 /* 503 * Since the system's going to halt shortly, don't bother 504 * freeing mbufs. 505 */ 506 fxp_stop(sc, 0); 507 } 508 /* 509 * Power handler routine. Called when the system is transitioning 510 * into/out of power save modes. As with fxp_shutdown, the main 511 * purpose of this routine is to shut off receiver DMA so it doesn't 512 * clobber kernel memory at the wrong time. 513 */ 514 void 515 fxp_power(int why, void *arg) 516 { 517 struct fxp_softc *sc = arg; 518 struct ifnet *ifp; 519 int s; 520 521 s = splnet(); 522 switch (why) { 523 case PWR_SUSPEND: 524 case PWR_STANDBY: 525 fxp_stop(sc, 0); 526 break; 527 case PWR_RESUME: 528 ifp = &sc->sc_ethercom.ec_if; 529 if (ifp->if_flags & IFF_UP) 530 fxp_init(sc); 531 break; 532 case PWR_SOFTSUSPEND: 533 case PWR_SOFTSTANDBY: 534 case PWR_SOFTRESUME: 535 break; 536 } 537 splx(s); 538 } 539 540 /* 541 * Initialize the interface media. 542 */ 543 void 544 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 545 { 546 u_int16_t data, myea[3]; 547 548 /* 549 * Reset to a stable state. 550 */ 551 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 552 DELAY(10); 553 554 sc->sc_eeprom_size = 0; 555 fxp_autosize_eeprom(sc); 556 if(sc->sc_eeprom_size == 0) { 557 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 558 sc->sc_eeprom_size = 6; /* XXX panic here? */ 559 } 560 #ifdef DEBUG 561 printf("%s: detected %d word EEPROM\n", 562 sc->sc_dev.dv_xname, 563 1 << sc->sc_eeprom_size); 564 #endif 565 566 /* 567 * Get info about the primary PHY 568 */ 569 fxp_read_eeprom(sc, &data, 6, 1); 570 sc->phy_primary_device = 571 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 572 573 /* 574 * Read MAC address. 575 */ 576 fxp_read_eeprom(sc, myea, 0, 3); 577 enaddr[0] = myea[0] & 0xff; 578 enaddr[1] = myea[0] >> 8; 579 enaddr[2] = myea[1] & 0xff; 580 enaddr[3] = myea[1] >> 8; 581 enaddr[4] = myea[2] & 0xff; 582 enaddr[5] = myea[2] >> 8; 583 584 /* 585 * Systems based on the ICH2/ICH2-M chip from Intel, as well 586 * as some i82559 designs, have a defect where the chip can 587 * cause a PCI protocol violation if it receives a CU_RESUME 588 * command when it is entering the IDLE state. 589 * 590 * The work-around is to disable Dynamic Standby Mode, so that 591 * the chip never deasserts #CLKRUN, and always remains in the 592 * active state. 593 * 594 * Unfortunately, the only way to disable Dynamic Standby is 595 * to frob an EEPROM setting and reboot (the EEPROM setting 596 * is only consulted when the PCI bus comes out of reset). 597 * 598 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 599 */ 600 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 601 fxp_read_eeprom(sc, &data, 10, 1); 602 if (data & 0x02) { /* STB enable */ 603 printf("%s: WARNING: Disabling dynamic standby mode in EEPROM to work around a\n", sc->sc_dev.dv_xname); 604 printf("%s: WARNING: hardware bug. You must reset the system before using this\n", sc->sc_dev.dv_xname); 605 printf("%s: WARNING: interface.\n", sc->sc_dev.dv_xname); 606 data &= ~0x02; 607 fxp_write_eeprom(sc, &data, 10, 1); 608 printf("%s: new EEPROM ID: 0x%04x\n", 609 sc->sc_dev.dv_xname, data); 610 fxp_eeprom_update_cksum(sc); 611 } 612 } 613 } 614 615 static void 616 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 617 { 618 uint16_t reg; 619 int x; 620 621 for (x = 1 << (len - 1); x != 0; x >>= 1) { 622 if (data & x) 623 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 624 else 625 reg = FXP_EEPROM_EECS; 626 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 627 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 628 reg | FXP_EEPROM_EESK); 629 DELAY(4); 630 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 631 DELAY(4); 632 } 633 } 634 635 /* 636 * Figure out EEPROM size. 637 * 638 * 559's can have either 64-word or 256-word EEPROMs, the 558 639 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 640 * talks about the existance of 16 to 256 word EEPROMs. 641 * 642 * The only known sizes are 64 and 256, where the 256 version is used 643 * by CardBus cards to store CIS information. 644 * 645 * The address is shifted in msb-to-lsb, and after the last 646 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 647 * after which follows the actual data. We try to detect this zero, by 648 * probing the data-out bit in the EEPROM control register just after 649 * having shifted in a bit. If the bit is zero, we assume we've 650 * shifted enough address bits. The data-out should be tri-state, 651 * before this, which should translate to a logical one. 652 * 653 * Other ways to do this would be to try to read a register with known 654 * contents with a varying number of address bits, but no such 655 * register seem to be available. The high bits of register 10 are 01 656 * on the 558 and 559, but apparently not on the 557. 657 * 658 * The Linux driver computes a checksum on the EEPROM data, but the 659 * value of this checksum is not very well documented. 660 */ 661 662 void 663 fxp_autosize_eeprom(struct fxp_softc *sc) 664 { 665 int x; 666 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 668 669 /* Shift in read opcode. */ 670 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 671 672 /* 673 * Shift in address, wait for the dummy zero following a correct 674 * address shift. 675 */ 676 for (x = 1; x <= 8; x++) { 677 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 679 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 680 DELAY(4); 681 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 682 FXP_EEPROM_EEDO) == 0) 683 break; 684 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 685 DELAY(4); 686 } 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 688 DELAY(4); 689 if(x != 6 && x != 8) { 690 #ifdef DEBUG 691 printf("%s: strange EEPROM size (%d)\n", 692 sc->sc_dev.dv_xname, 1 << x); 693 #endif 694 } else 695 sc->sc_eeprom_size = x; 696 } 697 698 /* 699 * Read from the serial EEPROM. Basically, you manually shift in 700 * the read opcode (one bit at a time) and then shift in the address, 701 * and then you shift out the data (all of this one bit at a time). 702 * The word size is 16 bits, so you have to provide the address for 703 * every 16 bits of data. 704 */ 705 void 706 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 707 { 708 u_int16_t reg; 709 int i, x; 710 711 for (i = 0; i < words; i++) { 712 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 713 714 /* Shift in read opcode. */ 715 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 716 717 /* Shift in address. */ 718 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 719 720 reg = FXP_EEPROM_EECS; 721 data[i] = 0; 722 723 /* Shift out data. */ 724 for (x = 16; x > 0; x--) { 725 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 726 reg | FXP_EEPROM_EESK); 727 DELAY(4); 728 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 729 FXP_EEPROM_EEDO) 730 data[i] |= (1 << (x - 1)); 731 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 732 DELAY(4); 733 } 734 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 735 DELAY(4); 736 } 737 } 738 739 /* 740 * Write data to the serial EEPROM. 741 */ 742 void 743 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 744 { 745 int i, j; 746 747 for (i = 0; i < words; i++) { 748 /* Erase/write enable. */ 749 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 750 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 751 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 752 sc->sc_eeprom_size); 753 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 754 DELAY(4); 755 756 /* Shift in write opcode, address, data. */ 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 758 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 759 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 760 fxp_eeprom_shiftin(sc, data[i], 16); 761 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 762 DELAY(4); 763 764 /* Wait for the EEPROM to finish up. */ 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 766 DELAY(4); 767 for (j = 0; j < 1000; j++) { 768 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 769 FXP_EEPROM_EEDO) 770 break; 771 DELAY(50); 772 } 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 774 DELAY(4); 775 776 /* Erase/write disable. */ 777 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 778 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 779 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 780 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 781 DELAY(4); 782 } 783 } 784 785 /* 786 * Update the checksum of the EEPROM. 787 */ 788 void 789 fxp_eeprom_update_cksum(struct fxp_softc *sc) 790 { 791 int i; 792 uint16_t data, cksum; 793 794 cksum = 0; 795 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 796 fxp_read_eeprom(sc, &data, i, 1); 797 cksum += data; 798 } 799 i = (1 << sc->sc_eeprom_size) - 1; 800 cksum = 0xbaba - cksum; 801 fxp_read_eeprom(sc, &data, i, 1); 802 fxp_write_eeprom(sc, &cksum, i, 1); 803 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 804 sc->sc_dev.dv_xname, i, data, cksum); 805 } 806 807 /* 808 * Start packet transmission on the interface. 809 */ 810 void 811 fxp_start(struct ifnet *ifp) 812 { 813 struct fxp_softc *sc = ifp->if_softc; 814 struct mbuf *m0, *m; 815 struct fxp_txdesc *txd; 816 struct fxp_txsoft *txs; 817 bus_dmamap_t dmamap; 818 int error, lasttx, nexttx, opending, seg; 819 820 /* 821 * If we want a re-init, bail out now. 822 */ 823 if (sc->sc_flags & FXPF_WANTINIT) { 824 ifp->if_flags |= IFF_OACTIVE; 825 return; 826 } 827 828 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 829 return; 830 831 /* 832 * Remember the previous txpending and the current lasttx. 833 */ 834 opending = sc->sc_txpending; 835 lasttx = sc->sc_txlast; 836 837 /* 838 * Loop through the send queue, setting up transmit descriptors 839 * until we drain the queue, or use up all available transmit 840 * descriptors. 841 */ 842 for (;;) { 843 /* 844 * Grab a packet off the queue. 845 */ 846 IF_DEQUEUE(&ifp->if_snd, m0); 847 if (m0 == NULL) 848 break; 849 850 if (sc->sc_txpending == FXP_NTXCB) { 851 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 852 break; 853 } 854 855 /* 856 * Get the next available transmit descriptor. 857 */ 858 nexttx = FXP_NEXTTX(sc->sc_txlast); 859 txd = FXP_CDTX(sc, nexttx); 860 txs = FXP_DSTX(sc, nexttx); 861 dmamap = txs->txs_dmamap; 862 863 /* 864 * Load the DMA map. If this fails, the packet either 865 * didn't fit in the allotted number of frags, or we were 866 * short on resources. In this case, we'll copy and try 867 * again. 868 */ 869 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 870 BUS_DMA_NOWAIT) != 0) { 871 MGETHDR(m, M_DONTWAIT, MT_DATA); 872 if (m == NULL) { 873 printf("%s: unable to allocate Tx mbuf\n", 874 sc->sc_dev.dv_xname); 875 IF_PREPEND(&ifp->if_snd, m0); 876 break; 877 } 878 if (m0->m_pkthdr.len > MHLEN) { 879 MCLGET(m, M_DONTWAIT); 880 if ((m->m_flags & M_EXT) == 0) { 881 printf("%s: unable to allocate Tx " 882 "cluster\n", sc->sc_dev.dv_xname); 883 m_freem(m); 884 IF_PREPEND(&ifp->if_snd, m0); 885 break; 886 } 887 } 888 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 889 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 890 m_freem(m0); 891 m0 = m; 892 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 893 m0, BUS_DMA_NOWAIT); 894 if (error) { 895 printf("%s: unable to load Tx buffer, " 896 "error = %d\n", sc->sc_dev.dv_xname, error); 897 IF_PREPEND(&ifp->if_snd, m0); 898 break; 899 } 900 } 901 902 /* Initialize the fraglist. */ 903 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 904 txd->txd_tbd[seg].tb_addr = 905 htole32(dmamap->dm_segs[seg].ds_addr); 906 txd->txd_tbd[seg].tb_size = 907 htole32(dmamap->dm_segs[seg].ds_len); 908 } 909 910 /* Sync the DMA map. */ 911 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 912 BUS_DMASYNC_PREWRITE); 913 914 /* 915 * Store a pointer to the packet so we can free it later. 916 */ 917 txs->txs_mbuf = m0; 918 919 /* 920 * Initialize the transmit descriptor. 921 */ 922 /* BIG_ENDIAN: no need to swap to store 0 */ 923 txd->txd_txcb.cb_status = 0; 924 txd->txd_txcb.cb_command = 925 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 926 txd->txd_txcb.tx_threshold = tx_threshold; 927 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 928 929 FXP_CDTXSYNC(sc, nexttx, 930 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 931 932 /* Advance the tx pointer. */ 933 sc->sc_txpending++; 934 sc->sc_txlast = nexttx; 935 936 #if NBPFILTER > 0 937 /* 938 * Pass packet to bpf if there is a listener. 939 */ 940 if (ifp->if_bpf) 941 bpf_mtap(ifp->if_bpf, m0); 942 #endif 943 } 944 945 if (sc->sc_txpending == FXP_NTXCB) { 946 /* No more slots; notify upper layer. */ 947 ifp->if_flags |= IFF_OACTIVE; 948 } 949 950 if (sc->sc_txpending != opending) { 951 /* 952 * We enqueued packets. If the transmitter was idle, 953 * reset the txdirty pointer. 954 */ 955 if (opending == 0) 956 sc->sc_txdirty = FXP_NEXTTX(lasttx); 957 958 /* 959 * Cause the chip to interrupt and suspend command 960 * processing once the last packet we've enqueued 961 * has been transmitted. 962 */ 963 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 964 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 965 FXP_CDTXSYNC(sc, sc->sc_txlast, 966 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 967 968 /* 969 * The entire packet chain is set up. Clear the suspend bit 970 * on the command prior to the first packet we set up. 971 */ 972 FXP_CDTXSYNC(sc, lasttx, 973 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 974 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 975 htole16(~FXP_CB_COMMAND_S); 976 FXP_CDTXSYNC(sc, lasttx, 977 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 978 979 /* 980 * Issue a Resume command in case the chip was suspended. 981 */ 982 fxp_scb_wait(sc); 983 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 984 985 /* Set a watchdog timer in case the chip flakes out. */ 986 ifp->if_timer = 5; 987 } 988 } 989 990 /* 991 * Process interface interrupts. 992 */ 993 int 994 fxp_intr(void *arg) 995 { 996 struct fxp_softc *sc = arg; 997 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 998 bus_dmamap_t rxmap; 999 int claimed = 0; 1000 u_int8_t statack; 1001 1002 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1003 return (0); 1004 /* 1005 * If the interface isn't running, don't try to 1006 * service the interrupt.. just ack it and bail. 1007 */ 1008 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1009 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1010 if (statack) { 1011 claimed = 1; 1012 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1013 } 1014 return (claimed); 1015 } 1016 1017 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1018 claimed = 1; 1019 1020 /* 1021 * First ACK all the interrupts in this pass. 1022 */ 1023 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1024 1025 /* 1026 * Process receiver interrupts. If a no-resource (RNR) 1027 * condition exists, get whatever packets we can and 1028 * re-start the receiver. 1029 */ 1030 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1031 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1032 fxp_rxintr(sc); 1033 } 1034 1035 if (statack & FXP_SCB_STATACK_RNR) { 1036 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1037 fxp_scb_wait(sc); 1038 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1039 rxmap->dm_segs[0].ds_addr + 1040 RFA_ALIGNMENT_FUDGE); 1041 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1042 } 1043 1044 /* 1045 * Free any finished transmit mbuf chains. 1046 */ 1047 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1048 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1049 fxp_txintr(sc); 1050 1051 /* 1052 * Try to get more packets going. 1053 */ 1054 fxp_start(ifp); 1055 1056 if (sc->sc_txpending == 0) { 1057 /* 1058 * If we want a re-init, do that now. 1059 */ 1060 if (sc->sc_flags & FXPF_WANTINIT) 1061 (void) fxp_init(sc); 1062 } 1063 } 1064 } 1065 1066 #if NRND > 0 1067 if (claimed) 1068 rnd_add_uint32(&sc->rnd_source, statack); 1069 #endif 1070 return (claimed); 1071 } 1072 1073 /* 1074 * Handle transmit completion interrupts. 1075 */ 1076 void 1077 fxp_txintr(struct fxp_softc *sc) 1078 { 1079 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1080 struct fxp_txdesc *txd; 1081 struct fxp_txsoft *txs; 1082 int i; 1083 u_int16_t txstat; 1084 1085 ifp->if_flags &= ~IFF_OACTIVE; 1086 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1087 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1088 txd = FXP_CDTX(sc, i); 1089 txs = FXP_DSTX(sc, i); 1090 1091 FXP_CDTXSYNC(sc, i, 1092 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1093 1094 txstat = le16toh(txd->txd_txcb.cb_status); 1095 1096 if ((txstat & FXP_CB_STATUS_C) == 0) 1097 break; 1098 1099 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1100 0, txs->txs_dmamap->dm_mapsize, 1101 BUS_DMASYNC_POSTWRITE); 1102 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1103 m_freem(txs->txs_mbuf); 1104 txs->txs_mbuf = NULL; 1105 } 1106 1107 /* Update the dirty transmit buffer pointer. */ 1108 sc->sc_txdirty = i; 1109 1110 /* 1111 * Cancel the watchdog timer if there are no pending 1112 * transmissions. 1113 */ 1114 if (sc->sc_txpending == 0) 1115 ifp->if_timer = 0; 1116 } 1117 1118 /* 1119 * Handle receive interrupts. 1120 */ 1121 void 1122 fxp_rxintr(struct fxp_softc *sc) 1123 { 1124 struct ethercom *ec = &sc->sc_ethercom; 1125 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1126 struct mbuf *m, *m0; 1127 bus_dmamap_t rxmap; 1128 struct fxp_rfa *rfa; 1129 struct ether_header *eh; 1130 u_int16_t len, rxstat; 1131 1132 for (;;) { 1133 m = sc->sc_rxq.ifq_head; 1134 rfa = FXP_MTORFA(m); 1135 rxmap = M_GETCTX(m, bus_dmamap_t); 1136 1137 FXP_RFASYNC(sc, m, 1138 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1139 1140 rxstat = le16toh(rfa->rfa_status); 1141 1142 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1143 /* 1144 * We have processed all of the 1145 * receive buffers. 1146 */ 1147 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1148 return; 1149 } 1150 1151 IF_DEQUEUE(&sc->sc_rxq, m); 1152 1153 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1154 1155 len = le16toh(rfa->actual_size) & 1156 (m->m_ext.ext_size - 1); 1157 1158 if (len < sizeof(struct ether_header)) { 1159 /* 1160 * Runt packet; drop it now. 1161 */ 1162 FXP_INIT_RFABUF(sc, m); 1163 continue; 1164 } 1165 1166 /* 1167 * If support for 802.1Q VLAN sized frames is 1168 * enabled, we need to do some additional error 1169 * checking (as we are saving bad frames, in 1170 * order to receive the larger ones). 1171 */ 1172 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1173 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1174 FXP_RFA_STATUS_RNR| 1175 FXP_RFA_STATUS_ALIGN| 1176 FXP_RFA_STATUS_CRC)) != 0) { 1177 FXP_INIT_RFABUF(sc, m); 1178 continue; 1179 } 1180 1181 /* 1182 * If the packet is small enough to fit in a 1183 * single header mbuf, allocate one and copy 1184 * the data into it. This greatly reduces 1185 * memory consumption when we receive lots 1186 * of small packets. 1187 * 1188 * Otherwise, we add a new buffer to the receive 1189 * chain. If this fails, we drop the packet and 1190 * recycle the old buffer. 1191 */ 1192 if (fxp_copy_small != 0 && len <= MHLEN) { 1193 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1194 if (m == NULL) 1195 goto dropit; 1196 memcpy(mtod(m0, caddr_t), 1197 mtod(m, caddr_t), len); 1198 FXP_INIT_RFABUF(sc, m); 1199 m = m0; 1200 } else { 1201 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1202 dropit: 1203 ifp->if_ierrors++; 1204 FXP_INIT_RFABUF(sc, m); 1205 continue; 1206 } 1207 } 1208 1209 m->m_pkthdr.rcvif = ifp; 1210 m->m_pkthdr.len = m->m_len = len; 1211 eh = mtod(m, struct ether_header *); 1212 1213 #if NBPFILTER > 0 1214 /* 1215 * Pass this up to any BPF listeners, but only 1216 * pass it up the stack it its for us. 1217 */ 1218 if (ifp->if_bpf) { 1219 bpf_mtap(ifp->if_bpf, m); 1220 1221 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1222 (rxstat & FXP_RFA_STATUS_IAMATCH) != 0 && 1223 (eh->ether_dhost[0] & 1) == 0) { 1224 m_freem(m); 1225 continue; 1226 } 1227 } 1228 #endif 1229 1230 /* Pass it on. */ 1231 (*ifp->if_input)(ifp, m); 1232 } 1233 } 1234 1235 /* 1236 * Update packet in/out/collision statistics. The i82557 doesn't 1237 * allow you to access these counters without doing a fairly 1238 * expensive DMA to get _all_ of the statistics it maintains, so 1239 * we do this operation here only once per second. The statistics 1240 * counters in the kernel are updated from the previous dump-stats 1241 * DMA and then a new dump-stats DMA is started. The on-chip 1242 * counters are zeroed when the DMA completes. If we can't start 1243 * the DMA immediately, we don't wait - we just prepare to read 1244 * them again next time. 1245 */ 1246 void 1247 fxp_tick(void *arg) 1248 { 1249 struct fxp_softc *sc = arg; 1250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1251 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1252 int s; 1253 1254 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1255 return; 1256 1257 s = splnet(); 1258 1259 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1260 1261 ifp->if_opackets += le32toh(sp->tx_good); 1262 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1263 if (sp->rx_good) { 1264 ifp->if_ipackets += le32toh(sp->rx_good); 1265 sc->sc_rxidle = 0; 1266 } else { 1267 sc->sc_rxidle++; 1268 } 1269 ifp->if_ierrors += 1270 le32toh(sp->rx_crc_errors) + 1271 le32toh(sp->rx_alignment_errors) + 1272 le32toh(sp->rx_rnr_errors) + 1273 le32toh(sp->rx_overrun_errors); 1274 /* 1275 * If any transmit underruns occurred, bump up the transmit 1276 * threshold by another 512 bytes (64 * 8). 1277 */ 1278 if (sp->tx_underruns) { 1279 ifp->if_oerrors += le32toh(sp->tx_underruns); 1280 if (tx_threshold < 192) 1281 tx_threshold += 64; 1282 } 1283 1284 /* 1285 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1286 * then assume the receiver has locked up and attempt to clear 1287 * the condition by reprogramming the multicast filter (actually, 1288 * resetting the interface). This is a work-around for a bug in 1289 * the 82557 where the receiver locks up if it gets certain types 1290 * of garbage in the syncronization bits prior to the packet header. 1291 * This bug is supposed to only occur in 10Mbps mode, but has been 1292 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1293 * speed transition). 1294 */ 1295 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1296 (void) fxp_init(sc); 1297 splx(s); 1298 return; 1299 } 1300 /* 1301 * If there is no pending command, start another stats 1302 * dump. Otherwise punt for now. 1303 */ 1304 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1305 /* 1306 * Start another stats dump. 1307 */ 1308 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1309 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1310 } else { 1311 /* 1312 * A previous command is still waiting to be accepted. 1313 * Just zero our copy of the stats and wait for the 1314 * next timer event to update them. 1315 */ 1316 /* BIG_ENDIAN: no swap required to store 0 */ 1317 sp->tx_good = 0; 1318 sp->tx_underruns = 0; 1319 sp->tx_total_collisions = 0; 1320 1321 sp->rx_good = 0; 1322 sp->rx_crc_errors = 0; 1323 sp->rx_alignment_errors = 0; 1324 sp->rx_rnr_errors = 0; 1325 sp->rx_overrun_errors = 0; 1326 } 1327 1328 if (sc->sc_flags & FXPF_MII) { 1329 /* Tick the MII clock. */ 1330 mii_tick(&sc->sc_mii); 1331 } 1332 1333 splx(s); 1334 1335 /* 1336 * Schedule another timeout one second from now. 1337 */ 1338 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1339 } 1340 1341 /* 1342 * Drain the receive queue. 1343 */ 1344 void 1345 fxp_rxdrain(struct fxp_softc *sc) 1346 { 1347 bus_dmamap_t rxmap; 1348 struct mbuf *m; 1349 1350 for (;;) { 1351 IF_DEQUEUE(&sc->sc_rxq, m); 1352 if (m == NULL) 1353 break; 1354 rxmap = M_GETCTX(m, bus_dmamap_t); 1355 bus_dmamap_unload(sc->sc_dmat, rxmap); 1356 FXP_RXMAP_PUT(sc, rxmap); 1357 m_freem(m); 1358 } 1359 } 1360 1361 /* 1362 * Stop the interface. Cancels the statistics updater and resets 1363 * the interface. 1364 */ 1365 void 1366 fxp_stop(struct fxp_softc *sc, int drain) 1367 { 1368 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1369 struct fxp_txsoft *txs; 1370 int i; 1371 1372 /* 1373 * Turn down interface (done early to avoid bad interactions 1374 * between panics, shutdown hooks, and the watchdog timer) 1375 */ 1376 ifp->if_timer = 0; 1377 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1378 1379 /* 1380 * Cancel stats updater. 1381 */ 1382 callout_stop(&sc->sc_callout); 1383 if (sc->sc_flags & FXPF_MII) { 1384 /* Down the MII. */ 1385 mii_down(&sc->sc_mii); 1386 } 1387 1388 /* 1389 * Issue software reset 1390 */ 1391 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1392 DELAY(10); 1393 1394 /* 1395 * Release any xmit buffers. 1396 */ 1397 for (i = 0; i < FXP_NTXCB; i++) { 1398 txs = FXP_DSTX(sc, i); 1399 if (txs->txs_mbuf != NULL) { 1400 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1401 m_freem(txs->txs_mbuf); 1402 txs->txs_mbuf = NULL; 1403 } 1404 } 1405 sc->sc_txpending = 0; 1406 1407 if (drain) { 1408 /* 1409 * Release the receive buffers. 1410 */ 1411 fxp_rxdrain(sc); 1412 } 1413 1414 } 1415 1416 /* 1417 * Watchdog/transmission transmit timeout handler. Called when a 1418 * transmission is started on the interface, but no interrupt is 1419 * received before the timeout. This usually indicates that the 1420 * card has wedged for some reason. 1421 */ 1422 void 1423 fxp_watchdog(struct ifnet *ifp) 1424 { 1425 struct fxp_softc *sc = ifp->if_softc; 1426 1427 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1428 ifp->if_oerrors++; 1429 1430 (void) fxp_init(sc); 1431 } 1432 1433 /* 1434 * Initialize the interface. Must be called at splnet(). 1435 */ 1436 int 1437 fxp_init(struct fxp_softc *sc) 1438 { 1439 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1440 struct fxp_cb_config *cbp; 1441 struct fxp_cb_ias *cb_ias; 1442 struct fxp_txdesc *txd; 1443 bus_dmamap_t rxmap; 1444 int i, prm, save_bf, lrxen, allm, error = 0; 1445 1446 /* 1447 * Cancel any pending I/O 1448 */ 1449 fxp_stop(sc, 0); 1450 1451 /* 1452 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1453 * flag, and this prevents the MII from detaching resulting in 1454 * a panic. The flags field should perhaps be split in runtime 1455 * flags and more static information. For now, just clear the 1456 * only other flag set. 1457 */ 1458 1459 sc->sc_flags &= ~FXPF_WANTINIT; 1460 1461 /* 1462 * Initialize base of CBL and RFA memory. Loading with zero 1463 * sets it up for regular linear addressing. 1464 */ 1465 fxp_scb_wait(sc); 1466 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1467 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1468 1469 fxp_scb_wait(sc); 1470 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1471 1472 /* 1473 * Initialize the multicast filter. Do this now, since we might 1474 * have to setup the config block differently. 1475 */ 1476 fxp_mc_setup(sc); 1477 1478 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1479 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1480 1481 /* 1482 * In order to support receiving 802.1Q VLAN frames, we have to 1483 * enable "save bad frames", since they are 4 bytes larger than 1484 * the normal Ethernet maximum frame length. On i82558 and later, 1485 * we have a better mechanism for this. 1486 */ 1487 save_bf = 0; 1488 lrxen = 0; 1489 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1490 if (sc->sc_rev < FXP_REV_82558_A4) 1491 save_bf = 1; 1492 else 1493 lrxen = 1; 1494 } 1495 1496 /* 1497 * Initialize base of dump-stats buffer. 1498 */ 1499 fxp_scb_wait(sc); 1500 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1501 sc->sc_cddma + FXP_CDSTATSOFF); 1502 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1503 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1504 1505 cbp = &sc->sc_control_data->fcd_configcb; 1506 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1507 1508 /* 1509 * This copy is kind of disgusting, but there are a bunch of must be 1510 * zero and must be one bits in this structure and this is the easiest 1511 * way to initialize them all to proper values. 1512 */ 1513 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1514 1515 /* BIG_ENDIAN: no need to swap to store 0 */ 1516 cbp->cb_status = 0; 1517 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1518 FXP_CB_COMMAND_EL); 1519 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1520 cbp->link_addr = 0xffffffff; /* (no) next command */ 1521 /* bytes in config block */ 1522 cbp->byte_count = FXP_CONFIG_LEN; 1523 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1524 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1525 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1526 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1527 cbp->type_enable = 0; /* actually reserved */ 1528 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1529 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1530 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1531 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1532 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1533 cbp->late_scb = 0; /* (don't) defer SCB update */ 1534 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1535 cbp->ci_int = 1; /* interrupt on CU idle */ 1536 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1537 cbp->ext_stats_dis = 1; /* disable extended counters */ 1538 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1539 cbp->save_bf = save_bf;/* save bad frames */ 1540 cbp->disc_short_rx = !prm; /* discard short packets */ 1541 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1542 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1543 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1544 /* interface mode */ 1545 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1546 cbp->csma_dis = 0; /* (don't) disable link */ 1547 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1548 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1549 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1550 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1551 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1552 cbp->nsai = 1; /* (don't) disable source addr insert */ 1553 cbp->preamble_length = 2; /* (7 byte) preamble */ 1554 cbp->loopback = 0; /* (don't) loopback */ 1555 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1556 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1557 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1558 cbp->promiscuous = prm; /* promiscuous mode */ 1559 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1560 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1561 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1562 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1563 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1564 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1565 cbp->padding = 1; /* (do) pad short tx packets */ 1566 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1567 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1568 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1569 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1570 /* must set wake_en in PMCSR also */ 1571 cbp->force_fdx = 0; /* (don't) force full duplex */ 1572 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1573 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1574 cbp->mc_all = allm; /* accept all multicasts */ 1575 1576 if (sc->sc_rev < FXP_REV_82558_A4) { 1577 /* 1578 * The i82557 has no hardware flow control, the values 1579 * here are the defaults for the chip. 1580 */ 1581 cbp->fc_delay_lsb = 0; 1582 cbp->fc_delay_msb = 0x40; 1583 cbp->pri_fc_thresh = 3; 1584 cbp->tx_fc_dis = 0; 1585 cbp->rx_fc_restop = 0; 1586 cbp->rx_fc_restart = 0; 1587 cbp->fc_filter = 0; 1588 cbp->pri_fc_loc = 1; 1589 } else { 1590 cbp->fc_delay_lsb = 0x1f; 1591 cbp->fc_delay_msb = 0x01; 1592 cbp->pri_fc_thresh = 3; 1593 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1594 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1595 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1596 cbp->fc_filter = !prm; /* drop FC frames to host */ 1597 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1598 } 1599 1600 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1601 1602 /* 1603 * Start the config command/DMA. 1604 */ 1605 fxp_scb_wait(sc); 1606 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1607 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1608 /* ...and wait for it to complete. */ 1609 i = 1000; 1610 do { 1611 FXP_CDCONFIGSYNC(sc, 1612 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1613 DELAY(1); 1614 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1615 if (i == 0) { 1616 printf("%s at line %d: dmasync timeout\n", 1617 sc->sc_dev.dv_xname, __LINE__); 1618 return ETIMEDOUT; 1619 } 1620 1621 /* 1622 * Initialize the station address. 1623 */ 1624 cb_ias = &sc->sc_control_data->fcd_iascb; 1625 /* BIG_ENDIAN: no need to swap to store 0 */ 1626 cb_ias->cb_status = 0; 1627 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1628 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1629 cb_ias->link_addr = 0xffffffff; 1630 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1631 1632 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1633 1634 /* 1635 * Start the IAS (Individual Address Setup) command/DMA. 1636 */ 1637 fxp_scb_wait(sc); 1638 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1639 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1640 /* ...and wait for it to complete. */ 1641 i = 1000; 1642 do { 1643 FXP_CDIASSYNC(sc, 1644 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1645 DELAY(1); 1646 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1647 if (i == 0) { 1648 printf("%s at line %d: dmasync timeout\n", 1649 sc->sc_dev.dv_xname, __LINE__); 1650 return ETIMEDOUT; 1651 } 1652 1653 /* 1654 * Initialize the transmit descriptor ring. txlast is initialized 1655 * to the end of the list so that it will wrap around to the first 1656 * descriptor when the first packet is transmitted. 1657 */ 1658 for (i = 0; i < FXP_NTXCB; i++) { 1659 txd = FXP_CDTX(sc, i); 1660 memset(txd, 0, sizeof(*txd)); 1661 txd->txd_txcb.cb_command = 1662 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1663 txd->txd_txcb.link_addr = 1664 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1665 if (sc->sc_flags & FXPF_EXT_TXCB) 1666 txd->txd_txcb.tbd_array_addr = 1667 htole32(FXP_CDTBDADDR(sc, i) + 1668 (2 * sizeof(struct fxp_tbd))); 1669 else 1670 txd->txd_txcb.tbd_array_addr = 1671 htole32(FXP_CDTBDADDR(sc, i)); 1672 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1673 } 1674 sc->sc_txpending = 0; 1675 sc->sc_txdirty = 0; 1676 sc->sc_txlast = FXP_NTXCB - 1; 1677 1678 /* 1679 * Initialize the receive buffer list. 1680 */ 1681 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1682 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1683 rxmap = FXP_RXMAP_GET(sc); 1684 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1685 printf("%s: unable to allocate or map rx " 1686 "buffer %d, error = %d\n", 1687 sc->sc_dev.dv_xname, 1688 sc->sc_rxq.ifq_len, error); 1689 /* 1690 * XXX Should attempt to run with fewer receive 1691 * XXX buffers instead of just failing. 1692 */ 1693 FXP_RXMAP_PUT(sc, rxmap); 1694 fxp_rxdrain(sc); 1695 goto out; 1696 } 1697 } 1698 sc->sc_rxidle = 0; 1699 1700 /* 1701 * Give the transmit ring to the chip. We do this by pointing 1702 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1703 * issuing a start command. It will execute the NOP and then 1704 * suspend, pointing at the first descriptor. 1705 */ 1706 fxp_scb_wait(sc); 1707 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1708 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1709 1710 /* 1711 * Initialize receiver buffer area - RFA. 1712 */ 1713 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1714 fxp_scb_wait(sc); 1715 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1716 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1717 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1718 1719 if (sc->sc_flags & FXPF_MII) { 1720 /* 1721 * Set current media. 1722 */ 1723 mii_mediachg(&sc->sc_mii); 1724 } 1725 1726 /* 1727 * ...all done! 1728 */ 1729 ifp->if_flags |= IFF_RUNNING; 1730 ifp->if_flags &= ~IFF_OACTIVE; 1731 1732 /* 1733 * Start the one second timer. 1734 */ 1735 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1736 1737 /* 1738 * Attempt to start output on the interface. 1739 */ 1740 fxp_start(ifp); 1741 1742 out: 1743 if (error) 1744 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1745 return (error); 1746 } 1747 1748 /* 1749 * Change media according to request. 1750 */ 1751 int 1752 fxp_mii_mediachange(struct ifnet *ifp) 1753 { 1754 struct fxp_softc *sc = ifp->if_softc; 1755 1756 if (ifp->if_flags & IFF_UP) 1757 mii_mediachg(&sc->sc_mii); 1758 return (0); 1759 } 1760 1761 /* 1762 * Notify the world which media we're using. 1763 */ 1764 void 1765 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1766 { 1767 struct fxp_softc *sc = ifp->if_softc; 1768 1769 if(sc->sc_enabled == 0) { 1770 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1771 ifmr->ifm_status = 0; 1772 return; 1773 } 1774 1775 mii_pollstat(&sc->sc_mii); 1776 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1777 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1778 } 1779 1780 int 1781 fxp_80c24_mediachange(struct ifnet *ifp) 1782 { 1783 1784 /* Nothing to do here. */ 1785 return (0); 1786 } 1787 1788 void 1789 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1790 { 1791 struct fxp_softc *sc = ifp->if_softc; 1792 1793 /* 1794 * Media is currently-selected media. We cannot determine 1795 * the link status. 1796 */ 1797 ifmr->ifm_status = 0; 1798 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1799 } 1800 1801 /* 1802 * Add a buffer to the end of the RFA buffer list. 1803 * Return 0 if successful, error code on failure. 1804 * 1805 * The RFA struct is stuck at the beginning of mbuf cluster and the 1806 * data pointer is fixed up to point just past it. 1807 */ 1808 int 1809 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1810 { 1811 struct mbuf *m; 1812 int error; 1813 1814 MGETHDR(m, M_DONTWAIT, MT_DATA); 1815 if (m == NULL) 1816 return (ENOBUFS); 1817 1818 MCLGET(m, M_DONTWAIT); 1819 if ((m->m_flags & M_EXT) == 0) { 1820 m_freem(m); 1821 return (ENOBUFS); 1822 } 1823 1824 if (unload) 1825 bus_dmamap_unload(sc->sc_dmat, rxmap); 1826 1827 M_SETCTX(m, rxmap); 1828 1829 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1830 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1831 if (error) { 1832 printf("%s: can't load rx DMA map %d, error = %d\n", 1833 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1834 panic("fxp_add_rfabuf"); /* XXX */ 1835 } 1836 1837 FXP_INIT_RFABUF(sc, m); 1838 1839 return (0); 1840 } 1841 1842 int 1843 fxp_mdi_read(struct device *self, int phy, int reg) 1844 { 1845 struct fxp_softc *sc = (struct fxp_softc *)self; 1846 int count = 10000; 1847 int value; 1848 1849 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1850 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1851 1852 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1853 && count--) 1854 DELAY(10); 1855 1856 if (count <= 0) 1857 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1858 1859 return (value & 0xffff); 1860 } 1861 1862 void 1863 fxp_statchg(struct device *self) 1864 { 1865 1866 /* Nothing to do. */ 1867 } 1868 1869 void 1870 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1871 { 1872 struct fxp_softc *sc = (struct fxp_softc *)self; 1873 int count = 10000; 1874 1875 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1876 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1877 (value & 0xffff)); 1878 1879 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1880 count--) 1881 DELAY(10); 1882 1883 if (count <= 0) 1884 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1885 } 1886 1887 int 1888 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1889 { 1890 struct fxp_softc *sc = ifp->if_softc; 1891 struct ifreq *ifr = (struct ifreq *)data; 1892 struct ifaddr *ifa = (struct ifaddr *)data; 1893 int s, error = 0; 1894 1895 s = splnet(); 1896 1897 switch (command) { 1898 case SIOCSIFADDR: 1899 if ((error = fxp_enable(sc)) != 0) 1900 break; 1901 ifp->if_flags |= IFF_UP; 1902 1903 switch (ifa->ifa_addr->sa_family) { 1904 #ifdef INET 1905 case AF_INET: 1906 if ((error = fxp_init(sc)) != 0) 1907 break; 1908 arp_ifinit(ifp, ifa); 1909 break; 1910 #endif /* INET */ 1911 #ifdef NS 1912 case AF_NS: 1913 { 1914 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1915 1916 if (ns_nullhost(*ina)) 1917 ina->x_host = *(union ns_host *) 1918 LLADDR(ifp->if_sadl); 1919 else 1920 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1921 ifp->if_addrlen); 1922 /* Set new address. */ 1923 error = fxp_init(sc); 1924 break; 1925 } 1926 #endif /* NS */ 1927 default: 1928 error = fxp_init(sc); 1929 break; 1930 } 1931 break; 1932 1933 case SIOCSIFMTU: 1934 if (ifr->ifr_mtu > ETHERMTU) 1935 error = EINVAL; 1936 else 1937 ifp->if_mtu = ifr->ifr_mtu; 1938 break; 1939 1940 case SIOCSIFFLAGS: 1941 if ((ifp->if_flags & IFF_UP) == 0 && 1942 (ifp->if_flags & IFF_RUNNING) != 0) { 1943 /* 1944 * If interface is marked down and it is running, then 1945 * stop it. 1946 */ 1947 fxp_stop(sc, 1); 1948 fxp_disable(sc); 1949 } else if ((ifp->if_flags & IFF_UP) != 0 && 1950 (ifp->if_flags & IFF_RUNNING) == 0) { 1951 /* 1952 * If interface is marked up and it is stopped, then 1953 * start it. 1954 */ 1955 if((error = fxp_enable(sc)) != 0) 1956 break; 1957 error = fxp_init(sc); 1958 } else if ((ifp->if_flags & IFF_UP) != 0) { 1959 /* 1960 * Reset the interface to pick up change in any other 1961 * flags that affect the hardware state. 1962 */ 1963 if((error = fxp_enable(sc)) != 0) 1964 break; 1965 error = fxp_init(sc); 1966 } 1967 break; 1968 1969 case SIOCADDMULTI: 1970 case SIOCDELMULTI: 1971 if(sc->sc_enabled == 0) { 1972 error = EIO; 1973 break; 1974 } 1975 error = (command == SIOCADDMULTI) ? 1976 ether_addmulti(ifr, &sc->sc_ethercom) : 1977 ether_delmulti(ifr, &sc->sc_ethercom); 1978 1979 if (error == ENETRESET) { 1980 /* 1981 * Multicast list has changed; set the hardware 1982 * filter accordingly. 1983 */ 1984 if (sc->sc_txpending) { 1985 sc->sc_flags |= FXPF_WANTINIT; 1986 error = 0; 1987 } else 1988 error = fxp_init(sc); 1989 } 1990 break; 1991 1992 case SIOCSIFMEDIA: 1993 case SIOCGIFMEDIA: 1994 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1995 break; 1996 1997 default: 1998 error = EINVAL; 1999 break; 2000 } 2001 2002 splx(s); 2003 return (error); 2004 } 2005 2006 /* 2007 * Program the multicast filter. 2008 * 2009 * This function must be called at splnet(). 2010 */ 2011 void 2012 fxp_mc_setup(struct fxp_softc *sc) 2013 { 2014 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2015 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2016 struct ethercom *ec = &sc->sc_ethercom; 2017 struct ether_multi *enm; 2018 struct ether_multistep step; 2019 int count, nmcasts; 2020 2021 #ifdef DIAGNOSTIC 2022 if (sc->sc_txpending) 2023 panic("fxp_mc_setup: pending transmissions"); 2024 #endif 2025 2026 ifp->if_flags &= ~IFF_ALLMULTI; 2027 2028 /* 2029 * Initialize multicast setup descriptor. 2030 */ 2031 nmcasts = 0; 2032 ETHER_FIRST_MULTI(step, ec, enm); 2033 while (enm != NULL) { 2034 /* 2035 * Check for too many multicast addresses or if we're 2036 * listening to a range. Either way, we simply have 2037 * to accept all multicasts. 2038 */ 2039 if (nmcasts >= MAXMCADDR || 2040 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2041 ETHER_ADDR_LEN) != 0) { 2042 /* 2043 * Callers of this function must do the 2044 * right thing with this. If we're called 2045 * from outside fxp_init(), the caller must 2046 * detect if the state if IFF_ALLMULTI changes. 2047 * If it does, the caller must then call 2048 * fxp_init(), since allmulti is handled by 2049 * the config block. 2050 */ 2051 ifp->if_flags |= IFF_ALLMULTI; 2052 return; 2053 } 2054 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2055 ETHER_ADDR_LEN); 2056 nmcasts++; 2057 ETHER_NEXT_MULTI(step, enm); 2058 } 2059 2060 /* BIG_ENDIAN: no need to swap to store 0 */ 2061 mcsp->cb_status = 0; 2062 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2063 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2064 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2065 2066 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2067 2068 /* 2069 * Wait until the command unit is not active. This should never 2070 * happen since nothing is queued, but make sure anyway. 2071 */ 2072 count = 100; 2073 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2074 FXP_SCB_CUS_ACTIVE && --count) 2075 DELAY(1); 2076 if (count == 0) { 2077 printf("%s at line %d: command queue timeout\n", 2078 sc->sc_dev.dv_xname, __LINE__); 2079 return; 2080 } 2081 2082 /* 2083 * Start the multicast setup command/DMA. 2084 */ 2085 fxp_scb_wait(sc); 2086 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2087 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2088 2089 /* ...and wait for it to complete. */ 2090 count = 1000; 2091 do { 2092 FXP_CDMCSSYNC(sc, 2093 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2094 DELAY(1); 2095 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2096 if (count == 0) { 2097 printf("%s at line %d: dmasync timeout\n", 2098 sc->sc_dev.dv_xname, __LINE__); 2099 return; 2100 } 2101 } 2102 2103 int 2104 fxp_enable(struct fxp_softc *sc) 2105 { 2106 2107 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2108 if ((*sc->sc_enable)(sc) != 0) { 2109 printf("%s: device enable failed\n", 2110 sc->sc_dev.dv_xname); 2111 return (EIO); 2112 } 2113 } 2114 2115 sc->sc_enabled = 1; 2116 return (0); 2117 } 2118 2119 void 2120 fxp_disable(struct fxp_softc *sc) 2121 { 2122 2123 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2124 (*sc->sc_disable)(sc); 2125 sc->sc_enabled = 0; 2126 } 2127 } 2128 2129 /* 2130 * fxp_activate: 2131 * 2132 * Handle device activation/deactivation requests. 2133 */ 2134 int 2135 fxp_activate(struct device *self, enum devact act) 2136 { 2137 struct fxp_softc *sc = (void *) self; 2138 int s, error = 0; 2139 2140 s = splnet(); 2141 switch (act) { 2142 case DVACT_ACTIVATE: 2143 error = EOPNOTSUPP; 2144 break; 2145 2146 case DVACT_DEACTIVATE: 2147 if (sc->sc_flags & FXPF_MII) 2148 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2149 MII_OFFSET_ANY); 2150 if_deactivate(&sc->sc_ethercom.ec_if); 2151 break; 2152 } 2153 splx(s); 2154 2155 return (error); 2156 } 2157 2158 /* 2159 * fxp_detach: 2160 * 2161 * Detach an i82557 interface. 2162 */ 2163 int 2164 fxp_detach(struct fxp_softc *sc) 2165 { 2166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2167 int i; 2168 2169 /* Succeed now if there's no work to do. */ 2170 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2171 return (0); 2172 2173 /* Unhook our tick handler. */ 2174 callout_stop(&sc->sc_callout); 2175 2176 if (sc->sc_flags & FXPF_MII) { 2177 /* Detach all PHYs */ 2178 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2179 } 2180 2181 /* Delete all remaining media. */ 2182 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2183 2184 #if NRND > 0 2185 rnd_detach_source(&sc->rnd_source); 2186 #endif 2187 #if NBPFILTER > 0 2188 bpfdetach(ifp); 2189 #endif 2190 ether_ifdetach(ifp); 2191 if_detach(ifp); 2192 2193 for (i = 0; i < FXP_NRFABUFS; i++) { 2194 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2195 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2196 } 2197 2198 for (i = 0; i < FXP_NTXCB; i++) { 2199 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2200 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2201 } 2202 2203 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2204 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2205 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2206 sizeof(struct fxp_control_data)); 2207 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2208 2209 shutdownhook_disestablish(sc->sc_sdhook); 2210 powerhook_disestablish(sc->sc_powerhook); 2211 2212 return (0); 2213 } 2214
Indexes created Sat Oct 25 16:10:12 GMT 2025