i82557.c revision 1.36
1 /* $NetBSD: i82557.c,v 1.36 2000/06/29 16:53:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <uvm/uvm_extern.h> 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia __P((struct fxp_softc *)); 169 int fxp_mii_mediachange __P((struct ifnet *)); 170 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 void fxp_80c24_initmedia __P((struct fxp_softc *)); 173 int fxp_80c24_mediachange __P((struct ifnet *)); 174 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176 inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178 void fxp_start __P((struct ifnet *)); 179 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180 int fxp_init __P((struct fxp_softc *)); 181 void fxp_rxdrain __P((struct fxp_softc *)); 182 void fxp_stop __P((struct fxp_softc *, int)); 183 void fxp_watchdog __P((struct ifnet *)); 184 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 185 int fxp_mdi_read __P((struct device *, int, int)); 186 void fxp_statchg __P((struct device *)); 187 void fxp_mdi_write __P((struct device *, int, int, int)); 188 void fxp_autosize_eeprom __P((struct fxp_softc*)); 189 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 190 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 191 void fxp_tick __P((void *)); 192 void fxp_mc_setup __P((struct fxp_softc *)); 193 194 void fxp_shutdown __P((void *)); 195 void fxp_power __P((int, void *)); 196 197 int fxp_copy_small = 0; 198 199 struct fxp_phytype { 200 int fp_phy; /* type of PHY, -1 for MII at the end. */ 201 void (*fp_init) __P((struct fxp_softc *)); 202 } fxp_phytype_table[] = { 203 { FXP_PHY_80C24, fxp_80c24_initmedia }, 204 { -1, fxp_mii_initmedia }, 205 }; 206 207 /* 208 * Set initial transmit threshold at 64 (512 bytes). This is 209 * increased by 64 (512 bytes) at a time, to maximum of 192 210 * (1536 bytes), if an underrun occurs. 211 */ 212 static int tx_threshold = 64; 213 214 /* 215 * Wait for the previous command to be accepted (but not necessarily 216 * completed). 217 */ 218 inline void 219 fxp_scb_wait(sc) 220 struct fxp_softc *sc; 221 { 222 int i = 10000; 223 224 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 225 delay(2); 226 if (i == 0) 227 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 228 } 229 230 /* 231 * Finish attaching an i82557 interface. Called by bus-specific front-end. 232 */ 233 void 234 fxp_attach(sc) 235 struct fxp_softc *sc; 236 { 237 u_int8_t enaddr[6]; 238 struct ifnet *ifp; 239 bus_dma_segment_t seg; 240 int rseg, i, error; 241 struct fxp_phytype *fp; 242 243 callout_init(&sc->sc_callout); 244 245 /* 246 * Allocate the control data structures, and create and load the 247 * DMA map for it. 248 */ 249 if ((error = bus_dmamem_alloc(sc->sc_dmat, 250 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 251 0)) != 0) { 252 printf("%s: unable to allocate control data, error = %d\n", 253 sc->sc_dev.dv_xname, error); 254 goto fail_0; 255 } 256 257 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 258 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 259 BUS_DMA_COHERENT)) != 0) { 260 printf("%s: unable to map control data, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 goto fail_1; 263 } 264 sc->sc_cdseg = seg; 265 sc->sc_cdnseg = rseg; 266 267 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 268 269 if ((error = bus_dmamap_create(sc->sc_dmat, 270 sizeof(struct fxp_control_data), 1, 271 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 272 printf("%s: unable to create control data DMA map, " 273 "error = %d\n", sc->sc_dev.dv_xname, error); 274 goto fail_2; 275 } 276 277 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 278 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 279 0)) != 0) { 280 printf("%s: can't load control data DMA map, error = %d\n", 281 sc->sc_dev.dv_xname, error); 282 goto fail_3; 283 } 284 285 /* 286 * Create the transmit buffer DMA maps. 287 */ 288 for (i = 0; i < FXP_NTXCB; i++) { 289 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 290 FXP_NTXSEG, MCLBYTES, 0, 0, 291 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 292 printf("%s: unable to create tx DMA map %d, " 293 "error = %d\n", sc->sc_dev.dv_xname, i, error); 294 goto fail_4; 295 } 296 } 297 298 /* 299 * Create the receive buffer DMA maps. 300 */ 301 for (i = 0; i < FXP_NRFABUFS; i++) { 302 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 303 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 304 printf("%s: unable to create rx DMA map %d, " 305 "error = %d\n", sc->sc_dev.dv_xname, i, error); 306 goto fail_5; 307 } 308 } 309 310 /* Initialize MAC address and media structures. */ 311 fxp_get_info(sc, enaddr); 312 313 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 314 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 315 316 ifp = &sc->sc_ethercom.ec_if; 317 318 /* 319 * Get info about our media interface, and initialize it. Note 320 * the table terminates itself with a phy of -1, indicating 321 * that we're using MII. 322 */ 323 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 324 if (fp->fp_phy == sc->phy_primary_device) 325 break; 326 (*fp->fp_init)(sc); 327 328 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 329 ifp->if_softc = sc; 330 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 331 ifp->if_ioctl = fxp_ioctl; 332 ifp->if_start = fxp_start; 333 ifp->if_watchdog = fxp_watchdog; 334 335 /* 336 * Attach the interface. 337 */ 338 if_attach(ifp); 339 ether_ifattach(ifp, enaddr); 340 #if NBPFILTER > 0 341 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 342 sizeof(struct ether_header)); 343 #endif 344 #if NRND > 0 345 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 346 RND_TYPE_NET, 0); 347 #endif 348 349 /* 350 * Add shutdown hook so that DMA is disabled prior to reboot. Not 351 * doing do could allow DMA to corrupt kernel memory during the 352 * reboot before the driver initializes. 353 */ 354 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 355 if (sc->sc_sdhook == NULL) 356 printf("%s: WARNING: unable to establish shutdown hook\n", 357 sc->sc_dev.dv_xname); 358 /* 359 * Add suspend hook, for similar reasons.. 360 */ 361 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 362 if (sc->sc_powerhook == NULL) 363 printf("%s: WARNING: unable to establish power hook\n", 364 sc->sc_dev.dv_xname); 365 366 /* The attach is successful. */ 367 sc->sc_flags |= FXPF_ATTACHED; 368 369 return; 370 371 /* 372 * Free any resources we've allocated during the failed attach 373 * attempt. Do this in reverse order and fall though. 374 */ 375 fail_5: 376 for (i = 0; i < FXP_NRFABUFS; i++) { 377 if (sc->sc_rxmaps[i] != NULL) 378 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 379 } 380 fail_4: 381 for (i = 0; i < FXP_NTXCB; i++) { 382 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 383 bus_dmamap_destroy(sc->sc_dmat, 384 FXP_DSTX(sc, i)->txs_dmamap); 385 } 386 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 387 fail_3: 388 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 389 fail_2: 390 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 391 sizeof(struct fxp_control_data)); 392 fail_1: 393 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 394 fail_0: 395 return; 396 } 397 398 void 399 fxp_mii_initmedia(sc) 400 struct fxp_softc *sc; 401 { 402 403 sc->sc_flags |= FXPF_MII; 404 405 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 406 sc->sc_mii.mii_readreg = fxp_mdi_read; 407 sc->sc_mii.mii_writereg = fxp_mdi_write; 408 sc->sc_mii.mii_statchg = fxp_statchg; 409 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 410 fxp_mii_mediastatus); 411 /* 412 * The i82557 wedges if all of its PHYs are isolated! 413 */ 414 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 415 MII_OFFSET_ANY, MIIF_NOISOLATE); 416 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 417 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 418 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 419 } else 420 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 421 } 422 423 void 424 fxp_80c24_initmedia(sc) 425 struct fxp_softc *sc; 426 { 427 428 /* 429 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 430 * doesn't have a programming interface of any sort. The 431 * media is sensed automatically based on how the link partner 432 * is configured. This is, in essence, manual configuration. 433 */ 434 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 435 sc->sc_dev.dv_xname); 436 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 437 fxp_80c24_mediastatus); 438 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 439 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 440 } 441 442 /* 443 * Device shutdown routine. Called at system shutdown after sync. The 444 * main purpose of this routine is to shut off receiver DMA so that 445 * kernel memory doesn't get clobbered during warmboot. 446 */ 447 void 448 fxp_shutdown(arg) 449 void *arg; 450 { 451 struct fxp_softc *sc = arg; 452 453 /* 454 * Since the system's going to halt shortly, don't bother 455 * freeing mbufs. 456 */ 457 fxp_stop(sc, 0); 458 } 459 /* 460 * Power handler routine. Called when the system is transitioning 461 * into/out of power save modes. As with fxp_shutdown, the main 462 * purpose of this routine is to shut off receiver DMA so it doesn't 463 * clobber kernel memory at the wrong time. 464 */ 465 void 466 fxp_power(why, arg) 467 int why; 468 void *arg; 469 { 470 struct fxp_softc *sc = arg; 471 struct ifnet *ifp; 472 int s; 473 474 s = splnet(); 475 if (why != PWR_RESUME) 476 fxp_stop(sc, 0); 477 else { 478 ifp = &sc->sc_ethercom.ec_if; 479 if (ifp->if_flags & IFF_UP) 480 fxp_init(sc); 481 } 482 splx(s); 483 } 484 485 /* 486 * Initialize the interface media. 487 */ 488 void 489 fxp_get_info(sc, enaddr) 490 struct fxp_softc *sc; 491 u_int8_t *enaddr; 492 { 493 u_int16_t data, myea[3]; 494 495 /* 496 * Reset to a stable state. 497 */ 498 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 499 DELAY(10); 500 501 sc->sc_eeprom_size = 0; 502 fxp_autosize_eeprom(sc); 503 if(sc->sc_eeprom_size == 0) { 504 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 505 sc->sc_eeprom_size = 6; /* XXX panic here? */ 506 } 507 #ifdef DEBUG 508 printf("%s: detected %d word EEPROM\n", 509 sc->sc_dev.dv_xname, 510 1 << sc->sc_eeprom_size); 511 #endif 512 513 /* 514 * Get info about the primary PHY 515 */ 516 fxp_read_eeprom(sc, &data, 6, 1); 517 sc->phy_primary_addr = data & 0xff; 518 sc->phy_primary_device = (data >> 8) & 0x3f; 519 sc->phy_10Mbps_only = data >> 15; 520 521 /* 522 * Read MAC address. 523 */ 524 fxp_read_eeprom(sc, myea, 0, 3); 525 enaddr[0] = myea[0] & 0xff; 526 enaddr[1] = myea[0] >> 8; 527 enaddr[2] = myea[1] & 0xff; 528 enaddr[3] = myea[1] >> 8; 529 enaddr[4] = myea[2] & 0xff; 530 enaddr[5] = myea[2] >> 8; 531 } 532 533 /* 534 * Figure out EEPROM size. 535 * 536 * 559's can have either 64-word or 256-word EEPROMs, the 558 537 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 538 * talks about the existance of 16 to 256 word EEPROMs. 539 * 540 * The only known sizes are 64 and 256, where the 256 version is used 541 * by CardBus cards to store CIS information. 542 * 543 * The address is shifted in msb-to-lsb, and after the last 544 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 545 * after which follows the actual data. We try to detect this zero, by 546 * probing the data-out bit in the EEPROM control register just after 547 * having shifted in a bit. If the bit is zero, we assume we've 548 * shifted enough address bits. The data-out should be tri-state, 549 * before this, which should translate to a logical one. 550 * 551 * Other ways to do this would be to try to read a register with known 552 * contents with a varying number of address bits, but no such 553 * register seem to be available. The high bits of register 10 are 01 554 * on the 558 and 559, but apparently not on the 557. 555 * 556 * The Linux driver computes a checksum on the EEPROM data, but the 557 * value of this checksum is not very well documented. 558 */ 559 560 void 561 fxp_autosize_eeprom(sc) 562 struct fxp_softc *sc; 563 { 564 u_int16_t reg; 565 int x; 566 567 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 568 /* 569 * Shift in read opcode. 570 */ 571 for (x = 3; x > 0; x--) { 572 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 573 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 574 } else { 575 reg = FXP_EEPROM_EECS; 576 } 577 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 578 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 579 reg | FXP_EEPROM_EESK); 580 DELAY(4); 581 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 582 DELAY(4); 583 } 584 /* 585 * Shift in address, wait for the dummy zero following a correct 586 * address shift. 587 */ 588 for (x = 1; x <= 8; x++) { 589 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 590 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 591 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 592 DELAY(4); 593 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 594 FXP_EEPROM_EEDO) == 0) 595 break; 596 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 597 DELAY(4); 598 } 599 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 600 DELAY(4); 601 if(x != 6 && x != 8) { 602 #ifdef DEBUG 603 printf("%s: strange EEPROM size (%d)\n", 604 sc->sc_dev.dv_xname, 1 << x); 605 #endif 606 } else 607 sc->sc_eeprom_size = x; 608 } 609 610 /* 611 * Read from the serial EEPROM. Basically, you manually shift in 612 * the read opcode (one bit at a time) and then shift in the address, 613 * and then you shift out the data (all of this one bit at a time). 614 * The word size is 16 bits, so you have to provide the address for 615 * every 16 bits of data. 616 */ 617 void 618 fxp_read_eeprom(sc, data, offset, words) 619 struct fxp_softc *sc; 620 u_int16_t *data; 621 int offset; 622 int words; 623 { 624 u_int16_t reg; 625 int i, x; 626 627 for (i = 0; i < words; i++) { 628 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 629 /* 630 * Shift in read opcode. 631 */ 632 for (x = 3; x > 0; x--) { 633 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 634 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 635 } else { 636 reg = FXP_EEPROM_EECS; 637 } 638 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 640 reg | FXP_EEPROM_EESK); 641 DELAY(4); 642 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 643 DELAY(4); 644 } 645 /* 646 * Shift in address. 647 */ 648 for (x = sc->sc_eeprom_size; x > 0; x--) { 649 if ((i + offset) & (1 << (x - 1))) { 650 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 651 } else { 652 reg = FXP_EEPROM_EECS; 653 } 654 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 655 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 656 reg | FXP_EEPROM_EESK); 657 DELAY(4); 658 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 659 DELAY(4); 660 } 661 reg = FXP_EEPROM_EECS; 662 data[i] = 0; 663 /* 664 * Shift out data. 665 */ 666 for (x = 16; x > 0; x--) { 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 668 reg | FXP_EEPROM_EESK); 669 DELAY(4); 670 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 671 FXP_EEPROM_EEDO) 672 data[i] |= (1 << (x - 1)); 673 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 674 DELAY(4); 675 } 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 677 DELAY(4); 678 } 679 } 680 681 /* 682 * Start packet transmission on the interface. 683 */ 684 void 685 fxp_start(ifp) 686 struct ifnet *ifp; 687 { 688 struct fxp_softc *sc = ifp->if_softc; 689 struct mbuf *m0, *m; 690 struct fxp_cb_tx *txd; 691 struct fxp_txsoft *txs; 692 struct fxp_tbdlist *tbd; 693 bus_dmamap_t dmamap; 694 int error, lasttx, nexttx, opending, seg; 695 696 /* 697 * If we want a re-init, bail out now. 698 */ 699 if (sc->sc_flags & FXPF_WANTINIT) { 700 ifp->if_flags |= IFF_OACTIVE; 701 return; 702 } 703 704 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 705 return; 706 707 /* 708 * Remember the previous txpending and the current lasttx. 709 */ 710 opending = sc->sc_txpending; 711 lasttx = sc->sc_txlast; 712 713 /* 714 * Loop through the send queue, setting up transmit descriptors 715 * until we drain the queue, or use up all available transmit 716 * descriptors. 717 */ 718 while (sc->sc_txpending < FXP_NTXCB) { 719 /* 720 * Grab a packet off the queue. 721 */ 722 IF_DEQUEUE(&ifp->if_snd, m0); 723 if (m0 == NULL) 724 break; 725 726 /* 727 * Get the next available transmit descriptor. 728 */ 729 nexttx = FXP_NEXTTX(sc->sc_txlast); 730 txd = FXP_CDTX(sc, nexttx); 731 tbd = FXP_CDTBD(sc, nexttx); 732 txs = FXP_DSTX(sc, nexttx); 733 dmamap = txs->txs_dmamap; 734 735 /* 736 * Load the DMA map. If this fails, the packet either 737 * didn't fit in the allotted number of frags, or we were 738 * short on resources. In this case, we'll copy and try 739 * again. 740 */ 741 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 742 BUS_DMA_NOWAIT) != 0) { 743 MGETHDR(m, M_DONTWAIT, MT_DATA); 744 if (m == NULL) { 745 printf("%s: unable to allocate Tx mbuf\n", 746 sc->sc_dev.dv_xname); 747 IF_PREPEND(&ifp->if_snd, m0); 748 break; 749 } 750 if (m0->m_pkthdr.len > MHLEN) { 751 MCLGET(m, M_DONTWAIT); 752 if ((m->m_flags & M_EXT) == 0) { 753 printf("%s: unable to allocate Tx " 754 "cluster\n", sc->sc_dev.dv_xname); 755 m_freem(m); 756 IF_PREPEND(&ifp->if_snd, m0); 757 break; 758 } 759 } 760 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 761 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 762 m_freem(m0); 763 m0 = m; 764 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 765 m0, BUS_DMA_NOWAIT); 766 if (error) { 767 printf("%s: unable to load Tx buffer, " 768 "error = %d\n", sc->sc_dev.dv_xname, error); 769 IF_PREPEND(&ifp->if_snd, m0); 770 break; 771 } 772 } 773 774 /* Initialize the fraglist. */ 775 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 776 tbd->tbd_d[seg].tb_addr = 777 htole32(dmamap->dm_segs[seg].ds_addr); 778 tbd->tbd_d[seg].tb_size = 779 htole32(dmamap->dm_segs[seg].ds_len); 780 } 781 782 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 783 784 /* Sync the DMA map. */ 785 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 786 BUS_DMASYNC_PREWRITE); 787 788 /* 789 * Store a pointer to the packet so we can free it later. 790 */ 791 txs->txs_mbuf = m0; 792 793 /* 794 * Initialize the transmit descriptor. 795 */ 796 /* BIG_ENDIAN: no need to swap to store 0 */ 797 txd->cb_status = 0; 798 txd->cb_command = 799 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 800 txd->tx_threshold = tx_threshold; 801 txd->tbd_number = dmamap->dm_nsegs; 802 803 FXP_CDTXSYNC(sc, nexttx, 804 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 805 806 /* Advance the tx pointer. */ 807 sc->sc_txpending++; 808 sc->sc_txlast = nexttx; 809 810 #if NBPFILTER > 0 811 /* 812 * Pass packet to bpf if there is a listener. 813 */ 814 if (ifp->if_bpf) 815 bpf_mtap(ifp->if_bpf, m0); 816 #endif 817 } 818 819 if (sc->sc_txpending == FXP_NTXCB) { 820 /* No more slots; notify upper layer. */ 821 ifp->if_flags |= IFF_OACTIVE; 822 } 823 824 if (sc->sc_txpending != opending) { 825 /* 826 * We enqueued packets. If the transmitter was idle, 827 * reset the txdirty pointer. 828 */ 829 if (opending == 0) 830 sc->sc_txdirty = FXP_NEXTTX(lasttx); 831 832 /* 833 * Cause the chip to interrupt and suspend command 834 * processing once the last packet we've enqueued 835 * has been transmitted. 836 */ 837 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 838 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 839 FXP_CDTXSYNC(sc, sc->sc_txlast, 840 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 841 842 /* 843 * The entire packet chain is set up. Clear the suspend bit 844 * on the command prior to the first packet we set up. 845 */ 846 FXP_CDTXSYNC(sc, lasttx, 847 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 848 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 849 FXP_CDTXSYNC(sc, lasttx, 850 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 851 852 /* 853 * Issue a Resume command in case the chip was suspended. 854 */ 855 fxp_scb_wait(sc); 856 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 857 858 /* Set a watchdog timer in case the chip flakes out. */ 859 ifp->if_timer = 5; 860 } 861 } 862 863 /* 864 * Process interface interrupts. 865 */ 866 int 867 fxp_intr(arg) 868 void *arg; 869 { 870 struct fxp_softc *sc = arg; 871 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 872 struct fxp_cb_tx *txd; 873 struct fxp_txsoft *txs; 874 struct mbuf *m, *m0; 875 bus_dmamap_t rxmap; 876 struct fxp_rfa *rfa; 877 struct ether_header *eh; 878 int i, claimed = 0; 879 u_int16_t len, rxstat, txstat; 880 u_int8_t statack; 881 882 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 883 return (0); 884 /* 885 * If the interface isn't running, don't try to 886 * service the interrupt.. just ack it and bail. 887 */ 888 if ((ifp->if_flags & IFF_RUNNING) == 0) { 889 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 890 if (statack) { 891 claimed = 1; 892 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 893 } 894 return (claimed); 895 } 896 897 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 898 claimed = 1; 899 900 /* 901 * First ACK all the interrupts in this pass. 902 */ 903 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 904 905 /* 906 * Process receiver interrupts. If a no-resource (RNR) 907 * condition exists, get whatever packets we can and 908 * re-start the receiver. 909 */ 910 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 911 rcvloop: 912 m = sc->sc_rxq.ifq_head; 913 rfa = FXP_MTORFA(m); 914 rxmap = M_GETCTX(m, bus_dmamap_t); 915 916 FXP_RFASYNC(sc, m, 917 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 918 919 rxstat = le16toh(rfa->rfa_status); 920 921 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 922 /* 923 * We have processed all of the 924 * receive buffers. 925 */ 926 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 927 goto do_transmit; 928 } 929 930 IF_DEQUEUE(&sc->sc_rxq, m); 931 932 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 933 934 len = le16toh(rfa->actual_size) & 935 (m->m_ext.ext_size - 1); 936 937 if (len < sizeof(struct ether_header)) { 938 /* 939 * Runt packet; drop it now. 940 */ 941 FXP_INIT_RFABUF(sc, m); 942 goto rcvloop; 943 } 944 945 /* 946 * If the packet is small enough to fit in a 947 * single header mbuf, allocate one and copy 948 * the data into it. This greatly reduces 949 * memory consumption when we receive lots 950 * of small packets. 951 * 952 * Otherwise, we add a new buffer to the receive 953 * chain. If this fails, we drop the packet and 954 * recycle the old buffer. 955 */ 956 if (fxp_copy_small != 0 && len <= MHLEN) { 957 MGETHDR(m0, M_DONTWAIT, MT_DATA); 958 if (m == NULL) 959 goto dropit; 960 memcpy(mtod(m0, caddr_t), 961 mtod(m, caddr_t), len); 962 FXP_INIT_RFABUF(sc, m); 963 m = m0; 964 } else { 965 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 966 dropit: 967 ifp->if_ierrors++; 968 FXP_INIT_RFABUF(sc, m); 969 goto rcvloop; 970 } 971 } 972 973 m->m_pkthdr.rcvif = ifp; 974 m->m_pkthdr.len = m->m_len = len; 975 eh = mtod(m, struct ether_header *); 976 977 #if NBPFILTER > 0 978 /* 979 * Pass this up to any BPF listeners, but only 980 * pass it up the stack it its for us. 981 */ 982 if (ifp->if_bpf) { 983 bpf_mtap(ifp->if_bpf, m); 984 985 if ((ifp->if_flags & IFF_PROMISC) != 0 && 986 (rxstat & FXP_RFA_STATUS_IAMATCH) != 0 && 987 (eh->ether_dhost[0] & 1) == 0) { 988 m_freem(m); 989 goto rcvloop; 990 } 991 } 992 #endif /* NBPFILTER > 0 */ 993 994 /* Pass it on. */ 995 (*ifp->if_input)(ifp, m); 996 goto rcvloop; 997 } 998 999 do_transmit: 1000 if (statack & FXP_SCB_STATACK_RNR) { 1001 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1002 fxp_scb_wait(sc); 1003 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1004 rxmap->dm_segs[0].ds_addr + 1005 RFA_ALIGNMENT_FUDGE); 1006 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1007 FXP_SCB_COMMAND_RU_START); 1008 } 1009 1010 /* 1011 * Free any finished transmit mbuf chains. 1012 */ 1013 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1014 ifp->if_flags &= ~IFF_OACTIVE; 1015 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1016 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1017 txd = FXP_CDTX(sc, i); 1018 txs = FXP_DSTX(sc, i); 1019 1020 FXP_CDTXSYNC(sc, i, 1021 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1022 1023 txstat = le16toh(txd->cb_status); 1024 1025 if ((txstat & FXP_CB_STATUS_C) == 0) 1026 break; 1027 1028 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1029 1030 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1031 0, txs->txs_dmamap->dm_mapsize, 1032 BUS_DMASYNC_POSTWRITE); 1033 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1034 m_freem(txs->txs_mbuf); 1035 txs->txs_mbuf = NULL; 1036 } 1037 1038 /* Update the dirty transmit buffer pointer. */ 1039 sc->sc_txdirty = i; 1040 1041 /* 1042 * Cancel the watchdog timer if there are no pending 1043 * transmissions. 1044 */ 1045 if (sc->sc_txpending == 0) { 1046 ifp->if_timer = 0; 1047 1048 /* 1049 * If we want a re-init, do that now. 1050 */ 1051 if (sc->sc_flags & FXPF_WANTINIT) 1052 (void) fxp_init(sc); 1053 } 1054 1055 /* 1056 * Try to get more packets going. 1057 */ 1058 fxp_start(ifp); 1059 } 1060 } 1061 1062 #if NRND > 0 1063 if (claimed) 1064 rnd_add_uint32(&sc->rnd_source, statack); 1065 #endif 1066 return (claimed); 1067 } 1068 1069 /* 1070 * Update packet in/out/collision statistics. The i82557 doesn't 1071 * allow you to access these counters without doing a fairly 1072 * expensive DMA to get _all_ of the statistics it maintains, so 1073 * we do this operation here only once per second. The statistics 1074 * counters in the kernel are updated from the previous dump-stats 1075 * DMA and then a new dump-stats DMA is started. The on-chip 1076 * counters are zeroed when the DMA completes. If we can't start 1077 * the DMA immediately, we don't wait - we just prepare to read 1078 * them again next time. 1079 */ 1080 void 1081 fxp_tick(arg) 1082 void *arg; 1083 { 1084 struct fxp_softc *sc = arg; 1085 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1086 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1087 int s; 1088 1089 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1090 return; 1091 1092 s = splnet(); 1093 1094 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1095 1096 ifp->if_opackets += le32toh(sp->tx_good); 1097 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1098 if (sp->rx_good) { 1099 ifp->if_ipackets += le32toh(sp->rx_good); 1100 sc->sc_rxidle = 0; 1101 } else { 1102 sc->sc_rxidle++; 1103 } 1104 ifp->if_ierrors += 1105 le32toh(sp->rx_crc_errors) + 1106 le32toh(sp->rx_alignment_errors) + 1107 le32toh(sp->rx_rnr_errors) + 1108 le32toh(sp->rx_overrun_errors); 1109 /* 1110 * If any transmit underruns occured, bump up the transmit 1111 * threshold by another 512 bytes (64 * 8). 1112 */ 1113 if (sp->tx_underruns) { 1114 ifp->if_oerrors += le32toh(sp->tx_underruns); 1115 if (tx_threshold < 192) 1116 tx_threshold += 64; 1117 } 1118 1119 /* 1120 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1121 * then assume the receiver has locked up and attempt to clear 1122 * the condition by reprogramming the multicast filter (actually, 1123 * resetting the interface). This is a work-around for a bug in 1124 * the 82557 where the receiver locks up if it gets certain types 1125 * of garbage in the syncronization bits prior to the packet header. 1126 * This bug is supposed to only occur in 10Mbps mode, but has been 1127 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1128 * speed transition). 1129 */ 1130 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1131 (void) fxp_init(sc); 1132 splx(s); 1133 return; 1134 } 1135 /* 1136 * If there is no pending command, start another stats 1137 * dump. Otherwise punt for now. 1138 */ 1139 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1140 /* 1141 * Start another stats dump. 1142 */ 1143 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1144 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1145 FXP_SCB_COMMAND_CU_DUMPRESET); 1146 } else { 1147 /* 1148 * A previous command is still waiting to be accepted. 1149 * Just zero our copy of the stats and wait for the 1150 * next timer event to update them. 1151 */ 1152 /* BIG_ENDIAN: no swap required to store 0 */ 1153 sp->tx_good = 0; 1154 sp->tx_underruns = 0; 1155 sp->tx_total_collisions = 0; 1156 1157 sp->rx_good = 0; 1158 sp->rx_crc_errors = 0; 1159 sp->rx_alignment_errors = 0; 1160 sp->rx_rnr_errors = 0; 1161 sp->rx_overrun_errors = 0; 1162 } 1163 1164 if (sc->sc_flags & FXPF_MII) { 1165 /* Tick the MII clock. */ 1166 mii_tick(&sc->sc_mii); 1167 } 1168 1169 splx(s); 1170 1171 /* 1172 * Schedule another timeout one second from now. 1173 */ 1174 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1175 } 1176 1177 /* 1178 * Drain the receive queue. 1179 */ 1180 void 1181 fxp_rxdrain(sc) 1182 struct fxp_softc *sc; 1183 { 1184 bus_dmamap_t rxmap; 1185 struct mbuf *m; 1186 1187 for (;;) { 1188 IF_DEQUEUE(&sc->sc_rxq, m); 1189 if (m == NULL) 1190 break; 1191 rxmap = M_GETCTX(m, bus_dmamap_t); 1192 bus_dmamap_unload(sc->sc_dmat, rxmap); 1193 FXP_RXMAP_PUT(sc, rxmap); 1194 m_freem(m); 1195 } 1196 } 1197 1198 /* 1199 * Stop the interface. Cancels the statistics updater and resets 1200 * the interface. 1201 */ 1202 void 1203 fxp_stop(sc, drain) 1204 struct fxp_softc *sc; 1205 int drain; 1206 { 1207 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1208 struct fxp_txsoft *txs; 1209 int i; 1210 1211 /* 1212 * Turn down interface (done early to avoid bad interactions 1213 * between panics, shutdown hooks, and the watchdog timer) 1214 */ 1215 ifp->if_timer = 0; 1216 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1217 1218 /* 1219 * Cancel stats updater. 1220 */ 1221 callout_stop(&sc->sc_callout); 1222 if (sc->sc_flags & FXPF_MII) { 1223 /* Down the MII. */ 1224 mii_down(&sc->sc_mii); 1225 } 1226 1227 /* 1228 * Issue software reset 1229 */ 1230 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1231 DELAY(10); 1232 1233 /* 1234 * Release any xmit buffers. 1235 */ 1236 for (i = 0; i < FXP_NTXCB; i++) { 1237 txs = FXP_DSTX(sc, i); 1238 if (txs->txs_mbuf != NULL) { 1239 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1240 m_freem(txs->txs_mbuf); 1241 txs->txs_mbuf = NULL; 1242 } 1243 } 1244 sc->sc_txpending = 0; 1245 1246 if (drain) { 1247 /* 1248 * Release the receive buffers. 1249 */ 1250 fxp_rxdrain(sc); 1251 } 1252 1253 } 1254 1255 /* 1256 * Watchdog/transmission transmit timeout handler. Called when a 1257 * transmission is started on the interface, but no interrupt is 1258 * received before the timeout. This usually indicates that the 1259 * card has wedged for some reason. 1260 */ 1261 void 1262 fxp_watchdog(ifp) 1263 struct ifnet *ifp; 1264 { 1265 struct fxp_softc *sc = ifp->if_softc; 1266 1267 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1268 ifp->if_oerrors++; 1269 1270 (void) fxp_init(sc); 1271 } 1272 1273 /* 1274 * Initialize the interface. Must be called at splnet(). 1275 */ 1276 int 1277 fxp_init(sc) 1278 struct fxp_softc *sc; 1279 { 1280 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1281 struct fxp_cb_config *cbp; 1282 struct fxp_cb_ias *cb_ias; 1283 struct fxp_cb_tx *txd; 1284 bus_dmamap_t rxmap; 1285 int i, prm, allm, error = 0; 1286 1287 /* 1288 * Cancel any pending I/O 1289 */ 1290 fxp_stop(sc, 0); 1291 1292 /* 1293 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1294 * flag, and this prevents the MII from detaching resulting in 1295 * a panic. The flags field should perhaps be split in runtime 1296 * flags and more static information. For now, just clear the 1297 * only other flag set. 1298 */ 1299 1300 sc->sc_flags &= ~FXPF_WANTINIT; 1301 1302 /* 1303 * Initialize base of CBL and RFA memory. Loading with zero 1304 * sets it up for regular linear addressing. 1305 */ 1306 fxp_scb_wait(sc); 1307 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1309 1310 fxp_scb_wait(sc); 1311 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1312 1313 /* 1314 * Initialize the multicast filter. Do this now, since we might 1315 * have to setup the config block differently. 1316 */ 1317 fxp_mc_setup(sc); 1318 1319 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1320 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1321 1322 /* 1323 * Initialize base of dump-stats buffer. 1324 */ 1325 fxp_scb_wait(sc); 1326 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1327 sc->sc_cddma + FXP_CDSTATSOFF); 1328 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1329 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1330 1331 cbp = &sc->sc_control_data->fcd_configcb; 1332 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1333 1334 /* 1335 * This copy is kind of disgusting, but there are a bunch of must be 1336 * zero and must be one bits in this structure and this is the easiest 1337 * way to initialize them all to proper values. 1338 */ 1339 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1340 1341 /* BIG_ENDIAN: no need to swap to store 0 */ 1342 cbp->cb_status = 0; 1343 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1344 FXP_CB_COMMAND_EL); 1345 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1346 cbp->link_addr = 0xffffffff; /* (no) next command */ 1347 cbp->byte_count = 22; /* (22) bytes to config */ 1348 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1349 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1350 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1351 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1352 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1353 cbp->dma_bce = 0; /* (disable) dma max counters */ 1354 cbp->late_scb = 0; /* (don't) defer SCB update */ 1355 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1356 cbp->ci_int = 1; /* interrupt on CU idle */ 1357 cbp->save_bf = prm; /* save bad frames */ 1358 cbp->disc_short_rx = !prm; /* discard short packets */ 1359 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1360 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1361 cbp->nsai = 1; /* (don't) disable source addr insert */ 1362 cbp->preamble_length = 2; /* (7 byte) preamble */ 1363 cbp->loopback = 0; /* (don't) loopback */ 1364 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1365 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1366 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1367 cbp->promiscuous = prm; /* promiscuous mode */ 1368 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1369 cbp->crscdt = 0; /* (CRS only) */ 1370 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1371 cbp->padding = 1; /* (do) pad short tx packets */ 1372 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1373 cbp->force_fdx = 0; /* (don't) force full duplex */ 1374 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1375 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1376 cbp->mc_all = allm; /* accept all multicasts */ 1377 1378 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1379 1380 /* 1381 * Start the config command/DMA. 1382 */ 1383 fxp_scb_wait(sc); 1384 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1385 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1386 /* ...and wait for it to complete. */ 1387 i = 1000; 1388 do { 1389 FXP_CDCONFIGSYNC(sc, 1390 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1391 DELAY(1); 1392 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1393 if (i == 0) { 1394 printf("%s at line %d: dmasync timeout\n", 1395 sc->sc_dev.dv_xname, __LINE__); 1396 return ETIMEDOUT; 1397 } 1398 1399 /* 1400 * Initialize the station address. 1401 */ 1402 cb_ias = &sc->sc_control_data->fcd_iascb; 1403 /* BIG_ENDIAN: no need to swap to store 0 */ 1404 cb_ias->cb_status = 0; 1405 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1406 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1407 cb_ias->link_addr = 0xffffffff; 1408 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1409 1410 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1411 1412 /* 1413 * Start the IAS (Individual Address Setup) command/DMA. 1414 */ 1415 fxp_scb_wait(sc); 1416 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1417 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1418 /* ...and wait for it to complete. */ 1419 i = 1000; 1420 do { 1421 FXP_CDIASSYNC(sc, 1422 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1423 DELAY(1); 1424 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1425 if (i == 0) { 1426 printf("%s at line %d: dmasync timeout\n", 1427 sc->sc_dev.dv_xname, __LINE__); 1428 return ETIMEDOUT; 1429 } 1430 1431 /* 1432 * Initialize the transmit descriptor ring. txlast is initialized 1433 * to the end of the list so that it will wrap around to the first 1434 * descriptor when the first packet is transmitted. 1435 */ 1436 for (i = 0; i < FXP_NTXCB; i++) { 1437 txd = FXP_CDTX(sc, i); 1438 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1439 txd->cb_command = 1440 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1441 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1442 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1443 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1444 } 1445 sc->sc_txpending = 0; 1446 sc->sc_txdirty = 0; 1447 sc->sc_txlast = FXP_NTXCB - 1; 1448 1449 /* 1450 * Initialize the receive buffer list. 1451 */ 1452 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1453 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1454 rxmap = FXP_RXMAP_GET(sc); 1455 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1456 printf("%s: unable to allocate or map rx " 1457 "buffer %d, error = %d\n", 1458 sc->sc_dev.dv_xname, 1459 sc->sc_rxq.ifq_len, error); 1460 /* 1461 * XXX Should attempt to run with fewer receive 1462 * XXX buffers instead of just failing. 1463 */ 1464 FXP_RXMAP_PUT(sc, rxmap); 1465 fxp_rxdrain(sc); 1466 goto out; 1467 } 1468 } 1469 sc->sc_rxidle = 0; 1470 1471 /* 1472 * Give the transmit ring to the chip. We do this by pointing 1473 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1474 * issuing a start command. It will execute the NOP and then 1475 * suspend, pointing at the first descriptor. 1476 */ 1477 fxp_scb_wait(sc); 1478 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1479 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1480 1481 /* 1482 * Initialize receiver buffer area - RFA. 1483 */ 1484 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1485 fxp_scb_wait(sc); 1486 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1487 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1488 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1489 1490 if (sc->sc_flags & FXPF_MII) { 1491 /* 1492 * Set current media. 1493 */ 1494 mii_mediachg(&sc->sc_mii); 1495 } 1496 1497 /* 1498 * ...all done! 1499 */ 1500 ifp->if_flags |= IFF_RUNNING; 1501 ifp->if_flags &= ~IFF_OACTIVE; 1502 1503 /* 1504 * Start the one second timer. 1505 */ 1506 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1507 1508 /* 1509 * Attempt to start output on the interface. 1510 */ 1511 fxp_start(ifp); 1512 1513 out: 1514 if (error) 1515 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1516 return (error); 1517 } 1518 1519 /* 1520 * Change media according to request. 1521 */ 1522 int 1523 fxp_mii_mediachange(ifp) 1524 struct ifnet *ifp; 1525 { 1526 struct fxp_softc *sc = ifp->if_softc; 1527 1528 if (ifp->if_flags & IFF_UP) 1529 mii_mediachg(&sc->sc_mii); 1530 return (0); 1531 } 1532 1533 /* 1534 * Notify the world which media we're using. 1535 */ 1536 void 1537 fxp_mii_mediastatus(ifp, ifmr) 1538 struct ifnet *ifp; 1539 struct ifmediareq *ifmr; 1540 { 1541 struct fxp_softc *sc = ifp->if_softc; 1542 1543 if(sc->sc_enabled == 0) { 1544 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1545 ifmr->ifm_status = 0; 1546 return; 1547 } 1548 1549 mii_pollstat(&sc->sc_mii); 1550 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1551 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1552 } 1553 1554 int 1555 fxp_80c24_mediachange(ifp) 1556 struct ifnet *ifp; 1557 { 1558 1559 /* Nothing to do here. */ 1560 return (0); 1561 } 1562 1563 void 1564 fxp_80c24_mediastatus(ifp, ifmr) 1565 struct ifnet *ifp; 1566 struct ifmediareq *ifmr; 1567 { 1568 struct fxp_softc *sc = ifp->if_softc; 1569 1570 /* 1571 * Media is currently-selected media. We cannot determine 1572 * the link status. 1573 */ 1574 ifmr->ifm_status = 0; 1575 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1576 } 1577 1578 /* 1579 * Add a buffer to the end of the RFA buffer list. 1580 * Return 0 if successful, error code on failure. 1581 * 1582 * The RFA struct is stuck at the beginning of mbuf cluster and the 1583 * data pointer is fixed up to point just past it. 1584 */ 1585 int 1586 fxp_add_rfabuf(sc, rxmap, unload) 1587 struct fxp_softc *sc; 1588 bus_dmamap_t rxmap; 1589 int unload; 1590 { 1591 struct mbuf *m; 1592 int error; 1593 1594 MGETHDR(m, M_DONTWAIT, MT_DATA); 1595 if (m == NULL) 1596 return (ENOBUFS); 1597 1598 MCLGET(m, M_DONTWAIT); 1599 if ((m->m_flags & M_EXT) == 0) { 1600 m_freem(m); 1601 return (ENOBUFS); 1602 } 1603 1604 if (unload) 1605 bus_dmamap_unload(sc->sc_dmat, rxmap); 1606 1607 M_SETCTX(m, rxmap); 1608 1609 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1610 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1611 if (error) { 1612 printf("%s: can't load rx DMA map %d, error = %d\n", 1613 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1614 panic("fxp_add_rfabuf"); /* XXX */ 1615 } 1616 1617 FXP_INIT_RFABUF(sc, m); 1618 1619 return (0); 1620 } 1621 1622 volatile int 1623 fxp_mdi_read(self, phy, reg) 1624 struct device *self; 1625 int phy; 1626 int reg; 1627 { 1628 struct fxp_softc *sc = (struct fxp_softc *)self; 1629 int count = 10000; 1630 int value; 1631 1632 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1633 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1634 1635 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1636 && count--) 1637 DELAY(10); 1638 1639 if (count <= 0) 1640 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1641 1642 return (value & 0xffff); 1643 } 1644 1645 void 1646 fxp_statchg(self) 1647 struct device *self; 1648 { 1649 1650 /* Nothing to do. */ 1651 } 1652 1653 void 1654 fxp_mdi_write(self, phy, reg, value) 1655 struct device *self; 1656 int phy; 1657 int reg; 1658 int value; 1659 { 1660 struct fxp_softc *sc = (struct fxp_softc *)self; 1661 int count = 10000; 1662 1663 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1664 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1665 (value & 0xffff)); 1666 1667 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1668 count--) 1669 DELAY(10); 1670 1671 if (count <= 0) 1672 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1673 } 1674 1675 int 1676 fxp_ioctl(ifp, command, data) 1677 struct ifnet *ifp; 1678 u_long command; 1679 caddr_t data; 1680 { 1681 struct fxp_softc *sc = ifp->if_softc; 1682 struct ifreq *ifr = (struct ifreq *)data; 1683 struct ifaddr *ifa = (struct ifaddr *)data; 1684 int s, error = 0; 1685 1686 s = splnet(); 1687 1688 switch (command) { 1689 case SIOCSIFADDR: 1690 if ((error = fxp_enable(sc)) != 0) 1691 break; 1692 ifp->if_flags |= IFF_UP; 1693 1694 switch (ifa->ifa_addr->sa_family) { 1695 #ifdef INET 1696 case AF_INET: 1697 if ((error = fxp_init(sc)) != 0) 1698 break; 1699 arp_ifinit(ifp, ifa); 1700 break; 1701 #endif /* INET */ 1702 #ifdef NS 1703 case AF_NS: 1704 { 1705 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1706 1707 if (ns_nullhost(*ina)) 1708 ina->x_host = *(union ns_host *) 1709 LLADDR(ifp->if_sadl); 1710 else 1711 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1712 ifp->if_addrlen); 1713 /* Set new address. */ 1714 error = fxp_init(sc); 1715 break; 1716 } 1717 #endif /* NS */ 1718 default: 1719 error = fxp_init(sc); 1720 break; 1721 } 1722 break; 1723 1724 case SIOCSIFMTU: 1725 if (ifr->ifr_mtu > ETHERMTU) 1726 error = EINVAL; 1727 else 1728 ifp->if_mtu = ifr->ifr_mtu; 1729 break; 1730 1731 case SIOCSIFFLAGS: 1732 if ((ifp->if_flags & IFF_UP) == 0 && 1733 (ifp->if_flags & IFF_RUNNING) != 0) { 1734 /* 1735 * If interface is marked down and it is running, then 1736 * stop it. 1737 */ 1738 fxp_stop(sc, 1); 1739 fxp_disable(sc); 1740 } else if ((ifp->if_flags & IFF_UP) != 0 && 1741 (ifp->if_flags & IFF_RUNNING) == 0) { 1742 /* 1743 * If interface is marked up and it is stopped, then 1744 * start it. 1745 */ 1746 if((error = fxp_enable(sc)) != 0) 1747 break; 1748 error = fxp_init(sc); 1749 } else if ((ifp->if_flags & IFF_UP) != 0) { 1750 /* 1751 * Reset the interface to pick up change in any other 1752 * flags that affect the hardware state. 1753 */ 1754 if((error = fxp_enable(sc)) != 0) 1755 break; 1756 error = fxp_init(sc); 1757 } 1758 break; 1759 1760 case SIOCADDMULTI: 1761 case SIOCDELMULTI: 1762 if(sc->sc_enabled == 0) { 1763 error = EIO; 1764 break; 1765 } 1766 error = (command == SIOCADDMULTI) ? 1767 ether_addmulti(ifr, &sc->sc_ethercom) : 1768 ether_delmulti(ifr, &sc->sc_ethercom); 1769 1770 if (error == ENETRESET) { 1771 /* 1772 * Multicast list has changed; set the hardware 1773 * filter accordingly. 1774 */ 1775 if (sc->sc_txpending) { 1776 sc->sc_flags |= FXPF_WANTINIT; 1777 error = 0; 1778 } else 1779 error = fxp_init(sc); 1780 } 1781 break; 1782 1783 case SIOCSIFMEDIA: 1784 case SIOCGIFMEDIA: 1785 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1786 break; 1787 1788 default: 1789 error = EINVAL; 1790 break; 1791 } 1792 1793 splx(s); 1794 return (error); 1795 } 1796 1797 /* 1798 * Program the multicast filter. 1799 * 1800 * This function must be called at splnet(). 1801 */ 1802 void 1803 fxp_mc_setup(sc) 1804 struct fxp_softc *sc; 1805 { 1806 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1807 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1808 struct ethercom *ec = &sc->sc_ethercom; 1809 struct ether_multi *enm; 1810 struct ether_multistep step; 1811 int count, nmcasts; 1812 1813 #ifdef DIAGNOSTIC 1814 if (sc->sc_txpending) 1815 panic("fxp_mc_setup: pending transmissions"); 1816 #endif 1817 1818 ifp->if_flags &= ~IFF_ALLMULTI; 1819 1820 /* 1821 * Initialize multicast setup descriptor. 1822 */ 1823 nmcasts = 0; 1824 ETHER_FIRST_MULTI(step, ec, enm); 1825 while (enm != NULL) { 1826 /* 1827 * Check for too many multicast addresses or if we're 1828 * listening to a range. Either way, we simply have 1829 * to accept all multicasts. 1830 */ 1831 if (nmcasts >= MAXMCADDR || 1832 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1833 ETHER_ADDR_LEN) != 0) { 1834 /* 1835 * Callers of this function must do the 1836 * right thing with this. If we're called 1837 * from outside fxp_init(), the caller must 1838 * detect if the state if IFF_ALLMULTI changes. 1839 * If it does, the caller must then call 1840 * fxp_init(), since allmulti is handled by 1841 * the config block. 1842 */ 1843 ifp->if_flags |= IFF_ALLMULTI; 1844 return; 1845 } 1846 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1847 ETHER_ADDR_LEN); 1848 nmcasts++; 1849 ETHER_NEXT_MULTI(step, enm); 1850 } 1851 1852 /* BIG_ENDIAN: no need to swap to store 0 */ 1853 mcsp->cb_status = 0; 1854 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1855 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1856 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1857 1858 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1859 1860 /* 1861 * Wait until the command unit is not active. This should never 1862 * happen since nothing is queued, but make sure anyway. 1863 */ 1864 count = 100; 1865 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1866 FXP_SCB_CUS_ACTIVE && --count) 1867 DELAY(1); 1868 if (count == 0) { 1869 printf("%s at line %d: command queue timeout\n", 1870 sc->sc_dev.dv_xname, __LINE__); 1871 return; 1872 } 1873 1874 /* 1875 * Start the multicast setup command/DMA. 1876 */ 1877 fxp_scb_wait(sc); 1878 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1879 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1880 1881 /* ...and wait for it to complete. */ 1882 count = 1000; 1883 do { 1884 FXP_CDMCSSYNC(sc, 1885 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1886 DELAY(1); 1887 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1888 if (count == 0) { 1889 printf("%s at line %d: dmasync timeout\n", 1890 sc->sc_dev.dv_xname, __LINE__); 1891 return; 1892 } 1893 } 1894 1895 int 1896 fxp_enable(sc) 1897 struct fxp_softc *sc; 1898 { 1899 1900 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1901 if ((*sc->sc_enable)(sc) != 0) { 1902 printf("%s: device enable failed\n", 1903 sc->sc_dev.dv_xname); 1904 return (EIO); 1905 } 1906 } 1907 1908 sc->sc_enabled = 1; 1909 return (0); 1910 } 1911 1912 void 1913 fxp_disable(sc) 1914 struct fxp_softc *sc; 1915 { 1916 1917 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1918 (*sc->sc_disable)(sc); 1919 sc->sc_enabled = 0; 1920 } 1921 } 1922 1923 /* 1924 * fxp_activate: 1925 * 1926 * Handle device activation/deactivation requests. 1927 */ 1928 int 1929 fxp_activate(self, act) 1930 struct device *self; 1931 enum devact act; 1932 { 1933 struct fxp_softc *sc = (void *) self; 1934 int s, error = 0; 1935 1936 s = splnet(); 1937 switch (act) { 1938 case DVACT_ACTIVATE: 1939 error = EOPNOTSUPP; 1940 break; 1941 1942 case DVACT_DEACTIVATE: 1943 if (sc->sc_flags & FXPF_MII) 1944 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1945 MII_OFFSET_ANY); 1946 if_deactivate(&sc->sc_ethercom.ec_if); 1947 break; 1948 } 1949 splx(s); 1950 1951 return (error); 1952 } 1953 1954 /* 1955 * fxp_detach: 1956 * 1957 * Detach an i82557 interface. 1958 */ 1959 int 1960 fxp_detach(sc) 1961 struct fxp_softc *sc; 1962 { 1963 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1964 int i; 1965 1966 /* Succeed now if there's no work to do. */ 1967 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1968 return (0); 1969 1970 /* Unhook our tick handler. */ 1971 callout_stop(&sc->sc_callout); 1972 1973 if (sc->sc_flags & FXPF_MII) { 1974 /* Detach all PHYs */ 1975 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1976 } 1977 1978 /* Delete all remaining media. */ 1979 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1980 1981 #if NRND > 0 1982 rnd_detach_source(&sc->rnd_source); 1983 #endif 1984 #if NBPFILTER > 0 1985 bpfdetach(ifp); 1986 #endif 1987 ether_ifdetach(ifp); 1988 if_detach(ifp); 1989 1990 for (i = 0; i < FXP_NRFABUFS; i++) { 1991 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1992 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1993 } 1994 1995 for (i = 0; i < FXP_NTXCB; i++) { 1996 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1997 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1998 } 1999 2000 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2001 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2002 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2003 sizeof(struct fxp_control_data)); 2004 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2005 2006 shutdownhook_disestablish(sc->sc_sdhook); 2007 powerhook_disestablish(sc->sc_powerhook); 2008 2009 return (0); 2010 } 2011
Indexes created Mon Sep 29 21:09:56 GMT 2025