i82557.c revision 1.39
1 /* $NetBSD: i82557.c,v 1.39 2000/10/03 23:35:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <uvm/uvm_extern.h> 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia __P((struct fxp_softc *)); 169 int fxp_mii_mediachange __P((struct ifnet *)); 170 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 void fxp_80c24_initmedia __P((struct fxp_softc *)); 173 int fxp_80c24_mediachange __P((struct ifnet *)); 174 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176 inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178 void fxp_start __P((struct ifnet *)); 179 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180 int fxp_init __P((struct fxp_softc *)); 181 void fxp_rxdrain __P((struct fxp_softc *)); 182 void fxp_stop __P((struct fxp_softc *, int)); 183 void fxp_watchdog __P((struct ifnet *)); 184 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 185 int fxp_mdi_read __P((struct device *, int, int)); 186 void fxp_statchg __P((struct device *)); 187 void fxp_mdi_write __P((struct device *, int, int, int)); 188 void fxp_autosize_eeprom __P((struct fxp_softc*)); 189 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 190 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 191 void fxp_tick __P((void *)); 192 void fxp_mc_setup __P((struct fxp_softc *)); 193 194 void fxp_shutdown __P((void *)); 195 void fxp_power __P((int, void *)); 196 197 int fxp_copy_small = 0; 198 199 struct fxp_phytype { 200 int fp_phy; /* type of PHY, -1 for MII at the end. */ 201 void (*fp_init) __P((struct fxp_softc *)); 202 } fxp_phytype_table[] = { 203 { FXP_PHY_80C24, fxp_80c24_initmedia }, 204 { -1, fxp_mii_initmedia }, 205 }; 206 207 /* 208 * Set initial transmit threshold at 64 (512 bytes). This is 209 * increased by 64 (512 bytes) at a time, to maximum of 192 210 * (1536 bytes), if an underrun occurs. 211 */ 212 static int tx_threshold = 64; 213 214 /* 215 * Wait for the previous command to be accepted (but not necessarily 216 * completed). 217 */ 218 inline void 219 fxp_scb_wait(sc) 220 struct fxp_softc *sc; 221 { 222 int i = 10000; 223 224 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 225 delay(2); 226 if (i == 0) 227 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 228 } 229 230 /* 231 * Finish attaching an i82557 interface. Called by bus-specific front-end. 232 */ 233 void 234 fxp_attach(sc) 235 struct fxp_softc *sc; 236 { 237 u_int8_t enaddr[ETHER_ADDR_LEN]; 238 struct ifnet *ifp; 239 bus_dma_segment_t seg; 240 int rseg, i, error; 241 struct fxp_phytype *fp; 242 243 callout_init(&sc->sc_callout); 244 245 /* 246 * Allocate the control data structures, and create and load the 247 * DMA map for it. 248 */ 249 if ((error = bus_dmamem_alloc(sc->sc_dmat, 250 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 251 0)) != 0) { 252 printf("%s: unable to allocate control data, error = %d\n", 253 sc->sc_dev.dv_xname, error); 254 goto fail_0; 255 } 256 257 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 258 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 259 BUS_DMA_COHERENT)) != 0) { 260 printf("%s: unable to map control data, error = %d\n", 261 sc->sc_dev.dv_xname, error); 262 goto fail_1; 263 } 264 sc->sc_cdseg = seg; 265 sc->sc_cdnseg = rseg; 266 267 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 268 269 if ((error = bus_dmamap_create(sc->sc_dmat, 270 sizeof(struct fxp_control_data), 1, 271 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 272 printf("%s: unable to create control data DMA map, " 273 "error = %d\n", sc->sc_dev.dv_xname, error); 274 goto fail_2; 275 } 276 277 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 278 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 279 0)) != 0) { 280 printf("%s: can't load control data DMA map, error = %d\n", 281 sc->sc_dev.dv_xname, error); 282 goto fail_3; 283 } 284 285 /* 286 * Create the transmit buffer DMA maps. 287 */ 288 for (i = 0; i < FXP_NTXCB; i++) { 289 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 290 FXP_NTXSEG, MCLBYTES, 0, 0, 291 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 292 printf("%s: unable to create tx DMA map %d, " 293 "error = %d\n", sc->sc_dev.dv_xname, i, error); 294 goto fail_4; 295 } 296 } 297 298 /* 299 * Create the receive buffer DMA maps. 300 */ 301 for (i = 0; i < FXP_NRFABUFS; i++) { 302 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 303 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 304 printf("%s: unable to create rx DMA map %d, " 305 "error = %d\n", sc->sc_dev.dv_xname, i, error); 306 goto fail_5; 307 } 308 } 309 310 /* Initialize MAC address and media structures. */ 311 fxp_get_info(sc, enaddr); 312 313 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 314 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 315 316 ifp = &sc->sc_ethercom.ec_if; 317 318 /* 319 * Get info about our media interface, and initialize it. Note 320 * the table terminates itself with a phy of -1, indicating 321 * that we're using MII. 322 */ 323 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 324 if (fp->fp_phy == sc->phy_primary_device) 325 break; 326 (*fp->fp_init)(sc); 327 328 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 329 ifp->if_softc = sc; 330 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 331 ifp->if_ioctl = fxp_ioctl; 332 ifp->if_start = fxp_start; 333 ifp->if_watchdog = fxp_watchdog; 334 335 /* 336 * We can support 802.1Q VLAN-sized frames. 337 */ 338 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 339 340 /* 341 * Attach the interface. 342 */ 343 if_attach(ifp); 344 ether_ifattach(ifp, enaddr); 345 #if NBPFILTER > 0 346 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 347 sizeof(struct ether_header)); 348 #endif 349 #if NRND > 0 350 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 351 RND_TYPE_NET, 0); 352 #endif 353 354 /* 355 * Add shutdown hook so that DMA is disabled prior to reboot. Not 356 * doing do could allow DMA to corrupt kernel memory during the 357 * reboot before the driver initializes. 358 */ 359 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 360 if (sc->sc_sdhook == NULL) 361 printf("%s: WARNING: unable to establish shutdown hook\n", 362 sc->sc_dev.dv_xname); 363 /* 364 * Add suspend hook, for similar reasons.. 365 */ 366 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 367 if (sc->sc_powerhook == NULL) 368 printf("%s: WARNING: unable to establish power hook\n", 369 sc->sc_dev.dv_xname); 370 371 /* The attach is successful. */ 372 sc->sc_flags |= FXPF_ATTACHED; 373 374 return; 375 376 /* 377 * Free any resources we've allocated during the failed attach 378 * attempt. Do this in reverse order and fall though. 379 */ 380 fail_5: 381 for (i = 0; i < FXP_NRFABUFS; i++) { 382 if (sc->sc_rxmaps[i] != NULL) 383 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 384 } 385 fail_4: 386 for (i = 0; i < FXP_NTXCB; i++) { 387 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 388 bus_dmamap_destroy(sc->sc_dmat, 389 FXP_DSTX(sc, i)->txs_dmamap); 390 } 391 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 392 fail_3: 393 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 394 fail_2: 395 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 396 sizeof(struct fxp_control_data)); 397 fail_1: 398 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 399 fail_0: 400 return; 401 } 402 403 void 404 fxp_mii_initmedia(sc) 405 struct fxp_softc *sc; 406 { 407 408 sc->sc_flags |= FXPF_MII; 409 410 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 411 sc->sc_mii.mii_readreg = fxp_mdi_read; 412 sc->sc_mii.mii_writereg = fxp_mdi_write; 413 sc->sc_mii.mii_statchg = fxp_statchg; 414 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 415 fxp_mii_mediastatus); 416 /* 417 * The i82557 wedges if all of its PHYs are isolated! 418 */ 419 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 420 MII_OFFSET_ANY, MIIF_NOISOLATE); 421 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 422 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 423 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 424 } else 425 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 426 } 427 428 void 429 fxp_80c24_initmedia(sc) 430 struct fxp_softc *sc; 431 { 432 433 /* 434 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 435 * doesn't have a programming interface of any sort. The 436 * media is sensed automatically based on how the link partner 437 * is configured. This is, in essence, manual configuration. 438 */ 439 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 440 sc->sc_dev.dv_xname); 441 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 442 fxp_80c24_mediastatus); 443 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 444 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 445 } 446 447 /* 448 * Device shutdown routine. Called at system shutdown after sync. The 449 * main purpose of this routine is to shut off receiver DMA so that 450 * kernel memory doesn't get clobbered during warmboot. 451 */ 452 void 453 fxp_shutdown(arg) 454 void *arg; 455 { 456 struct fxp_softc *sc = arg; 457 458 /* 459 * Since the system's going to halt shortly, don't bother 460 * freeing mbufs. 461 */ 462 fxp_stop(sc, 0); 463 } 464 /* 465 * Power handler routine. Called when the system is transitioning 466 * into/out of power save modes. As with fxp_shutdown, the main 467 * purpose of this routine is to shut off receiver DMA so it doesn't 468 * clobber kernel memory at the wrong time. 469 */ 470 void 471 fxp_power(why, arg) 472 int why; 473 void *arg; 474 { 475 struct fxp_softc *sc = arg; 476 struct ifnet *ifp; 477 int s; 478 479 s = splnet(); 480 if (why != PWR_RESUME) 481 fxp_stop(sc, 0); 482 else { 483 ifp = &sc->sc_ethercom.ec_if; 484 if (ifp->if_flags & IFF_UP) 485 fxp_init(sc); 486 } 487 splx(s); 488 } 489 490 /* 491 * Initialize the interface media. 492 */ 493 void 494 fxp_get_info(sc, enaddr) 495 struct fxp_softc *sc; 496 u_int8_t *enaddr; 497 { 498 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 499 500 /* 501 * Reset to a stable state. 502 */ 503 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 504 DELAY(10); 505 506 sc->sc_eeprom_size = 0; 507 fxp_autosize_eeprom(sc); 508 if(sc->sc_eeprom_size == 0) { 509 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 510 sc->sc_eeprom_size = 6; /* XXX panic here? */ 511 } 512 #ifdef DEBUG 513 printf("%s: detected %d word EEPROM\n", 514 sc->sc_dev.dv_xname, 515 1 << sc->sc_eeprom_size); 516 #endif 517 518 /* 519 * Get info about the primary PHY 520 */ 521 fxp_read_eeprom(sc, &data, 6, 1); 522 sc->phy_primary_addr = data & 0xff; 523 sc->phy_primary_device = (data >> 8) & 0x3f; 524 sc->phy_10Mbps_only = data >> 15; 525 526 /* 527 * Read MAC address. 528 */ 529 fxp_read_eeprom(sc, myea, 0, 3); 530 enaddr[0] = myea[0] & 0xff; 531 enaddr[1] = myea[0] >> 8; 532 enaddr[2] = myea[1] & 0xff; 533 enaddr[3] = myea[1] >> 8; 534 enaddr[4] = myea[2] & 0xff; 535 enaddr[5] = myea[2] >> 8; 536 } 537 538 /* 539 * Figure out EEPROM size. 540 * 541 * 559's can have either 64-word or 256-word EEPROMs, the 558 542 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 543 * talks about the existance of 16 to 256 word EEPROMs. 544 * 545 * The only known sizes are 64 and 256, where the 256 version is used 546 * by CardBus cards to store CIS information. 547 * 548 * The address is shifted in msb-to-lsb, and after the last 549 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 550 * after which follows the actual data. We try to detect this zero, by 551 * probing the data-out bit in the EEPROM control register just after 552 * having shifted in a bit. If the bit is zero, we assume we've 553 * shifted enough address bits. The data-out should be tri-state, 554 * before this, which should translate to a logical one. 555 * 556 * Other ways to do this would be to try to read a register with known 557 * contents with a varying number of address bits, but no such 558 * register seem to be available. The high bits of register 10 are 01 559 * on the 558 and 559, but apparently not on the 557. 560 * 561 * The Linux driver computes a checksum on the EEPROM data, but the 562 * value of this checksum is not very well documented. 563 */ 564 565 void 566 fxp_autosize_eeprom(sc) 567 struct fxp_softc *sc; 568 { 569 u_int16_t reg; 570 int x; 571 572 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 573 /* 574 * Shift in read opcode. 575 */ 576 for (x = 3; x > 0; x--) { 577 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 578 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 579 } else { 580 reg = FXP_EEPROM_EECS; 581 } 582 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 583 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 584 reg | FXP_EEPROM_EESK); 585 DELAY(4); 586 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 587 DELAY(4); 588 } 589 /* 590 * Shift in address, wait for the dummy zero following a correct 591 * address shift. 592 */ 593 for (x = 1; x <= 8; x++) { 594 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 595 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 596 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 597 DELAY(4); 598 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 599 FXP_EEPROM_EEDO) == 0) 600 break; 601 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 602 DELAY(4); 603 } 604 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 605 DELAY(4); 606 if(x != 6 && x != 8) { 607 #ifdef DEBUG 608 printf("%s: strange EEPROM size (%d)\n", 609 sc->sc_dev.dv_xname, 1 << x); 610 #endif 611 } else 612 sc->sc_eeprom_size = x; 613 } 614 615 /* 616 * Read from the serial EEPROM. Basically, you manually shift in 617 * the read opcode (one bit at a time) and then shift in the address, 618 * and then you shift out the data (all of this one bit at a time). 619 * The word size is 16 bits, so you have to provide the address for 620 * every 16 bits of data. 621 */ 622 void 623 fxp_read_eeprom(sc, data, offset, words) 624 struct fxp_softc *sc; 625 u_int16_t *data; 626 int offset; 627 int words; 628 { 629 u_int16_t reg; 630 int i, x; 631 632 for (i = 0; i < words; i++) { 633 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 634 /* 635 * Shift in read opcode. 636 */ 637 for (x = 3; x > 0; x--) { 638 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 639 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 640 } else { 641 reg = FXP_EEPROM_EECS; 642 } 643 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 644 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 645 reg | FXP_EEPROM_EESK); 646 DELAY(4); 647 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 648 DELAY(4); 649 } 650 /* 651 * Shift in address. 652 */ 653 for (x = sc->sc_eeprom_size; x > 0; x--) { 654 if ((i + offset) & (1 << (x - 1))) { 655 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 656 } else { 657 reg = FXP_EEPROM_EECS; 658 } 659 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 660 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 661 reg | FXP_EEPROM_EESK); 662 DELAY(4); 663 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 664 DELAY(4); 665 } 666 reg = FXP_EEPROM_EECS; 667 data[i] = 0; 668 /* 669 * Shift out data. 670 */ 671 for (x = 16; x > 0; x--) { 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 673 reg | FXP_EEPROM_EESK); 674 DELAY(4); 675 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 676 FXP_EEPROM_EEDO) 677 data[i] |= (1 << (x - 1)); 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 679 DELAY(4); 680 } 681 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 682 DELAY(4); 683 } 684 } 685 686 /* 687 * Start packet transmission on the interface. 688 */ 689 void 690 fxp_start(ifp) 691 struct ifnet *ifp; 692 { 693 struct fxp_softc *sc = ifp->if_softc; 694 struct mbuf *m0, *m; 695 struct fxp_cb_tx *txd; 696 struct fxp_txsoft *txs; 697 struct fxp_tbdlist *tbd; 698 bus_dmamap_t dmamap; 699 int error, lasttx, nexttx, opending, seg; 700 701 /* 702 * If we want a re-init, bail out now. 703 */ 704 if (sc->sc_flags & FXPF_WANTINIT) { 705 ifp->if_flags |= IFF_OACTIVE; 706 return; 707 } 708 709 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 710 return; 711 712 /* 713 * Remember the previous txpending and the current lasttx. 714 */ 715 opending = sc->sc_txpending; 716 lasttx = sc->sc_txlast; 717 718 /* 719 * Loop through the send queue, setting up transmit descriptors 720 * until we drain the queue, or use up all available transmit 721 * descriptors. 722 */ 723 while (sc->sc_txpending < FXP_NTXCB) { 724 /* 725 * Grab a packet off the queue. 726 */ 727 IF_DEQUEUE(&ifp->if_snd, m0); 728 if (m0 == NULL) 729 break; 730 731 /* 732 * Get the next available transmit descriptor. 733 */ 734 nexttx = FXP_NEXTTX(sc->sc_txlast); 735 txd = FXP_CDTX(sc, nexttx); 736 tbd = FXP_CDTBD(sc, nexttx); 737 txs = FXP_DSTX(sc, nexttx); 738 dmamap = txs->txs_dmamap; 739 740 /* 741 * Load the DMA map. If this fails, the packet either 742 * didn't fit in the allotted number of frags, or we were 743 * short on resources. In this case, we'll copy and try 744 * again. 745 */ 746 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 747 BUS_DMA_NOWAIT) != 0) { 748 MGETHDR(m, M_DONTWAIT, MT_DATA); 749 if (m == NULL) { 750 printf("%s: unable to allocate Tx mbuf\n", 751 sc->sc_dev.dv_xname); 752 IF_PREPEND(&ifp->if_snd, m0); 753 break; 754 } 755 if (m0->m_pkthdr.len > MHLEN) { 756 MCLGET(m, M_DONTWAIT); 757 if ((m->m_flags & M_EXT) == 0) { 758 printf("%s: unable to allocate Tx " 759 "cluster\n", sc->sc_dev.dv_xname); 760 m_freem(m); 761 IF_PREPEND(&ifp->if_snd, m0); 762 break; 763 } 764 } 765 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 766 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 767 m_freem(m0); 768 m0 = m; 769 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 770 m0, BUS_DMA_NOWAIT); 771 if (error) { 772 printf("%s: unable to load Tx buffer, " 773 "error = %d\n", sc->sc_dev.dv_xname, error); 774 IF_PREPEND(&ifp->if_snd, m0); 775 break; 776 } 777 } 778 779 /* Initialize the fraglist. */ 780 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 781 tbd->tbd_d[seg].tb_addr = 782 htole32(dmamap->dm_segs[seg].ds_addr); 783 tbd->tbd_d[seg].tb_size = 784 htole32(dmamap->dm_segs[seg].ds_len); 785 } 786 787 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 788 789 /* Sync the DMA map. */ 790 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 791 BUS_DMASYNC_PREWRITE); 792 793 /* 794 * Store a pointer to the packet so we can free it later. 795 */ 796 txs->txs_mbuf = m0; 797 798 /* 799 * Initialize the transmit descriptor. 800 */ 801 /* BIG_ENDIAN: no need to swap to store 0 */ 802 txd->cb_status = 0; 803 txd->cb_command = 804 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 805 txd->tx_threshold = tx_threshold; 806 txd->tbd_number = dmamap->dm_nsegs; 807 808 FXP_CDTXSYNC(sc, nexttx, 809 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 810 811 /* Advance the tx pointer. */ 812 sc->sc_txpending++; 813 sc->sc_txlast = nexttx; 814 815 #if NBPFILTER > 0 816 /* 817 * Pass packet to bpf if there is a listener. 818 */ 819 if (ifp->if_bpf) 820 bpf_mtap(ifp->if_bpf, m0); 821 #endif 822 } 823 824 if (sc->sc_txpending == FXP_NTXCB) { 825 /* No more slots; notify upper layer. */ 826 ifp->if_flags |= IFF_OACTIVE; 827 } 828 829 if (sc->sc_txpending != opending) { 830 /* 831 * We enqueued packets. If the transmitter was idle, 832 * reset the txdirty pointer. 833 */ 834 if (opending == 0) 835 sc->sc_txdirty = FXP_NEXTTX(lasttx); 836 837 /* 838 * Cause the chip to interrupt and suspend command 839 * processing once the last packet we've enqueued 840 * has been transmitted. 841 */ 842 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 843 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 844 FXP_CDTXSYNC(sc, sc->sc_txlast, 845 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 846 847 /* 848 * The entire packet chain is set up. Clear the suspend bit 849 * on the command prior to the first packet we set up. 850 */ 851 FXP_CDTXSYNC(sc, lasttx, 852 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 853 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 854 FXP_CDTXSYNC(sc, lasttx, 855 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856 857 /* 858 * Issue a Resume command in case the chip was suspended. 859 */ 860 fxp_scb_wait(sc); 861 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 862 863 /* Set a watchdog timer in case the chip flakes out. */ 864 ifp->if_timer = 5; 865 } 866 } 867 868 /* 869 * Process interface interrupts. 870 */ 871 int 872 fxp_intr(arg) 873 void *arg; 874 { 875 struct fxp_softc *sc = arg; 876 struct ethercom *ec = &sc->sc_ethercom; 877 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 878 struct fxp_cb_tx *txd; 879 struct fxp_txsoft *txs; 880 struct mbuf *m, *m0; 881 bus_dmamap_t rxmap; 882 struct fxp_rfa *rfa; 883 int i, claimed = 0; 884 u_int16_t len, rxstat, txstat; 885 u_int8_t statack; 886 887 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 888 return (0); 889 /* 890 * If the interface isn't running, don't try to 891 * service the interrupt.. just ack it and bail. 892 */ 893 if ((ifp->if_flags & IFF_RUNNING) == 0) { 894 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 895 if (statack) { 896 claimed = 1; 897 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 898 } 899 return (claimed); 900 } 901 902 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 903 claimed = 1; 904 905 /* 906 * First ACK all the interrupts in this pass. 907 */ 908 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 909 910 /* 911 * Process receiver interrupts. If a no-resource (RNR) 912 * condition exists, get whatever packets we can and 913 * re-start the receiver. 914 */ 915 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 916 rcvloop: 917 m = sc->sc_rxq.ifq_head; 918 rfa = FXP_MTORFA(m); 919 rxmap = M_GETCTX(m, bus_dmamap_t); 920 921 FXP_RFASYNC(sc, m, 922 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 923 924 rxstat = le16toh(rfa->rfa_status); 925 926 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 927 /* 928 * We have processed all of the 929 * receive buffers. 930 */ 931 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 932 goto do_transmit; 933 } 934 935 IF_DEQUEUE(&sc->sc_rxq, m); 936 937 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 938 939 len = le16toh(rfa->actual_size) & 940 (m->m_ext.ext_size - 1); 941 942 if (len < sizeof(struct ether_header)) { 943 /* 944 * Runt packet; drop it now. 945 */ 946 FXP_INIT_RFABUF(sc, m); 947 goto rcvloop; 948 } 949 950 /* 951 * If support for 802.1Q VLAN sized frames is 952 * enabled, we need to do some additional error 953 * checking (as we are saving bad frames, in 954 * order to receive the larger ones). 955 */ 956 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 957 (rxstat & (FXP_RFA_STATUS_OVERRUN| 958 FXP_RFA_STATUS_RNR| 959 FXP_RFA_STATUS_ALIGN| 960 FXP_RFA_STATUS_CRC)) != 0) { 961 FXP_INIT_RFABUF(sc, m); 962 goto rcvloop; 963 } 964 965 /* 966 * If the packet is small enough to fit in a 967 * single header mbuf, allocate one and copy 968 * the data into it. This greatly reduces 969 * memory consumption when we receive lots 970 * of small packets. 971 * 972 * Otherwise, we add a new buffer to the receive 973 * chain. If this fails, we drop the packet and 974 * recycle the old buffer. 975 */ 976 if (fxp_copy_small != 0 && len <= MHLEN) { 977 MGETHDR(m0, M_DONTWAIT, MT_DATA); 978 if (m == NULL) 979 goto dropit; 980 memcpy(mtod(m0, caddr_t), 981 mtod(m, caddr_t), len); 982 FXP_INIT_RFABUF(sc, m); 983 m = m0; 984 } else { 985 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 986 dropit: 987 ifp->if_ierrors++; 988 FXP_INIT_RFABUF(sc, m); 989 goto rcvloop; 990 } 991 } 992 993 m->m_pkthdr.rcvif = ifp; 994 m->m_pkthdr.len = m->m_len = len; 995 996 #if NBPFILTER > 0 997 /* 998 * Pass this up to any BPF listeners, but only 999 * pass it up the stack it its for us. 1000 */ 1001 if (ifp->if_bpf) 1002 bpf_mtap(ifp->if_bpf, m); 1003 #endif 1004 1005 /* Pass it on. */ 1006 (*ifp->if_input)(ifp, m); 1007 goto rcvloop; 1008 } 1009 1010 do_transmit: 1011 if (statack & FXP_SCB_STATACK_RNR) { 1012 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1013 fxp_scb_wait(sc); 1014 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1015 rxmap->dm_segs[0].ds_addr + 1016 RFA_ALIGNMENT_FUDGE); 1017 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1018 FXP_SCB_COMMAND_RU_START); 1019 } 1020 1021 /* 1022 * Free any finished transmit mbuf chains. 1023 */ 1024 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1025 ifp->if_flags &= ~IFF_OACTIVE; 1026 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1027 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1028 txd = FXP_CDTX(sc, i); 1029 txs = FXP_DSTX(sc, i); 1030 1031 FXP_CDTXSYNC(sc, i, 1032 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1033 1034 txstat = le16toh(txd->cb_status); 1035 1036 if ((txstat & FXP_CB_STATUS_C) == 0) 1037 break; 1038 1039 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1040 1041 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1042 0, txs->txs_dmamap->dm_mapsize, 1043 BUS_DMASYNC_POSTWRITE); 1044 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1045 m_freem(txs->txs_mbuf); 1046 txs->txs_mbuf = NULL; 1047 } 1048 1049 /* Update the dirty transmit buffer pointer. */ 1050 sc->sc_txdirty = i; 1051 1052 /* 1053 * Cancel the watchdog timer if there are no pending 1054 * transmissions. 1055 */ 1056 if (sc->sc_txpending == 0) { 1057 ifp->if_timer = 0; 1058 1059 /* 1060 * If we want a re-init, do that now. 1061 */ 1062 if (sc->sc_flags & FXPF_WANTINIT) 1063 (void) fxp_init(sc); 1064 } 1065 1066 /* 1067 * Try to get more packets going. 1068 */ 1069 fxp_start(ifp); 1070 } 1071 } 1072 1073 #if NRND > 0 1074 if (claimed) 1075 rnd_add_uint32(&sc->rnd_source, statack); 1076 #endif 1077 return (claimed); 1078 } 1079 1080 /* 1081 * Update packet in/out/collision statistics. The i82557 doesn't 1082 * allow you to access these counters without doing a fairly 1083 * expensive DMA to get _all_ of the statistics it maintains, so 1084 * we do this operation here only once per second. The statistics 1085 * counters in the kernel are updated from the previous dump-stats 1086 * DMA and then a new dump-stats DMA is started. The on-chip 1087 * counters are zeroed when the DMA completes. If we can't start 1088 * the DMA immediately, we don't wait - we just prepare to read 1089 * them again next time. 1090 */ 1091 void 1092 fxp_tick(arg) 1093 void *arg; 1094 { 1095 struct fxp_softc *sc = arg; 1096 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1097 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1098 int s; 1099 1100 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1101 return; 1102 1103 s = splnet(); 1104 1105 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1106 1107 ifp->if_opackets += le32toh(sp->tx_good); 1108 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1109 if (sp->rx_good) { 1110 ifp->if_ipackets += le32toh(sp->rx_good); 1111 sc->sc_rxidle = 0; 1112 } else { 1113 sc->sc_rxidle++; 1114 } 1115 ifp->if_ierrors += 1116 le32toh(sp->rx_crc_errors) + 1117 le32toh(sp->rx_alignment_errors) + 1118 le32toh(sp->rx_rnr_errors) + 1119 le32toh(sp->rx_overrun_errors); 1120 /* 1121 * If any transmit underruns occured, bump up the transmit 1122 * threshold by another 512 bytes (64 * 8). 1123 */ 1124 if (sp->tx_underruns) { 1125 ifp->if_oerrors += le32toh(sp->tx_underruns); 1126 if (tx_threshold < 192) 1127 tx_threshold += 64; 1128 } 1129 1130 /* 1131 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1132 * then assume the receiver has locked up and attempt to clear 1133 * the condition by reprogramming the multicast filter (actually, 1134 * resetting the interface). This is a work-around for a bug in 1135 * the 82557 where the receiver locks up if it gets certain types 1136 * of garbage in the syncronization bits prior to the packet header. 1137 * This bug is supposed to only occur in 10Mbps mode, but has been 1138 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1139 * speed transition). 1140 */ 1141 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1142 (void) fxp_init(sc); 1143 splx(s); 1144 return; 1145 } 1146 /* 1147 * If there is no pending command, start another stats 1148 * dump. Otherwise punt for now. 1149 */ 1150 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1151 /* 1152 * Start another stats dump. 1153 */ 1154 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1155 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1156 FXP_SCB_COMMAND_CU_DUMPRESET); 1157 } else { 1158 /* 1159 * A previous command is still waiting to be accepted. 1160 * Just zero our copy of the stats and wait for the 1161 * next timer event to update them. 1162 */ 1163 /* BIG_ENDIAN: no swap required to store 0 */ 1164 sp->tx_good = 0; 1165 sp->tx_underruns = 0; 1166 sp->tx_total_collisions = 0; 1167 1168 sp->rx_good = 0; 1169 sp->rx_crc_errors = 0; 1170 sp->rx_alignment_errors = 0; 1171 sp->rx_rnr_errors = 0; 1172 sp->rx_overrun_errors = 0; 1173 } 1174 1175 if (sc->sc_flags & FXPF_MII) { 1176 /* Tick the MII clock. */ 1177 mii_tick(&sc->sc_mii); 1178 } 1179 1180 splx(s); 1181 1182 /* 1183 * Schedule another timeout one second from now. 1184 */ 1185 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1186 } 1187 1188 /* 1189 * Drain the receive queue. 1190 */ 1191 void 1192 fxp_rxdrain(sc) 1193 struct fxp_softc *sc; 1194 { 1195 bus_dmamap_t rxmap; 1196 struct mbuf *m; 1197 1198 for (;;) { 1199 IF_DEQUEUE(&sc->sc_rxq, m); 1200 if (m == NULL) 1201 break; 1202 rxmap = M_GETCTX(m, bus_dmamap_t); 1203 bus_dmamap_unload(sc->sc_dmat, rxmap); 1204 FXP_RXMAP_PUT(sc, rxmap); 1205 m_freem(m); 1206 } 1207 } 1208 1209 /* 1210 * Stop the interface. Cancels the statistics updater and resets 1211 * the interface. 1212 */ 1213 void 1214 fxp_stop(sc, drain) 1215 struct fxp_softc *sc; 1216 int drain; 1217 { 1218 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1219 struct fxp_txsoft *txs; 1220 int i; 1221 1222 /* 1223 * Turn down interface (done early to avoid bad interactions 1224 * between panics, shutdown hooks, and the watchdog timer) 1225 */ 1226 ifp->if_timer = 0; 1227 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1228 1229 /* 1230 * Cancel stats updater. 1231 */ 1232 callout_stop(&sc->sc_callout); 1233 if (sc->sc_flags & FXPF_MII) { 1234 /* Down the MII. */ 1235 mii_down(&sc->sc_mii); 1236 } 1237 1238 /* 1239 * Issue software reset 1240 */ 1241 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1242 DELAY(10); 1243 1244 /* 1245 * Release any xmit buffers. 1246 */ 1247 for (i = 0; i < FXP_NTXCB; i++) { 1248 txs = FXP_DSTX(sc, i); 1249 if (txs->txs_mbuf != NULL) { 1250 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1251 m_freem(txs->txs_mbuf); 1252 txs->txs_mbuf = NULL; 1253 } 1254 } 1255 sc->sc_txpending = 0; 1256 1257 if (drain) { 1258 /* 1259 * Release the receive buffers. 1260 */ 1261 fxp_rxdrain(sc); 1262 } 1263 1264 } 1265 1266 /* 1267 * Watchdog/transmission transmit timeout handler. Called when a 1268 * transmission is started on the interface, but no interrupt is 1269 * received before the timeout. This usually indicates that the 1270 * card has wedged for some reason. 1271 */ 1272 void 1273 fxp_watchdog(ifp) 1274 struct ifnet *ifp; 1275 { 1276 struct fxp_softc *sc = ifp->if_softc; 1277 1278 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1279 ifp->if_oerrors++; 1280 1281 (void) fxp_init(sc); 1282 } 1283 1284 /* 1285 * Initialize the interface. Must be called at splnet(). 1286 */ 1287 int 1288 fxp_init(sc) 1289 struct fxp_softc *sc; 1290 { 1291 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1292 struct fxp_cb_config *cbp; 1293 struct fxp_cb_ias *cb_ias; 1294 struct fxp_cb_tx *txd; 1295 bus_dmamap_t rxmap; 1296 int i, prm, save_bf, allm, error = 0; 1297 1298 /* 1299 * Cancel any pending I/O 1300 */ 1301 fxp_stop(sc, 0); 1302 1303 /* 1304 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1305 * flag, and this prevents the MII from detaching resulting in 1306 * a panic. The flags field should perhaps be split in runtime 1307 * flags and more static information. For now, just clear the 1308 * only other flag set. 1309 */ 1310 1311 sc->sc_flags &= ~FXPF_WANTINIT; 1312 1313 /* 1314 * Initialize base of CBL and RFA memory. Loading with zero 1315 * sets it up for regular linear addressing. 1316 */ 1317 fxp_scb_wait(sc); 1318 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1319 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1320 1321 fxp_scb_wait(sc); 1322 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1323 1324 /* 1325 * Initialize the multicast filter. Do this now, since we might 1326 * have to setup the config block differently. 1327 */ 1328 fxp_mc_setup(sc); 1329 1330 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1331 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1332 1333 /* 1334 * In order to support receiving 802.1Q VLAN frames, we have to 1335 * enable "save bad frames", since they are 4 bytes larger than 1336 * the normal Ethernet maximum frame length. 1337 */ 1338 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1339 1340 /* 1341 * Initialize base of dump-stats buffer. 1342 */ 1343 fxp_scb_wait(sc); 1344 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1345 sc->sc_cddma + FXP_CDSTATSOFF); 1346 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1347 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1348 1349 cbp = &sc->sc_control_data->fcd_configcb; 1350 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1351 1352 /* 1353 * This copy is kind of disgusting, but there are a bunch of must be 1354 * zero and must be one bits in this structure and this is the easiest 1355 * way to initialize them all to proper values. 1356 */ 1357 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1358 1359 /* BIG_ENDIAN: no need to swap to store 0 */ 1360 cbp->cb_status = 0; 1361 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1362 FXP_CB_COMMAND_EL); 1363 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1364 cbp->link_addr = 0xffffffff; /* (no) next command */ 1365 cbp->byte_count = 22; /* (22) bytes to config */ 1366 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1367 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1368 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1369 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1370 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1371 cbp->dma_bce = 0; /* (disable) dma max counters */ 1372 cbp->late_scb = 0; /* (don't) defer SCB update */ 1373 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1374 cbp->ci_int = 1; /* interrupt on CU idle */ 1375 cbp->save_bf = save_bf;/* save bad frames */ 1376 cbp->disc_short_rx = !prm; /* discard short packets */ 1377 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1378 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1379 cbp->nsai = 1; /* (don't) disable source addr insert */ 1380 cbp->preamble_length = 2; /* (7 byte) preamble */ 1381 cbp->loopback = 0; /* (don't) loopback */ 1382 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1383 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1384 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1385 cbp->promiscuous = prm; /* promiscuous mode */ 1386 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1387 cbp->crscdt = 0; /* (CRS only) */ 1388 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1389 cbp->padding = 1; /* (do) pad short tx packets */ 1390 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1391 cbp->force_fdx = 0; /* (don't) force full duplex */ 1392 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1393 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1394 cbp->mc_all = allm; /* accept all multicasts */ 1395 1396 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1397 1398 /* 1399 * Start the config command/DMA. 1400 */ 1401 fxp_scb_wait(sc); 1402 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1403 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1404 /* ...and wait for it to complete. */ 1405 i = 1000; 1406 do { 1407 FXP_CDCONFIGSYNC(sc, 1408 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1409 DELAY(1); 1410 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1411 if (i == 0) { 1412 printf("%s at line %d: dmasync timeout\n", 1413 sc->sc_dev.dv_xname, __LINE__); 1414 return ETIMEDOUT; 1415 } 1416 1417 /* 1418 * Initialize the station address. 1419 */ 1420 cb_ias = &sc->sc_control_data->fcd_iascb; 1421 /* BIG_ENDIAN: no need to swap to store 0 */ 1422 cb_ias->cb_status = 0; 1423 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1424 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1425 cb_ias->link_addr = 0xffffffff; 1426 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1427 1428 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1429 1430 /* 1431 * Start the IAS (Individual Address Setup) command/DMA. 1432 */ 1433 fxp_scb_wait(sc); 1434 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1435 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1436 /* ...and wait for it to complete. */ 1437 i = 1000; 1438 do { 1439 FXP_CDIASSYNC(sc, 1440 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1441 DELAY(1); 1442 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1443 if (i == 0) { 1444 printf("%s at line %d: dmasync timeout\n", 1445 sc->sc_dev.dv_xname, __LINE__); 1446 return ETIMEDOUT; 1447 } 1448 1449 /* 1450 * Initialize the transmit descriptor ring. txlast is initialized 1451 * to the end of the list so that it will wrap around to the first 1452 * descriptor when the first packet is transmitted. 1453 */ 1454 for (i = 0; i < FXP_NTXCB; i++) { 1455 txd = FXP_CDTX(sc, i); 1456 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1457 txd->cb_command = 1458 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1459 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1460 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1461 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1462 } 1463 sc->sc_txpending = 0; 1464 sc->sc_txdirty = 0; 1465 sc->sc_txlast = FXP_NTXCB - 1; 1466 1467 /* 1468 * Initialize the receive buffer list. 1469 */ 1470 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1471 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1472 rxmap = FXP_RXMAP_GET(sc); 1473 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1474 printf("%s: unable to allocate or map rx " 1475 "buffer %d, error = %d\n", 1476 sc->sc_dev.dv_xname, 1477 sc->sc_rxq.ifq_len, error); 1478 /* 1479 * XXX Should attempt to run with fewer receive 1480 * XXX buffers instead of just failing. 1481 */ 1482 FXP_RXMAP_PUT(sc, rxmap); 1483 fxp_rxdrain(sc); 1484 goto out; 1485 } 1486 } 1487 sc->sc_rxidle = 0; 1488 1489 /* 1490 * Give the transmit ring to the chip. We do this by pointing 1491 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1492 * issuing a start command. It will execute the NOP and then 1493 * suspend, pointing at the first descriptor. 1494 */ 1495 fxp_scb_wait(sc); 1496 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1497 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1498 1499 /* 1500 * Initialize receiver buffer area - RFA. 1501 */ 1502 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1503 fxp_scb_wait(sc); 1504 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1505 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1506 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1507 1508 if (sc->sc_flags & FXPF_MII) { 1509 /* 1510 * Set current media. 1511 */ 1512 mii_mediachg(&sc->sc_mii); 1513 } 1514 1515 /* 1516 * ...all done! 1517 */ 1518 ifp->if_flags |= IFF_RUNNING; 1519 ifp->if_flags &= ~IFF_OACTIVE; 1520 1521 /* 1522 * Start the one second timer. 1523 */ 1524 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1525 1526 /* 1527 * Attempt to start output on the interface. 1528 */ 1529 fxp_start(ifp); 1530 1531 out: 1532 if (error) 1533 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1534 return (error); 1535 } 1536 1537 /* 1538 * Change media according to request. 1539 */ 1540 int 1541 fxp_mii_mediachange(ifp) 1542 struct ifnet *ifp; 1543 { 1544 struct fxp_softc *sc = ifp->if_softc; 1545 1546 if (ifp->if_flags & IFF_UP) 1547 mii_mediachg(&sc->sc_mii); 1548 return (0); 1549 } 1550 1551 /* 1552 * Notify the world which media we're using. 1553 */ 1554 void 1555 fxp_mii_mediastatus(ifp, ifmr) 1556 struct ifnet *ifp; 1557 struct ifmediareq *ifmr; 1558 { 1559 struct fxp_softc *sc = ifp->if_softc; 1560 1561 if(sc->sc_enabled == 0) { 1562 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1563 ifmr->ifm_status = 0; 1564 return; 1565 } 1566 1567 mii_pollstat(&sc->sc_mii); 1568 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1569 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1570 } 1571 1572 int 1573 fxp_80c24_mediachange(ifp) 1574 struct ifnet *ifp; 1575 { 1576 1577 /* Nothing to do here. */ 1578 return (0); 1579 } 1580 1581 void 1582 fxp_80c24_mediastatus(ifp, ifmr) 1583 struct ifnet *ifp; 1584 struct ifmediareq *ifmr; 1585 { 1586 struct fxp_softc *sc = ifp->if_softc; 1587 1588 /* 1589 * Media is currently-selected media. We cannot determine 1590 * the link status. 1591 */ 1592 ifmr->ifm_status = 0; 1593 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1594 } 1595 1596 /* 1597 * Add a buffer to the end of the RFA buffer list. 1598 * Return 0 if successful, error code on failure. 1599 * 1600 * The RFA struct is stuck at the beginning of mbuf cluster and the 1601 * data pointer is fixed up to point just past it. 1602 */ 1603 int 1604 fxp_add_rfabuf(sc, rxmap, unload) 1605 struct fxp_softc *sc; 1606 bus_dmamap_t rxmap; 1607 int unload; 1608 { 1609 struct mbuf *m; 1610 int error; 1611 1612 MGETHDR(m, M_DONTWAIT, MT_DATA); 1613 if (m == NULL) 1614 return (ENOBUFS); 1615 1616 MCLGET(m, M_DONTWAIT); 1617 if ((m->m_flags & M_EXT) == 0) { 1618 m_freem(m); 1619 return (ENOBUFS); 1620 } 1621 1622 if (unload) 1623 bus_dmamap_unload(sc->sc_dmat, rxmap); 1624 1625 M_SETCTX(m, rxmap); 1626 1627 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1628 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1629 if (error) { 1630 printf("%s: can't load rx DMA map %d, error = %d\n", 1631 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1632 panic("fxp_add_rfabuf"); /* XXX */ 1633 } 1634 1635 FXP_INIT_RFABUF(sc, m); 1636 1637 return (0); 1638 } 1639 1640 volatile int 1641 fxp_mdi_read(self, phy, reg) 1642 struct device *self; 1643 int phy; 1644 int reg; 1645 { 1646 struct fxp_softc *sc = (struct fxp_softc *)self; 1647 int count = 10000; 1648 int value; 1649 1650 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1651 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1652 1653 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1654 && count--) 1655 DELAY(10); 1656 1657 if (count <= 0) 1658 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1659 1660 return (value & 0xffff); 1661 } 1662 1663 void 1664 fxp_statchg(self) 1665 struct device *self; 1666 { 1667 1668 /* Nothing to do. */ 1669 } 1670 1671 void 1672 fxp_mdi_write(self, phy, reg, value) 1673 struct device *self; 1674 int phy; 1675 int reg; 1676 int value; 1677 { 1678 struct fxp_softc *sc = (struct fxp_softc *)self; 1679 int count = 10000; 1680 1681 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1682 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1683 (value & 0xffff)); 1684 1685 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1686 count--) 1687 DELAY(10); 1688 1689 if (count <= 0) 1690 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1691 } 1692 1693 int 1694 fxp_ioctl(ifp, command, data) 1695 struct ifnet *ifp; 1696 u_long command; 1697 caddr_t data; 1698 { 1699 struct fxp_softc *sc = ifp->if_softc; 1700 struct ifreq *ifr = (struct ifreq *)data; 1701 struct ifaddr *ifa = (struct ifaddr *)data; 1702 int s, error = 0; 1703 1704 s = splnet(); 1705 1706 switch (command) { 1707 case SIOCSIFADDR: 1708 if ((error = fxp_enable(sc)) != 0) 1709 break; 1710 ifp->if_flags |= IFF_UP; 1711 1712 switch (ifa->ifa_addr->sa_family) { 1713 #ifdef INET 1714 case AF_INET: 1715 if ((error = fxp_init(sc)) != 0) 1716 break; 1717 arp_ifinit(ifp, ifa); 1718 break; 1719 #endif /* INET */ 1720 #ifdef NS 1721 case AF_NS: 1722 { 1723 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1724 1725 if (ns_nullhost(*ina)) 1726 ina->x_host = *(union ns_host *) 1727 LLADDR(ifp->if_sadl); 1728 else 1729 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1730 ifp->if_addrlen); 1731 /* Set new address. */ 1732 error = fxp_init(sc); 1733 break; 1734 } 1735 #endif /* NS */ 1736 default: 1737 error = fxp_init(sc); 1738 break; 1739 } 1740 break; 1741 1742 case SIOCSIFMTU: 1743 if (ifr->ifr_mtu > ETHERMTU) 1744 error = EINVAL; 1745 else 1746 ifp->if_mtu = ifr->ifr_mtu; 1747 break; 1748 1749 case SIOCSIFFLAGS: 1750 if ((ifp->if_flags & IFF_UP) == 0 && 1751 (ifp->if_flags & IFF_RUNNING) != 0) { 1752 /* 1753 * If interface is marked down and it is running, then 1754 * stop it. 1755 */ 1756 fxp_stop(sc, 1); 1757 fxp_disable(sc); 1758 } else if ((ifp->if_flags & IFF_UP) != 0 && 1759 (ifp->if_flags & IFF_RUNNING) == 0) { 1760 /* 1761 * If interface is marked up and it is stopped, then 1762 * start it. 1763 */ 1764 if((error = fxp_enable(sc)) != 0) 1765 break; 1766 error = fxp_init(sc); 1767 } else if ((ifp->if_flags & IFF_UP) != 0) { 1768 /* 1769 * Reset the interface to pick up change in any other 1770 * flags that affect the hardware state. 1771 */ 1772 if((error = fxp_enable(sc)) != 0) 1773 break; 1774 error = fxp_init(sc); 1775 } 1776 break; 1777 1778 case SIOCADDMULTI: 1779 case SIOCDELMULTI: 1780 if(sc->sc_enabled == 0) { 1781 error = EIO; 1782 break; 1783 } 1784 error = (command == SIOCADDMULTI) ? 1785 ether_addmulti(ifr, &sc->sc_ethercom) : 1786 ether_delmulti(ifr, &sc->sc_ethercom); 1787 1788 if (error == ENETRESET) { 1789 /* 1790 * Multicast list has changed; set the hardware 1791 * filter accordingly. 1792 */ 1793 if (sc->sc_txpending) { 1794 sc->sc_flags |= FXPF_WANTINIT; 1795 error = 0; 1796 } else 1797 error = fxp_init(sc); 1798 } 1799 break; 1800 1801 case SIOCSIFMEDIA: 1802 case SIOCGIFMEDIA: 1803 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1804 break; 1805 1806 default: 1807 error = EINVAL; 1808 break; 1809 } 1810 1811 splx(s); 1812 return (error); 1813 } 1814 1815 /* 1816 * Program the multicast filter. 1817 * 1818 * This function must be called at splnet(). 1819 */ 1820 void 1821 fxp_mc_setup(sc) 1822 struct fxp_softc *sc; 1823 { 1824 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1826 struct ethercom *ec = &sc->sc_ethercom; 1827 struct ether_multi *enm; 1828 struct ether_multistep step; 1829 int count, nmcasts; 1830 1831 #ifdef DIAGNOSTIC 1832 if (sc->sc_txpending) 1833 panic("fxp_mc_setup: pending transmissions"); 1834 #endif 1835 1836 ifp->if_flags &= ~IFF_ALLMULTI; 1837 1838 /* 1839 * Initialize multicast setup descriptor. 1840 */ 1841 nmcasts = 0; 1842 ETHER_FIRST_MULTI(step, ec, enm); 1843 while (enm != NULL) { 1844 /* 1845 * Check for too many multicast addresses or if we're 1846 * listening to a range. Either way, we simply have 1847 * to accept all multicasts. 1848 */ 1849 if (nmcasts >= MAXMCADDR || 1850 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1851 ETHER_ADDR_LEN) != 0) { 1852 /* 1853 * Callers of this function must do the 1854 * right thing with this. If we're called 1855 * from outside fxp_init(), the caller must 1856 * detect if the state if IFF_ALLMULTI changes. 1857 * If it does, the caller must then call 1858 * fxp_init(), since allmulti is handled by 1859 * the config block. 1860 */ 1861 ifp->if_flags |= IFF_ALLMULTI; 1862 return; 1863 } 1864 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1865 ETHER_ADDR_LEN); 1866 nmcasts++; 1867 ETHER_NEXT_MULTI(step, enm); 1868 } 1869 1870 /* BIG_ENDIAN: no need to swap to store 0 */ 1871 mcsp->cb_status = 0; 1872 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1873 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1874 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1875 1876 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1877 1878 /* 1879 * Wait until the command unit is not active. This should never 1880 * happen since nothing is queued, but make sure anyway. 1881 */ 1882 count = 100; 1883 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1884 FXP_SCB_CUS_ACTIVE && --count) 1885 DELAY(1); 1886 if (count == 0) { 1887 printf("%s at line %d: command queue timeout\n", 1888 sc->sc_dev.dv_xname, __LINE__); 1889 return; 1890 } 1891 1892 /* 1893 * Start the multicast setup command/DMA. 1894 */ 1895 fxp_scb_wait(sc); 1896 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1897 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1898 1899 /* ...and wait for it to complete. */ 1900 count = 1000; 1901 do { 1902 FXP_CDMCSSYNC(sc, 1903 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1904 DELAY(1); 1905 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1906 if (count == 0) { 1907 printf("%s at line %d: dmasync timeout\n", 1908 sc->sc_dev.dv_xname, __LINE__); 1909 return; 1910 } 1911 } 1912 1913 int 1914 fxp_enable(sc) 1915 struct fxp_softc *sc; 1916 { 1917 1918 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1919 if ((*sc->sc_enable)(sc) != 0) { 1920 printf("%s: device enable failed\n", 1921 sc->sc_dev.dv_xname); 1922 return (EIO); 1923 } 1924 } 1925 1926 sc->sc_enabled = 1; 1927 return (0); 1928 } 1929 1930 void 1931 fxp_disable(sc) 1932 struct fxp_softc *sc; 1933 { 1934 1935 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1936 (*sc->sc_disable)(sc); 1937 sc->sc_enabled = 0; 1938 } 1939 } 1940 1941 /* 1942 * fxp_activate: 1943 * 1944 * Handle device activation/deactivation requests. 1945 */ 1946 int 1947 fxp_activate(self, act) 1948 struct device *self; 1949 enum devact act; 1950 { 1951 struct fxp_softc *sc = (void *) self; 1952 int s, error = 0; 1953 1954 s = splnet(); 1955 switch (act) { 1956 case DVACT_ACTIVATE: 1957 error = EOPNOTSUPP; 1958 break; 1959 1960 case DVACT_DEACTIVATE: 1961 if (sc->sc_flags & FXPF_MII) 1962 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1963 MII_OFFSET_ANY); 1964 if_deactivate(&sc->sc_ethercom.ec_if); 1965 break; 1966 } 1967 splx(s); 1968 1969 return (error); 1970 } 1971 1972 /* 1973 * fxp_detach: 1974 * 1975 * Detach an i82557 interface. 1976 */ 1977 int 1978 fxp_detach(sc) 1979 struct fxp_softc *sc; 1980 { 1981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1982 int i; 1983 1984 /* Succeed now if there's no work to do. */ 1985 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1986 return (0); 1987 1988 /* Unhook our tick handler. */ 1989 callout_stop(&sc->sc_callout); 1990 1991 if (sc->sc_flags & FXPF_MII) { 1992 /* Detach all PHYs */ 1993 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1994 } 1995 1996 /* Delete all remaining media. */ 1997 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1998 1999 #if NRND > 0 2000 rnd_detach_source(&sc->rnd_source); 2001 #endif 2002 #if NBPFILTER > 0 2003 bpfdetach(ifp); 2004 #endif 2005 ether_ifdetach(ifp); 2006 if_detach(ifp); 2007 2008 for (i = 0; i < FXP_NRFABUFS; i++) { 2009 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2010 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2011 } 2012 2013 for (i = 0; i < FXP_NTXCB; i++) { 2014 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2015 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2016 } 2017 2018 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2019 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2020 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2021 sizeof(struct fxp_control_data)); 2022 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2023 2024 shutdownhook_disestablish(sc->sc_sdhook); 2025 powerhook_disestablish(sc->sc_powerhook); 2026 2027 return (0); 2028 } 2029
Indexes created Tue Sep 30 20:09:53 GMT 2025