i82557.c revision 1.40
1 /* $NetBSD: i82557.c,v 1.40 2000/10/11 16:57:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <uvm/uvm_extern.h> 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia __P((struct fxp_softc *)); 169 int fxp_mii_mediachange __P((struct ifnet *)); 170 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 void fxp_80c24_initmedia __P((struct fxp_softc *)); 173 int fxp_80c24_mediachange __P((struct ifnet *)); 174 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176 inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178 void fxp_start __P((struct ifnet *)); 179 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180 void fxp_watchdog __P((struct ifnet *)); 181 int fxp_init __P((struct ifnet *)); 182 void fxp_stop __P((struct ifnet *, int)); 183 184 void fxp_rxdrain __P((struct fxp_softc *)); 185 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 186 int fxp_mdi_read __P((struct device *, int, int)); 187 void fxp_statchg __P((struct device *)); 188 void fxp_mdi_write __P((struct device *, int, int, int)); 189 void fxp_autosize_eeprom __P((struct fxp_softc*)); 190 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 191 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 192 void fxp_tick __P((void *)); 193 void fxp_mc_setup __P((struct fxp_softc *)); 194 195 void fxp_shutdown __P((void *)); 196 void fxp_power __P((int, void *)); 197 198 int fxp_copy_small = 0; 199 200 struct fxp_phytype { 201 int fp_phy; /* type of PHY, -1 for MII at the end. */ 202 void (*fp_init) __P((struct fxp_softc *)); 203 } fxp_phytype_table[] = { 204 { FXP_PHY_80C24, fxp_80c24_initmedia }, 205 { -1, fxp_mii_initmedia }, 206 }; 207 208 /* 209 * Set initial transmit threshold at 64 (512 bytes). This is 210 * increased by 64 (512 bytes) at a time, to maximum of 192 211 * (1536 bytes), if an underrun occurs. 212 */ 213 static int tx_threshold = 64; 214 215 /* 216 * Wait for the previous command to be accepted (but not necessarily 217 * completed). 218 */ 219 inline void 220 fxp_scb_wait(sc) 221 struct fxp_softc *sc; 222 { 223 int i = 10000; 224 225 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 226 delay(2); 227 if (i == 0) 228 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 229 } 230 231 /* 232 * Finish attaching an i82557 interface. Called by bus-specific front-end. 233 */ 234 void 235 fxp_attach(sc) 236 struct fxp_softc *sc; 237 { 238 u_int8_t enaddr[ETHER_ADDR_LEN]; 239 struct ifnet *ifp; 240 bus_dma_segment_t seg; 241 int rseg, i, error; 242 struct fxp_phytype *fp; 243 244 callout_init(&sc->sc_callout); 245 246 /* 247 * Allocate the control data structures, and create and load the 248 * DMA map for it. 249 */ 250 if ((error = bus_dmamem_alloc(sc->sc_dmat, 251 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 252 0)) != 0) { 253 printf("%s: unable to allocate control data, error = %d\n", 254 sc->sc_dev.dv_xname, error); 255 goto fail_0; 256 } 257 258 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 259 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 260 BUS_DMA_COHERENT)) != 0) { 261 printf("%s: unable to map control data, error = %d\n", 262 sc->sc_dev.dv_xname, error); 263 goto fail_1; 264 } 265 sc->sc_cdseg = seg; 266 sc->sc_cdnseg = rseg; 267 268 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 269 270 if ((error = bus_dmamap_create(sc->sc_dmat, 271 sizeof(struct fxp_control_data), 1, 272 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 273 printf("%s: unable to create control data DMA map, " 274 "error = %d\n", sc->sc_dev.dv_xname, error); 275 goto fail_2; 276 } 277 278 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 279 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 280 0)) != 0) { 281 printf("%s: can't load control data DMA map, error = %d\n", 282 sc->sc_dev.dv_xname, error); 283 goto fail_3; 284 } 285 286 /* 287 * Create the transmit buffer DMA maps. 288 */ 289 for (i = 0; i < FXP_NTXCB; i++) { 290 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 291 FXP_NTXSEG, MCLBYTES, 0, 0, 292 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 293 printf("%s: unable to create tx DMA map %d, " 294 "error = %d\n", sc->sc_dev.dv_xname, i, error); 295 goto fail_4; 296 } 297 } 298 299 /* 300 * Create the receive buffer DMA maps. 301 */ 302 for (i = 0; i < FXP_NRFABUFS; i++) { 303 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 304 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 305 printf("%s: unable to create rx DMA map %d, " 306 "error = %d\n", sc->sc_dev.dv_xname, i, error); 307 goto fail_5; 308 } 309 } 310 311 /* Initialize MAC address and media structures. */ 312 fxp_get_info(sc, enaddr); 313 314 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 315 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 316 317 ifp = &sc->sc_ethercom.ec_if; 318 319 /* 320 * Get info about our media interface, and initialize it. Note 321 * the table terminates itself with a phy of -1, indicating 322 * that we're using MII. 323 */ 324 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 325 if (fp->fp_phy == sc->phy_primary_device) 326 break; 327 (*fp->fp_init)(sc); 328 329 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 330 ifp->if_softc = sc; 331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332 ifp->if_ioctl = fxp_ioctl; 333 ifp->if_start = fxp_start; 334 ifp->if_watchdog = fxp_watchdog; 335 ifp->if_init = fxp_init; 336 ifp->if_stop = fxp_stop; 337 338 /* 339 * We can support 802.1Q VLAN-sized frames. 340 */ 341 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 342 343 /* 344 * Attach the interface. 345 */ 346 if_attach(ifp); 347 ether_ifattach(ifp, enaddr); 348 #if NBPFILTER > 0 349 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 350 sizeof(struct ether_header)); 351 #endif 352 #if NRND > 0 353 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 354 RND_TYPE_NET, 0); 355 #endif 356 357 /* 358 * Add shutdown hook so that DMA is disabled prior to reboot. Not 359 * doing do could allow DMA to corrupt kernel memory during the 360 * reboot before the driver initializes. 361 */ 362 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 363 if (sc->sc_sdhook == NULL) 364 printf("%s: WARNING: unable to establish shutdown hook\n", 365 sc->sc_dev.dv_xname); 366 /* 367 * Add suspend hook, for similar reasons.. 368 */ 369 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 370 if (sc->sc_powerhook == NULL) 371 printf("%s: WARNING: unable to establish power hook\n", 372 sc->sc_dev.dv_xname); 373 374 /* The attach is successful. */ 375 sc->sc_flags |= FXPF_ATTACHED; 376 377 return; 378 379 /* 380 * Free any resources we've allocated during the failed attach 381 * attempt. Do this in reverse order and fall though. 382 */ 383 fail_5: 384 for (i = 0; i < FXP_NRFABUFS; i++) { 385 if (sc->sc_rxmaps[i] != NULL) 386 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 387 } 388 fail_4: 389 for (i = 0; i < FXP_NTXCB; i++) { 390 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 391 bus_dmamap_destroy(sc->sc_dmat, 392 FXP_DSTX(sc, i)->txs_dmamap); 393 } 394 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 395 fail_3: 396 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 397 fail_2: 398 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 399 sizeof(struct fxp_control_data)); 400 fail_1: 401 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 402 fail_0: 403 return; 404 } 405 406 void 407 fxp_mii_initmedia(sc) 408 struct fxp_softc *sc; 409 { 410 411 sc->sc_flags |= FXPF_MII; 412 413 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 414 sc->sc_mii.mii_readreg = fxp_mdi_read; 415 sc->sc_mii.mii_writereg = fxp_mdi_write; 416 sc->sc_mii.mii_statchg = fxp_statchg; 417 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 418 fxp_mii_mediastatus); 419 /* 420 * The i82557 wedges if all of its PHYs are isolated! 421 */ 422 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 423 MII_OFFSET_ANY, MIIF_NOISOLATE); 424 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 425 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 426 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 427 } else 428 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 429 } 430 431 void 432 fxp_80c24_initmedia(sc) 433 struct fxp_softc *sc; 434 { 435 436 /* 437 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 438 * doesn't have a programming interface of any sort. The 439 * media is sensed automatically based on how the link partner 440 * is configured. This is, in essence, manual configuration. 441 */ 442 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 443 sc->sc_dev.dv_xname); 444 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 445 fxp_80c24_mediastatus); 446 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 447 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 448 } 449 450 /* 451 * Device shutdown routine. Called at system shutdown after sync. The 452 * main purpose of this routine is to shut off receiver DMA so that 453 * kernel memory doesn't get clobbered during warmboot. 454 */ 455 void 456 fxp_shutdown(arg) 457 void *arg; 458 { 459 struct fxp_softc *sc = arg; 460 461 /* 462 * Since the system's going to halt shortly, don't bother 463 * freeing mbufs. 464 */ 465 fxp_stop(&sc->sc_ethercom.ec_if, 0); 466 } 467 /* 468 * Power handler routine. Called when the system is transitioning 469 * into/out of power save modes. As with fxp_shutdown, the main 470 * purpose of this routine is to shut off receiver DMA so it doesn't 471 * clobber kernel memory at the wrong time. 472 */ 473 void 474 fxp_power(why, arg) 475 int why; 476 void *arg; 477 { 478 struct fxp_softc *sc = arg; 479 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 480 int s; 481 482 s = splnet(); 483 if (why != PWR_RESUME) 484 fxp_stop(ifp, 0); 485 else { 486 if (ifp->if_flags & IFF_UP) 487 fxp_init(ifp); 488 } 489 splx(s); 490 } 491 492 /* 493 * Initialize the interface media. 494 */ 495 void 496 fxp_get_info(sc, enaddr) 497 struct fxp_softc *sc; 498 u_int8_t *enaddr; 499 { 500 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 501 502 /* 503 * Reset to a stable state. 504 */ 505 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 506 DELAY(10); 507 508 sc->sc_eeprom_size = 0; 509 fxp_autosize_eeprom(sc); 510 if(sc->sc_eeprom_size == 0) { 511 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 512 sc->sc_eeprom_size = 6; /* XXX panic here? */ 513 } 514 #ifdef DEBUG 515 printf("%s: detected %d word EEPROM\n", 516 sc->sc_dev.dv_xname, 517 1 << sc->sc_eeprom_size); 518 #endif 519 520 /* 521 * Get info about the primary PHY 522 */ 523 fxp_read_eeprom(sc, &data, 6, 1); 524 sc->phy_primary_addr = data & 0xff; 525 sc->phy_primary_device = (data >> 8) & 0x3f; 526 sc->phy_10Mbps_only = data >> 15; 527 528 /* 529 * Read MAC address. 530 */ 531 fxp_read_eeprom(sc, myea, 0, 3); 532 enaddr[0] = myea[0] & 0xff; 533 enaddr[1] = myea[0] >> 8; 534 enaddr[2] = myea[1] & 0xff; 535 enaddr[3] = myea[1] >> 8; 536 enaddr[4] = myea[2] & 0xff; 537 enaddr[5] = myea[2] >> 8; 538 } 539 540 /* 541 * Figure out EEPROM size. 542 * 543 * 559's can have either 64-word or 256-word EEPROMs, the 558 544 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 545 * talks about the existance of 16 to 256 word EEPROMs. 546 * 547 * The only known sizes are 64 and 256, where the 256 version is used 548 * by CardBus cards to store CIS information. 549 * 550 * The address is shifted in msb-to-lsb, and after the last 551 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 552 * after which follows the actual data. We try to detect this zero, by 553 * probing the data-out bit in the EEPROM control register just after 554 * having shifted in a bit. If the bit is zero, we assume we've 555 * shifted enough address bits. The data-out should be tri-state, 556 * before this, which should translate to a logical one. 557 * 558 * Other ways to do this would be to try to read a register with known 559 * contents with a varying number of address bits, but no such 560 * register seem to be available. The high bits of register 10 are 01 561 * on the 558 and 559, but apparently not on the 557. 562 * 563 * The Linux driver computes a checksum on the EEPROM data, but the 564 * value of this checksum is not very well documented. 565 */ 566 567 void 568 fxp_autosize_eeprom(sc) 569 struct fxp_softc *sc; 570 { 571 u_int16_t reg; 572 int x; 573 574 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 575 /* 576 * Shift in read opcode. 577 */ 578 for (x = 3; x > 0; x--) { 579 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 580 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 581 } else { 582 reg = FXP_EEPROM_EECS; 583 } 584 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 585 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 586 reg | FXP_EEPROM_EESK); 587 DELAY(4); 588 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 589 DELAY(4); 590 } 591 /* 592 * Shift in address, wait for the dummy zero following a correct 593 * address shift. 594 */ 595 for (x = 1; x <= 8; x++) { 596 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 597 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 598 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 599 DELAY(4); 600 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 601 FXP_EEPROM_EEDO) == 0) 602 break; 603 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 604 DELAY(4); 605 } 606 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 607 DELAY(4); 608 if(x != 6 && x != 8) { 609 #ifdef DEBUG 610 printf("%s: strange EEPROM size (%d)\n", 611 sc->sc_dev.dv_xname, 1 << x); 612 #endif 613 } else 614 sc->sc_eeprom_size = x; 615 } 616 617 /* 618 * Read from the serial EEPROM. Basically, you manually shift in 619 * the read opcode (one bit at a time) and then shift in the address, 620 * and then you shift out the data (all of this one bit at a time). 621 * The word size is 16 bits, so you have to provide the address for 622 * every 16 bits of data. 623 */ 624 void 625 fxp_read_eeprom(sc, data, offset, words) 626 struct fxp_softc *sc; 627 u_int16_t *data; 628 int offset; 629 int words; 630 { 631 u_int16_t reg; 632 int i, x; 633 634 for (i = 0; i < words; i++) { 635 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 636 /* 637 * Shift in read opcode. 638 */ 639 for (x = 3; x > 0; x--) { 640 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 641 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 642 } else { 643 reg = FXP_EEPROM_EECS; 644 } 645 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 646 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 647 reg | FXP_EEPROM_EESK); 648 DELAY(4); 649 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 650 DELAY(4); 651 } 652 /* 653 * Shift in address. 654 */ 655 for (x = sc->sc_eeprom_size; x > 0; x--) { 656 if ((i + offset) & (1 << (x - 1))) { 657 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 658 } else { 659 reg = FXP_EEPROM_EECS; 660 } 661 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 662 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 663 reg | FXP_EEPROM_EESK); 664 DELAY(4); 665 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 666 DELAY(4); 667 } 668 reg = FXP_EEPROM_EECS; 669 data[i] = 0; 670 /* 671 * Shift out data. 672 */ 673 for (x = 16; x > 0; x--) { 674 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 675 reg | FXP_EEPROM_EESK); 676 DELAY(4); 677 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 678 FXP_EEPROM_EEDO) 679 data[i] |= (1 << (x - 1)); 680 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 681 DELAY(4); 682 } 683 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 684 DELAY(4); 685 } 686 } 687 688 /* 689 * Start packet transmission on the interface. 690 */ 691 void 692 fxp_start(ifp) 693 struct ifnet *ifp; 694 { 695 struct fxp_softc *sc = ifp->if_softc; 696 struct mbuf *m0, *m; 697 struct fxp_cb_tx *txd; 698 struct fxp_txsoft *txs; 699 struct fxp_tbdlist *tbd; 700 bus_dmamap_t dmamap; 701 int error, lasttx, nexttx, opending, seg; 702 703 /* 704 * If we want a re-init, bail out now. 705 */ 706 if (sc->sc_flags & FXPF_WANTINIT) { 707 ifp->if_flags |= IFF_OACTIVE; 708 return; 709 } 710 711 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 712 return; 713 714 /* 715 * Remember the previous txpending and the current lasttx. 716 */ 717 opending = sc->sc_txpending; 718 lasttx = sc->sc_txlast; 719 720 /* 721 * Loop through the send queue, setting up transmit descriptors 722 * until we drain the queue, or use up all available transmit 723 * descriptors. 724 */ 725 while (sc->sc_txpending < FXP_NTXCB) { 726 /* 727 * Grab a packet off the queue. 728 */ 729 IF_DEQUEUE(&ifp->if_snd, m0); 730 if (m0 == NULL) 731 break; 732 733 /* 734 * Get the next available transmit descriptor. 735 */ 736 nexttx = FXP_NEXTTX(sc->sc_txlast); 737 txd = FXP_CDTX(sc, nexttx); 738 tbd = FXP_CDTBD(sc, nexttx); 739 txs = FXP_DSTX(sc, nexttx); 740 dmamap = txs->txs_dmamap; 741 742 /* 743 * Load the DMA map. If this fails, the packet either 744 * didn't fit in the allotted number of frags, or we were 745 * short on resources. In this case, we'll copy and try 746 * again. 747 */ 748 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 749 BUS_DMA_NOWAIT) != 0) { 750 MGETHDR(m, M_DONTWAIT, MT_DATA); 751 if (m == NULL) { 752 printf("%s: unable to allocate Tx mbuf\n", 753 sc->sc_dev.dv_xname); 754 IF_PREPEND(&ifp->if_snd, m0); 755 break; 756 } 757 if (m0->m_pkthdr.len > MHLEN) { 758 MCLGET(m, M_DONTWAIT); 759 if ((m->m_flags & M_EXT) == 0) { 760 printf("%s: unable to allocate Tx " 761 "cluster\n", sc->sc_dev.dv_xname); 762 m_freem(m); 763 IF_PREPEND(&ifp->if_snd, m0); 764 break; 765 } 766 } 767 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 768 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 769 m_freem(m0); 770 m0 = m; 771 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 772 m0, BUS_DMA_NOWAIT); 773 if (error) { 774 printf("%s: unable to load Tx buffer, " 775 "error = %d\n", sc->sc_dev.dv_xname, error); 776 IF_PREPEND(&ifp->if_snd, m0); 777 break; 778 } 779 } 780 781 /* Initialize the fraglist. */ 782 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 783 tbd->tbd_d[seg].tb_addr = 784 htole32(dmamap->dm_segs[seg].ds_addr); 785 tbd->tbd_d[seg].tb_size = 786 htole32(dmamap->dm_segs[seg].ds_len); 787 } 788 789 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 790 791 /* Sync the DMA map. */ 792 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 793 BUS_DMASYNC_PREWRITE); 794 795 /* 796 * Store a pointer to the packet so we can free it later. 797 */ 798 txs->txs_mbuf = m0; 799 800 /* 801 * Initialize the transmit descriptor. 802 */ 803 /* BIG_ENDIAN: no need to swap to store 0 */ 804 txd->cb_status = 0; 805 txd->cb_command = 806 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 807 txd->tx_threshold = tx_threshold; 808 txd->tbd_number = dmamap->dm_nsegs; 809 810 FXP_CDTXSYNC(sc, nexttx, 811 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 812 813 /* Advance the tx pointer. */ 814 sc->sc_txpending++; 815 sc->sc_txlast = nexttx; 816 817 #if NBPFILTER > 0 818 /* 819 * Pass packet to bpf if there is a listener. 820 */ 821 if (ifp->if_bpf) 822 bpf_mtap(ifp->if_bpf, m0); 823 #endif 824 } 825 826 if (sc->sc_txpending == FXP_NTXCB) { 827 /* No more slots; notify upper layer. */ 828 ifp->if_flags |= IFF_OACTIVE; 829 } 830 831 if (sc->sc_txpending != opending) { 832 /* 833 * We enqueued packets. If the transmitter was idle, 834 * reset the txdirty pointer. 835 */ 836 if (opending == 0) 837 sc->sc_txdirty = FXP_NEXTTX(lasttx); 838 839 /* 840 * Cause the chip to interrupt and suspend command 841 * processing once the last packet we've enqueued 842 * has been transmitted. 843 */ 844 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 845 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 846 FXP_CDTXSYNC(sc, sc->sc_txlast, 847 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 848 849 /* 850 * The entire packet chain is set up. Clear the suspend bit 851 * on the command prior to the first packet we set up. 852 */ 853 FXP_CDTXSYNC(sc, lasttx, 854 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 855 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 856 FXP_CDTXSYNC(sc, lasttx, 857 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 858 859 /* 860 * Issue a Resume command in case the chip was suspended. 861 */ 862 fxp_scb_wait(sc); 863 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 864 865 /* Set a watchdog timer in case the chip flakes out. */ 866 ifp->if_timer = 5; 867 } 868 } 869 870 /* 871 * Process interface interrupts. 872 */ 873 int 874 fxp_intr(arg) 875 void *arg; 876 { 877 struct fxp_softc *sc = arg; 878 struct ethercom *ec = &sc->sc_ethercom; 879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 880 struct fxp_cb_tx *txd; 881 struct fxp_txsoft *txs; 882 struct mbuf *m, *m0; 883 bus_dmamap_t rxmap; 884 struct fxp_rfa *rfa; 885 int i, claimed = 0; 886 u_int16_t len, rxstat, txstat; 887 u_int8_t statack; 888 889 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 890 return (0); 891 /* 892 * If the interface isn't running, don't try to 893 * service the interrupt.. just ack it and bail. 894 */ 895 if ((ifp->if_flags & IFF_RUNNING) == 0) { 896 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 897 if (statack) { 898 claimed = 1; 899 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 900 } 901 return (claimed); 902 } 903 904 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 905 claimed = 1; 906 907 /* 908 * First ACK all the interrupts in this pass. 909 */ 910 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 911 912 /* 913 * Process receiver interrupts. If a no-resource (RNR) 914 * condition exists, get whatever packets we can and 915 * re-start the receiver. 916 */ 917 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 918 rcvloop: 919 m = sc->sc_rxq.ifq_head; 920 rfa = FXP_MTORFA(m); 921 rxmap = M_GETCTX(m, bus_dmamap_t); 922 923 FXP_RFASYNC(sc, m, 924 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 925 926 rxstat = le16toh(rfa->rfa_status); 927 928 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 929 /* 930 * We have processed all of the 931 * receive buffers. 932 */ 933 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 934 goto do_transmit; 935 } 936 937 IF_DEQUEUE(&sc->sc_rxq, m); 938 939 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 940 941 len = le16toh(rfa->actual_size) & 942 (m->m_ext.ext_size - 1); 943 944 if (len < sizeof(struct ether_header)) { 945 /* 946 * Runt packet; drop it now. 947 */ 948 FXP_INIT_RFABUF(sc, m); 949 goto rcvloop; 950 } 951 952 /* 953 * If support for 802.1Q VLAN sized frames is 954 * enabled, we need to do some additional error 955 * checking (as we are saving bad frames, in 956 * order to receive the larger ones). 957 */ 958 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 959 (rxstat & (FXP_RFA_STATUS_OVERRUN| 960 FXP_RFA_STATUS_RNR| 961 FXP_RFA_STATUS_ALIGN| 962 FXP_RFA_STATUS_CRC)) != 0) { 963 FXP_INIT_RFABUF(sc, m); 964 goto rcvloop; 965 } 966 967 /* 968 * If the packet is small enough to fit in a 969 * single header mbuf, allocate one and copy 970 * the data into it. This greatly reduces 971 * memory consumption when we receive lots 972 * of small packets. 973 * 974 * Otherwise, we add a new buffer to the receive 975 * chain. If this fails, we drop the packet and 976 * recycle the old buffer. 977 */ 978 if (fxp_copy_small != 0 && len <= MHLEN) { 979 MGETHDR(m0, M_DONTWAIT, MT_DATA); 980 if (m == NULL) 981 goto dropit; 982 memcpy(mtod(m0, caddr_t), 983 mtod(m, caddr_t), len); 984 FXP_INIT_RFABUF(sc, m); 985 m = m0; 986 } else { 987 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 988 dropit: 989 ifp->if_ierrors++; 990 FXP_INIT_RFABUF(sc, m); 991 goto rcvloop; 992 } 993 } 994 995 m->m_pkthdr.rcvif = ifp; 996 m->m_pkthdr.len = m->m_len = len; 997 998 #if NBPFILTER > 0 999 /* 1000 * Pass this up to any BPF listeners, but only 1001 * pass it up the stack it its for us. 1002 */ 1003 if (ifp->if_bpf) 1004 bpf_mtap(ifp->if_bpf, m); 1005 #endif 1006 1007 /* Pass it on. */ 1008 (*ifp->if_input)(ifp, m); 1009 goto rcvloop; 1010 } 1011 1012 do_transmit: 1013 if (statack & FXP_SCB_STATACK_RNR) { 1014 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1015 fxp_scb_wait(sc); 1016 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1017 rxmap->dm_segs[0].ds_addr + 1018 RFA_ALIGNMENT_FUDGE); 1019 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1020 FXP_SCB_COMMAND_RU_START); 1021 } 1022 1023 /* 1024 * Free any finished transmit mbuf chains. 1025 */ 1026 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1027 ifp->if_flags &= ~IFF_OACTIVE; 1028 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1029 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1030 txd = FXP_CDTX(sc, i); 1031 txs = FXP_DSTX(sc, i); 1032 1033 FXP_CDTXSYNC(sc, i, 1034 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1035 1036 txstat = le16toh(txd->cb_status); 1037 1038 if ((txstat & FXP_CB_STATUS_C) == 0) 1039 break; 1040 1041 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1042 1043 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1044 0, txs->txs_dmamap->dm_mapsize, 1045 BUS_DMASYNC_POSTWRITE); 1046 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1047 m_freem(txs->txs_mbuf); 1048 txs->txs_mbuf = NULL; 1049 } 1050 1051 /* Update the dirty transmit buffer pointer. */ 1052 sc->sc_txdirty = i; 1053 1054 /* 1055 * Cancel the watchdog timer if there are no pending 1056 * transmissions. 1057 */ 1058 if (sc->sc_txpending == 0) { 1059 ifp->if_timer = 0; 1060 1061 /* 1062 * If we want a re-init, do that now. 1063 */ 1064 if (sc->sc_flags & FXPF_WANTINIT) 1065 (void) fxp_init(ifp); 1066 } 1067 1068 /* 1069 * Try to get more packets going. 1070 */ 1071 fxp_start(ifp); 1072 } 1073 } 1074 1075 #if NRND > 0 1076 if (claimed) 1077 rnd_add_uint32(&sc->rnd_source, statack); 1078 #endif 1079 return (claimed); 1080 } 1081 1082 /* 1083 * Update packet in/out/collision statistics. The i82557 doesn't 1084 * allow you to access these counters without doing a fairly 1085 * expensive DMA to get _all_ of the statistics it maintains, so 1086 * we do this operation here only once per second. The statistics 1087 * counters in the kernel are updated from the previous dump-stats 1088 * DMA and then a new dump-stats DMA is started. The on-chip 1089 * counters are zeroed when the DMA completes. If we can't start 1090 * the DMA immediately, we don't wait - we just prepare to read 1091 * them again next time. 1092 */ 1093 void 1094 fxp_tick(arg) 1095 void *arg; 1096 { 1097 struct fxp_softc *sc = arg; 1098 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1099 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1100 int s; 1101 1102 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1103 return; 1104 1105 s = splnet(); 1106 1107 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1108 1109 ifp->if_opackets += le32toh(sp->tx_good); 1110 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1111 if (sp->rx_good) { 1112 ifp->if_ipackets += le32toh(sp->rx_good); 1113 sc->sc_rxidle = 0; 1114 } else { 1115 sc->sc_rxidle++; 1116 } 1117 ifp->if_ierrors += 1118 le32toh(sp->rx_crc_errors) + 1119 le32toh(sp->rx_alignment_errors) + 1120 le32toh(sp->rx_rnr_errors) + 1121 le32toh(sp->rx_overrun_errors); 1122 /* 1123 * If any transmit underruns occured, bump up the transmit 1124 * threshold by another 512 bytes (64 * 8). 1125 */ 1126 if (sp->tx_underruns) { 1127 ifp->if_oerrors += le32toh(sp->tx_underruns); 1128 if (tx_threshold < 192) 1129 tx_threshold += 64; 1130 } 1131 1132 /* 1133 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1134 * then assume the receiver has locked up and attempt to clear 1135 * the condition by reprogramming the multicast filter (actually, 1136 * resetting the interface). This is a work-around for a bug in 1137 * the 82557 where the receiver locks up if it gets certain types 1138 * of garbage in the syncronization bits prior to the packet header. 1139 * This bug is supposed to only occur in 10Mbps mode, but has been 1140 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1141 * speed transition). 1142 */ 1143 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1144 (void) fxp_init(ifp); 1145 splx(s); 1146 return; 1147 } 1148 /* 1149 * If there is no pending command, start another stats 1150 * dump. Otherwise punt for now. 1151 */ 1152 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1153 /* 1154 * Start another stats dump. 1155 */ 1156 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1157 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1158 FXP_SCB_COMMAND_CU_DUMPRESET); 1159 } else { 1160 /* 1161 * A previous command is still waiting to be accepted. 1162 * Just zero our copy of the stats and wait for the 1163 * next timer event to update them. 1164 */ 1165 /* BIG_ENDIAN: no swap required to store 0 */ 1166 sp->tx_good = 0; 1167 sp->tx_underruns = 0; 1168 sp->tx_total_collisions = 0; 1169 1170 sp->rx_good = 0; 1171 sp->rx_crc_errors = 0; 1172 sp->rx_alignment_errors = 0; 1173 sp->rx_rnr_errors = 0; 1174 sp->rx_overrun_errors = 0; 1175 } 1176 1177 if (sc->sc_flags & FXPF_MII) { 1178 /* Tick the MII clock. */ 1179 mii_tick(&sc->sc_mii); 1180 } 1181 1182 splx(s); 1183 1184 /* 1185 * Schedule another timeout one second from now. 1186 */ 1187 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1188 } 1189 1190 /* 1191 * Drain the receive queue. 1192 */ 1193 void 1194 fxp_rxdrain(sc) 1195 struct fxp_softc *sc; 1196 { 1197 bus_dmamap_t rxmap; 1198 struct mbuf *m; 1199 1200 for (;;) { 1201 IF_DEQUEUE(&sc->sc_rxq, m); 1202 if (m == NULL) 1203 break; 1204 rxmap = M_GETCTX(m, bus_dmamap_t); 1205 bus_dmamap_unload(sc->sc_dmat, rxmap); 1206 FXP_RXMAP_PUT(sc, rxmap); 1207 m_freem(m); 1208 } 1209 } 1210 1211 /* 1212 * Stop the interface. Cancels the statistics updater and resets 1213 * the interface. 1214 */ 1215 void 1216 fxp_stop(ifp, disable) 1217 struct ifnet *ifp; 1218 int disable; 1219 { 1220 struct fxp_softc *sc = ifp->if_softc; 1221 struct fxp_txsoft *txs; 1222 int i; 1223 1224 /* 1225 * Turn down interface (done early to avoid bad interactions 1226 * between panics, shutdown hooks, and the watchdog timer) 1227 */ 1228 ifp->if_timer = 0; 1229 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1230 1231 /* 1232 * Cancel stats updater. 1233 */ 1234 callout_stop(&sc->sc_callout); 1235 if (sc->sc_flags & FXPF_MII) { 1236 /* Down the MII. */ 1237 mii_down(&sc->sc_mii); 1238 } 1239 1240 /* 1241 * Issue software reset 1242 */ 1243 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1244 DELAY(10); 1245 1246 /* 1247 * Release any xmit buffers. 1248 */ 1249 for (i = 0; i < FXP_NTXCB; i++) { 1250 txs = FXP_DSTX(sc, i); 1251 if (txs->txs_mbuf != NULL) { 1252 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1253 m_freem(txs->txs_mbuf); 1254 txs->txs_mbuf = NULL; 1255 } 1256 } 1257 sc->sc_txpending = 0; 1258 1259 if (disable) { 1260 fxp_rxdrain(sc); 1261 fxp_disable(sc); 1262 } 1263 1264 } 1265 1266 /* 1267 * Watchdog/transmission transmit timeout handler. Called when a 1268 * transmission is started on the interface, but no interrupt is 1269 * received before the timeout. This usually indicates that the 1270 * card has wedged for some reason. 1271 */ 1272 void 1273 fxp_watchdog(ifp) 1274 struct ifnet *ifp; 1275 { 1276 struct fxp_softc *sc = ifp->if_softc; 1277 1278 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1279 ifp->if_oerrors++; 1280 1281 (void) fxp_init(ifp); 1282 } 1283 1284 /* 1285 * Initialize the interface. Must be called at splnet(). 1286 */ 1287 int 1288 fxp_init(ifp) 1289 struct ifnet *ifp; 1290 { 1291 struct fxp_softc *sc = ifp->if_softc; 1292 struct fxp_cb_config *cbp; 1293 struct fxp_cb_ias *cb_ias; 1294 struct fxp_cb_tx *txd; 1295 bus_dmamap_t rxmap; 1296 int i, prm, save_bf, allm, error = 0; 1297 1298 if ((error = fxp_enable(sc)) != 0) 1299 goto out; 1300 1301 /* 1302 * Cancel any pending I/O 1303 */ 1304 fxp_stop(ifp, 0); 1305 1306 /* 1307 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1308 * flag, and this prevents the MII from detaching resulting in 1309 * a panic. The flags field should perhaps be split in runtime 1310 * flags and more static information. For now, just clear the 1311 * only other flag set. 1312 */ 1313 1314 sc->sc_flags &= ~FXPF_WANTINIT; 1315 1316 /* 1317 * Initialize base of CBL and RFA memory. Loading with zero 1318 * sets it up for regular linear addressing. 1319 */ 1320 fxp_scb_wait(sc); 1321 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1322 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1323 1324 fxp_scb_wait(sc); 1325 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1326 1327 /* 1328 * Initialize the multicast filter. Do this now, since we might 1329 * have to setup the config block differently. 1330 */ 1331 fxp_mc_setup(sc); 1332 1333 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1334 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1335 1336 /* 1337 * In order to support receiving 802.1Q VLAN frames, we have to 1338 * enable "save bad frames", since they are 4 bytes larger than 1339 * the normal Ethernet maximum frame length. 1340 */ 1341 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1342 1343 /* 1344 * Initialize base of dump-stats buffer. 1345 */ 1346 fxp_scb_wait(sc); 1347 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1348 sc->sc_cddma + FXP_CDSTATSOFF); 1349 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1350 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1351 1352 cbp = &sc->sc_control_data->fcd_configcb; 1353 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1354 1355 /* 1356 * This copy is kind of disgusting, but there are a bunch of must be 1357 * zero and must be one bits in this structure and this is the easiest 1358 * way to initialize them all to proper values. 1359 */ 1360 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1361 1362 /* BIG_ENDIAN: no need to swap to store 0 */ 1363 cbp->cb_status = 0; 1364 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1365 FXP_CB_COMMAND_EL); 1366 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1367 cbp->link_addr = 0xffffffff; /* (no) next command */ 1368 cbp->byte_count = 22; /* (22) bytes to config */ 1369 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1370 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1371 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1372 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1373 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1374 cbp->dma_bce = 0; /* (disable) dma max counters */ 1375 cbp->late_scb = 0; /* (don't) defer SCB update */ 1376 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1377 cbp->ci_int = 1; /* interrupt on CU idle */ 1378 cbp->save_bf = save_bf;/* save bad frames */ 1379 cbp->disc_short_rx = !prm; /* discard short packets */ 1380 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1381 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1382 cbp->nsai = 1; /* (don't) disable source addr insert */ 1383 cbp->preamble_length = 2; /* (7 byte) preamble */ 1384 cbp->loopback = 0; /* (don't) loopback */ 1385 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1386 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1387 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1388 cbp->promiscuous = prm; /* promiscuous mode */ 1389 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1390 cbp->crscdt = 0; /* (CRS only) */ 1391 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1392 cbp->padding = 1; /* (do) pad short tx packets */ 1393 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1394 cbp->force_fdx = 0; /* (don't) force full duplex */ 1395 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1396 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1397 cbp->mc_all = allm; /* accept all multicasts */ 1398 1399 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1400 1401 /* 1402 * Start the config command/DMA. 1403 */ 1404 fxp_scb_wait(sc); 1405 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1406 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1407 /* ...and wait for it to complete. */ 1408 i = 1000; 1409 do { 1410 FXP_CDCONFIGSYNC(sc, 1411 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1412 DELAY(1); 1413 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1414 if (i == 0) { 1415 printf("%s at line %d: dmasync timeout\n", 1416 sc->sc_dev.dv_xname, __LINE__); 1417 return ETIMEDOUT; 1418 } 1419 1420 /* 1421 * Initialize the station address. 1422 */ 1423 cb_ias = &sc->sc_control_data->fcd_iascb; 1424 /* BIG_ENDIAN: no need to swap to store 0 */ 1425 cb_ias->cb_status = 0; 1426 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1427 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1428 cb_ias->link_addr = 0xffffffff; 1429 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1430 1431 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1432 1433 /* 1434 * Start the IAS (Individual Address Setup) command/DMA. 1435 */ 1436 fxp_scb_wait(sc); 1437 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1438 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1439 /* ...and wait for it to complete. */ 1440 i = 1000; 1441 do { 1442 FXP_CDIASSYNC(sc, 1443 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1444 DELAY(1); 1445 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1446 if (i == 0) { 1447 printf("%s at line %d: dmasync timeout\n", 1448 sc->sc_dev.dv_xname, __LINE__); 1449 return ETIMEDOUT; 1450 } 1451 1452 /* 1453 * Initialize the transmit descriptor ring. txlast is initialized 1454 * to the end of the list so that it will wrap around to the first 1455 * descriptor when the first packet is transmitted. 1456 */ 1457 for (i = 0; i < FXP_NTXCB; i++) { 1458 txd = FXP_CDTX(sc, i); 1459 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1460 txd->cb_command = 1461 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1462 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1463 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1464 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1465 } 1466 sc->sc_txpending = 0; 1467 sc->sc_txdirty = 0; 1468 sc->sc_txlast = FXP_NTXCB - 1; 1469 1470 /* 1471 * Initialize the receive buffer list. 1472 */ 1473 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1474 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1475 rxmap = FXP_RXMAP_GET(sc); 1476 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1477 printf("%s: unable to allocate or map rx " 1478 "buffer %d, error = %d\n", 1479 sc->sc_dev.dv_xname, 1480 sc->sc_rxq.ifq_len, error); 1481 /* 1482 * XXX Should attempt to run with fewer receive 1483 * XXX buffers instead of just failing. 1484 */ 1485 FXP_RXMAP_PUT(sc, rxmap); 1486 fxp_rxdrain(sc); 1487 goto out; 1488 } 1489 } 1490 sc->sc_rxidle = 0; 1491 1492 /* 1493 * Give the transmit ring to the chip. We do this by pointing 1494 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1495 * issuing a start command. It will execute the NOP and then 1496 * suspend, pointing at the first descriptor. 1497 */ 1498 fxp_scb_wait(sc); 1499 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1500 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1501 1502 /* 1503 * Initialize receiver buffer area - RFA. 1504 */ 1505 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1506 fxp_scb_wait(sc); 1507 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1508 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1509 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1510 1511 if (sc->sc_flags & FXPF_MII) { 1512 /* 1513 * Set current media. 1514 */ 1515 mii_mediachg(&sc->sc_mii); 1516 } 1517 1518 /* 1519 * ...all done! 1520 */ 1521 ifp->if_flags |= IFF_RUNNING; 1522 ifp->if_flags &= ~IFF_OACTIVE; 1523 1524 /* 1525 * Start the one second timer. 1526 */ 1527 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1528 1529 /* 1530 * Attempt to start output on the interface. 1531 */ 1532 fxp_start(ifp); 1533 1534 out: 1535 if (error) { 1536 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1537 ifp->if_timer = 0; 1538 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1539 } 1540 return (error); 1541 } 1542 1543 /* 1544 * Change media according to request. 1545 */ 1546 int 1547 fxp_mii_mediachange(ifp) 1548 struct ifnet *ifp; 1549 { 1550 struct fxp_softc *sc = ifp->if_softc; 1551 1552 if (ifp->if_flags & IFF_UP) 1553 mii_mediachg(&sc->sc_mii); 1554 return (0); 1555 } 1556 1557 /* 1558 * Notify the world which media we're using. 1559 */ 1560 void 1561 fxp_mii_mediastatus(ifp, ifmr) 1562 struct ifnet *ifp; 1563 struct ifmediareq *ifmr; 1564 { 1565 struct fxp_softc *sc = ifp->if_softc; 1566 1567 if(sc->sc_enabled == 0) { 1568 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1569 ifmr->ifm_status = 0; 1570 return; 1571 } 1572 1573 mii_pollstat(&sc->sc_mii); 1574 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1575 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1576 } 1577 1578 int 1579 fxp_80c24_mediachange(ifp) 1580 struct ifnet *ifp; 1581 { 1582 1583 /* Nothing to do here. */ 1584 return (0); 1585 } 1586 1587 void 1588 fxp_80c24_mediastatus(ifp, ifmr) 1589 struct ifnet *ifp; 1590 struct ifmediareq *ifmr; 1591 { 1592 struct fxp_softc *sc = ifp->if_softc; 1593 1594 /* 1595 * Media is currently-selected media. We cannot determine 1596 * the link status. 1597 */ 1598 ifmr->ifm_status = 0; 1599 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1600 } 1601 1602 /* 1603 * Add a buffer to the end of the RFA buffer list. 1604 * Return 0 if successful, error code on failure. 1605 * 1606 * The RFA struct is stuck at the beginning of mbuf cluster and the 1607 * data pointer is fixed up to point just past it. 1608 */ 1609 int 1610 fxp_add_rfabuf(sc, rxmap, unload) 1611 struct fxp_softc *sc; 1612 bus_dmamap_t rxmap; 1613 int unload; 1614 { 1615 struct mbuf *m; 1616 int error; 1617 1618 MGETHDR(m, M_DONTWAIT, MT_DATA); 1619 if (m == NULL) 1620 return (ENOBUFS); 1621 1622 MCLGET(m, M_DONTWAIT); 1623 if ((m->m_flags & M_EXT) == 0) { 1624 m_freem(m); 1625 return (ENOBUFS); 1626 } 1627 1628 if (unload) 1629 bus_dmamap_unload(sc->sc_dmat, rxmap); 1630 1631 M_SETCTX(m, rxmap); 1632 1633 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1634 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1635 if (error) { 1636 printf("%s: can't load rx DMA map %d, error = %d\n", 1637 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1638 panic("fxp_add_rfabuf"); /* XXX */ 1639 } 1640 1641 FXP_INIT_RFABUF(sc, m); 1642 1643 return (0); 1644 } 1645 1646 volatile int 1647 fxp_mdi_read(self, phy, reg) 1648 struct device *self; 1649 int phy; 1650 int reg; 1651 { 1652 struct fxp_softc *sc = (struct fxp_softc *)self; 1653 int count = 10000; 1654 int value; 1655 1656 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1657 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1658 1659 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1660 && count--) 1661 DELAY(10); 1662 1663 if (count <= 0) 1664 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1665 1666 return (value & 0xffff); 1667 } 1668 1669 void 1670 fxp_statchg(self) 1671 struct device *self; 1672 { 1673 1674 /* Nothing to do. */ 1675 } 1676 1677 void 1678 fxp_mdi_write(self, phy, reg, value) 1679 struct device *self; 1680 int phy; 1681 int reg; 1682 int value; 1683 { 1684 struct fxp_softc *sc = (struct fxp_softc *)self; 1685 int count = 10000; 1686 1687 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1688 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1689 (value & 0xffff)); 1690 1691 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1692 count--) 1693 DELAY(10); 1694 1695 if (count <= 0) 1696 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1697 } 1698 1699 int 1700 fxp_ioctl(ifp, cmd, data) 1701 struct ifnet *ifp; 1702 u_long cmd; 1703 caddr_t data; 1704 { 1705 struct fxp_softc *sc = ifp->if_softc; 1706 struct ifreq *ifr = (struct ifreq *)data; 1707 int s, error; 1708 1709 s = splnet(); 1710 1711 switch (cmd) { 1712 case SIOCSIFMEDIA: 1713 case SIOCGIFMEDIA: 1714 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1715 break; 1716 1717 default: 1718 error = ether_ioctl(ifp, cmd, data); 1719 if (error == ENETRESET) { 1720 if (sc->sc_enabled) { 1721 /* 1722 * Multicast list has changed; set the 1723 * hardware filter accordingly. 1724 */ 1725 if (sc->sc_txpending) { 1726 sc->sc_flags |= FXPF_WANTINIT; 1727 error = 0; 1728 } else 1729 error = fxp_init(ifp); 1730 } else 1731 error = 0; 1732 } 1733 break; 1734 } 1735 1736 /* Try to get more packets going. */ 1737 if (sc->sc_enabled) 1738 fxp_start(ifp); 1739 1740 splx(s); 1741 return (error); 1742 } 1743 1744 /* 1745 * Program the multicast filter. 1746 * 1747 * This function must be called at splnet(). 1748 */ 1749 void 1750 fxp_mc_setup(sc) 1751 struct fxp_softc *sc; 1752 { 1753 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1754 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1755 struct ethercom *ec = &sc->sc_ethercom; 1756 struct ether_multi *enm; 1757 struct ether_multistep step; 1758 int count, nmcasts; 1759 1760 #ifdef DIAGNOSTIC 1761 if (sc->sc_txpending) 1762 panic("fxp_mc_setup: pending transmissions"); 1763 #endif 1764 1765 ifp->if_flags &= ~IFF_ALLMULTI; 1766 1767 /* 1768 * Initialize multicast setup descriptor. 1769 */ 1770 nmcasts = 0; 1771 ETHER_FIRST_MULTI(step, ec, enm); 1772 while (enm != NULL) { 1773 /* 1774 * Check for too many multicast addresses or if we're 1775 * listening to a range. Either way, we simply have 1776 * to accept all multicasts. 1777 */ 1778 if (nmcasts >= MAXMCADDR || 1779 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1780 ETHER_ADDR_LEN) != 0) { 1781 /* 1782 * Callers of this function must do the 1783 * right thing with this. If we're called 1784 * from outside fxp_init(), the caller must 1785 * detect if the state if IFF_ALLMULTI changes. 1786 * If it does, the caller must then call 1787 * fxp_init(), since allmulti is handled by 1788 * the config block. 1789 */ 1790 ifp->if_flags |= IFF_ALLMULTI; 1791 return; 1792 } 1793 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1794 ETHER_ADDR_LEN); 1795 nmcasts++; 1796 ETHER_NEXT_MULTI(step, enm); 1797 } 1798 1799 /* BIG_ENDIAN: no need to swap to store 0 */ 1800 mcsp->cb_status = 0; 1801 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1802 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1803 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1804 1805 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1806 1807 /* 1808 * Wait until the command unit is not active. This should never 1809 * happen since nothing is queued, but make sure anyway. 1810 */ 1811 count = 100; 1812 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1813 FXP_SCB_CUS_ACTIVE && --count) 1814 DELAY(1); 1815 if (count == 0) { 1816 printf("%s at line %d: command queue timeout\n", 1817 sc->sc_dev.dv_xname, __LINE__); 1818 return; 1819 } 1820 1821 /* 1822 * Start the multicast setup command/DMA. 1823 */ 1824 fxp_scb_wait(sc); 1825 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1826 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1827 1828 /* ...and wait for it to complete. */ 1829 count = 1000; 1830 do { 1831 FXP_CDMCSSYNC(sc, 1832 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1833 DELAY(1); 1834 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1835 if (count == 0) { 1836 printf("%s at line %d: dmasync timeout\n", 1837 sc->sc_dev.dv_xname, __LINE__); 1838 return; 1839 } 1840 } 1841 1842 int 1843 fxp_enable(sc) 1844 struct fxp_softc *sc; 1845 { 1846 1847 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1848 if ((*sc->sc_enable)(sc) != 0) { 1849 printf("%s: device enable failed\n", 1850 sc->sc_dev.dv_xname); 1851 return (EIO); 1852 } 1853 } 1854 1855 sc->sc_enabled = 1; 1856 return (0); 1857 } 1858 1859 void 1860 fxp_disable(sc) 1861 struct fxp_softc *sc; 1862 { 1863 1864 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1865 (*sc->sc_disable)(sc); 1866 sc->sc_enabled = 0; 1867 } 1868 } 1869 1870 /* 1871 * fxp_activate: 1872 * 1873 * Handle device activation/deactivation requests. 1874 */ 1875 int 1876 fxp_activate(self, act) 1877 struct device *self; 1878 enum devact act; 1879 { 1880 struct fxp_softc *sc = (void *) self; 1881 int s, error = 0; 1882 1883 s = splnet(); 1884 switch (act) { 1885 case DVACT_ACTIVATE: 1886 error = EOPNOTSUPP; 1887 break; 1888 1889 case DVACT_DEACTIVATE: 1890 if (sc->sc_flags & FXPF_MII) 1891 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1892 MII_OFFSET_ANY); 1893 if_deactivate(&sc->sc_ethercom.ec_if); 1894 break; 1895 } 1896 splx(s); 1897 1898 return (error); 1899 } 1900 1901 /* 1902 * fxp_detach: 1903 * 1904 * Detach an i82557 interface. 1905 */ 1906 int 1907 fxp_detach(sc) 1908 struct fxp_softc *sc; 1909 { 1910 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1911 int i; 1912 1913 /* Succeed now if there's no work to do. */ 1914 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1915 return (0); 1916 1917 /* Unhook our tick handler. */ 1918 callout_stop(&sc->sc_callout); 1919 1920 if (sc->sc_flags & FXPF_MII) { 1921 /* Detach all PHYs */ 1922 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1923 } 1924 1925 /* Delete all remaining media. */ 1926 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1927 1928 #if NRND > 0 1929 rnd_detach_source(&sc->rnd_source); 1930 #endif 1931 #if NBPFILTER > 0 1932 bpfdetach(ifp); 1933 #endif 1934 ether_ifdetach(ifp); 1935 if_detach(ifp); 1936 1937 for (i = 0; i < FXP_NRFABUFS; i++) { 1938 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1939 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1940 } 1941 1942 for (i = 0; i < FXP_NTXCB; i++) { 1943 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1944 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1945 } 1946 1947 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1948 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1949 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1950 sizeof(struct fxp_control_data)); 1951 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1952 1953 shutdownhook_disestablish(sc->sc_sdhook); 1954 powerhook_disestablish(sc->sc_powerhook); 1955 1956 return (0); 1957 } 1958
Indexes created Tue Sep 30 11:09:46 GMT 2025