i82557.c revision 1.41
1 /* $NetBSD: i82557.c,v 1.41 2000/11/15 01:02:16 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <uvm/uvm_extern.h> 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia __P((struct fxp_softc *)); 169 int fxp_mii_mediachange __P((struct ifnet *)); 170 void fxp_mii_mediastatus __P((struct ifnet *, struct ifmediareq *)); 171 172 void fxp_80c24_initmedia __P((struct fxp_softc *)); 173 int fxp_80c24_mediachange __P((struct ifnet *)); 174 void fxp_80c24_mediastatus __P((struct ifnet *, struct ifmediareq *)); 175 176 inline void fxp_scb_wait __P((struct fxp_softc *)); 177 178 void fxp_start __P((struct ifnet *)); 179 int fxp_ioctl __P((struct ifnet *, u_long, caddr_t)); 180 void fxp_watchdog __P((struct ifnet *)); 181 int fxp_init __P((struct ifnet *)); 182 void fxp_stop __P((struct ifnet *, int)); 183 184 void fxp_rxdrain __P((struct fxp_softc *)); 185 int fxp_add_rfabuf __P((struct fxp_softc *, bus_dmamap_t, int)); 186 int fxp_mdi_read __P((struct device *, int, int)); 187 void fxp_statchg __P((struct device *)); 188 void fxp_mdi_write __P((struct device *, int, int, int)); 189 void fxp_autosize_eeprom __P((struct fxp_softc*)); 190 void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *, int, int)); 191 void fxp_get_info __P((struct fxp_softc *, u_int8_t *)); 192 void fxp_tick __P((void *)); 193 void fxp_mc_setup __P((struct fxp_softc *)); 194 195 void fxp_shutdown __P((void *)); 196 void fxp_power __P((int, void *)); 197 198 int fxp_copy_small = 0; 199 200 struct fxp_phytype { 201 int fp_phy; /* type of PHY, -1 for MII at the end. */ 202 void (*fp_init) __P((struct fxp_softc *)); 203 } fxp_phytype_table[] = { 204 { FXP_PHY_80C24, fxp_80c24_initmedia }, 205 { -1, fxp_mii_initmedia }, 206 }; 207 208 /* 209 * Set initial transmit threshold at 64 (512 bytes). This is 210 * increased by 64 (512 bytes) at a time, to maximum of 192 211 * (1536 bytes), if an underrun occurs. 212 */ 213 static int tx_threshold = 64; 214 215 /* 216 * Wait for the previous command to be accepted (but not necessarily 217 * completed). 218 */ 219 inline void 220 fxp_scb_wait(sc) 221 struct fxp_softc *sc; 222 { 223 int i = 10000; 224 225 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 226 delay(2); 227 if (i == 0) 228 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 229 } 230 231 /* 232 * Finish attaching an i82557 interface. Called by bus-specific front-end. 233 */ 234 void 235 fxp_attach(sc) 236 struct fxp_softc *sc; 237 { 238 u_int8_t enaddr[ETHER_ADDR_LEN]; 239 struct ifnet *ifp; 240 bus_dma_segment_t seg; 241 int rseg, i, error; 242 struct fxp_phytype *fp; 243 244 callout_init(&sc->sc_callout); 245 246 /* 247 * Allocate the control data structures, and create and load the 248 * DMA map for it. 249 */ 250 if ((error = bus_dmamem_alloc(sc->sc_dmat, 251 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 252 0)) != 0) { 253 printf("%s: unable to allocate control data, error = %d\n", 254 sc->sc_dev.dv_xname, error); 255 goto fail_0; 256 } 257 258 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 259 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 260 BUS_DMA_COHERENT)) != 0) { 261 printf("%s: unable to map control data, error = %d\n", 262 sc->sc_dev.dv_xname, error); 263 goto fail_1; 264 } 265 sc->sc_cdseg = seg; 266 sc->sc_cdnseg = rseg; 267 268 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 269 270 if ((error = bus_dmamap_create(sc->sc_dmat, 271 sizeof(struct fxp_control_data), 1, 272 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 273 printf("%s: unable to create control data DMA map, " 274 "error = %d\n", sc->sc_dev.dv_xname, error); 275 goto fail_2; 276 } 277 278 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 279 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 280 0)) != 0) { 281 printf("%s: can't load control data DMA map, error = %d\n", 282 sc->sc_dev.dv_xname, error); 283 goto fail_3; 284 } 285 286 /* 287 * Create the transmit buffer DMA maps. 288 */ 289 for (i = 0; i < FXP_NTXCB; i++) { 290 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 291 FXP_NTXSEG, MCLBYTES, 0, 0, 292 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 293 printf("%s: unable to create tx DMA map %d, " 294 "error = %d\n", sc->sc_dev.dv_xname, i, error); 295 goto fail_4; 296 } 297 } 298 299 /* 300 * Create the receive buffer DMA maps. 301 */ 302 for (i = 0; i < FXP_NRFABUFS; i++) { 303 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 304 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 305 printf("%s: unable to create rx DMA map %d, " 306 "error = %d\n", sc->sc_dev.dv_xname, i, error); 307 goto fail_5; 308 } 309 } 310 311 /* Initialize MAC address and media structures. */ 312 fxp_get_info(sc, enaddr); 313 314 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 315 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 316 317 ifp = &sc->sc_ethercom.ec_if; 318 319 /* 320 * Get info about our media interface, and initialize it. Note 321 * the table terminates itself with a phy of -1, indicating 322 * that we're using MII. 323 */ 324 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 325 if (fp->fp_phy == sc->phy_primary_device) 326 break; 327 (*fp->fp_init)(sc); 328 329 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 330 ifp->if_softc = sc; 331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332 ifp->if_ioctl = fxp_ioctl; 333 ifp->if_start = fxp_start; 334 ifp->if_watchdog = fxp_watchdog; 335 ifp->if_init = fxp_init; 336 ifp->if_stop = fxp_stop; 337 338 /* 339 * We can support 802.1Q VLAN-sized frames. 340 */ 341 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 342 343 /* 344 * Attach the interface. 345 */ 346 if_attach(ifp); 347 ether_ifattach(ifp, enaddr); 348 #if NRND > 0 349 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 350 RND_TYPE_NET, 0); 351 #endif 352 353 /* 354 * Add shutdown hook so that DMA is disabled prior to reboot. Not 355 * doing do could allow DMA to corrupt kernel memory during the 356 * reboot before the driver initializes. 357 */ 358 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 359 if (sc->sc_sdhook == NULL) 360 printf("%s: WARNING: unable to establish shutdown hook\n", 361 sc->sc_dev.dv_xname); 362 /* 363 * Add suspend hook, for similar reasons.. 364 */ 365 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 366 if (sc->sc_powerhook == NULL) 367 printf("%s: WARNING: unable to establish power hook\n", 368 sc->sc_dev.dv_xname); 369 370 /* The attach is successful. */ 371 sc->sc_flags |= FXPF_ATTACHED; 372 373 return; 374 375 /* 376 * Free any resources we've allocated during the failed attach 377 * attempt. Do this in reverse order and fall though. 378 */ 379 fail_5: 380 for (i = 0; i < FXP_NRFABUFS; i++) { 381 if (sc->sc_rxmaps[i] != NULL) 382 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 383 } 384 fail_4: 385 for (i = 0; i < FXP_NTXCB; i++) { 386 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 387 bus_dmamap_destroy(sc->sc_dmat, 388 FXP_DSTX(sc, i)->txs_dmamap); 389 } 390 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 391 fail_3: 392 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 393 fail_2: 394 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 395 sizeof(struct fxp_control_data)); 396 fail_1: 397 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 398 fail_0: 399 return; 400 } 401 402 void 403 fxp_mii_initmedia(sc) 404 struct fxp_softc *sc; 405 { 406 407 sc->sc_flags |= FXPF_MII; 408 409 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 410 sc->sc_mii.mii_readreg = fxp_mdi_read; 411 sc->sc_mii.mii_writereg = fxp_mdi_write; 412 sc->sc_mii.mii_statchg = fxp_statchg; 413 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 414 fxp_mii_mediastatus); 415 /* 416 * The i82557 wedges if all of its PHYs are isolated! 417 */ 418 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 419 MII_OFFSET_ANY, MIIF_NOISOLATE); 420 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 421 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 422 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 423 } else 424 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 425 } 426 427 void 428 fxp_80c24_initmedia(sc) 429 struct fxp_softc *sc; 430 { 431 432 /* 433 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 434 * doesn't have a programming interface of any sort. The 435 * media is sensed automatically based on how the link partner 436 * is configured. This is, in essence, manual configuration. 437 */ 438 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 439 sc->sc_dev.dv_xname); 440 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 441 fxp_80c24_mediastatus); 442 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 443 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 444 } 445 446 /* 447 * Device shutdown routine. Called at system shutdown after sync. The 448 * main purpose of this routine is to shut off receiver DMA so that 449 * kernel memory doesn't get clobbered during warmboot. 450 */ 451 void 452 fxp_shutdown(arg) 453 void *arg; 454 { 455 struct fxp_softc *sc = arg; 456 457 /* 458 * Since the system's going to halt shortly, don't bother 459 * freeing mbufs. 460 */ 461 fxp_stop(&sc->sc_ethercom.ec_if, 0); 462 } 463 /* 464 * Power handler routine. Called when the system is transitioning 465 * into/out of power save modes. As with fxp_shutdown, the main 466 * purpose of this routine is to shut off receiver DMA so it doesn't 467 * clobber kernel memory at the wrong time. 468 */ 469 void 470 fxp_power(why, arg) 471 int why; 472 void *arg; 473 { 474 struct fxp_softc *sc = arg; 475 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 476 int s; 477 478 s = splnet(); 479 if (why != PWR_RESUME) 480 fxp_stop(ifp, 0); 481 else { 482 if (ifp->if_flags & IFF_UP) 483 fxp_init(ifp); 484 } 485 splx(s); 486 } 487 488 /* 489 * Initialize the interface media. 490 */ 491 void 492 fxp_get_info(sc, enaddr) 493 struct fxp_softc *sc; 494 u_int8_t *enaddr; 495 { 496 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 497 498 /* 499 * Reset to a stable state. 500 */ 501 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 502 DELAY(10); 503 504 sc->sc_eeprom_size = 0; 505 fxp_autosize_eeprom(sc); 506 if(sc->sc_eeprom_size == 0) { 507 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 508 sc->sc_eeprom_size = 6; /* XXX panic here? */ 509 } 510 #ifdef DEBUG 511 printf("%s: detected %d word EEPROM\n", 512 sc->sc_dev.dv_xname, 513 1 << sc->sc_eeprom_size); 514 #endif 515 516 /* 517 * Get info about the primary PHY 518 */ 519 fxp_read_eeprom(sc, &data, 6, 1); 520 sc->phy_primary_addr = data & 0xff; 521 sc->phy_primary_device = (data >> 8) & 0x3f; 522 sc->phy_10Mbps_only = data >> 15; 523 524 /* 525 * Read MAC address. 526 */ 527 fxp_read_eeprom(sc, myea, 0, 3); 528 enaddr[0] = myea[0] & 0xff; 529 enaddr[1] = myea[0] >> 8; 530 enaddr[2] = myea[1] & 0xff; 531 enaddr[3] = myea[1] >> 8; 532 enaddr[4] = myea[2] & 0xff; 533 enaddr[5] = myea[2] >> 8; 534 } 535 536 /* 537 * Figure out EEPROM size. 538 * 539 * 559's can have either 64-word or 256-word EEPROMs, the 558 540 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 541 * talks about the existance of 16 to 256 word EEPROMs. 542 * 543 * The only known sizes are 64 and 256, where the 256 version is used 544 * by CardBus cards to store CIS information. 545 * 546 * The address is shifted in msb-to-lsb, and after the last 547 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 548 * after which follows the actual data. We try to detect this zero, by 549 * probing the data-out bit in the EEPROM control register just after 550 * having shifted in a bit. If the bit is zero, we assume we've 551 * shifted enough address bits. The data-out should be tri-state, 552 * before this, which should translate to a logical one. 553 * 554 * Other ways to do this would be to try to read a register with known 555 * contents with a varying number of address bits, but no such 556 * register seem to be available. The high bits of register 10 are 01 557 * on the 558 and 559, but apparently not on the 557. 558 * 559 * The Linux driver computes a checksum on the EEPROM data, but the 560 * value of this checksum is not very well documented. 561 */ 562 563 void 564 fxp_autosize_eeprom(sc) 565 struct fxp_softc *sc; 566 { 567 u_int16_t reg; 568 int x; 569 570 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 571 /* 572 * Shift in read opcode. 573 */ 574 for (x = 3; x > 0; x--) { 575 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 576 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 577 } else { 578 reg = FXP_EEPROM_EECS; 579 } 580 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 581 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 582 reg | FXP_EEPROM_EESK); 583 DELAY(4); 584 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 585 DELAY(4); 586 } 587 /* 588 * Shift in address, wait for the dummy zero following a correct 589 * address shift. 590 */ 591 for (x = 1; x <= 8; x++) { 592 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 593 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 594 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 595 DELAY(4); 596 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 597 FXP_EEPROM_EEDO) == 0) 598 break; 599 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 600 DELAY(4); 601 } 602 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 603 DELAY(4); 604 if(x != 6 && x != 8) { 605 #ifdef DEBUG 606 printf("%s: strange EEPROM size (%d)\n", 607 sc->sc_dev.dv_xname, 1 << x); 608 #endif 609 } else 610 sc->sc_eeprom_size = x; 611 } 612 613 /* 614 * Read from the serial EEPROM. Basically, you manually shift in 615 * the read opcode (one bit at a time) and then shift in the address, 616 * and then you shift out the data (all of this one bit at a time). 617 * The word size is 16 bits, so you have to provide the address for 618 * every 16 bits of data. 619 */ 620 void 621 fxp_read_eeprom(sc, data, offset, words) 622 struct fxp_softc *sc; 623 u_int16_t *data; 624 int offset; 625 int words; 626 { 627 u_int16_t reg; 628 int i, x; 629 630 for (i = 0; i < words; i++) { 631 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 632 /* 633 * Shift in read opcode. 634 */ 635 for (x = 3; x > 0; x--) { 636 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 637 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 638 } else { 639 reg = FXP_EEPROM_EECS; 640 } 641 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 642 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 643 reg | FXP_EEPROM_EESK); 644 DELAY(4); 645 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 646 DELAY(4); 647 } 648 /* 649 * Shift in address. 650 */ 651 for (x = sc->sc_eeprom_size; x > 0; x--) { 652 if ((i + offset) & (1 << (x - 1))) { 653 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 654 } else { 655 reg = FXP_EEPROM_EECS; 656 } 657 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 658 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 659 reg | FXP_EEPROM_EESK); 660 DELAY(4); 661 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 662 DELAY(4); 663 } 664 reg = FXP_EEPROM_EECS; 665 data[i] = 0; 666 /* 667 * Shift out data. 668 */ 669 for (x = 16; x > 0; x--) { 670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 671 reg | FXP_EEPROM_EESK); 672 DELAY(4); 673 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 674 FXP_EEPROM_EEDO) 675 data[i] |= (1 << (x - 1)); 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 677 DELAY(4); 678 } 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 680 DELAY(4); 681 } 682 } 683 684 /* 685 * Start packet transmission on the interface. 686 */ 687 void 688 fxp_start(ifp) 689 struct ifnet *ifp; 690 { 691 struct fxp_softc *sc = ifp->if_softc; 692 struct mbuf *m0, *m; 693 struct fxp_cb_tx *txd; 694 struct fxp_txsoft *txs; 695 struct fxp_tbdlist *tbd; 696 bus_dmamap_t dmamap; 697 int error, lasttx, nexttx, opending, seg; 698 699 /* 700 * If we want a re-init, bail out now. 701 */ 702 if (sc->sc_flags & FXPF_WANTINIT) { 703 ifp->if_flags |= IFF_OACTIVE; 704 return; 705 } 706 707 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 708 return; 709 710 /* 711 * Remember the previous txpending and the current lasttx. 712 */ 713 opending = sc->sc_txpending; 714 lasttx = sc->sc_txlast; 715 716 /* 717 * Loop through the send queue, setting up transmit descriptors 718 * until we drain the queue, or use up all available transmit 719 * descriptors. 720 */ 721 while (sc->sc_txpending < FXP_NTXCB) { 722 /* 723 * Grab a packet off the queue. 724 */ 725 IF_DEQUEUE(&ifp->if_snd, m0); 726 if (m0 == NULL) 727 break; 728 729 /* 730 * Get the next available transmit descriptor. 731 */ 732 nexttx = FXP_NEXTTX(sc->sc_txlast); 733 txd = FXP_CDTX(sc, nexttx); 734 tbd = FXP_CDTBD(sc, nexttx); 735 txs = FXP_DSTX(sc, nexttx); 736 dmamap = txs->txs_dmamap; 737 738 /* 739 * Load the DMA map. If this fails, the packet either 740 * didn't fit in the allotted number of frags, or we were 741 * short on resources. In this case, we'll copy and try 742 * again. 743 */ 744 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 745 BUS_DMA_NOWAIT) != 0) { 746 MGETHDR(m, M_DONTWAIT, MT_DATA); 747 if (m == NULL) { 748 printf("%s: unable to allocate Tx mbuf\n", 749 sc->sc_dev.dv_xname); 750 IF_PREPEND(&ifp->if_snd, m0); 751 break; 752 } 753 if (m0->m_pkthdr.len > MHLEN) { 754 MCLGET(m, M_DONTWAIT); 755 if ((m->m_flags & M_EXT) == 0) { 756 printf("%s: unable to allocate Tx " 757 "cluster\n", sc->sc_dev.dv_xname); 758 m_freem(m); 759 IF_PREPEND(&ifp->if_snd, m0); 760 break; 761 } 762 } 763 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 764 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 765 m_freem(m0); 766 m0 = m; 767 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 768 m0, BUS_DMA_NOWAIT); 769 if (error) { 770 printf("%s: unable to load Tx buffer, " 771 "error = %d\n", sc->sc_dev.dv_xname, error); 772 IF_PREPEND(&ifp->if_snd, m0); 773 break; 774 } 775 } 776 777 /* Initialize the fraglist. */ 778 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 779 tbd->tbd_d[seg].tb_addr = 780 htole32(dmamap->dm_segs[seg].ds_addr); 781 tbd->tbd_d[seg].tb_size = 782 htole32(dmamap->dm_segs[seg].ds_len); 783 } 784 785 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 786 787 /* Sync the DMA map. */ 788 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 789 BUS_DMASYNC_PREWRITE); 790 791 /* 792 * Store a pointer to the packet so we can free it later. 793 */ 794 txs->txs_mbuf = m0; 795 796 /* 797 * Initialize the transmit descriptor. 798 */ 799 /* BIG_ENDIAN: no need to swap to store 0 */ 800 txd->cb_status = 0; 801 txd->cb_command = 802 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 803 txd->tx_threshold = tx_threshold; 804 txd->tbd_number = dmamap->dm_nsegs; 805 806 FXP_CDTXSYNC(sc, nexttx, 807 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 808 809 /* Advance the tx pointer. */ 810 sc->sc_txpending++; 811 sc->sc_txlast = nexttx; 812 813 #if NBPFILTER > 0 814 /* 815 * Pass packet to bpf if there is a listener. 816 */ 817 if (ifp->if_bpf) 818 bpf_mtap(ifp->if_bpf, m0); 819 #endif 820 } 821 822 if (sc->sc_txpending == FXP_NTXCB) { 823 /* No more slots; notify upper layer. */ 824 ifp->if_flags |= IFF_OACTIVE; 825 } 826 827 if (sc->sc_txpending != opending) { 828 /* 829 * We enqueued packets. If the transmitter was idle, 830 * reset the txdirty pointer. 831 */ 832 if (opending == 0) 833 sc->sc_txdirty = FXP_NEXTTX(lasttx); 834 835 /* 836 * Cause the chip to interrupt and suspend command 837 * processing once the last packet we've enqueued 838 * has been transmitted. 839 */ 840 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 841 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 842 FXP_CDTXSYNC(sc, sc->sc_txlast, 843 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 844 845 /* 846 * The entire packet chain is set up. Clear the suspend bit 847 * on the command prior to the first packet we set up. 848 */ 849 FXP_CDTXSYNC(sc, lasttx, 850 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 851 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 852 FXP_CDTXSYNC(sc, lasttx, 853 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 854 855 /* 856 * Issue a Resume command in case the chip was suspended. 857 */ 858 fxp_scb_wait(sc); 859 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 860 861 /* Set a watchdog timer in case the chip flakes out. */ 862 ifp->if_timer = 5; 863 } 864 } 865 866 /* 867 * Process interface interrupts. 868 */ 869 int 870 fxp_intr(arg) 871 void *arg; 872 { 873 struct fxp_softc *sc = arg; 874 struct ethercom *ec = &sc->sc_ethercom; 875 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 876 struct fxp_cb_tx *txd; 877 struct fxp_txsoft *txs; 878 struct mbuf *m, *m0; 879 bus_dmamap_t rxmap; 880 struct fxp_rfa *rfa; 881 int i, claimed = 0; 882 u_int16_t len, rxstat, txstat; 883 u_int8_t statack; 884 885 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 886 return (0); 887 /* 888 * If the interface isn't running, don't try to 889 * service the interrupt.. just ack it and bail. 890 */ 891 if ((ifp->if_flags & IFF_RUNNING) == 0) { 892 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 893 if (statack) { 894 claimed = 1; 895 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 896 } 897 return (claimed); 898 } 899 900 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 901 claimed = 1; 902 903 /* 904 * First ACK all the interrupts in this pass. 905 */ 906 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 907 908 /* 909 * Process receiver interrupts. If a no-resource (RNR) 910 * condition exists, get whatever packets we can and 911 * re-start the receiver. 912 */ 913 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 914 rcvloop: 915 m = sc->sc_rxq.ifq_head; 916 rfa = FXP_MTORFA(m); 917 rxmap = M_GETCTX(m, bus_dmamap_t); 918 919 FXP_RFASYNC(sc, m, 920 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 921 922 rxstat = le16toh(rfa->rfa_status); 923 924 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 925 /* 926 * We have processed all of the 927 * receive buffers. 928 */ 929 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 930 goto do_transmit; 931 } 932 933 IF_DEQUEUE(&sc->sc_rxq, m); 934 935 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 936 937 len = le16toh(rfa->actual_size) & 938 (m->m_ext.ext_size - 1); 939 940 if (len < sizeof(struct ether_header)) { 941 /* 942 * Runt packet; drop it now. 943 */ 944 FXP_INIT_RFABUF(sc, m); 945 goto rcvloop; 946 } 947 948 /* 949 * If support for 802.1Q VLAN sized frames is 950 * enabled, we need to do some additional error 951 * checking (as we are saving bad frames, in 952 * order to receive the larger ones). 953 */ 954 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 955 (rxstat & (FXP_RFA_STATUS_OVERRUN| 956 FXP_RFA_STATUS_RNR| 957 FXP_RFA_STATUS_ALIGN| 958 FXP_RFA_STATUS_CRC)) != 0) { 959 FXP_INIT_RFABUF(sc, m); 960 goto rcvloop; 961 } 962 963 /* 964 * If the packet is small enough to fit in a 965 * single header mbuf, allocate one and copy 966 * the data into it. This greatly reduces 967 * memory consumption when we receive lots 968 * of small packets. 969 * 970 * Otherwise, we add a new buffer to the receive 971 * chain. If this fails, we drop the packet and 972 * recycle the old buffer. 973 */ 974 if (fxp_copy_small != 0 && len <= MHLEN) { 975 MGETHDR(m0, M_DONTWAIT, MT_DATA); 976 if (m == NULL) 977 goto dropit; 978 memcpy(mtod(m0, caddr_t), 979 mtod(m, caddr_t), len); 980 FXP_INIT_RFABUF(sc, m); 981 m = m0; 982 } else { 983 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 984 dropit: 985 ifp->if_ierrors++; 986 FXP_INIT_RFABUF(sc, m); 987 goto rcvloop; 988 } 989 } 990 991 m->m_pkthdr.rcvif = ifp; 992 m->m_pkthdr.len = m->m_len = len; 993 994 #if NBPFILTER > 0 995 /* 996 * Pass this up to any BPF listeners, but only 997 * pass it up the stack it its for us. 998 */ 999 if (ifp->if_bpf) 1000 bpf_mtap(ifp->if_bpf, m); 1001 #endif 1002 1003 /* Pass it on. */ 1004 (*ifp->if_input)(ifp, m); 1005 goto rcvloop; 1006 } 1007 1008 do_transmit: 1009 if (statack & FXP_SCB_STATACK_RNR) { 1010 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1011 fxp_scb_wait(sc); 1012 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1013 rxmap->dm_segs[0].ds_addr + 1014 RFA_ALIGNMENT_FUDGE); 1015 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1016 FXP_SCB_COMMAND_RU_START); 1017 } 1018 1019 /* 1020 * Free any finished transmit mbuf chains. 1021 */ 1022 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1023 ifp->if_flags &= ~IFF_OACTIVE; 1024 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1025 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1026 txd = FXP_CDTX(sc, i); 1027 txs = FXP_DSTX(sc, i); 1028 1029 FXP_CDTXSYNC(sc, i, 1030 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1031 1032 txstat = le16toh(txd->cb_status); 1033 1034 if ((txstat & FXP_CB_STATUS_C) == 0) 1035 break; 1036 1037 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1038 1039 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1040 0, txs->txs_dmamap->dm_mapsize, 1041 BUS_DMASYNC_POSTWRITE); 1042 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1043 m_freem(txs->txs_mbuf); 1044 txs->txs_mbuf = NULL; 1045 } 1046 1047 /* Update the dirty transmit buffer pointer. */ 1048 sc->sc_txdirty = i; 1049 1050 /* 1051 * Cancel the watchdog timer if there are no pending 1052 * transmissions. 1053 */ 1054 if (sc->sc_txpending == 0) { 1055 ifp->if_timer = 0; 1056 1057 /* 1058 * If we want a re-init, do that now. 1059 */ 1060 if (sc->sc_flags & FXPF_WANTINIT) 1061 (void) fxp_init(ifp); 1062 } 1063 1064 /* 1065 * Try to get more packets going. 1066 */ 1067 fxp_start(ifp); 1068 } 1069 } 1070 1071 #if NRND > 0 1072 if (claimed) 1073 rnd_add_uint32(&sc->rnd_source, statack); 1074 #endif 1075 return (claimed); 1076 } 1077 1078 /* 1079 * Update packet in/out/collision statistics. The i82557 doesn't 1080 * allow you to access these counters without doing a fairly 1081 * expensive DMA to get _all_ of the statistics it maintains, so 1082 * we do this operation here only once per second. The statistics 1083 * counters in the kernel are updated from the previous dump-stats 1084 * DMA and then a new dump-stats DMA is started. The on-chip 1085 * counters are zeroed when the DMA completes. If we can't start 1086 * the DMA immediately, we don't wait - we just prepare to read 1087 * them again next time. 1088 */ 1089 void 1090 fxp_tick(arg) 1091 void *arg; 1092 { 1093 struct fxp_softc *sc = arg; 1094 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1095 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1096 int s; 1097 1098 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1099 return; 1100 1101 s = splnet(); 1102 1103 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1104 1105 ifp->if_opackets += le32toh(sp->tx_good); 1106 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1107 if (sp->rx_good) { 1108 ifp->if_ipackets += le32toh(sp->rx_good); 1109 sc->sc_rxidle = 0; 1110 } else { 1111 sc->sc_rxidle++; 1112 } 1113 ifp->if_ierrors += 1114 le32toh(sp->rx_crc_errors) + 1115 le32toh(sp->rx_alignment_errors) + 1116 le32toh(sp->rx_rnr_errors) + 1117 le32toh(sp->rx_overrun_errors); 1118 /* 1119 * If any transmit underruns occured, bump up the transmit 1120 * threshold by another 512 bytes (64 * 8). 1121 */ 1122 if (sp->tx_underruns) { 1123 ifp->if_oerrors += le32toh(sp->tx_underruns); 1124 if (tx_threshold < 192) 1125 tx_threshold += 64; 1126 } 1127 1128 /* 1129 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1130 * then assume the receiver has locked up and attempt to clear 1131 * the condition by reprogramming the multicast filter (actually, 1132 * resetting the interface). This is a work-around for a bug in 1133 * the 82557 where the receiver locks up if it gets certain types 1134 * of garbage in the syncronization bits prior to the packet header. 1135 * This bug is supposed to only occur in 10Mbps mode, but has been 1136 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1137 * speed transition). 1138 */ 1139 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1140 (void) fxp_init(ifp); 1141 splx(s); 1142 return; 1143 } 1144 /* 1145 * If there is no pending command, start another stats 1146 * dump. Otherwise punt for now. 1147 */ 1148 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1149 /* 1150 * Start another stats dump. 1151 */ 1152 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1153 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1154 FXP_SCB_COMMAND_CU_DUMPRESET); 1155 } else { 1156 /* 1157 * A previous command is still waiting to be accepted. 1158 * Just zero our copy of the stats and wait for the 1159 * next timer event to update them. 1160 */ 1161 /* BIG_ENDIAN: no swap required to store 0 */ 1162 sp->tx_good = 0; 1163 sp->tx_underruns = 0; 1164 sp->tx_total_collisions = 0; 1165 1166 sp->rx_good = 0; 1167 sp->rx_crc_errors = 0; 1168 sp->rx_alignment_errors = 0; 1169 sp->rx_rnr_errors = 0; 1170 sp->rx_overrun_errors = 0; 1171 } 1172 1173 if (sc->sc_flags & FXPF_MII) { 1174 /* Tick the MII clock. */ 1175 mii_tick(&sc->sc_mii); 1176 } 1177 1178 splx(s); 1179 1180 /* 1181 * Schedule another timeout one second from now. 1182 */ 1183 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1184 } 1185 1186 /* 1187 * Drain the receive queue. 1188 */ 1189 void 1190 fxp_rxdrain(sc) 1191 struct fxp_softc *sc; 1192 { 1193 bus_dmamap_t rxmap; 1194 struct mbuf *m; 1195 1196 for (;;) { 1197 IF_DEQUEUE(&sc->sc_rxq, m); 1198 if (m == NULL) 1199 break; 1200 rxmap = M_GETCTX(m, bus_dmamap_t); 1201 bus_dmamap_unload(sc->sc_dmat, rxmap); 1202 FXP_RXMAP_PUT(sc, rxmap); 1203 m_freem(m); 1204 } 1205 } 1206 1207 /* 1208 * Stop the interface. Cancels the statistics updater and resets 1209 * the interface. 1210 */ 1211 void 1212 fxp_stop(ifp, disable) 1213 struct ifnet *ifp; 1214 int disable; 1215 { 1216 struct fxp_softc *sc = ifp->if_softc; 1217 struct fxp_txsoft *txs; 1218 int i; 1219 1220 /* 1221 * Turn down interface (done early to avoid bad interactions 1222 * between panics, shutdown hooks, and the watchdog timer) 1223 */ 1224 ifp->if_timer = 0; 1225 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1226 1227 /* 1228 * Cancel stats updater. 1229 */ 1230 callout_stop(&sc->sc_callout); 1231 if (sc->sc_flags & FXPF_MII) { 1232 /* Down the MII. */ 1233 mii_down(&sc->sc_mii); 1234 } 1235 1236 /* 1237 * Issue software reset 1238 */ 1239 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1240 DELAY(10); 1241 1242 /* 1243 * Release any xmit buffers. 1244 */ 1245 for (i = 0; i < FXP_NTXCB; i++) { 1246 txs = FXP_DSTX(sc, i); 1247 if (txs->txs_mbuf != NULL) { 1248 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1249 m_freem(txs->txs_mbuf); 1250 txs->txs_mbuf = NULL; 1251 } 1252 } 1253 sc->sc_txpending = 0; 1254 1255 if (disable) { 1256 fxp_rxdrain(sc); 1257 fxp_disable(sc); 1258 } 1259 1260 } 1261 1262 /* 1263 * Watchdog/transmission transmit timeout handler. Called when a 1264 * transmission is started on the interface, but no interrupt is 1265 * received before the timeout. This usually indicates that the 1266 * card has wedged for some reason. 1267 */ 1268 void 1269 fxp_watchdog(ifp) 1270 struct ifnet *ifp; 1271 { 1272 struct fxp_softc *sc = ifp->if_softc; 1273 1274 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1275 ifp->if_oerrors++; 1276 1277 (void) fxp_init(ifp); 1278 } 1279 1280 /* 1281 * Initialize the interface. Must be called at splnet(). 1282 */ 1283 int 1284 fxp_init(ifp) 1285 struct ifnet *ifp; 1286 { 1287 struct fxp_softc *sc = ifp->if_softc; 1288 struct fxp_cb_config *cbp; 1289 struct fxp_cb_ias *cb_ias; 1290 struct fxp_cb_tx *txd; 1291 bus_dmamap_t rxmap; 1292 int i, prm, save_bf, allm, error = 0; 1293 1294 if ((error = fxp_enable(sc)) != 0) 1295 goto out; 1296 1297 /* 1298 * Cancel any pending I/O 1299 */ 1300 fxp_stop(ifp, 0); 1301 1302 /* 1303 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1304 * flag, and this prevents the MII from detaching resulting in 1305 * a panic. The flags field should perhaps be split in runtime 1306 * flags and more static information. For now, just clear the 1307 * only other flag set. 1308 */ 1309 1310 sc->sc_flags &= ~FXPF_WANTINIT; 1311 1312 /* 1313 * Initialize base of CBL and RFA memory. Loading with zero 1314 * sets it up for regular linear addressing. 1315 */ 1316 fxp_scb_wait(sc); 1317 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1319 1320 fxp_scb_wait(sc); 1321 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1322 1323 /* 1324 * Initialize the multicast filter. Do this now, since we might 1325 * have to setup the config block differently. 1326 */ 1327 fxp_mc_setup(sc); 1328 1329 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1330 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1331 1332 /* 1333 * In order to support receiving 802.1Q VLAN frames, we have to 1334 * enable "save bad frames", since they are 4 bytes larger than 1335 * the normal Ethernet maximum frame length. 1336 */ 1337 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1338 1339 /* 1340 * Initialize base of dump-stats buffer. 1341 */ 1342 fxp_scb_wait(sc); 1343 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1344 sc->sc_cddma + FXP_CDSTATSOFF); 1345 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1346 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1347 1348 cbp = &sc->sc_control_data->fcd_configcb; 1349 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1350 1351 /* 1352 * This copy is kind of disgusting, but there are a bunch of must be 1353 * zero and must be one bits in this structure and this is the easiest 1354 * way to initialize them all to proper values. 1355 */ 1356 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1357 1358 /* BIG_ENDIAN: no need to swap to store 0 */ 1359 cbp->cb_status = 0; 1360 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1361 FXP_CB_COMMAND_EL); 1362 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1363 cbp->link_addr = 0xffffffff; /* (no) next command */ 1364 cbp->byte_count = 22; /* (22) bytes to config */ 1365 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1366 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1367 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1368 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1369 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1370 cbp->dma_bce = 0; /* (disable) dma max counters */ 1371 cbp->late_scb = 0; /* (don't) defer SCB update */ 1372 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1373 cbp->ci_int = 1; /* interrupt on CU idle */ 1374 cbp->save_bf = save_bf;/* save bad frames */ 1375 cbp->disc_short_rx = !prm; /* discard short packets */ 1376 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1377 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1378 cbp->nsai = 1; /* (don't) disable source addr insert */ 1379 cbp->preamble_length = 2; /* (7 byte) preamble */ 1380 cbp->loopback = 0; /* (don't) loopback */ 1381 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1382 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1383 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1384 cbp->promiscuous = prm; /* promiscuous mode */ 1385 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1386 cbp->crscdt = 0; /* (CRS only) */ 1387 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1388 cbp->padding = 1; /* (do) pad short tx packets */ 1389 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1390 cbp->force_fdx = 0; /* (don't) force full duplex */ 1391 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1392 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1393 cbp->mc_all = allm; /* accept all multicasts */ 1394 1395 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1396 1397 /* 1398 * Start the config command/DMA. 1399 */ 1400 fxp_scb_wait(sc); 1401 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1402 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1403 /* ...and wait for it to complete. */ 1404 i = 1000; 1405 do { 1406 FXP_CDCONFIGSYNC(sc, 1407 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1408 DELAY(1); 1409 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1410 if (i == 0) { 1411 printf("%s at line %d: dmasync timeout\n", 1412 sc->sc_dev.dv_xname, __LINE__); 1413 return ETIMEDOUT; 1414 } 1415 1416 /* 1417 * Initialize the station address. 1418 */ 1419 cb_ias = &sc->sc_control_data->fcd_iascb; 1420 /* BIG_ENDIAN: no need to swap to store 0 */ 1421 cb_ias->cb_status = 0; 1422 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1423 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1424 cb_ias->link_addr = 0xffffffff; 1425 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1426 1427 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1428 1429 /* 1430 * Start the IAS (Individual Address Setup) command/DMA. 1431 */ 1432 fxp_scb_wait(sc); 1433 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1434 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1435 /* ...and wait for it to complete. */ 1436 i = 1000; 1437 do { 1438 FXP_CDIASSYNC(sc, 1439 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1440 DELAY(1); 1441 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1442 if (i == 0) { 1443 printf("%s at line %d: dmasync timeout\n", 1444 sc->sc_dev.dv_xname, __LINE__); 1445 return ETIMEDOUT; 1446 } 1447 1448 /* 1449 * Initialize the transmit descriptor ring. txlast is initialized 1450 * to the end of the list so that it will wrap around to the first 1451 * descriptor when the first packet is transmitted. 1452 */ 1453 for (i = 0; i < FXP_NTXCB; i++) { 1454 txd = FXP_CDTX(sc, i); 1455 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1456 txd->cb_command = 1457 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1458 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1459 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1460 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1461 } 1462 sc->sc_txpending = 0; 1463 sc->sc_txdirty = 0; 1464 sc->sc_txlast = FXP_NTXCB - 1; 1465 1466 /* 1467 * Initialize the receive buffer list. 1468 */ 1469 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1470 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1471 rxmap = FXP_RXMAP_GET(sc); 1472 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1473 printf("%s: unable to allocate or map rx " 1474 "buffer %d, error = %d\n", 1475 sc->sc_dev.dv_xname, 1476 sc->sc_rxq.ifq_len, error); 1477 /* 1478 * XXX Should attempt to run with fewer receive 1479 * XXX buffers instead of just failing. 1480 */ 1481 FXP_RXMAP_PUT(sc, rxmap); 1482 fxp_rxdrain(sc); 1483 goto out; 1484 } 1485 } 1486 sc->sc_rxidle = 0; 1487 1488 /* 1489 * Give the transmit ring to the chip. We do this by pointing 1490 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1491 * issuing a start command. It will execute the NOP and then 1492 * suspend, pointing at the first descriptor. 1493 */ 1494 fxp_scb_wait(sc); 1495 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1496 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1497 1498 /* 1499 * Initialize receiver buffer area - RFA. 1500 */ 1501 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1502 fxp_scb_wait(sc); 1503 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1504 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1505 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1506 1507 if (sc->sc_flags & FXPF_MII) { 1508 /* 1509 * Set current media. 1510 */ 1511 mii_mediachg(&sc->sc_mii); 1512 } 1513 1514 /* 1515 * ...all done! 1516 */ 1517 ifp->if_flags |= IFF_RUNNING; 1518 ifp->if_flags &= ~IFF_OACTIVE; 1519 1520 /* 1521 * Start the one second timer. 1522 */ 1523 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1524 1525 /* 1526 * Attempt to start output on the interface. 1527 */ 1528 fxp_start(ifp); 1529 1530 out: 1531 if (error) { 1532 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1533 ifp->if_timer = 0; 1534 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1535 } 1536 return (error); 1537 } 1538 1539 /* 1540 * Change media according to request. 1541 */ 1542 int 1543 fxp_mii_mediachange(ifp) 1544 struct ifnet *ifp; 1545 { 1546 struct fxp_softc *sc = ifp->if_softc; 1547 1548 if (ifp->if_flags & IFF_UP) 1549 mii_mediachg(&sc->sc_mii); 1550 return (0); 1551 } 1552 1553 /* 1554 * Notify the world which media we're using. 1555 */ 1556 void 1557 fxp_mii_mediastatus(ifp, ifmr) 1558 struct ifnet *ifp; 1559 struct ifmediareq *ifmr; 1560 { 1561 struct fxp_softc *sc = ifp->if_softc; 1562 1563 if(sc->sc_enabled == 0) { 1564 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1565 ifmr->ifm_status = 0; 1566 return; 1567 } 1568 1569 mii_pollstat(&sc->sc_mii); 1570 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1571 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1572 } 1573 1574 int 1575 fxp_80c24_mediachange(ifp) 1576 struct ifnet *ifp; 1577 { 1578 1579 /* Nothing to do here. */ 1580 return (0); 1581 } 1582 1583 void 1584 fxp_80c24_mediastatus(ifp, ifmr) 1585 struct ifnet *ifp; 1586 struct ifmediareq *ifmr; 1587 { 1588 struct fxp_softc *sc = ifp->if_softc; 1589 1590 /* 1591 * Media is currently-selected media. We cannot determine 1592 * the link status. 1593 */ 1594 ifmr->ifm_status = 0; 1595 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1596 } 1597 1598 /* 1599 * Add a buffer to the end of the RFA buffer list. 1600 * Return 0 if successful, error code on failure. 1601 * 1602 * The RFA struct is stuck at the beginning of mbuf cluster and the 1603 * data pointer is fixed up to point just past it. 1604 */ 1605 int 1606 fxp_add_rfabuf(sc, rxmap, unload) 1607 struct fxp_softc *sc; 1608 bus_dmamap_t rxmap; 1609 int unload; 1610 { 1611 struct mbuf *m; 1612 int error; 1613 1614 MGETHDR(m, M_DONTWAIT, MT_DATA); 1615 if (m == NULL) 1616 return (ENOBUFS); 1617 1618 MCLGET(m, M_DONTWAIT); 1619 if ((m->m_flags & M_EXT) == 0) { 1620 m_freem(m); 1621 return (ENOBUFS); 1622 } 1623 1624 if (unload) 1625 bus_dmamap_unload(sc->sc_dmat, rxmap); 1626 1627 M_SETCTX(m, rxmap); 1628 1629 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1630 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1631 if (error) { 1632 printf("%s: can't load rx DMA map %d, error = %d\n", 1633 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1634 panic("fxp_add_rfabuf"); /* XXX */ 1635 } 1636 1637 FXP_INIT_RFABUF(sc, m); 1638 1639 return (0); 1640 } 1641 1642 volatile int 1643 fxp_mdi_read(self, phy, reg) 1644 struct device *self; 1645 int phy; 1646 int reg; 1647 { 1648 struct fxp_softc *sc = (struct fxp_softc *)self; 1649 int count = 10000; 1650 int value; 1651 1652 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1653 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1654 1655 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1656 && count--) 1657 DELAY(10); 1658 1659 if (count <= 0) 1660 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1661 1662 return (value & 0xffff); 1663 } 1664 1665 void 1666 fxp_statchg(self) 1667 struct device *self; 1668 { 1669 1670 /* Nothing to do. */ 1671 } 1672 1673 void 1674 fxp_mdi_write(self, phy, reg, value) 1675 struct device *self; 1676 int phy; 1677 int reg; 1678 int value; 1679 { 1680 struct fxp_softc *sc = (struct fxp_softc *)self; 1681 int count = 10000; 1682 1683 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1684 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1685 (value & 0xffff)); 1686 1687 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1688 count--) 1689 DELAY(10); 1690 1691 if (count <= 0) 1692 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1693 } 1694 1695 int 1696 fxp_ioctl(ifp, cmd, data) 1697 struct ifnet *ifp; 1698 u_long cmd; 1699 caddr_t data; 1700 { 1701 struct fxp_softc *sc = ifp->if_softc; 1702 struct ifreq *ifr = (struct ifreq *)data; 1703 int s, error; 1704 1705 s = splnet(); 1706 1707 switch (cmd) { 1708 case SIOCSIFMEDIA: 1709 case SIOCGIFMEDIA: 1710 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1711 break; 1712 1713 default: 1714 error = ether_ioctl(ifp, cmd, data); 1715 if (error == ENETRESET) { 1716 if (sc->sc_enabled) { 1717 /* 1718 * Multicast list has changed; set the 1719 * hardware filter accordingly. 1720 */ 1721 if (sc->sc_txpending) { 1722 sc->sc_flags |= FXPF_WANTINIT; 1723 error = 0; 1724 } else 1725 error = fxp_init(ifp); 1726 } else 1727 error = 0; 1728 } 1729 break; 1730 } 1731 1732 /* Try to get more packets going. */ 1733 if (sc->sc_enabled) 1734 fxp_start(ifp); 1735 1736 splx(s); 1737 return (error); 1738 } 1739 1740 /* 1741 * Program the multicast filter. 1742 * 1743 * This function must be called at splnet(). 1744 */ 1745 void 1746 fxp_mc_setup(sc) 1747 struct fxp_softc *sc; 1748 { 1749 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1750 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1751 struct ethercom *ec = &sc->sc_ethercom; 1752 struct ether_multi *enm; 1753 struct ether_multistep step; 1754 int count, nmcasts; 1755 1756 #ifdef DIAGNOSTIC 1757 if (sc->sc_txpending) 1758 panic("fxp_mc_setup: pending transmissions"); 1759 #endif 1760 1761 ifp->if_flags &= ~IFF_ALLMULTI; 1762 1763 /* 1764 * Initialize multicast setup descriptor. 1765 */ 1766 nmcasts = 0; 1767 ETHER_FIRST_MULTI(step, ec, enm); 1768 while (enm != NULL) { 1769 /* 1770 * Check for too many multicast addresses or if we're 1771 * listening to a range. Either way, we simply have 1772 * to accept all multicasts. 1773 */ 1774 if (nmcasts >= MAXMCADDR || 1775 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1776 ETHER_ADDR_LEN) != 0) { 1777 /* 1778 * Callers of this function must do the 1779 * right thing with this. If we're called 1780 * from outside fxp_init(), the caller must 1781 * detect if the state if IFF_ALLMULTI changes. 1782 * If it does, the caller must then call 1783 * fxp_init(), since allmulti is handled by 1784 * the config block. 1785 */ 1786 ifp->if_flags |= IFF_ALLMULTI; 1787 return; 1788 } 1789 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1790 ETHER_ADDR_LEN); 1791 nmcasts++; 1792 ETHER_NEXT_MULTI(step, enm); 1793 } 1794 1795 /* BIG_ENDIAN: no need to swap to store 0 */ 1796 mcsp->cb_status = 0; 1797 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1798 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1799 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1800 1801 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1802 1803 /* 1804 * Wait until the command unit is not active. This should never 1805 * happen since nothing is queued, but make sure anyway. 1806 */ 1807 count = 100; 1808 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1809 FXP_SCB_CUS_ACTIVE && --count) 1810 DELAY(1); 1811 if (count == 0) { 1812 printf("%s at line %d: command queue timeout\n", 1813 sc->sc_dev.dv_xname, __LINE__); 1814 return; 1815 } 1816 1817 /* 1818 * Start the multicast setup command/DMA. 1819 */ 1820 fxp_scb_wait(sc); 1821 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1822 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1823 1824 /* ...and wait for it to complete. */ 1825 count = 1000; 1826 do { 1827 FXP_CDMCSSYNC(sc, 1828 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1829 DELAY(1); 1830 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1831 if (count == 0) { 1832 printf("%s at line %d: dmasync timeout\n", 1833 sc->sc_dev.dv_xname, __LINE__); 1834 return; 1835 } 1836 } 1837 1838 int 1839 fxp_enable(sc) 1840 struct fxp_softc *sc; 1841 { 1842 1843 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1844 if ((*sc->sc_enable)(sc) != 0) { 1845 printf("%s: device enable failed\n", 1846 sc->sc_dev.dv_xname); 1847 return (EIO); 1848 } 1849 } 1850 1851 sc->sc_enabled = 1; 1852 return (0); 1853 } 1854 1855 void 1856 fxp_disable(sc) 1857 struct fxp_softc *sc; 1858 { 1859 1860 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1861 (*sc->sc_disable)(sc); 1862 sc->sc_enabled = 0; 1863 } 1864 } 1865 1866 /* 1867 * fxp_activate: 1868 * 1869 * Handle device activation/deactivation requests. 1870 */ 1871 int 1872 fxp_activate(self, act) 1873 struct device *self; 1874 enum devact act; 1875 { 1876 struct fxp_softc *sc = (void *) self; 1877 int s, error = 0; 1878 1879 s = splnet(); 1880 switch (act) { 1881 case DVACT_ACTIVATE: 1882 error = EOPNOTSUPP; 1883 break; 1884 1885 case DVACT_DEACTIVATE: 1886 if (sc->sc_flags & FXPF_MII) 1887 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1888 MII_OFFSET_ANY); 1889 if_deactivate(&sc->sc_ethercom.ec_if); 1890 break; 1891 } 1892 splx(s); 1893 1894 return (error); 1895 } 1896 1897 /* 1898 * fxp_detach: 1899 * 1900 * Detach an i82557 interface. 1901 */ 1902 int 1903 fxp_detach(sc) 1904 struct fxp_softc *sc; 1905 { 1906 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1907 int i; 1908 1909 /* Succeed now if there's no work to do. */ 1910 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1911 return (0); 1912 1913 /* Unhook our tick handler. */ 1914 callout_stop(&sc->sc_callout); 1915 1916 if (sc->sc_flags & FXPF_MII) { 1917 /* Detach all PHYs */ 1918 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1919 } 1920 1921 /* Delete all remaining media. */ 1922 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1923 1924 #if NRND > 0 1925 rnd_detach_source(&sc->rnd_source); 1926 #endif 1927 ether_ifdetach(ifp); 1928 if_detach(ifp); 1929 1930 for (i = 0; i < FXP_NRFABUFS; i++) { 1931 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1932 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1933 } 1934 1935 for (i = 0; i < FXP_NTXCB; i++) { 1936 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1937 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1938 } 1939 1940 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1941 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1942 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1943 sizeof(struct fxp_control_data)); 1944 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1945 1946 shutdownhook_disestablish(sc->sc_sdhook); 1947 powerhook_disestablish(sc->sc_powerhook); 1948 1949 return (0); 1950 } 1951
Indexes created Wed Oct 29 01:09:52 GMT 2025