i82557.c revision 1.46
1 /* $NetBSD: i82557.c,v 1.46 2001/05/21 20:59:38 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <uvm/uvm_extern.h> 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia(struct fxp_softc *); 169 int fxp_mii_mediachange(struct ifnet *); 170 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 171 172 void fxp_80c24_initmedia(struct fxp_softc *); 173 int fxp_80c24_mediachange(struct ifnet *); 174 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 175 176 void fxp_start(struct ifnet *); 177 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 178 void fxp_watchdog(struct ifnet *); 179 int fxp_init(struct ifnet *); 180 void fxp_stop(struct ifnet *, int); 181 182 void fxp_rxdrain(struct fxp_softc *); 183 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 184 int fxp_mdi_read(struct device *, int, int); 185 void fxp_statchg(struct device *); 186 void fxp_mdi_write(struct device *, int, int, int); 187 void fxp_autosize_eeprom(struct fxp_softc*); 188 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 189 void fxp_get_info(struct fxp_softc *, u_int8_t *); 190 void fxp_tick(void *); 191 void fxp_mc_setup(struct fxp_softc *); 192 193 void fxp_shutdown(void *); 194 void fxp_power(int, void *); 195 196 int fxp_copy_small = 0; 197 198 struct fxp_phytype { 199 int fp_phy; /* type of PHY, -1 for MII at the end. */ 200 void (*fp_init)(struct fxp_softc *); 201 } fxp_phytype_table[] = { 202 { FXP_PHY_80C24, fxp_80c24_initmedia }, 203 { -1, fxp_mii_initmedia }, 204 }; 205 206 /* 207 * Set initial transmit threshold at 64 (512 bytes). This is 208 * increased by 64 (512 bytes) at a time, to maximum of 192 209 * (1536 bytes), if an underrun occurs. 210 */ 211 static int tx_threshold = 64; 212 213 /* 214 * Wait for the previous command to be accepted (but not necessarily 215 * completed). 216 */ 217 static __inline void 218 fxp_scb_wait(struct fxp_softc *sc) 219 { 220 int i = 10000; 221 222 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 223 delay(2); 224 if (i == 0) 225 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 226 } 227 228 /* 229 * Finish attaching an i82557 interface. Called by bus-specific front-end. 230 */ 231 void 232 fxp_attach(struct fxp_softc *sc) 233 { 234 u_int8_t enaddr[ETHER_ADDR_LEN]; 235 struct ifnet *ifp; 236 bus_dma_segment_t seg; 237 int rseg, i, error; 238 struct fxp_phytype *fp; 239 240 callout_init(&sc->sc_callout); 241 242 /* 243 * Allocate the control data structures, and create and load the 244 * DMA map for it. 245 */ 246 if ((error = bus_dmamem_alloc(sc->sc_dmat, 247 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 248 0)) != 0) { 249 printf("%s: unable to allocate control data, error = %d\n", 250 sc->sc_dev.dv_xname, error); 251 goto fail_0; 252 } 253 254 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 255 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 256 BUS_DMA_COHERENT)) != 0) { 257 printf("%s: unable to map control data, error = %d\n", 258 sc->sc_dev.dv_xname, error); 259 goto fail_1; 260 } 261 sc->sc_cdseg = seg; 262 sc->sc_cdnseg = rseg; 263 264 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 265 266 if ((error = bus_dmamap_create(sc->sc_dmat, 267 sizeof(struct fxp_control_data), 1, 268 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 269 printf("%s: unable to create control data DMA map, " 270 "error = %d\n", sc->sc_dev.dv_xname, error); 271 goto fail_2; 272 } 273 274 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 275 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 276 0)) != 0) { 277 printf("%s: can't load control data DMA map, error = %d\n", 278 sc->sc_dev.dv_xname, error); 279 goto fail_3; 280 } 281 282 /* 283 * Create the transmit buffer DMA maps. 284 */ 285 for (i = 0; i < FXP_NTXCB; i++) { 286 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 287 FXP_NTXSEG, MCLBYTES, 0, 0, 288 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 289 printf("%s: unable to create tx DMA map %d, " 290 "error = %d\n", sc->sc_dev.dv_xname, i, error); 291 goto fail_4; 292 } 293 } 294 295 /* 296 * Create the receive buffer DMA maps. 297 */ 298 for (i = 0; i < FXP_NRFABUFS; i++) { 299 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 300 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 301 printf("%s: unable to create rx DMA map %d, " 302 "error = %d\n", sc->sc_dev.dv_xname, i, error); 303 goto fail_5; 304 } 305 } 306 307 /* Initialize MAC address and media structures. */ 308 fxp_get_info(sc, enaddr); 309 310 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 311 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 312 313 ifp = &sc->sc_ethercom.ec_if; 314 315 /* 316 * Get info about our media interface, and initialize it. Note 317 * the table terminates itself with a phy of -1, indicating 318 * that we're using MII. 319 */ 320 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 321 if (fp->fp_phy == sc->phy_primary_device) 322 break; 323 (*fp->fp_init)(sc); 324 325 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 326 ifp->if_softc = sc; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 ifp->if_ioctl = fxp_ioctl; 329 ifp->if_start = fxp_start; 330 ifp->if_watchdog = fxp_watchdog; 331 ifp->if_init = fxp_init; 332 ifp->if_stop = fxp_stop; 333 IFQ_SET_READY(&ifp->if_snd); 334 335 /* 336 * We can support 802.1Q VLAN-sized frames. 337 */ 338 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 339 340 /* 341 * Attach the interface. 342 */ 343 if_attach(ifp); 344 ether_ifattach(ifp, enaddr); 345 #if NRND > 0 346 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 347 RND_TYPE_NET, 0); 348 #endif 349 350 /* 351 * Add shutdown hook so that DMA is disabled prior to reboot. Not 352 * doing do could allow DMA to corrupt kernel memory during the 353 * reboot before the driver initializes. 354 */ 355 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 356 if (sc->sc_sdhook == NULL) 357 printf("%s: WARNING: unable to establish shutdown hook\n", 358 sc->sc_dev.dv_xname); 359 /* 360 * Add suspend hook, for similar reasons.. 361 */ 362 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 363 if (sc->sc_powerhook == NULL) 364 printf("%s: WARNING: unable to establish power hook\n", 365 sc->sc_dev.dv_xname); 366 367 /* The attach is successful. */ 368 sc->sc_flags |= FXPF_ATTACHED; 369 370 return; 371 372 /* 373 * Free any resources we've allocated during the failed attach 374 * attempt. Do this in reverse order and fall though. 375 */ 376 fail_5: 377 for (i = 0; i < FXP_NRFABUFS; i++) { 378 if (sc->sc_rxmaps[i] != NULL) 379 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 380 } 381 fail_4: 382 for (i = 0; i < FXP_NTXCB; i++) { 383 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 384 bus_dmamap_destroy(sc->sc_dmat, 385 FXP_DSTX(sc, i)->txs_dmamap); 386 } 387 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 388 fail_3: 389 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 390 fail_2: 391 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 392 sizeof(struct fxp_control_data)); 393 fail_1: 394 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 395 fail_0: 396 return; 397 } 398 399 void 400 fxp_mii_initmedia(struct fxp_softc *sc) 401 { 402 403 sc->sc_flags |= FXPF_MII; 404 405 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 406 sc->sc_mii.mii_readreg = fxp_mdi_read; 407 sc->sc_mii.mii_writereg = fxp_mdi_write; 408 sc->sc_mii.mii_statchg = fxp_statchg; 409 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 410 fxp_mii_mediastatus); 411 /* 412 * The i82557 wedges if all of its PHYs are isolated! 413 */ 414 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 415 MII_OFFSET_ANY, MIIF_NOISOLATE); 416 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 417 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 418 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 419 } else 420 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 421 } 422 423 void 424 fxp_80c24_initmedia(struct fxp_softc *sc) 425 { 426 427 /* 428 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 429 * doesn't have a programming interface of any sort. The 430 * media is sensed automatically based on how the link partner 431 * is configured. This is, in essence, manual configuration. 432 */ 433 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 434 sc->sc_dev.dv_xname); 435 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 436 fxp_80c24_mediastatus); 437 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 438 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 439 } 440 441 /* 442 * Device shutdown routine. Called at system shutdown after sync. The 443 * main purpose of this routine is to shut off receiver DMA so that 444 * kernel memory doesn't get clobbered during warmboot. 445 */ 446 void 447 fxp_shutdown(void *arg) 448 { 449 struct fxp_softc *sc = arg; 450 451 /* 452 * Since the system's going to halt shortly, don't bother 453 * freeing mbufs. 454 */ 455 fxp_stop(&sc->sc_ethercom.ec_if, 0); 456 } 457 /* 458 * Power handler routine. Called when the system is transitioning 459 * into/out of power save modes. As with fxp_shutdown, the main 460 * purpose of this routine is to shut off receiver DMA so it doesn't 461 * clobber kernel memory at the wrong time. 462 */ 463 void 464 fxp_power(int why, void *arg) 465 { 466 struct fxp_softc *sc = arg; 467 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 468 int s; 469 470 s = splnet(); 471 switch (why) { 472 case PWR_SUSPEND: 473 case PWR_STANDBY: 474 fxp_stop(ifp, 0); 475 break; 476 case PWR_RESUME: 477 if (ifp->if_flags & IFF_UP) 478 fxp_init(ifp); 479 break; 480 case PWR_SOFTSUSPEND: 481 case PWR_SOFTSTANDBY: 482 case PWR_SOFTRESUME: 483 break; 484 } 485 splx(s); 486 } 487 488 /* 489 * Initialize the interface media. 490 */ 491 void 492 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 493 { 494 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 495 496 /* 497 * Reset to a stable state. 498 */ 499 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 500 DELAY(10); 501 502 sc->sc_eeprom_size = 0; 503 fxp_autosize_eeprom(sc); 504 if(sc->sc_eeprom_size == 0) { 505 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 506 sc->sc_eeprom_size = 6; /* XXX panic here? */ 507 } 508 #ifdef DEBUG 509 printf("%s: detected %d word EEPROM\n", 510 sc->sc_dev.dv_xname, 511 1 << sc->sc_eeprom_size); 512 #endif 513 514 /* 515 * Get info about the primary PHY 516 */ 517 fxp_read_eeprom(sc, &data, 6, 1); 518 sc->phy_primary_addr = data & 0xff; 519 sc->phy_primary_device = (data >> 8) & 0x3f; 520 sc->phy_10Mbps_only = data >> 15; 521 522 /* 523 * Read MAC address. 524 */ 525 fxp_read_eeprom(sc, myea, 0, 3); 526 enaddr[0] = myea[0] & 0xff; 527 enaddr[1] = myea[0] >> 8; 528 enaddr[2] = myea[1] & 0xff; 529 enaddr[3] = myea[1] >> 8; 530 enaddr[4] = myea[2] & 0xff; 531 enaddr[5] = myea[2] >> 8; 532 } 533 534 /* 535 * Figure out EEPROM size. 536 * 537 * 559's can have either 64-word or 256-word EEPROMs, the 558 538 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 539 * talks about the existance of 16 to 256 word EEPROMs. 540 * 541 * The only known sizes are 64 and 256, where the 256 version is used 542 * by CardBus cards to store CIS information. 543 * 544 * The address is shifted in msb-to-lsb, and after the last 545 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 546 * after which follows the actual data. We try to detect this zero, by 547 * probing the data-out bit in the EEPROM control register just after 548 * having shifted in a bit. If the bit is zero, we assume we've 549 * shifted enough address bits. The data-out should be tri-state, 550 * before this, which should translate to a logical one. 551 * 552 * Other ways to do this would be to try to read a register with known 553 * contents with a varying number of address bits, but no such 554 * register seem to be available. The high bits of register 10 are 01 555 * on the 558 and 559, but apparently not on the 557. 556 * 557 * The Linux driver computes a checksum on the EEPROM data, but the 558 * value of this checksum is not very well documented. 559 */ 560 561 void 562 fxp_autosize_eeprom(struct fxp_softc *sc) 563 { 564 u_int16_t reg; 565 int x; 566 567 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 568 /* 569 * Shift in read opcode. 570 */ 571 for (x = 3; x > 0; x--) { 572 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 573 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 574 } else { 575 reg = FXP_EEPROM_EECS; 576 } 577 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 578 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 579 reg | FXP_EEPROM_EESK); 580 DELAY(4); 581 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 582 DELAY(4); 583 } 584 /* 585 * Shift in address, wait for the dummy zero following a correct 586 * address shift. 587 */ 588 for (x = 1; x <= 8; x++) { 589 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 590 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 591 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 592 DELAY(4); 593 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 594 FXP_EEPROM_EEDO) == 0) 595 break; 596 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 597 DELAY(4); 598 } 599 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 600 DELAY(4); 601 if(x != 6 && x != 8) { 602 #ifdef DEBUG 603 printf("%s: strange EEPROM size (%d)\n", 604 sc->sc_dev.dv_xname, 1 << x); 605 #endif 606 } else 607 sc->sc_eeprom_size = x; 608 } 609 610 /* 611 * Read from the serial EEPROM. Basically, you manually shift in 612 * the read opcode (one bit at a time) and then shift in the address, 613 * and then you shift out the data (all of this one bit at a time). 614 * The word size is 16 bits, so you have to provide the address for 615 * every 16 bits of data. 616 */ 617 void 618 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 619 { 620 u_int16_t reg; 621 int i, x; 622 623 for (i = 0; i < words; i++) { 624 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 625 /* 626 * Shift in read opcode. 627 */ 628 for (x = 3; x > 0; x--) { 629 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 630 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 631 } else { 632 reg = FXP_EEPROM_EECS; 633 } 634 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 635 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 636 reg | FXP_EEPROM_EESK); 637 DELAY(4); 638 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 639 DELAY(4); 640 } 641 /* 642 * Shift in address. 643 */ 644 for (x = sc->sc_eeprom_size; x > 0; x--) { 645 if ((i + offset) & (1 << (x - 1))) { 646 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 647 } else { 648 reg = FXP_EEPROM_EECS; 649 } 650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 652 reg | FXP_EEPROM_EESK); 653 DELAY(4); 654 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 655 DELAY(4); 656 } 657 reg = FXP_EEPROM_EECS; 658 data[i] = 0; 659 /* 660 * Shift out data. 661 */ 662 for (x = 16; x > 0; x--) { 663 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 664 reg | FXP_EEPROM_EESK); 665 DELAY(4); 666 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 667 FXP_EEPROM_EEDO) 668 data[i] |= (1 << (x - 1)); 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 670 DELAY(4); 671 } 672 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 673 DELAY(4); 674 } 675 } 676 677 /* 678 * Start packet transmission on the interface. 679 */ 680 void 681 fxp_start(struct ifnet *ifp) 682 { 683 struct fxp_softc *sc = ifp->if_softc; 684 struct mbuf *m0, *m; 685 struct fxp_cb_tx *txd; 686 struct fxp_txsoft *txs; 687 struct fxp_tbdlist *tbd; 688 bus_dmamap_t dmamap; 689 int error, lasttx, nexttx, opending, seg; 690 691 /* 692 * If we want a re-init, bail out now. 693 */ 694 if (sc->sc_flags & FXPF_WANTINIT) { 695 ifp->if_flags |= IFF_OACTIVE; 696 return; 697 } 698 699 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 700 return; 701 702 /* 703 * Remember the previous txpending and the current lasttx. 704 */ 705 opending = sc->sc_txpending; 706 lasttx = sc->sc_txlast; 707 708 /* 709 * Loop through the send queue, setting up transmit descriptors 710 * until we drain the queue, or use up all available transmit 711 * descriptors. 712 */ 713 while (sc->sc_txpending < FXP_NTXCB) { 714 /* 715 * Grab a packet off the queue. 716 */ 717 IFQ_POLL(&ifp->if_snd, m0); 718 if (m0 == NULL) 719 break; 720 m = NULL; 721 722 /* 723 * Get the next available transmit descriptor. 724 */ 725 nexttx = FXP_NEXTTX(sc->sc_txlast); 726 txd = FXP_CDTX(sc, nexttx); 727 tbd = FXP_CDTBD(sc, nexttx); 728 txs = FXP_DSTX(sc, nexttx); 729 dmamap = txs->txs_dmamap; 730 731 /* 732 * Load the DMA map. If this fails, the packet either 733 * didn't fit in the allotted number of frags, or we were 734 * short on resources. In this case, we'll copy and try 735 * again. 736 */ 737 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 738 BUS_DMA_NOWAIT) != 0) { 739 MGETHDR(m, M_DONTWAIT, MT_DATA); 740 if (m == NULL) { 741 printf("%s: unable to allocate Tx mbuf\n", 742 sc->sc_dev.dv_xname); 743 break; 744 } 745 if (m0->m_pkthdr.len > MHLEN) { 746 MCLGET(m, M_DONTWAIT); 747 if ((m->m_flags & M_EXT) == 0) { 748 printf("%s: unable to allocate Tx " 749 "cluster\n", sc->sc_dev.dv_xname); 750 m_freem(m); 751 break; 752 } 753 } 754 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 755 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 756 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 757 m, BUS_DMA_NOWAIT); 758 if (error) { 759 printf("%s: unable to load Tx buffer, " 760 "error = %d\n", sc->sc_dev.dv_xname, error); 761 break; 762 } 763 } 764 765 IFQ_DEQUEUE(&ifp->if_snd, m0); 766 if (m != NULL) { 767 m_freem(m0); 768 m0 = m; 769 } 770 771 /* Initialize the fraglist. */ 772 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 773 tbd->tbd_d[seg].tb_addr = 774 htole32(dmamap->dm_segs[seg].ds_addr); 775 tbd->tbd_d[seg].tb_size = 776 htole32(dmamap->dm_segs[seg].ds_len); 777 } 778 779 FXP_CDTBDSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 780 781 /* Sync the DMA map. */ 782 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 783 BUS_DMASYNC_PREWRITE); 784 785 /* 786 * Store a pointer to the packet so we can free it later. 787 */ 788 txs->txs_mbuf = m0; 789 790 /* 791 * Initialize the transmit descriptor. 792 */ 793 /* BIG_ENDIAN: no need to swap to store 0 */ 794 txd->cb_status = 0; 795 txd->cb_command = 796 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 797 txd->tx_threshold = tx_threshold; 798 txd->tbd_number = dmamap->dm_nsegs; 799 800 FXP_CDTXSYNC(sc, nexttx, 801 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 802 803 /* Advance the tx pointer. */ 804 sc->sc_txpending++; 805 sc->sc_txlast = nexttx; 806 807 #if NBPFILTER > 0 808 /* 809 * Pass packet to bpf if there is a listener. 810 */ 811 if (ifp->if_bpf) 812 bpf_mtap(ifp->if_bpf, m0); 813 #endif 814 } 815 816 if (sc->sc_txpending == FXP_NTXCB) { 817 /* No more slots; notify upper layer. */ 818 ifp->if_flags |= IFF_OACTIVE; 819 } 820 821 if (sc->sc_txpending != opending) { 822 /* 823 * We enqueued packets. If the transmitter was idle, 824 * reset the txdirty pointer. 825 */ 826 if (opending == 0) 827 sc->sc_txdirty = FXP_NEXTTX(lasttx); 828 829 /* 830 * Cause the chip to interrupt and suspend command 831 * processing once the last packet we've enqueued 832 * has been transmitted. 833 */ 834 FXP_CDTX(sc, sc->sc_txlast)->cb_command |= 835 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 836 FXP_CDTXSYNC(sc, sc->sc_txlast, 837 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 838 839 /* 840 * The entire packet chain is set up. Clear the suspend bit 841 * on the command prior to the first packet we set up. 842 */ 843 FXP_CDTXSYNC(sc, lasttx, 844 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 845 FXP_CDTX(sc, lasttx)->cb_command &= htole16(~FXP_CB_COMMAND_S); 846 FXP_CDTXSYNC(sc, lasttx, 847 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 848 849 /* 850 * Issue a Resume command in case the chip was suspended. 851 */ 852 fxp_scb_wait(sc); 853 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME); 854 855 /* Set a watchdog timer in case the chip flakes out. */ 856 ifp->if_timer = 5; 857 } 858 } 859 860 /* 861 * Process interface interrupts. 862 */ 863 int 864 fxp_intr(void *arg) 865 { 866 struct fxp_softc *sc = arg; 867 struct ethercom *ec = &sc->sc_ethercom; 868 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 869 struct fxp_cb_tx *txd; 870 struct fxp_txsoft *txs; 871 struct mbuf *m, *m0; 872 bus_dmamap_t rxmap; 873 struct fxp_rfa *rfa; 874 int i, claimed = 0; 875 u_int16_t len, rxstat, txstat; 876 u_int8_t statack; 877 878 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 879 return (0); 880 /* 881 * If the interface isn't running, don't try to 882 * service the interrupt.. just ack it and bail. 883 */ 884 if ((ifp->if_flags & IFF_RUNNING) == 0) { 885 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 886 if (statack) { 887 claimed = 1; 888 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 889 } 890 return (claimed); 891 } 892 893 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 894 claimed = 1; 895 896 /* 897 * First ACK all the interrupts in this pass. 898 */ 899 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 900 901 /* 902 * Process receiver interrupts. If a no-resource (RNR) 903 * condition exists, get whatever packets we can and 904 * re-start the receiver. 905 */ 906 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 907 rcvloop: 908 m = sc->sc_rxq.ifq_head; 909 rfa = FXP_MTORFA(m); 910 rxmap = M_GETCTX(m, bus_dmamap_t); 911 912 FXP_RFASYNC(sc, m, 913 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 914 915 rxstat = le16toh(rfa->rfa_status); 916 917 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 918 /* 919 * We have processed all of the 920 * receive buffers. 921 */ 922 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 923 goto do_transmit; 924 } 925 926 IF_DEQUEUE(&sc->sc_rxq, m); 927 928 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 929 930 len = le16toh(rfa->actual_size) & 931 (m->m_ext.ext_size - 1); 932 933 if (len < sizeof(struct ether_header)) { 934 /* 935 * Runt packet; drop it now. 936 */ 937 FXP_INIT_RFABUF(sc, m); 938 goto rcvloop; 939 } 940 941 /* 942 * If support for 802.1Q VLAN sized frames is 943 * enabled, we need to do some additional error 944 * checking (as we are saving bad frames, in 945 * order to receive the larger ones). 946 */ 947 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 948 (rxstat & (FXP_RFA_STATUS_OVERRUN| 949 FXP_RFA_STATUS_RNR| 950 FXP_RFA_STATUS_ALIGN| 951 FXP_RFA_STATUS_CRC)) != 0) { 952 FXP_INIT_RFABUF(sc, m); 953 goto rcvloop; 954 } 955 956 /* 957 * If the packet is small enough to fit in a 958 * single header mbuf, allocate one and copy 959 * the data into it. This greatly reduces 960 * memory consumption when we receive lots 961 * of small packets. 962 * 963 * Otherwise, we add a new buffer to the receive 964 * chain. If this fails, we drop the packet and 965 * recycle the old buffer. 966 */ 967 if (fxp_copy_small != 0 && len <= MHLEN) { 968 MGETHDR(m0, M_DONTWAIT, MT_DATA); 969 if (m == NULL) 970 goto dropit; 971 memcpy(mtod(m0, caddr_t), 972 mtod(m, caddr_t), len); 973 FXP_INIT_RFABUF(sc, m); 974 m = m0; 975 } else { 976 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 977 dropit: 978 ifp->if_ierrors++; 979 FXP_INIT_RFABUF(sc, m); 980 goto rcvloop; 981 } 982 } 983 984 m->m_pkthdr.rcvif = ifp; 985 m->m_pkthdr.len = m->m_len = len; 986 987 #if NBPFILTER > 0 988 /* 989 * Pass this up to any BPF listeners, but only 990 * pass it up the stack it its for us. 991 */ 992 if (ifp->if_bpf) 993 bpf_mtap(ifp->if_bpf, m); 994 #endif 995 996 /* Pass it on. */ 997 (*ifp->if_input)(ifp, m); 998 goto rcvloop; 999 } 1000 1001 do_transmit: 1002 if (statack & FXP_SCB_STATACK_RNR) { 1003 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1004 fxp_scb_wait(sc); 1005 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1006 rxmap->dm_segs[0].ds_addr + 1007 RFA_ALIGNMENT_FUDGE); 1008 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1009 FXP_SCB_COMMAND_RU_START); 1010 } 1011 1012 /* 1013 * Free any finished transmit mbuf chains. 1014 */ 1015 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1016 ifp->if_flags &= ~IFF_OACTIVE; 1017 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1018 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1019 txd = FXP_CDTX(sc, i); 1020 txs = FXP_DSTX(sc, i); 1021 1022 FXP_CDTXSYNC(sc, i, 1023 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1024 1025 txstat = le16toh(txd->cb_status); 1026 1027 if ((txstat & FXP_CB_STATUS_C) == 0) 1028 break; 1029 1030 FXP_CDTBDSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 1031 1032 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1033 0, txs->txs_dmamap->dm_mapsize, 1034 BUS_DMASYNC_POSTWRITE); 1035 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1036 m_freem(txs->txs_mbuf); 1037 txs->txs_mbuf = NULL; 1038 } 1039 1040 /* Update the dirty transmit buffer pointer. */ 1041 sc->sc_txdirty = i; 1042 1043 /* 1044 * Cancel the watchdog timer if there are no pending 1045 * transmissions. 1046 */ 1047 if (sc->sc_txpending == 0) { 1048 ifp->if_timer = 0; 1049 1050 /* 1051 * If we want a re-init, do that now. 1052 */ 1053 if (sc->sc_flags & FXPF_WANTINIT) 1054 (void) fxp_init(ifp); 1055 } 1056 1057 /* 1058 * Try to get more packets going. 1059 */ 1060 fxp_start(ifp); 1061 } 1062 } 1063 1064 #if NRND > 0 1065 if (claimed) 1066 rnd_add_uint32(&sc->rnd_source, statack); 1067 #endif 1068 return (claimed); 1069 } 1070 1071 /* 1072 * Update packet in/out/collision statistics. The i82557 doesn't 1073 * allow you to access these counters without doing a fairly 1074 * expensive DMA to get _all_ of the statistics it maintains, so 1075 * we do this operation here only once per second. The statistics 1076 * counters in the kernel are updated from the previous dump-stats 1077 * DMA and then a new dump-stats DMA is started. The on-chip 1078 * counters are zeroed when the DMA completes. If we can't start 1079 * the DMA immediately, we don't wait - we just prepare to read 1080 * them again next time. 1081 */ 1082 void 1083 fxp_tick(void *arg) 1084 { 1085 struct fxp_softc *sc = arg; 1086 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1087 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1088 int s; 1089 1090 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1091 return; 1092 1093 s = splnet(); 1094 1095 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1096 1097 ifp->if_opackets += le32toh(sp->tx_good); 1098 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1099 if (sp->rx_good) { 1100 ifp->if_ipackets += le32toh(sp->rx_good); 1101 sc->sc_rxidle = 0; 1102 } else { 1103 sc->sc_rxidle++; 1104 } 1105 ifp->if_ierrors += 1106 le32toh(sp->rx_crc_errors) + 1107 le32toh(sp->rx_alignment_errors) + 1108 le32toh(sp->rx_rnr_errors) + 1109 le32toh(sp->rx_overrun_errors); 1110 /* 1111 * If any transmit underruns occured, bump up the transmit 1112 * threshold by another 512 bytes (64 * 8). 1113 */ 1114 if (sp->tx_underruns) { 1115 ifp->if_oerrors += le32toh(sp->tx_underruns); 1116 if (tx_threshold < 192) 1117 tx_threshold += 64; 1118 } 1119 1120 /* 1121 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1122 * then assume the receiver has locked up and attempt to clear 1123 * the condition by reprogramming the multicast filter (actually, 1124 * resetting the interface). This is a work-around for a bug in 1125 * the 82557 where the receiver locks up if it gets certain types 1126 * of garbage in the syncronization bits prior to the packet header. 1127 * This bug is supposed to only occur in 10Mbps mode, but has been 1128 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1129 * speed transition). 1130 */ 1131 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1132 (void) fxp_init(ifp); 1133 splx(s); 1134 return; 1135 } 1136 /* 1137 * If there is no pending command, start another stats 1138 * dump. Otherwise punt for now. 1139 */ 1140 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1141 /* 1142 * Start another stats dump. 1143 */ 1144 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1145 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, 1146 FXP_SCB_COMMAND_CU_DUMPRESET); 1147 } else { 1148 /* 1149 * A previous command is still waiting to be accepted. 1150 * Just zero our copy of the stats and wait for the 1151 * next timer event to update them. 1152 */ 1153 /* BIG_ENDIAN: no swap required to store 0 */ 1154 sp->tx_good = 0; 1155 sp->tx_underruns = 0; 1156 sp->tx_total_collisions = 0; 1157 1158 sp->rx_good = 0; 1159 sp->rx_crc_errors = 0; 1160 sp->rx_alignment_errors = 0; 1161 sp->rx_rnr_errors = 0; 1162 sp->rx_overrun_errors = 0; 1163 } 1164 1165 if (sc->sc_flags & FXPF_MII) { 1166 /* Tick the MII clock. */ 1167 mii_tick(&sc->sc_mii); 1168 } 1169 1170 splx(s); 1171 1172 /* 1173 * Schedule another timeout one second from now. 1174 */ 1175 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1176 } 1177 1178 /* 1179 * Drain the receive queue. 1180 */ 1181 void 1182 fxp_rxdrain(struct fxp_softc *sc) 1183 { 1184 bus_dmamap_t rxmap; 1185 struct mbuf *m; 1186 1187 for (;;) { 1188 IF_DEQUEUE(&sc->sc_rxq, m); 1189 if (m == NULL) 1190 break; 1191 rxmap = M_GETCTX(m, bus_dmamap_t); 1192 bus_dmamap_unload(sc->sc_dmat, rxmap); 1193 FXP_RXMAP_PUT(sc, rxmap); 1194 m_freem(m); 1195 } 1196 } 1197 1198 /* 1199 * Stop the interface. Cancels the statistics updater and resets 1200 * the interface. 1201 */ 1202 void 1203 fxp_stop(struct ifnet *ifp, int disable) 1204 { 1205 struct fxp_softc *sc = ifp->if_softc; 1206 struct fxp_txsoft *txs; 1207 int i; 1208 1209 /* 1210 * Turn down interface (done early to avoid bad interactions 1211 * between panics, shutdown hooks, and the watchdog timer) 1212 */ 1213 ifp->if_timer = 0; 1214 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1215 1216 /* 1217 * Cancel stats updater. 1218 */ 1219 callout_stop(&sc->sc_callout); 1220 if (sc->sc_flags & FXPF_MII) { 1221 /* Down the MII. */ 1222 mii_down(&sc->sc_mii); 1223 } 1224 1225 /* 1226 * Issue software reset 1227 */ 1228 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1229 DELAY(10); 1230 1231 /* 1232 * Release any xmit buffers. 1233 */ 1234 for (i = 0; i < FXP_NTXCB; i++) { 1235 txs = FXP_DSTX(sc, i); 1236 if (txs->txs_mbuf != NULL) { 1237 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1238 m_freem(txs->txs_mbuf); 1239 txs->txs_mbuf = NULL; 1240 } 1241 } 1242 sc->sc_txpending = 0; 1243 1244 if (disable) { 1245 fxp_rxdrain(sc); 1246 fxp_disable(sc); 1247 } 1248 1249 } 1250 1251 /* 1252 * Watchdog/transmission transmit timeout handler. Called when a 1253 * transmission is started on the interface, but no interrupt is 1254 * received before the timeout. This usually indicates that the 1255 * card has wedged for some reason. 1256 */ 1257 void 1258 fxp_watchdog(struct ifnet *ifp) 1259 { 1260 struct fxp_softc *sc = ifp->if_softc; 1261 1262 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1263 ifp->if_oerrors++; 1264 1265 (void) fxp_init(ifp); 1266 } 1267 1268 /* 1269 * Initialize the interface. Must be called at splnet(). 1270 */ 1271 int 1272 fxp_init(struct ifnet *ifp) 1273 { 1274 struct fxp_softc *sc = ifp->if_softc; 1275 struct fxp_cb_config *cbp; 1276 struct fxp_cb_ias *cb_ias; 1277 struct fxp_cb_tx *txd; 1278 bus_dmamap_t rxmap; 1279 int i, prm, save_bf, allm, error = 0; 1280 1281 if ((error = fxp_enable(sc)) != 0) 1282 goto out; 1283 1284 /* 1285 * Cancel any pending I/O 1286 */ 1287 fxp_stop(ifp, 0); 1288 1289 /* 1290 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1291 * flag, and this prevents the MII from detaching resulting in 1292 * a panic. The flags field should perhaps be split in runtime 1293 * flags and more static information. For now, just clear the 1294 * only other flag set. 1295 */ 1296 1297 sc->sc_flags &= ~FXPF_WANTINIT; 1298 1299 /* 1300 * Initialize base of CBL and RFA memory. Loading with zero 1301 * sets it up for regular linear addressing. 1302 */ 1303 fxp_scb_wait(sc); 1304 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1305 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE); 1306 1307 fxp_scb_wait(sc); 1308 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE); 1309 1310 /* 1311 * Initialize the multicast filter. Do this now, since we might 1312 * have to setup the config block differently. 1313 */ 1314 fxp_mc_setup(sc); 1315 1316 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1317 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1318 1319 /* 1320 * In order to support receiving 802.1Q VLAN frames, we have to 1321 * enable "save bad frames", since they are 4 bytes larger than 1322 * the normal Ethernet maximum frame length. 1323 */ 1324 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1325 1326 /* 1327 * Initialize base of dump-stats buffer. 1328 */ 1329 fxp_scb_wait(sc); 1330 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1331 sc->sc_cddma + FXP_CDSTATSOFF); 1332 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1333 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR); 1334 1335 cbp = &sc->sc_control_data->fcd_configcb; 1336 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1337 1338 /* 1339 * This copy is kind of disgusting, but there are a bunch of must be 1340 * zero and must be one bits in this structure and this is the easiest 1341 * way to initialize them all to proper values. 1342 */ 1343 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1344 1345 /* BIG_ENDIAN: no need to swap to store 0 */ 1346 cbp->cb_status = 0; 1347 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1348 FXP_CB_COMMAND_EL); 1349 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1350 cbp->link_addr = 0xffffffff; /* (no) next command */ 1351 cbp->byte_count = 22; /* (22) bytes to config */ 1352 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1353 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1354 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1355 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1356 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1357 cbp->dma_bce = 0; /* (disable) dma max counters */ 1358 cbp->late_scb = 0; /* (don't) defer SCB update */ 1359 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1360 cbp->ci_int = 1; /* interrupt on CU idle */ 1361 cbp->save_bf = save_bf;/* save bad frames */ 1362 cbp->disc_short_rx = !prm; /* discard short packets */ 1363 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1364 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1365 cbp->nsai = 1; /* (don't) disable source addr insert */ 1366 cbp->preamble_length = 2; /* (7 byte) preamble */ 1367 cbp->loopback = 0; /* (don't) loopback */ 1368 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1369 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1370 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1371 cbp->promiscuous = prm; /* promiscuous mode */ 1372 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1373 cbp->crscdt = 0; /* (CRS only) */ 1374 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1375 cbp->padding = 1; /* (do) pad short tx packets */ 1376 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1377 cbp->force_fdx = 0; /* (don't) force full duplex */ 1378 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1379 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1380 cbp->mc_all = allm; /* accept all multicasts */ 1381 1382 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1383 1384 /* 1385 * Start the config command/DMA. 1386 */ 1387 fxp_scb_wait(sc); 1388 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1389 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1390 /* ...and wait for it to complete. */ 1391 i = 1000; 1392 do { 1393 FXP_CDCONFIGSYNC(sc, 1394 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1395 DELAY(1); 1396 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1397 if (i == 0) { 1398 printf("%s at line %d: dmasync timeout\n", 1399 sc->sc_dev.dv_xname, __LINE__); 1400 return ETIMEDOUT; 1401 } 1402 1403 /* 1404 * Initialize the station address. 1405 */ 1406 cb_ias = &sc->sc_control_data->fcd_iascb; 1407 /* BIG_ENDIAN: no need to swap to store 0 */ 1408 cb_ias->cb_status = 0; 1409 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1410 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1411 cb_ias->link_addr = 0xffffffff; 1412 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1413 1414 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1415 1416 /* 1417 * Start the IAS (Individual Address Setup) command/DMA. 1418 */ 1419 fxp_scb_wait(sc); 1420 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1421 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1422 /* ...and wait for it to complete. */ 1423 i = 1000; 1424 do { 1425 FXP_CDIASSYNC(sc, 1426 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1427 DELAY(1); 1428 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1429 if (i == 0) { 1430 printf("%s at line %d: dmasync timeout\n", 1431 sc->sc_dev.dv_xname, __LINE__); 1432 return ETIMEDOUT; 1433 } 1434 1435 /* 1436 * Initialize the transmit descriptor ring. txlast is initialized 1437 * to the end of the list so that it will wrap around to the first 1438 * descriptor when the first packet is transmitted. 1439 */ 1440 for (i = 0; i < FXP_NTXCB; i++) { 1441 txd = FXP_CDTX(sc, i); 1442 memset(txd, 0, sizeof(struct fxp_cb_tx)); 1443 txd->cb_command = 1444 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1445 txd->tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1446 txd->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1447 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1448 } 1449 sc->sc_txpending = 0; 1450 sc->sc_txdirty = 0; 1451 sc->sc_txlast = FXP_NTXCB - 1; 1452 1453 /* 1454 * Initialize the receive buffer list. 1455 */ 1456 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1457 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1458 rxmap = FXP_RXMAP_GET(sc); 1459 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1460 printf("%s: unable to allocate or map rx " 1461 "buffer %d, error = %d\n", 1462 sc->sc_dev.dv_xname, 1463 sc->sc_rxq.ifq_len, error); 1464 /* 1465 * XXX Should attempt to run with fewer receive 1466 * XXX buffers instead of just failing. 1467 */ 1468 FXP_RXMAP_PUT(sc, rxmap); 1469 fxp_rxdrain(sc); 1470 goto out; 1471 } 1472 } 1473 sc->sc_rxidle = 0; 1474 1475 /* 1476 * Give the transmit ring to the chip. We do this by pointing 1477 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1478 * issuing a start command. It will execute the NOP and then 1479 * suspend, pointing at the first descriptor. 1480 */ 1481 fxp_scb_wait(sc); 1482 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1483 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1484 1485 /* 1486 * Initialize receiver buffer area - RFA. 1487 */ 1488 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1489 fxp_scb_wait(sc); 1490 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1491 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1492 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START); 1493 1494 if (sc->sc_flags & FXPF_MII) { 1495 /* 1496 * Set current media. 1497 */ 1498 mii_mediachg(&sc->sc_mii); 1499 } 1500 1501 /* 1502 * ...all done! 1503 */ 1504 ifp->if_flags |= IFF_RUNNING; 1505 ifp->if_flags &= ~IFF_OACTIVE; 1506 1507 /* 1508 * Start the one second timer. 1509 */ 1510 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1511 1512 /* 1513 * Attempt to start output on the interface. 1514 */ 1515 fxp_start(ifp); 1516 1517 out: 1518 if (error) { 1519 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1520 ifp->if_timer = 0; 1521 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1522 } 1523 return (error); 1524 } 1525 1526 /* 1527 * Change media according to request. 1528 */ 1529 int 1530 fxp_mii_mediachange(struct ifnet *ifp) 1531 { 1532 struct fxp_softc *sc = ifp->if_softc; 1533 1534 if (ifp->if_flags & IFF_UP) 1535 mii_mediachg(&sc->sc_mii); 1536 return (0); 1537 } 1538 1539 /* 1540 * Notify the world which media we're using. 1541 */ 1542 void 1543 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1544 { 1545 struct fxp_softc *sc = ifp->if_softc; 1546 1547 if(sc->sc_enabled == 0) { 1548 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1549 ifmr->ifm_status = 0; 1550 return; 1551 } 1552 1553 mii_pollstat(&sc->sc_mii); 1554 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1555 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1556 } 1557 1558 int 1559 fxp_80c24_mediachange(struct ifnet *ifp) 1560 { 1561 1562 /* Nothing to do here. */ 1563 return (0); 1564 } 1565 1566 void 1567 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1568 { 1569 struct fxp_softc *sc = ifp->if_softc; 1570 1571 /* 1572 * Media is currently-selected media. We cannot determine 1573 * the link status. 1574 */ 1575 ifmr->ifm_status = 0; 1576 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1577 } 1578 1579 /* 1580 * Add a buffer to the end of the RFA buffer list. 1581 * Return 0 if successful, error code on failure. 1582 * 1583 * The RFA struct is stuck at the beginning of mbuf cluster and the 1584 * data pointer is fixed up to point just past it. 1585 */ 1586 int 1587 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1588 { 1589 struct mbuf *m; 1590 int error; 1591 1592 MGETHDR(m, M_DONTWAIT, MT_DATA); 1593 if (m == NULL) 1594 return (ENOBUFS); 1595 1596 MCLGET(m, M_DONTWAIT); 1597 if ((m->m_flags & M_EXT) == 0) { 1598 m_freem(m); 1599 return (ENOBUFS); 1600 } 1601 1602 if (unload) 1603 bus_dmamap_unload(sc->sc_dmat, rxmap); 1604 1605 M_SETCTX(m, rxmap); 1606 1607 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1608 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1609 if (error) { 1610 printf("%s: can't load rx DMA map %d, error = %d\n", 1611 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1612 panic("fxp_add_rfabuf"); /* XXX */ 1613 } 1614 1615 FXP_INIT_RFABUF(sc, m); 1616 1617 return (0); 1618 } 1619 1620 int 1621 fxp_mdi_read(struct device *self, int phy, int reg) 1622 { 1623 struct fxp_softc *sc = (struct fxp_softc *)self; 1624 int count = 10000; 1625 int value; 1626 1627 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1628 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1629 1630 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1631 && count--) 1632 DELAY(10); 1633 1634 if (count <= 0) 1635 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1636 1637 return (value & 0xffff); 1638 } 1639 1640 void 1641 fxp_statchg(struct device *self) 1642 { 1643 1644 /* Nothing to do. */ 1645 } 1646 1647 void 1648 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1649 { 1650 struct fxp_softc *sc = (struct fxp_softc *)self; 1651 int count = 10000; 1652 1653 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1654 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1655 (value & 0xffff)); 1656 1657 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1658 count--) 1659 DELAY(10); 1660 1661 if (count <= 0) 1662 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1663 } 1664 1665 int 1666 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1667 { 1668 struct fxp_softc *sc = ifp->if_softc; 1669 struct ifreq *ifr = (struct ifreq *)data; 1670 int s, error; 1671 1672 s = splnet(); 1673 1674 switch (cmd) { 1675 case SIOCSIFMEDIA: 1676 case SIOCGIFMEDIA: 1677 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1678 break; 1679 1680 default: 1681 error = ether_ioctl(ifp, cmd, data); 1682 if (error == ENETRESET) { 1683 if (sc->sc_enabled) { 1684 /* 1685 * Multicast list has changed; set the 1686 * hardware filter accordingly. 1687 */ 1688 if (sc->sc_txpending) { 1689 sc->sc_flags |= FXPF_WANTINIT; 1690 error = 0; 1691 } else 1692 error = fxp_init(ifp); 1693 } else 1694 error = 0; 1695 } 1696 break; 1697 } 1698 1699 /* Try to get more packets going. */ 1700 if (sc->sc_enabled) 1701 fxp_start(ifp); 1702 1703 splx(s); 1704 return (error); 1705 } 1706 1707 /* 1708 * Program the multicast filter. 1709 * 1710 * This function must be called at splnet(). 1711 */ 1712 void 1713 fxp_mc_setup(struct fxp_softc *sc) 1714 { 1715 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1716 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1717 struct ethercom *ec = &sc->sc_ethercom; 1718 struct ether_multi *enm; 1719 struct ether_multistep step; 1720 int count, nmcasts; 1721 1722 #ifdef DIAGNOSTIC 1723 if (sc->sc_txpending) 1724 panic("fxp_mc_setup: pending transmissions"); 1725 #endif 1726 1727 ifp->if_flags &= ~IFF_ALLMULTI; 1728 1729 /* 1730 * Initialize multicast setup descriptor. 1731 */ 1732 nmcasts = 0; 1733 ETHER_FIRST_MULTI(step, ec, enm); 1734 while (enm != NULL) { 1735 /* 1736 * Check for too many multicast addresses or if we're 1737 * listening to a range. Either way, we simply have 1738 * to accept all multicasts. 1739 */ 1740 if (nmcasts >= MAXMCADDR || 1741 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1742 ETHER_ADDR_LEN) != 0) { 1743 /* 1744 * Callers of this function must do the 1745 * right thing with this. If we're called 1746 * from outside fxp_init(), the caller must 1747 * detect if the state if IFF_ALLMULTI changes. 1748 * If it does, the caller must then call 1749 * fxp_init(), since allmulti is handled by 1750 * the config block. 1751 */ 1752 ifp->if_flags |= IFF_ALLMULTI; 1753 return; 1754 } 1755 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1756 ETHER_ADDR_LEN); 1757 nmcasts++; 1758 ETHER_NEXT_MULTI(step, enm); 1759 } 1760 1761 /* BIG_ENDIAN: no need to swap to store 0 */ 1762 mcsp->cb_status = 0; 1763 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1764 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1765 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1766 1767 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1768 1769 /* 1770 * Wait until the command unit is not active. This should never 1771 * happen since nothing is queued, but make sure anyway. 1772 */ 1773 count = 100; 1774 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1775 FXP_SCB_CUS_ACTIVE && --count) 1776 DELAY(1); 1777 if (count == 0) { 1778 printf("%s at line %d: command queue timeout\n", 1779 sc->sc_dev.dv_xname, __LINE__); 1780 return; 1781 } 1782 1783 /* 1784 * Start the multicast setup command/DMA. 1785 */ 1786 fxp_scb_wait(sc); 1787 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1788 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START); 1789 1790 /* ...and wait for it to complete. */ 1791 count = 1000; 1792 do { 1793 FXP_CDMCSSYNC(sc, 1794 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1795 DELAY(1); 1796 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1797 if (count == 0) { 1798 printf("%s at line %d: dmasync timeout\n", 1799 sc->sc_dev.dv_xname, __LINE__); 1800 return; 1801 } 1802 } 1803 1804 int 1805 fxp_enable(struct fxp_softc *sc) 1806 { 1807 1808 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1809 if ((*sc->sc_enable)(sc) != 0) { 1810 printf("%s: device enable failed\n", 1811 sc->sc_dev.dv_xname); 1812 return (EIO); 1813 } 1814 } 1815 1816 sc->sc_enabled = 1; 1817 return (0); 1818 } 1819 1820 void 1821 fxp_disable(struct fxp_softc *sc) 1822 { 1823 1824 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1825 (*sc->sc_disable)(sc); 1826 sc->sc_enabled = 0; 1827 } 1828 } 1829 1830 /* 1831 * fxp_activate: 1832 * 1833 * Handle device activation/deactivation requests. 1834 */ 1835 int 1836 fxp_activate(struct device *self, enum devact act) 1837 { 1838 struct fxp_softc *sc = (void *) self; 1839 int s, error = 0; 1840 1841 s = splnet(); 1842 switch (act) { 1843 case DVACT_ACTIVATE: 1844 error = EOPNOTSUPP; 1845 break; 1846 1847 case DVACT_DEACTIVATE: 1848 if (sc->sc_flags & FXPF_MII) 1849 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1850 MII_OFFSET_ANY); 1851 if_deactivate(&sc->sc_ethercom.ec_if); 1852 break; 1853 } 1854 splx(s); 1855 1856 return (error); 1857 } 1858 1859 /* 1860 * fxp_detach: 1861 * 1862 * Detach an i82557 interface. 1863 */ 1864 int 1865 fxp_detach(struct fxp_softc *sc) 1866 { 1867 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1868 int i; 1869 1870 /* Succeed now if there's no work to do. */ 1871 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1872 return (0); 1873 1874 /* Unhook our tick handler. */ 1875 callout_stop(&sc->sc_callout); 1876 1877 if (sc->sc_flags & FXPF_MII) { 1878 /* Detach all PHYs */ 1879 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1880 } 1881 1882 /* Delete all remaining media. */ 1883 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1884 1885 #if NRND > 0 1886 rnd_detach_source(&sc->rnd_source); 1887 #endif 1888 ether_ifdetach(ifp); 1889 if_detach(ifp); 1890 1891 for (i = 0; i < FXP_NRFABUFS; i++) { 1892 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1893 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1894 } 1895 1896 for (i = 0; i < FXP_NTXCB; i++) { 1897 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1898 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1899 } 1900 1901 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1902 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1903 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1904 sizeof(struct fxp_control_data)); 1905 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1906 1907 shutdownhook_disestablish(sc->sc_sdhook); 1908 powerhook_disestablish(sc->sc_powerhook); 1909 1910 return (0); 1911 } 1912
Indexes created Mon Sep 29 21:09:56 GMT 2025