i82557.c revision 1.50
1 /* $NetBSD: i82557.c,v 1.50 2001/05/21 23:58:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice unmodified, this list of conditions, and the following 49 * disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * Id: if_fxp.c,v 1.47 1998/01/08 23:42:29 eivind Exp 67 */ 68 69 /* 70 * Device driver for the Intel i82557 fast Ethernet controller, 71 * and its successors, the i82558 and i82559. 72 */ 73 74 #include "opt_inet.h" 75 #include "opt_ns.h" 76 #include "bpfilter.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 90 #include <machine/endian.h> 91 92 #include <uvm/uvm_extern.h> 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/i82557reg.h> 123 #include <dev/ic/i82557var.h> 124 125 /* 126 * NOTE! On the Alpha, we have an alignment constraint. The 127 * card DMAs the packet immediately following the RFA. However, 128 * the first thing in the packet is a 14-byte Ethernet header. 129 * This means that the packet is misaligned. To compensate, 130 * we actually offset the RFA 2 bytes into the cluster. This 131 * alignes the packet after the Ethernet header at a 32-bit 132 * boundary. HOWEVER! This means that the RFA is misaligned! 133 */ 134 #define RFA_ALIGNMENT_FUDGE 2 135 136 /* 137 * Template for default configuration parameters. 138 * See struct fxp_cb_config for the bit definitions. 139 */ 140 u_int8_t fxp_cb_config_template[] = { 141 0x0, 0x0, /* cb_status */ 142 0x80, 0x2, /* cb_command */ 143 0xff, 0xff, 0xff, 0xff, /* link_addr */ 144 0x16, /* 0 */ 145 0x8, /* 1 */ 146 0x0, /* 2 */ 147 0x0, /* 3 */ 148 0x0, /* 4 */ 149 0x80, /* 5 */ 150 0xb2, /* 6 */ 151 0x3, /* 7 */ 152 0x1, /* 8 */ 153 0x0, /* 9 */ 154 0x26, /* 10 */ 155 0x0, /* 11 */ 156 0x60, /* 12 */ 157 0x0, /* 13 */ 158 0xf2, /* 14 */ 159 0x48, /* 15 */ 160 0x0, /* 16 */ 161 0x40, /* 17 */ 162 0xf3, /* 18 */ 163 0x0, /* 19 */ 164 0x3f, /* 20 */ 165 0x5 /* 21 */ 166 }; 167 168 void fxp_mii_initmedia(struct fxp_softc *); 169 int fxp_mii_mediachange(struct ifnet *); 170 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 171 172 void fxp_80c24_initmedia(struct fxp_softc *); 173 int fxp_80c24_mediachange(struct ifnet *); 174 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 175 176 void fxp_start(struct ifnet *); 177 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 178 void fxp_watchdog(struct ifnet *); 179 int fxp_init(struct ifnet *); 180 void fxp_stop(struct ifnet *, int); 181 182 void fxp_rxdrain(struct fxp_softc *); 183 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 184 int fxp_mdi_read(struct device *, int, int); 185 void fxp_statchg(struct device *); 186 void fxp_mdi_write(struct device *, int, int, int); 187 void fxp_autosize_eeprom(struct fxp_softc*); 188 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 189 void fxp_get_info(struct fxp_softc *, u_int8_t *); 190 void fxp_tick(void *); 191 void fxp_mc_setup(struct fxp_softc *); 192 193 void fxp_shutdown(void *); 194 void fxp_power(int, void *); 195 196 int fxp_copy_small = 0; 197 198 struct fxp_phytype { 199 int fp_phy; /* type of PHY, -1 for MII at the end. */ 200 void (*fp_init)(struct fxp_softc *); 201 } fxp_phytype_table[] = { 202 { FXP_PHY_80C24, fxp_80c24_initmedia }, 203 { -1, fxp_mii_initmedia }, 204 }; 205 206 /* 207 * Set initial transmit threshold at 64 (512 bytes). This is 208 * increased by 64 (512 bytes) at a time, to maximum of 192 209 * (1536 bytes), if an underrun occurs. 210 */ 211 static int tx_threshold = 64; 212 213 /* 214 * Wait for the previous command to be accepted (but not necessarily 215 * completed). 216 */ 217 static __inline void 218 fxp_scb_wait(struct fxp_softc *sc) 219 { 220 int i = 10000; 221 222 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 223 delay(2); 224 if (i == 0) 225 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 226 } 227 228 /* 229 * Submit a command to the i82557. 230 */ 231 static __inline void 232 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 233 { 234 235 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 236 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 237 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_NOP); 238 fxp_scb_wait(sc); 239 } 240 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 241 } 242 243 /* 244 * Finish attaching an i82557 interface. Called by bus-specific front-end. 245 */ 246 void 247 fxp_attach(struct fxp_softc *sc) 248 { 249 u_int8_t enaddr[ETHER_ADDR_LEN]; 250 struct ifnet *ifp; 251 bus_dma_segment_t seg; 252 int rseg, i, error; 253 struct fxp_phytype *fp; 254 255 callout_init(&sc->sc_callout); 256 257 /* 258 * Allocate the control data structures, and create and load the 259 * DMA map for it. 260 */ 261 if ((error = bus_dmamem_alloc(sc->sc_dmat, 262 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 263 0)) != 0) { 264 printf("%s: unable to allocate control data, error = %d\n", 265 sc->sc_dev.dv_xname, error); 266 goto fail_0; 267 } 268 269 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 270 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 271 BUS_DMA_COHERENT)) != 0) { 272 printf("%s: unable to map control data, error = %d\n", 273 sc->sc_dev.dv_xname, error); 274 goto fail_1; 275 } 276 sc->sc_cdseg = seg; 277 sc->sc_cdnseg = rseg; 278 279 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 280 281 if ((error = bus_dmamap_create(sc->sc_dmat, 282 sizeof(struct fxp_control_data), 1, 283 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 284 printf("%s: unable to create control data DMA map, " 285 "error = %d\n", sc->sc_dev.dv_xname, error); 286 goto fail_2; 287 } 288 289 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 290 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 291 0)) != 0) { 292 printf("%s: can't load control data DMA map, error = %d\n", 293 sc->sc_dev.dv_xname, error); 294 goto fail_3; 295 } 296 297 /* 298 * Create the transmit buffer DMA maps. 299 */ 300 for (i = 0; i < FXP_NTXCB; i++) { 301 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 302 FXP_NTXSEG, MCLBYTES, 0, 0, 303 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 304 printf("%s: unable to create tx DMA map %d, " 305 "error = %d\n", sc->sc_dev.dv_xname, i, error); 306 goto fail_4; 307 } 308 } 309 310 /* 311 * Create the receive buffer DMA maps. 312 */ 313 for (i = 0; i < FXP_NRFABUFS; i++) { 314 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 315 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 316 printf("%s: unable to create rx DMA map %d, " 317 "error = %d\n", sc->sc_dev.dv_xname, i, error); 318 goto fail_5; 319 } 320 } 321 322 /* Initialize MAC address and media structures. */ 323 fxp_get_info(sc, enaddr); 324 325 printf("%s: Ethernet address %s, %s Mb/s\n", sc->sc_dev.dv_xname, 326 ether_sprintf(enaddr), sc->phy_10Mbps_only ? "10" : "10/100"); 327 328 ifp = &sc->sc_ethercom.ec_if; 329 330 /* 331 * Get info about our media interface, and initialize it. Note 332 * the table terminates itself with a phy of -1, indicating 333 * that we're using MII. 334 */ 335 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 336 if (fp->fp_phy == sc->phy_primary_device) 337 break; 338 (*fp->fp_init)(sc); 339 340 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 341 ifp->if_softc = sc; 342 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 343 ifp->if_ioctl = fxp_ioctl; 344 ifp->if_start = fxp_start; 345 ifp->if_watchdog = fxp_watchdog; 346 ifp->if_init = fxp_init; 347 ifp->if_stop = fxp_stop; 348 IFQ_SET_READY(&ifp->if_snd); 349 350 /* 351 * We can support 802.1Q VLAN-sized frames. 352 */ 353 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 354 355 /* 356 * Attach the interface. 357 */ 358 if_attach(ifp); 359 ether_ifattach(ifp, enaddr); 360 #if NRND > 0 361 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 362 RND_TYPE_NET, 0); 363 #endif 364 365 /* 366 * Add shutdown hook so that DMA is disabled prior to reboot. Not 367 * doing do could allow DMA to corrupt kernel memory during the 368 * reboot before the driver initializes. 369 */ 370 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 371 if (sc->sc_sdhook == NULL) 372 printf("%s: WARNING: unable to establish shutdown hook\n", 373 sc->sc_dev.dv_xname); 374 /* 375 * Add suspend hook, for similar reasons.. 376 */ 377 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 378 if (sc->sc_powerhook == NULL) 379 printf("%s: WARNING: unable to establish power hook\n", 380 sc->sc_dev.dv_xname); 381 382 /* The attach is successful. */ 383 sc->sc_flags |= FXPF_ATTACHED; 384 385 return; 386 387 /* 388 * Free any resources we've allocated during the failed attach 389 * attempt. Do this in reverse order and fall though. 390 */ 391 fail_5: 392 for (i = 0; i < FXP_NRFABUFS; i++) { 393 if (sc->sc_rxmaps[i] != NULL) 394 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 395 } 396 fail_4: 397 for (i = 0; i < FXP_NTXCB; i++) { 398 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 399 bus_dmamap_destroy(sc->sc_dmat, 400 FXP_DSTX(sc, i)->txs_dmamap); 401 } 402 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 403 fail_3: 404 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 405 fail_2: 406 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 407 sizeof(struct fxp_control_data)); 408 fail_1: 409 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 410 fail_0: 411 return; 412 } 413 414 void 415 fxp_mii_initmedia(struct fxp_softc *sc) 416 { 417 418 sc->sc_flags |= FXPF_MII; 419 420 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 421 sc->sc_mii.mii_readreg = fxp_mdi_read; 422 sc->sc_mii.mii_writereg = fxp_mdi_write; 423 sc->sc_mii.mii_statchg = fxp_statchg; 424 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 425 fxp_mii_mediastatus); 426 /* 427 * The i82557 wedges if all of its PHYs are isolated! 428 */ 429 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 430 MII_OFFSET_ANY, MIIF_NOISOLATE); 431 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 432 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 433 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 434 } else 435 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 436 } 437 438 void 439 fxp_80c24_initmedia(struct fxp_softc *sc) 440 { 441 442 /* 443 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 444 * doesn't have a programming interface of any sort. The 445 * media is sensed automatically based on how the link partner 446 * is configured. This is, in essence, manual configuration. 447 */ 448 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 449 sc->sc_dev.dv_xname); 450 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 451 fxp_80c24_mediastatus); 452 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 453 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 454 } 455 456 /* 457 * Device shutdown routine. Called at system shutdown after sync. The 458 * main purpose of this routine is to shut off receiver DMA so that 459 * kernel memory doesn't get clobbered during warmboot. 460 */ 461 void 462 fxp_shutdown(void *arg) 463 { 464 struct fxp_softc *sc = arg; 465 466 /* 467 * Since the system's going to halt shortly, don't bother 468 * freeing mbufs. 469 */ 470 fxp_stop(&sc->sc_ethercom.ec_if, 0); 471 } 472 /* 473 * Power handler routine. Called when the system is transitioning 474 * into/out of power save modes. As with fxp_shutdown, the main 475 * purpose of this routine is to shut off receiver DMA so it doesn't 476 * clobber kernel memory at the wrong time. 477 */ 478 void 479 fxp_power(int why, void *arg) 480 { 481 struct fxp_softc *sc = arg; 482 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 483 int s; 484 485 s = splnet(); 486 switch (why) { 487 case PWR_SUSPEND: 488 case PWR_STANDBY: 489 fxp_stop(ifp, 0); 490 break; 491 case PWR_RESUME: 492 if (ifp->if_flags & IFF_UP) 493 fxp_init(ifp); 494 break; 495 case PWR_SOFTSUSPEND: 496 case PWR_SOFTSTANDBY: 497 case PWR_SOFTRESUME: 498 break; 499 } 500 splx(s); 501 } 502 503 /* 504 * Initialize the interface media. 505 */ 506 void 507 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 508 { 509 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 510 511 /* 512 * Reset to a stable state. 513 */ 514 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 515 DELAY(10); 516 517 sc->sc_eeprom_size = 0; 518 fxp_autosize_eeprom(sc); 519 if(sc->sc_eeprom_size == 0) { 520 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 521 sc->sc_eeprom_size = 6; /* XXX panic here? */ 522 } 523 #ifdef DEBUG 524 printf("%s: detected %d word EEPROM\n", 525 sc->sc_dev.dv_xname, 526 1 << sc->sc_eeprom_size); 527 #endif 528 529 /* 530 * Get info about the primary PHY 531 */ 532 fxp_read_eeprom(sc, &data, 6, 1); 533 sc->phy_primary_addr = data & 0xff; 534 sc->phy_primary_device = (data >> 8) & 0x3f; 535 sc->phy_10Mbps_only = data >> 15; 536 537 /* 538 * Read MAC address. 539 */ 540 fxp_read_eeprom(sc, myea, 0, 3); 541 enaddr[0] = myea[0] & 0xff; 542 enaddr[1] = myea[0] >> 8; 543 enaddr[2] = myea[1] & 0xff; 544 enaddr[3] = myea[1] >> 8; 545 enaddr[4] = myea[2] & 0xff; 546 enaddr[5] = myea[2] >> 8; 547 } 548 549 /* 550 * Figure out EEPROM size. 551 * 552 * 559's can have either 64-word or 256-word EEPROMs, the 558 553 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 554 * talks about the existance of 16 to 256 word EEPROMs. 555 * 556 * The only known sizes are 64 and 256, where the 256 version is used 557 * by CardBus cards to store CIS information. 558 * 559 * The address is shifted in msb-to-lsb, and after the last 560 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 561 * after which follows the actual data. We try to detect this zero, by 562 * probing the data-out bit in the EEPROM control register just after 563 * having shifted in a bit. If the bit is zero, we assume we've 564 * shifted enough address bits. The data-out should be tri-state, 565 * before this, which should translate to a logical one. 566 * 567 * Other ways to do this would be to try to read a register with known 568 * contents with a varying number of address bits, but no such 569 * register seem to be available. The high bits of register 10 are 01 570 * on the 558 and 559, but apparently not on the 557. 571 * 572 * The Linux driver computes a checksum on the EEPROM data, but the 573 * value of this checksum is not very well documented. 574 */ 575 576 void 577 fxp_autosize_eeprom(struct fxp_softc *sc) 578 { 579 u_int16_t reg; 580 int x; 581 582 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 583 /* 584 * Shift in read opcode. 585 */ 586 for (x = 3; x > 0; x--) { 587 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 588 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 589 } else { 590 reg = FXP_EEPROM_EECS; 591 } 592 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 593 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 594 reg | FXP_EEPROM_EESK); 595 DELAY(4); 596 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 597 DELAY(4); 598 } 599 /* 600 * Shift in address, wait for the dummy zero following a correct 601 * address shift. 602 */ 603 for (x = 1; x <= 8; x++) { 604 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 605 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 606 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 607 DELAY(4); 608 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 609 FXP_EEPROM_EEDO) == 0) 610 break; 611 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 612 DELAY(4); 613 } 614 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 615 DELAY(4); 616 if(x != 6 && x != 8) { 617 #ifdef DEBUG 618 printf("%s: strange EEPROM size (%d)\n", 619 sc->sc_dev.dv_xname, 1 << x); 620 #endif 621 } else 622 sc->sc_eeprom_size = x; 623 } 624 625 /* 626 * Read from the serial EEPROM. Basically, you manually shift in 627 * the read opcode (one bit at a time) and then shift in the address, 628 * and then you shift out the data (all of this one bit at a time). 629 * The word size is 16 bits, so you have to provide the address for 630 * every 16 bits of data. 631 */ 632 void 633 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 634 { 635 u_int16_t reg; 636 int i, x; 637 638 for (i = 0; i < words; i++) { 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 640 /* 641 * Shift in read opcode. 642 */ 643 for (x = 3; x > 0; x--) { 644 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 645 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 646 } else { 647 reg = FXP_EEPROM_EECS; 648 } 649 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 651 reg | FXP_EEPROM_EESK); 652 DELAY(4); 653 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 654 DELAY(4); 655 } 656 /* 657 * Shift in address. 658 */ 659 for (x = sc->sc_eeprom_size; x > 0; x--) { 660 if ((i + offset) & (1 << (x - 1))) { 661 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 662 } else { 663 reg = FXP_EEPROM_EECS; 664 } 665 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 667 reg | FXP_EEPROM_EESK); 668 DELAY(4); 669 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 670 DELAY(4); 671 } 672 reg = FXP_EEPROM_EECS; 673 data[i] = 0; 674 /* 675 * Shift out data. 676 */ 677 for (x = 16; x > 0; x--) { 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 679 reg | FXP_EEPROM_EESK); 680 DELAY(4); 681 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 682 FXP_EEPROM_EEDO) 683 data[i] |= (1 << (x - 1)); 684 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 685 DELAY(4); 686 } 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 688 DELAY(4); 689 } 690 } 691 692 /* 693 * Start packet transmission on the interface. 694 */ 695 void 696 fxp_start(struct ifnet *ifp) 697 { 698 struct fxp_softc *sc = ifp->if_softc; 699 struct mbuf *m0, *m; 700 struct fxp_txdesc *txd; 701 struct fxp_txsoft *txs; 702 bus_dmamap_t dmamap; 703 int error, lasttx, nexttx, opending, seg; 704 705 /* 706 * If we want a re-init, bail out now. 707 */ 708 if (sc->sc_flags & FXPF_WANTINIT) { 709 ifp->if_flags |= IFF_OACTIVE; 710 return; 711 } 712 713 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 714 return; 715 716 /* 717 * Remember the previous txpending and the current lasttx. 718 */ 719 opending = sc->sc_txpending; 720 lasttx = sc->sc_txlast; 721 722 /* 723 * Loop through the send queue, setting up transmit descriptors 724 * until we drain the queue, or use up all available transmit 725 * descriptors. 726 */ 727 while (sc->sc_txpending < FXP_NTXCB) { 728 /* 729 * Grab a packet off the queue. 730 */ 731 IFQ_POLL(&ifp->if_snd, m0); 732 if (m0 == NULL) 733 break; 734 m = NULL; 735 736 /* 737 * Get the next available transmit descriptor. 738 */ 739 nexttx = FXP_NEXTTX(sc->sc_txlast); 740 txd = FXP_CDTX(sc, nexttx); 741 txs = FXP_DSTX(sc, nexttx); 742 dmamap = txs->txs_dmamap; 743 744 /* 745 * Load the DMA map. If this fails, the packet either 746 * didn't fit in the allotted number of frags, or we were 747 * short on resources. In this case, we'll copy and try 748 * again. 749 */ 750 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 751 BUS_DMA_NOWAIT) != 0) { 752 MGETHDR(m, M_DONTWAIT, MT_DATA); 753 if (m == NULL) { 754 printf("%s: unable to allocate Tx mbuf\n", 755 sc->sc_dev.dv_xname); 756 break; 757 } 758 if (m0->m_pkthdr.len > MHLEN) { 759 MCLGET(m, M_DONTWAIT); 760 if ((m->m_flags & M_EXT) == 0) { 761 printf("%s: unable to allocate Tx " 762 "cluster\n", sc->sc_dev.dv_xname); 763 m_freem(m); 764 break; 765 } 766 } 767 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 768 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 769 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 770 m, BUS_DMA_NOWAIT); 771 if (error) { 772 printf("%s: unable to load Tx buffer, " 773 "error = %d\n", sc->sc_dev.dv_xname, error); 774 break; 775 } 776 } 777 778 IFQ_DEQUEUE(&ifp->if_snd, m0); 779 if (m != NULL) { 780 m_freem(m0); 781 m0 = m; 782 } 783 784 /* Initialize the fraglist. */ 785 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 786 txd->txd_tbd[seg].tb_addr = 787 htole32(dmamap->dm_segs[seg].ds_addr); 788 txd->txd_tbd[seg].tb_size = 789 htole32(dmamap->dm_segs[seg].ds_len); 790 } 791 792 /* Sync the DMA map. */ 793 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 794 BUS_DMASYNC_PREWRITE); 795 796 /* 797 * Store a pointer to the packet so we can free it later. 798 */ 799 txs->txs_mbuf = m0; 800 801 /* 802 * Initialize the transmit descriptor. 803 */ 804 /* BIG_ENDIAN: no need to swap to store 0 */ 805 txd->txd_txcb.cb_status = 0; 806 txd->txd_txcb.cb_command = 807 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 808 txd->txd_txcb.tx_threshold = tx_threshold; 809 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 810 811 FXP_CDTXSYNC(sc, nexttx, 812 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 813 814 /* Advance the tx pointer. */ 815 sc->sc_txpending++; 816 sc->sc_txlast = nexttx; 817 818 #if NBPFILTER > 0 819 /* 820 * Pass packet to bpf if there is a listener. 821 */ 822 if (ifp->if_bpf) 823 bpf_mtap(ifp->if_bpf, m0); 824 #endif 825 } 826 827 if (sc->sc_txpending == FXP_NTXCB) { 828 /* No more slots; notify upper layer. */ 829 ifp->if_flags |= IFF_OACTIVE; 830 } 831 832 if (sc->sc_txpending != opending) { 833 /* 834 * We enqueued packets. If the transmitter was idle, 835 * reset the txdirty pointer. 836 */ 837 if (opending == 0) 838 sc->sc_txdirty = FXP_NEXTTX(lasttx); 839 840 /* 841 * Cause the chip to interrupt and suspend command 842 * processing once the last packet we've enqueued 843 * has been transmitted. 844 */ 845 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 846 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 847 FXP_CDTXSYNC(sc, sc->sc_txlast, 848 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 849 850 /* 851 * The entire packet chain is set up. Clear the suspend bit 852 * on the command prior to the first packet we set up. 853 */ 854 FXP_CDTXSYNC(sc, lasttx, 855 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 856 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 857 htole16(~FXP_CB_COMMAND_S); 858 FXP_CDTXSYNC(sc, lasttx, 859 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 860 861 /* 862 * Issue a Resume command in case the chip was suspended. 863 */ 864 fxp_scb_wait(sc); 865 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 866 867 /* Set a watchdog timer in case the chip flakes out. */ 868 ifp->if_timer = 5; 869 } 870 } 871 872 /* 873 * Process interface interrupts. 874 */ 875 int 876 fxp_intr(void *arg) 877 { 878 struct fxp_softc *sc = arg; 879 struct ethercom *ec = &sc->sc_ethercom; 880 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 881 struct fxp_txdesc *txd; 882 struct fxp_txsoft *txs; 883 struct mbuf *m, *m0; 884 bus_dmamap_t rxmap; 885 struct fxp_rfa *rfa; 886 int i, claimed = 0; 887 u_int16_t len, rxstat, txstat; 888 u_int8_t statack; 889 890 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 891 return (0); 892 /* 893 * If the interface isn't running, don't try to 894 * service the interrupt.. just ack it and bail. 895 */ 896 if ((ifp->if_flags & IFF_RUNNING) == 0) { 897 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 898 if (statack) { 899 claimed = 1; 900 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 901 } 902 return (claimed); 903 } 904 905 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 906 claimed = 1; 907 908 /* 909 * First ACK all the interrupts in this pass. 910 */ 911 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 912 913 /* 914 * Process receiver interrupts. If a no-resource (RNR) 915 * condition exists, get whatever packets we can and 916 * re-start the receiver. 917 */ 918 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 919 rcvloop: 920 m = sc->sc_rxq.ifq_head; 921 rfa = FXP_MTORFA(m); 922 rxmap = M_GETCTX(m, bus_dmamap_t); 923 924 FXP_RFASYNC(sc, m, 925 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 926 927 rxstat = le16toh(rfa->rfa_status); 928 929 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 930 /* 931 * We have processed all of the 932 * receive buffers. 933 */ 934 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 935 goto do_transmit; 936 } 937 938 IF_DEQUEUE(&sc->sc_rxq, m); 939 940 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 941 942 len = le16toh(rfa->actual_size) & 943 (m->m_ext.ext_size - 1); 944 945 if (len < sizeof(struct ether_header)) { 946 /* 947 * Runt packet; drop it now. 948 */ 949 FXP_INIT_RFABUF(sc, m); 950 goto rcvloop; 951 } 952 953 /* 954 * If support for 802.1Q VLAN sized frames is 955 * enabled, we need to do some additional error 956 * checking (as we are saving bad frames, in 957 * order to receive the larger ones). 958 */ 959 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 960 (rxstat & (FXP_RFA_STATUS_OVERRUN| 961 FXP_RFA_STATUS_RNR| 962 FXP_RFA_STATUS_ALIGN| 963 FXP_RFA_STATUS_CRC)) != 0) { 964 FXP_INIT_RFABUF(sc, m); 965 goto rcvloop; 966 } 967 968 /* 969 * If the packet is small enough to fit in a 970 * single header mbuf, allocate one and copy 971 * the data into it. This greatly reduces 972 * memory consumption when we receive lots 973 * of small packets. 974 * 975 * Otherwise, we add a new buffer to the receive 976 * chain. If this fails, we drop the packet and 977 * recycle the old buffer. 978 */ 979 if (fxp_copy_small != 0 && len <= MHLEN) { 980 MGETHDR(m0, M_DONTWAIT, MT_DATA); 981 if (m == NULL) 982 goto dropit; 983 memcpy(mtod(m0, caddr_t), 984 mtod(m, caddr_t), len); 985 FXP_INIT_RFABUF(sc, m); 986 m = m0; 987 } else { 988 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 989 dropit: 990 ifp->if_ierrors++; 991 FXP_INIT_RFABUF(sc, m); 992 goto rcvloop; 993 } 994 } 995 996 m->m_pkthdr.rcvif = ifp; 997 m->m_pkthdr.len = m->m_len = len; 998 999 #if NBPFILTER > 0 1000 /* 1001 * Pass this up to any BPF listeners, but only 1002 * pass it up the stack it its for us. 1003 */ 1004 if (ifp->if_bpf) 1005 bpf_mtap(ifp->if_bpf, m); 1006 #endif 1007 1008 /* Pass it on. */ 1009 (*ifp->if_input)(ifp, m); 1010 goto rcvloop; 1011 } 1012 1013 do_transmit: 1014 if (statack & FXP_SCB_STATACK_RNR) { 1015 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1016 fxp_scb_wait(sc); 1017 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1018 rxmap->dm_segs[0].ds_addr + 1019 RFA_ALIGNMENT_FUDGE); 1020 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1021 } 1022 1023 /* 1024 * Free any finished transmit mbuf chains. 1025 */ 1026 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1027 ifp->if_flags &= ~IFF_OACTIVE; 1028 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1029 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1030 txd = FXP_CDTX(sc, i); 1031 txs = FXP_DSTX(sc, i); 1032 1033 FXP_CDTXSYNC(sc, i, 1034 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1035 1036 txstat = le16toh(txd->txd_txcb.cb_status); 1037 1038 if ((txstat & FXP_CB_STATUS_C) == 0) 1039 break; 1040 1041 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1042 0, txs->txs_dmamap->dm_mapsize, 1043 BUS_DMASYNC_POSTWRITE); 1044 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1045 m_freem(txs->txs_mbuf); 1046 txs->txs_mbuf = NULL; 1047 } 1048 1049 /* Update the dirty transmit buffer pointer. */ 1050 sc->sc_txdirty = i; 1051 1052 /* 1053 * Cancel the watchdog timer if there are no pending 1054 * transmissions. 1055 */ 1056 if (sc->sc_txpending == 0) { 1057 ifp->if_timer = 0; 1058 1059 /* 1060 * If we want a re-init, do that now. 1061 */ 1062 if (sc->sc_flags & FXPF_WANTINIT) 1063 (void) fxp_init(ifp); 1064 } 1065 1066 /* 1067 * Try to get more packets going. 1068 */ 1069 fxp_start(ifp); 1070 } 1071 } 1072 1073 #if NRND > 0 1074 if (claimed) 1075 rnd_add_uint32(&sc->rnd_source, statack); 1076 #endif 1077 return (claimed); 1078 } 1079 1080 /* 1081 * Update packet in/out/collision statistics. The i82557 doesn't 1082 * allow you to access these counters without doing a fairly 1083 * expensive DMA to get _all_ of the statistics it maintains, so 1084 * we do this operation here only once per second. The statistics 1085 * counters in the kernel are updated from the previous dump-stats 1086 * DMA and then a new dump-stats DMA is started. The on-chip 1087 * counters are zeroed when the DMA completes. If we can't start 1088 * the DMA immediately, we don't wait - we just prepare to read 1089 * them again next time. 1090 */ 1091 void 1092 fxp_tick(void *arg) 1093 { 1094 struct fxp_softc *sc = arg; 1095 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1096 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1097 int s; 1098 1099 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1100 return; 1101 1102 s = splnet(); 1103 1104 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1105 1106 ifp->if_opackets += le32toh(sp->tx_good); 1107 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1108 if (sp->rx_good) { 1109 ifp->if_ipackets += le32toh(sp->rx_good); 1110 sc->sc_rxidle = 0; 1111 } else { 1112 sc->sc_rxidle++; 1113 } 1114 ifp->if_ierrors += 1115 le32toh(sp->rx_crc_errors) + 1116 le32toh(sp->rx_alignment_errors) + 1117 le32toh(sp->rx_rnr_errors) + 1118 le32toh(sp->rx_overrun_errors); 1119 /* 1120 * If any transmit underruns occured, bump up the transmit 1121 * threshold by another 512 bytes (64 * 8). 1122 */ 1123 if (sp->tx_underruns) { 1124 ifp->if_oerrors += le32toh(sp->tx_underruns); 1125 if (tx_threshold < 192) 1126 tx_threshold += 64; 1127 } 1128 1129 /* 1130 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1131 * then assume the receiver has locked up and attempt to clear 1132 * the condition by reprogramming the multicast filter (actually, 1133 * resetting the interface). This is a work-around for a bug in 1134 * the 82557 where the receiver locks up if it gets certain types 1135 * of garbage in the syncronization bits prior to the packet header. 1136 * This bug is supposed to only occur in 10Mbps mode, but has been 1137 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1138 * speed transition). 1139 */ 1140 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1141 (void) fxp_init(ifp); 1142 splx(s); 1143 return; 1144 } 1145 /* 1146 * If there is no pending command, start another stats 1147 * dump. Otherwise punt for now. 1148 */ 1149 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1150 /* 1151 * Start another stats dump. 1152 */ 1153 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1154 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1155 } else { 1156 /* 1157 * A previous command is still waiting to be accepted. 1158 * Just zero our copy of the stats and wait for the 1159 * next timer event to update them. 1160 */ 1161 /* BIG_ENDIAN: no swap required to store 0 */ 1162 sp->tx_good = 0; 1163 sp->tx_underruns = 0; 1164 sp->tx_total_collisions = 0; 1165 1166 sp->rx_good = 0; 1167 sp->rx_crc_errors = 0; 1168 sp->rx_alignment_errors = 0; 1169 sp->rx_rnr_errors = 0; 1170 sp->rx_overrun_errors = 0; 1171 } 1172 1173 if (sc->sc_flags & FXPF_MII) { 1174 /* Tick the MII clock. */ 1175 mii_tick(&sc->sc_mii); 1176 } 1177 1178 splx(s); 1179 1180 /* 1181 * Schedule another timeout one second from now. 1182 */ 1183 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1184 } 1185 1186 /* 1187 * Drain the receive queue. 1188 */ 1189 void 1190 fxp_rxdrain(struct fxp_softc *sc) 1191 { 1192 bus_dmamap_t rxmap; 1193 struct mbuf *m; 1194 1195 for (;;) { 1196 IF_DEQUEUE(&sc->sc_rxq, m); 1197 if (m == NULL) 1198 break; 1199 rxmap = M_GETCTX(m, bus_dmamap_t); 1200 bus_dmamap_unload(sc->sc_dmat, rxmap); 1201 FXP_RXMAP_PUT(sc, rxmap); 1202 m_freem(m); 1203 } 1204 } 1205 1206 /* 1207 * Stop the interface. Cancels the statistics updater and resets 1208 * the interface. 1209 */ 1210 void 1211 fxp_stop(struct ifnet *ifp, int disable) 1212 { 1213 struct fxp_softc *sc = ifp->if_softc; 1214 struct fxp_txsoft *txs; 1215 int i; 1216 1217 /* 1218 * Turn down interface (done early to avoid bad interactions 1219 * between panics, shutdown hooks, and the watchdog timer) 1220 */ 1221 ifp->if_timer = 0; 1222 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1223 1224 /* 1225 * Cancel stats updater. 1226 */ 1227 callout_stop(&sc->sc_callout); 1228 if (sc->sc_flags & FXPF_MII) { 1229 /* Down the MII. */ 1230 mii_down(&sc->sc_mii); 1231 } 1232 1233 /* 1234 * Issue software reset 1235 */ 1236 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1237 DELAY(10); 1238 1239 /* 1240 * Release any xmit buffers. 1241 */ 1242 for (i = 0; i < FXP_NTXCB; i++) { 1243 txs = FXP_DSTX(sc, i); 1244 if (txs->txs_mbuf != NULL) { 1245 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1246 m_freem(txs->txs_mbuf); 1247 txs->txs_mbuf = NULL; 1248 } 1249 } 1250 sc->sc_txpending = 0; 1251 1252 if (disable) { 1253 fxp_rxdrain(sc); 1254 fxp_disable(sc); 1255 } 1256 1257 } 1258 1259 /* 1260 * Watchdog/transmission transmit timeout handler. Called when a 1261 * transmission is started on the interface, but no interrupt is 1262 * received before the timeout. This usually indicates that the 1263 * card has wedged for some reason. 1264 */ 1265 void 1266 fxp_watchdog(struct ifnet *ifp) 1267 { 1268 struct fxp_softc *sc = ifp->if_softc; 1269 1270 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1271 ifp->if_oerrors++; 1272 1273 (void) fxp_init(ifp); 1274 } 1275 1276 /* 1277 * Initialize the interface. Must be called at splnet(). 1278 */ 1279 int 1280 fxp_init(struct ifnet *ifp) 1281 { 1282 struct fxp_softc *sc = ifp->if_softc; 1283 struct fxp_cb_config *cbp; 1284 struct fxp_cb_ias *cb_ias; 1285 struct fxp_txdesc *txd; 1286 bus_dmamap_t rxmap; 1287 int i, prm, save_bf, allm, error = 0; 1288 1289 if ((error = fxp_enable(sc)) != 0) 1290 goto out; 1291 1292 /* 1293 * Cancel any pending I/O 1294 */ 1295 fxp_stop(ifp, 0); 1296 1297 /* 1298 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1299 * flag, and this prevents the MII from detaching resulting in 1300 * a panic. The flags field should perhaps be split in runtime 1301 * flags and more static information. For now, just clear the 1302 * only other flag set. 1303 */ 1304 1305 sc->sc_flags &= ~FXPF_WANTINIT; 1306 1307 /* 1308 * Initialize base of CBL and RFA memory. Loading with zero 1309 * sets it up for regular linear addressing. 1310 */ 1311 fxp_scb_wait(sc); 1312 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1313 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1314 1315 fxp_scb_wait(sc); 1316 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1317 1318 /* 1319 * Initialize the multicast filter. Do this now, since we might 1320 * have to setup the config block differently. 1321 */ 1322 fxp_mc_setup(sc); 1323 1324 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1325 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1326 1327 /* 1328 * In order to support receiving 802.1Q VLAN frames, we have to 1329 * enable "save bad frames", since they are 4 bytes larger than 1330 * the normal Ethernet maximum frame length. 1331 */ 1332 save_bf = (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1 : 0; 1333 1334 /* 1335 * Initialize base of dump-stats buffer. 1336 */ 1337 fxp_scb_wait(sc); 1338 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1339 sc->sc_cddma + FXP_CDSTATSOFF); 1340 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1341 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1342 1343 cbp = &sc->sc_control_data->fcd_configcb; 1344 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1345 1346 /* 1347 * This copy is kind of disgusting, but there are a bunch of must be 1348 * zero and must be one bits in this structure and this is the easiest 1349 * way to initialize them all to proper values. 1350 */ 1351 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1352 1353 /* BIG_ENDIAN: no need to swap to store 0 */ 1354 cbp->cb_status = 0; 1355 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1356 FXP_CB_COMMAND_EL); 1357 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1358 cbp->link_addr = 0xffffffff; /* (no) next command */ 1359 cbp->byte_count = 22; /* (22) bytes to config */ 1360 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1361 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1362 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1363 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1364 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1365 cbp->dma_bce = 0; /* (disable) dma max counters */ 1366 cbp->late_scb = 0; /* (don't) defer SCB update */ 1367 cbp->tno_int = 0; /* (disable) tx not okay interrupt */ 1368 cbp->ci_int = 1; /* interrupt on CU idle */ 1369 cbp->save_bf = save_bf;/* save bad frames */ 1370 cbp->disc_short_rx = !prm; /* discard short packets */ 1371 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1372 cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */ 1373 cbp->nsai = 1; /* (don't) disable source addr insert */ 1374 cbp->preamble_length = 2; /* (7 byte) preamble */ 1375 cbp->loopback = 0; /* (don't) loopback */ 1376 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1377 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1378 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1379 cbp->promiscuous = prm; /* promiscuous mode */ 1380 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1381 cbp->crscdt = 0; /* (CRS only) */ 1382 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1383 cbp->padding = 1; /* (do) pad short tx packets */ 1384 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1385 cbp->force_fdx = 0; /* (don't) force full duplex */ 1386 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1387 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1388 cbp->mc_all = allm; /* accept all multicasts */ 1389 1390 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1391 1392 /* 1393 * Start the config command/DMA. 1394 */ 1395 fxp_scb_wait(sc); 1396 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1397 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1398 /* ...and wait for it to complete. */ 1399 i = 1000; 1400 do { 1401 FXP_CDCONFIGSYNC(sc, 1402 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1403 DELAY(1); 1404 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1405 if (i == 0) { 1406 printf("%s at line %d: dmasync timeout\n", 1407 sc->sc_dev.dv_xname, __LINE__); 1408 return ETIMEDOUT; 1409 } 1410 1411 /* 1412 * Initialize the station address. 1413 */ 1414 cb_ias = &sc->sc_control_data->fcd_iascb; 1415 /* BIG_ENDIAN: no need to swap to store 0 */ 1416 cb_ias->cb_status = 0; 1417 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1418 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1419 cb_ias->link_addr = 0xffffffff; 1420 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1421 1422 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1423 1424 /* 1425 * Start the IAS (Individual Address Setup) command/DMA. 1426 */ 1427 fxp_scb_wait(sc); 1428 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1429 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1430 /* ...and wait for it to complete. */ 1431 i = 1000; 1432 do { 1433 FXP_CDIASSYNC(sc, 1434 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1435 DELAY(1); 1436 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1437 if (i == 0) { 1438 printf("%s at line %d: dmasync timeout\n", 1439 sc->sc_dev.dv_xname, __LINE__); 1440 return ETIMEDOUT; 1441 } 1442 1443 /* 1444 * Initialize the transmit descriptor ring. txlast is initialized 1445 * to the end of the list so that it will wrap around to the first 1446 * descriptor when the first packet is transmitted. 1447 */ 1448 for (i = 0; i < FXP_NTXCB; i++) { 1449 txd = FXP_CDTX(sc, i); 1450 memset(txd, 0, sizeof(*txd)); 1451 txd->txd_txcb.cb_command = 1452 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1453 txd->txd_txcb.tbd_array_addr = htole32(FXP_CDTBDADDR(sc, i)); 1454 txd->txd_txcb.link_addr = 1455 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1456 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1457 } 1458 sc->sc_txpending = 0; 1459 sc->sc_txdirty = 0; 1460 sc->sc_txlast = FXP_NTXCB - 1; 1461 1462 /* 1463 * Initialize the receive buffer list. 1464 */ 1465 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1466 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1467 rxmap = FXP_RXMAP_GET(sc); 1468 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1469 printf("%s: unable to allocate or map rx " 1470 "buffer %d, error = %d\n", 1471 sc->sc_dev.dv_xname, 1472 sc->sc_rxq.ifq_len, error); 1473 /* 1474 * XXX Should attempt to run with fewer receive 1475 * XXX buffers instead of just failing. 1476 */ 1477 FXP_RXMAP_PUT(sc, rxmap); 1478 fxp_rxdrain(sc); 1479 goto out; 1480 } 1481 } 1482 sc->sc_rxidle = 0; 1483 1484 /* 1485 * Give the transmit ring to the chip. We do this by pointing 1486 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1487 * issuing a start command. It will execute the NOP and then 1488 * suspend, pointing at the first descriptor. 1489 */ 1490 fxp_scb_wait(sc); 1491 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1492 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1493 1494 /* 1495 * Initialize receiver buffer area - RFA. 1496 */ 1497 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1498 fxp_scb_wait(sc); 1499 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1500 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1501 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1502 1503 if (sc->sc_flags & FXPF_MII) { 1504 /* 1505 * Set current media. 1506 */ 1507 mii_mediachg(&sc->sc_mii); 1508 } 1509 1510 /* 1511 * ...all done! 1512 */ 1513 ifp->if_flags |= IFF_RUNNING; 1514 ifp->if_flags &= ~IFF_OACTIVE; 1515 1516 /* 1517 * Start the one second timer. 1518 */ 1519 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1520 1521 /* 1522 * Attempt to start output on the interface. 1523 */ 1524 fxp_start(ifp); 1525 1526 out: 1527 if (error) { 1528 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1529 ifp->if_timer = 0; 1530 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1531 } 1532 return (error); 1533 } 1534 1535 /* 1536 * Change media according to request. 1537 */ 1538 int 1539 fxp_mii_mediachange(struct ifnet *ifp) 1540 { 1541 struct fxp_softc *sc = ifp->if_softc; 1542 1543 if (ifp->if_flags & IFF_UP) 1544 mii_mediachg(&sc->sc_mii); 1545 return (0); 1546 } 1547 1548 /* 1549 * Notify the world which media we're using. 1550 */ 1551 void 1552 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1553 { 1554 struct fxp_softc *sc = ifp->if_softc; 1555 1556 if(sc->sc_enabled == 0) { 1557 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1558 ifmr->ifm_status = 0; 1559 return; 1560 } 1561 1562 mii_pollstat(&sc->sc_mii); 1563 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1564 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1565 } 1566 1567 int 1568 fxp_80c24_mediachange(struct ifnet *ifp) 1569 { 1570 1571 /* Nothing to do here. */ 1572 return (0); 1573 } 1574 1575 void 1576 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1577 { 1578 struct fxp_softc *sc = ifp->if_softc; 1579 1580 /* 1581 * Media is currently-selected media. We cannot determine 1582 * the link status. 1583 */ 1584 ifmr->ifm_status = 0; 1585 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1586 } 1587 1588 /* 1589 * Add a buffer to the end of the RFA buffer list. 1590 * Return 0 if successful, error code on failure. 1591 * 1592 * The RFA struct is stuck at the beginning of mbuf cluster and the 1593 * data pointer is fixed up to point just past it. 1594 */ 1595 int 1596 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1597 { 1598 struct mbuf *m; 1599 int error; 1600 1601 MGETHDR(m, M_DONTWAIT, MT_DATA); 1602 if (m == NULL) 1603 return (ENOBUFS); 1604 1605 MCLGET(m, M_DONTWAIT); 1606 if ((m->m_flags & M_EXT) == 0) { 1607 m_freem(m); 1608 return (ENOBUFS); 1609 } 1610 1611 if (unload) 1612 bus_dmamap_unload(sc->sc_dmat, rxmap); 1613 1614 M_SETCTX(m, rxmap); 1615 1616 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1617 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1618 if (error) { 1619 printf("%s: can't load rx DMA map %d, error = %d\n", 1620 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1621 panic("fxp_add_rfabuf"); /* XXX */ 1622 } 1623 1624 FXP_INIT_RFABUF(sc, m); 1625 1626 return (0); 1627 } 1628 1629 int 1630 fxp_mdi_read(struct device *self, int phy, int reg) 1631 { 1632 struct fxp_softc *sc = (struct fxp_softc *)self; 1633 int count = 10000; 1634 int value; 1635 1636 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1637 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1638 1639 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1640 && count--) 1641 DELAY(10); 1642 1643 if (count <= 0) 1644 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1645 1646 return (value & 0xffff); 1647 } 1648 1649 void 1650 fxp_statchg(struct device *self) 1651 { 1652 struct fxp_softc *sc = (void *) self; 1653 1654 /* 1655 * Determine whether or not we have to work-around the 1656 * Resume Bug. 1657 */ 1658 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1659 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1660 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1661 else 1662 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1663 } 1664 } 1665 1666 void 1667 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1668 { 1669 struct fxp_softc *sc = (struct fxp_softc *)self; 1670 int count = 10000; 1671 1672 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1673 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1674 (value & 0xffff)); 1675 1676 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1677 count--) 1678 DELAY(10); 1679 1680 if (count <= 0) 1681 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1682 } 1683 1684 int 1685 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1686 { 1687 struct fxp_softc *sc = ifp->if_softc; 1688 struct ifreq *ifr = (struct ifreq *)data; 1689 int s, error; 1690 1691 s = splnet(); 1692 1693 switch (cmd) { 1694 case SIOCSIFMEDIA: 1695 case SIOCGIFMEDIA: 1696 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1697 break; 1698 1699 default: 1700 error = ether_ioctl(ifp, cmd, data); 1701 if (error == ENETRESET) { 1702 if (sc->sc_enabled) { 1703 /* 1704 * Multicast list has changed; set the 1705 * hardware filter accordingly. 1706 */ 1707 if (sc->sc_txpending) { 1708 sc->sc_flags |= FXPF_WANTINIT; 1709 error = 0; 1710 } else 1711 error = fxp_init(ifp); 1712 } else 1713 error = 0; 1714 } 1715 break; 1716 } 1717 1718 /* Try to get more packets going. */ 1719 if (sc->sc_enabled) 1720 fxp_start(ifp); 1721 1722 splx(s); 1723 return (error); 1724 } 1725 1726 /* 1727 * Program the multicast filter. 1728 * 1729 * This function must be called at splnet(). 1730 */ 1731 void 1732 fxp_mc_setup(struct fxp_softc *sc) 1733 { 1734 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1735 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1736 struct ethercom *ec = &sc->sc_ethercom; 1737 struct ether_multi *enm; 1738 struct ether_multistep step; 1739 int count, nmcasts; 1740 1741 #ifdef DIAGNOSTIC 1742 if (sc->sc_txpending) 1743 panic("fxp_mc_setup: pending transmissions"); 1744 #endif 1745 1746 ifp->if_flags &= ~IFF_ALLMULTI; 1747 1748 /* 1749 * Initialize multicast setup descriptor. 1750 */ 1751 nmcasts = 0; 1752 ETHER_FIRST_MULTI(step, ec, enm); 1753 while (enm != NULL) { 1754 /* 1755 * Check for too many multicast addresses or if we're 1756 * listening to a range. Either way, we simply have 1757 * to accept all multicasts. 1758 */ 1759 if (nmcasts >= MAXMCADDR || 1760 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1761 ETHER_ADDR_LEN) != 0) { 1762 /* 1763 * Callers of this function must do the 1764 * right thing with this. If we're called 1765 * from outside fxp_init(), the caller must 1766 * detect if the state if IFF_ALLMULTI changes. 1767 * If it does, the caller must then call 1768 * fxp_init(), since allmulti is handled by 1769 * the config block. 1770 */ 1771 ifp->if_flags |= IFF_ALLMULTI; 1772 return; 1773 } 1774 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1775 ETHER_ADDR_LEN); 1776 nmcasts++; 1777 ETHER_NEXT_MULTI(step, enm); 1778 } 1779 1780 /* BIG_ENDIAN: no need to swap to store 0 */ 1781 mcsp->cb_status = 0; 1782 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1783 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1784 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1785 1786 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1787 1788 /* 1789 * Wait until the command unit is not active. This should never 1790 * happen since nothing is queued, but make sure anyway. 1791 */ 1792 count = 100; 1793 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1794 FXP_SCB_CUS_ACTIVE && --count) 1795 DELAY(1); 1796 if (count == 0) { 1797 printf("%s at line %d: command queue timeout\n", 1798 sc->sc_dev.dv_xname, __LINE__); 1799 return; 1800 } 1801 1802 /* 1803 * Start the multicast setup command/DMA. 1804 */ 1805 fxp_scb_wait(sc); 1806 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1807 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1808 1809 /* ...and wait for it to complete. */ 1810 count = 1000; 1811 do { 1812 FXP_CDMCSSYNC(sc, 1813 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1814 DELAY(1); 1815 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1816 if (count == 0) { 1817 printf("%s at line %d: dmasync timeout\n", 1818 sc->sc_dev.dv_xname, __LINE__); 1819 return; 1820 } 1821 } 1822 1823 int 1824 fxp_enable(struct fxp_softc *sc) 1825 { 1826 1827 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1828 if ((*sc->sc_enable)(sc) != 0) { 1829 printf("%s: device enable failed\n", 1830 sc->sc_dev.dv_xname); 1831 return (EIO); 1832 } 1833 } 1834 1835 sc->sc_enabled = 1; 1836 return (0); 1837 } 1838 1839 void 1840 fxp_disable(struct fxp_softc *sc) 1841 { 1842 1843 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1844 (*sc->sc_disable)(sc); 1845 sc->sc_enabled = 0; 1846 } 1847 } 1848 1849 /* 1850 * fxp_activate: 1851 * 1852 * Handle device activation/deactivation requests. 1853 */ 1854 int 1855 fxp_activate(struct device *self, enum devact act) 1856 { 1857 struct fxp_softc *sc = (void *) self; 1858 int s, error = 0; 1859 1860 s = splnet(); 1861 switch (act) { 1862 case DVACT_ACTIVATE: 1863 error = EOPNOTSUPP; 1864 break; 1865 1866 case DVACT_DEACTIVATE: 1867 if (sc->sc_flags & FXPF_MII) 1868 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1869 MII_OFFSET_ANY); 1870 if_deactivate(&sc->sc_ethercom.ec_if); 1871 break; 1872 } 1873 splx(s); 1874 1875 return (error); 1876 } 1877 1878 /* 1879 * fxp_detach: 1880 * 1881 * Detach an i82557 interface. 1882 */ 1883 int 1884 fxp_detach(struct fxp_softc *sc) 1885 { 1886 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1887 int i; 1888 1889 /* Succeed now if there's no work to do. */ 1890 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1891 return (0); 1892 1893 /* Unhook our tick handler. */ 1894 callout_stop(&sc->sc_callout); 1895 1896 if (sc->sc_flags & FXPF_MII) { 1897 /* Detach all PHYs */ 1898 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1899 } 1900 1901 /* Delete all remaining media. */ 1902 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1903 1904 #if NRND > 0 1905 rnd_detach_source(&sc->rnd_source); 1906 #endif 1907 ether_ifdetach(ifp); 1908 if_detach(ifp); 1909 1910 for (i = 0; i < FXP_NRFABUFS; i++) { 1911 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1912 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1913 } 1914 1915 for (i = 0; i < FXP_NTXCB; i++) { 1916 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1917 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1918 } 1919 1920 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1921 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1922 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1923 sizeof(struct fxp_control_data)); 1924 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1925 1926 shutdownhook_disestablish(sc->sc_sdhook); 1927 powerhook_disestablish(sc->sc_powerhook); 1928 1929 return (0); 1930 } 1931
Indexes created Tue Sep 30 11:09:46 GMT 2025