i82557.c revision 1.52
1 /* $NetBSD: i82557.c,v 1.52 2001/05/22 15:29:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include "opt_inet.h" 76 #include "opt_ns.h" 77 #include "bpfilter.h" 78 #include "rnd.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 91 #include <machine/endian.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NBPFILTER > 0 105 #include <net/bpf.h> 106 #endif 107 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 113 #ifdef NS 114 #include <netns/ns.h> 115 #include <netns/ns_if.h> 116 #endif 117 118 #include <machine/bus.h> 119 #include <machine/intr.h> 120 121 #include <dev/mii/miivar.h> 122 123 #include <dev/ic/i82557reg.h> 124 #include <dev/ic/i82557var.h> 125 126 /* 127 * NOTE! On the Alpha, we have an alignment constraint. The 128 * card DMAs the packet immediately following the RFA. However, 129 * the first thing in the packet is a 14-byte Ethernet header. 130 * This means that the packet is misaligned. To compensate, 131 * we actually offset the RFA 2 bytes into the cluster. This 132 * alignes the packet after the Ethernet header at a 32-bit 133 * boundary. HOWEVER! This means that the RFA is misaligned! 134 */ 135 #define RFA_ALIGNMENT_FUDGE 2 136 137 /* 138 * The configuration byte map has several undefined fields which 139 * must be one or must be zero. Set up a template for these bits 140 * only (assuming an i82557 chip), leaving the actual configuration 141 * for fxp_init(). 142 * 143 * See the definition of struct fxp_cb_config for the bit definitions. 144 */ 145 const u_int8_t fxp_cb_config_template[] = { 146 0x0, 0x0, /* cb_status */ 147 0x0, 0x0, /* cb_command */ 148 0x0, 0x0, 0x0, 0x0, /* link_addr */ 149 0x0, /* 0 */ 150 0x0, /* 1 */ 151 0x0, /* 2 */ 152 0x0, /* 3 */ 153 0x0, /* 4 */ 154 0x0, /* 5 */ 155 0x32, /* 6 */ 156 0x0, /* 7 */ 157 0x0, /* 8 */ 158 0x0, /* 9 */ 159 0x6, /* 10 */ 160 0x0, /* 11 */ 161 0x0, /* 12 */ 162 0x0, /* 13 */ 163 0xf2, /* 14 */ 164 0x48, /* 15 */ 165 0x0, /* 16 */ 166 0x40, /* 17 */ 167 0xf0, /* 18 */ 168 0x0, /* 19 */ 169 0x3f, /* 20 */ 170 0x5 /* 21 */ 171 }; 172 173 void fxp_mii_initmedia(struct fxp_softc *); 174 int fxp_mii_mediachange(struct ifnet *); 175 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 176 177 void fxp_80c24_initmedia(struct fxp_softc *); 178 int fxp_80c24_mediachange(struct ifnet *); 179 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 180 181 void fxp_start(struct ifnet *); 182 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 183 void fxp_watchdog(struct ifnet *); 184 int fxp_init(struct ifnet *); 185 void fxp_stop(struct ifnet *, int); 186 187 void fxp_rxdrain(struct fxp_softc *); 188 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 189 int fxp_mdi_read(struct device *, int, int); 190 void fxp_statchg(struct device *); 191 void fxp_mdi_write(struct device *, int, int, int); 192 void fxp_autosize_eeprom(struct fxp_softc*); 193 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 194 void fxp_get_info(struct fxp_softc *, u_int8_t *); 195 void fxp_tick(void *); 196 void fxp_mc_setup(struct fxp_softc *); 197 198 void fxp_shutdown(void *); 199 void fxp_power(int, void *); 200 201 int fxp_copy_small = 0; 202 203 struct fxp_phytype { 204 int fp_phy; /* type of PHY, -1 for MII at the end. */ 205 void (*fp_init)(struct fxp_softc *); 206 } fxp_phytype_table[] = { 207 { FXP_PHY_80C24, fxp_80c24_initmedia }, 208 { -1, fxp_mii_initmedia }, 209 }; 210 211 /* 212 * Set initial transmit threshold at 64 (512 bytes). This is 213 * increased by 64 (512 bytes) at a time, to maximum of 192 214 * (1536 bytes), if an underrun occurs. 215 */ 216 static int tx_threshold = 64; 217 218 /* 219 * Wait for the previous command to be accepted (but not necessarily 220 * completed). 221 */ 222 static __inline void 223 fxp_scb_wait(struct fxp_softc *sc) 224 { 225 int i = 10000; 226 227 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 228 delay(2); 229 if (i == 0) 230 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 231 } 232 233 /* 234 * Submit a command to the i82557. 235 */ 236 static __inline void 237 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 238 { 239 240 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 241 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 242 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_NOP); 243 fxp_scb_wait(sc); 244 } 245 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 246 } 247 248 /* 249 * Finish attaching an i82557 interface. Called by bus-specific front-end. 250 */ 251 void 252 fxp_attach(struct fxp_softc *sc) 253 { 254 u_int8_t enaddr[ETHER_ADDR_LEN]; 255 struct ifnet *ifp; 256 bus_dma_segment_t seg; 257 int rseg, i, error; 258 struct fxp_phytype *fp; 259 260 callout_init(&sc->sc_callout); 261 262 /* 263 * Enable some good stuff on i82558 and later. 264 */ 265 if (sc->sc_rev >= FXP_REV_82558_A4) { 266 /* Enable the extended TxCB. */ 267 sc->sc_flags |= FXPF_EXT_TXCB; 268 } 269 270 /* 271 * Allocate the control data structures, and create and load the 272 * DMA map for it. 273 */ 274 if ((error = bus_dmamem_alloc(sc->sc_dmat, 275 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 276 0)) != 0) { 277 printf("%s: unable to allocate control data, error = %d\n", 278 sc->sc_dev.dv_xname, error); 279 goto fail_0; 280 } 281 282 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 283 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 284 BUS_DMA_COHERENT)) != 0) { 285 printf("%s: unable to map control data, error = %d\n", 286 sc->sc_dev.dv_xname, error); 287 goto fail_1; 288 } 289 sc->sc_cdseg = seg; 290 sc->sc_cdnseg = rseg; 291 292 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 293 294 if ((error = bus_dmamap_create(sc->sc_dmat, 295 sizeof(struct fxp_control_data), 1, 296 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 297 printf("%s: unable to create control data DMA map, " 298 "error = %d\n", sc->sc_dev.dv_xname, error); 299 goto fail_2; 300 } 301 302 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 303 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 304 0)) != 0) { 305 printf("%s: can't load control data DMA map, error = %d\n", 306 sc->sc_dev.dv_xname, error); 307 goto fail_3; 308 } 309 310 /* 311 * Create the transmit buffer DMA maps. 312 */ 313 for (i = 0; i < FXP_NTXCB; i++) { 314 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 315 FXP_NTXSEG, MCLBYTES, 0, 0, 316 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 317 printf("%s: unable to create tx DMA map %d, " 318 "error = %d\n", sc->sc_dev.dv_xname, i, error); 319 goto fail_4; 320 } 321 } 322 323 /* 324 * Create the receive buffer DMA maps. 325 */ 326 for (i = 0; i < FXP_NRFABUFS; i++) { 327 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 328 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 329 printf("%s: unable to create rx DMA map %d, " 330 "error = %d\n", sc->sc_dev.dv_xname, i, error); 331 goto fail_5; 332 } 333 } 334 335 /* Initialize MAC address and media structures. */ 336 fxp_get_info(sc, enaddr); 337 338 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 339 ether_sprintf(enaddr)); 340 341 ifp = &sc->sc_ethercom.ec_if; 342 343 /* 344 * Get info about our media interface, and initialize it. Note 345 * the table terminates itself with a phy of -1, indicating 346 * that we're using MII. 347 */ 348 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 349 if (fp->fp_phy == sc->phy_primary_device) 350 break; 351 (*fp->fp_init)(sc); 352 353 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 354 ifp->if_softc = sc; 355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 356 ifp->if_ioctl = fxp_ioctl; 357 ifp->if_start = fxp_start; 358 ifp->if_watchdog = fxp_watchdog; 359 ifp->if_init = fxp_init; 360 ifp->if_stop = fxp_stop; 361 IFQ_SET_READY(&ifp->if_snd); 362 363 /* 364 * We can support 802.1Q VLAN-sized frames. 365 */ 366 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 367 368 /* 369 * Attach the interface. 370 */ 371 if_attach(ifp); 372 ether_ifattach(ifp, enaddr); 373 #if NRND > 0 374 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 375 RND_TYPE_NET, 0); 376 #endif 377 378 /* 379 * Add shutdown hook so that DMA is disabled prior to reboot. Not 380 * doing do could allow DMA to corrupt kernel memory during the 381 * reboot before the driver initializes. 382 */ 383 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 384 if (sc->sc_sdhook == NULL) 385 printf("%s: WARNING: unable to establish shutdown hook\n", 386 sc->sc_dev.dv_xname); 387 /* 388 * Add suspend hook, for similar reasons.. 389 */ 390 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 391 if (sc->sc_powerhook == NULL) 392 printf("%s: WARNING: unable to establish power hook\n", 393 sc->sc_dev.dv_xname); 394 395 /* The attach is successful. */ 396 sc->sc_flags |= FXPF_ATTACHED; 397 398 return; 399 400 /* 401 * Free any resources we've allocated during the failed attach 402 * attempt. Do this in reverse order and fall though. 403 */ 404 fail_5: 405 for (i = 0; i < FXP_NRFABUFS; i++) { 406 if (sc->sc_rxmaps[i] != NULL) 407 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 408 } 409 fail_4: 410 for (i = 0; i < FXP_NTXCB; i++) { 411 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 412 bus_dmamap_destroy(sc->sc_dmat, 413 FXP_DSTX(sc, i)->txs_dmamap); 414 } 415 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 416 fail_3: 417 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 418 fail_2: 419 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 420 sizeof(struct fxp_control_data)); 421 fail_1: 422 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 423 fail_0: 424 return; 425 } 426 427 void 428 fxp_mii_initmedia(struct fxp_softc *sc) 429 { 430 431 sc->sc_flags |= FXPF_MII; 432 433 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 434 sc->sc_mii.mii_readreg = fxp_mdi_read; 435 sc->sc_mii.mii_writereg = fxp_mdi_write; 436 sc->sc_mii.mii_statchg = fxp_statchg; 437 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 438 fxp_mii_mediastatus); 439 /* 440 * The i82557 wedges if all of its PHYs are isolated! 441 */ 442 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 443 MII_OFFSET_ANY, MIIF_NOISOLATE); 444 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 445 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 446 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 447 } else 448 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 449 } 450 451 void 452 fxp_80c24_initmedia(struct fxp_softc *sc) 453 { 454 455 /* 456 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 457 * doesn't have a programming interface of any sort. The 458 * media is sensed automatically based on how the link partner 459 * is configured. This is, in essence, manual configuration. 460 */ 461 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 462 sc->sc_dev.dv_xname); 463 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 464 fxp_80c24_mediastatus); 465 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 466 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 467 } 468 469 /* 470 * Device shutdown routine. Called at system shutdown after sync. The 471 * main purpose of this routine is to shut off receiver DMA so that 472 * kernel memory doesn't get clobbered during warmboot. 473 */ 474 void 475 fxp_shutdown(void *arg) 476 { 477 struct fxp_softc *sc = arg; 478 479 /* 480 * Since the system's going to halt shortly, don't bother 481 * freeing mbufs. 482 */ 483 fxp_stop(&sc->sc_ethercom.ec_if, 0); 484 } 485 /* 486 * Power handler routine. Called when the system is transitioning 487 * into/out of power save modes. As with fxp_shutdown, the main 488 * purpose of this routine is to shut off receiver DMA so it doesn't 489 * clobber kernel memory at the wrong time. 490 */ 491 void 492 fxp_power(int why, void *arg) 493 { 494 struct fxp_softc *sc = arg; 495 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 496 int s; 497 498 s = splnet(); 499 switch (why) { 500 case PWR_SUSPEND: 501 case PWR_STANDBY: 502 fxp_stop(ifp, 0); 503 break; 504 case PWR_RESUME: 505 if (ifp->if_flags & IFF_UP) 506 fxp_init(ifp); 507 break; 508 case PWR_SOFTSUSPEND: 509 case PWR_SOFTSTANDBY: 510 case PWR_SOFTRESUME: 511 break; 512 } 513 splx(s); 514 } 515 516 /* 517 * Initialize the interface media. 518 */ 519 void 520 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 521 { 522 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 523 524 /* 525 * Reset to a stable state. 526 */ 527 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 528 DELAY(10); 529 530 sc->sc_eeprom_size = 0; 531 fxp_autosize_eeprom(sc); 532 if(sc->sc_eeprom_size == 0) { 533 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 534 sc->sc_eeprom_size = 6; /* XXX panic here? */ 535 } 536 #ifdef DEBUG 537 printf("%s: detected %d word EEPROM\n", 538 sc->sc_dev.dv_xname, 539 1 << sc->sc_eeprom_size); 540 #endif 541 542 /* 543 * Get info about the primary PHY 544 */ 545 fxp_read_eeprom(sc, &data, 6, 1); 546 sc->phy_primary_device = 547 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 548 549 /* 550 * Read MAC address. 551 */ 552 fxp_read_eeprom(sc, myea, 0, 3); 553 enaddr[0] = myea[0] & 0xff; 554 enaddr[1] = myea[0] >> 8; 555 enaddr[2] = myea[1] & 0xff; 556 enaddr[3] = myea[1] >> 8; 557 enaddr[4] = myea[2] & 0xff; 558 enaddr[5] = myea[2] >> 8; 559 } 560 561 /* 562 * Figure out EEPROM size. 563 * 564 * 559's can have either 64-word or 256-word EEPROMs, the 558 565 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 566 * talks about the existance of 16 to 256 word EEPROMs. 567 * 568 * The only known sizes are 64 and 256, where the 256 version is used 569 * by CardBus cards to store CIS information. 570 * 571 * The address is shifted in msb-to-lsb, and after the last 572 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 573 * after which follows the actual data. We try to detect this zero, by 574 * probing the data-out bit in the EEPROM control register just after 575 * having shifted in a bit. If the bit is zero, we assume we've 576 * shifted enough address bits. The data-out should be tri-state, 577 * before this, which should translate to a logical one. 578 * 579 * Other ways to do this would be to try to read a register with known 580 * contents with a varying number of address bits, but no such 581 * register seem to be available. The high bits of register 10 are 01 582 * on the 558 and 559, but apparently not on the 557. 583 * 584 * The Linux driver computes a checksum on the EEPROM data, but the 585 * value of this checksum is not very well documented. 586 */ 587 588 void 589 fxp_autosize_eeprom(struct fxp_softc *sc) 590 { 591 u_int16_t reg; 592 int x; 593 594 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 595 /* 596 * Shift in read opcode. 597 */ 598 for (x = 3; x > 0; x--) { 599 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 600 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 601 } else { 602 reg = FXP_EEPROM_EECS; 603 } 604 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 605 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 606 reg | FXP_EEPROM_EESK); 607 DELAY(4); 608 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 609 DELAY(4); 610 } 611 /* 612 * Shift in address, wait for the dummy zero following a correct 613 * address shift. 614 */ 615 for (x = 1; x <= 8; x++) { 616 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 617 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 618 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 619 DELAY(4); 620 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 621 FXP_EEPROM_EEDO) == 0) 622 break; 623 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 624 DELAY(4); 625 } 626 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 627 DELAY(4); 628 if(x != 6 && x != 8) { 629 #ifdef DEBUG 630 printf("%s: strange EEPROM size (%d)\n", 631 sc->sc_dev.dv_xname, 1 << x); 632 #endif 633 } else 634 sc->sc_eeprom_size = x; 635 } 636 637 /* 638 * Read from the serial EEPROM. Basically, you manually shift in 639 * the read opcode (one bit at a time) and then shift in the address, 640 * and then you shift out the data (all of this one bit at a time). 641 * The word size is 16 bits, so you have to provide the address for 642 * every 16 bits of data. 643 */ 644 void 645 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 646 { 647 u_int16_t reg; 648 int i, x; 649 650 for (i = 0; i < words; i++) { 651 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 652 /* 653 * Shift in read opcode. 654 */ 655 for (x = 3; x > 0; x--) { 656 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 657 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 658 } else { 659 reg = FXP_EEPROM_EECS; 660 } 661 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 662 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 663 reg | FXP_EEPROM_EESK); 664 DELAY(4); 665 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 666 DELAY(4); 667 } 668 /* 669 * Shift in address. 670 */ 671 for (x = sc->sc_eeprom_size; x > 0; x--) { 672 if ((i + offset) & (1 << (x - 1))) { 673 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 674 } else { 675 reg = FXP_EEPROM_EECS; 676 } 677 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 679 reg | FXP_EEPROM_EESK); 680 DELAY(4); 681 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 682 DELAY(4); 683 } 684 reg = FXP_EEPROM_EECS; 685 data[i] = 0; 686 /* 687 * Shift out data. 688 */ 689 for (x = 16; x > 0; x--) { 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 691 reg | FXP_EEPROM_EESK); 692 DELAY(4); 693 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 694 FXP_EEPROM_EEDO) 695 data[i] |= (1 << (x - 1)); 696 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 697 DELAY(4); 698 } 699 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 700 DELAY(4); 701 } 702 } 703 704 /* 705 * Start packet transmission on the interface. 706 */ 707 void 708 fxp_start(struct ifnet *ifp) 709 { 710 struct fxp_softc *sc = ifp->if_softc; 711 struct mbuf *m0, *m; 712 struct fxp_txdesc *txd; 713 struct fxp_txsoft *txs; 714 bus_dmamap_t dmamap; 715 int error, lasttx, nexttx, opending, seg; 716 717 /* 718 * If we want a re-init, bail out now. 719 */ 720 if (sc->sc_flags & FXPF_WANTINIT) { 721 ifp->if_flags |= IFF_OACTIVE; 722 return; 723 } 724 725 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 726 return; 727 728 /* 729 * Remember the previous txpending and the current lasttx. 730 */ 731 opending = sc->sc_txpending; 732 lasttx = sc->sc_txlast; 733 734 /* 735 * Loop through the send queue, setting up transmit descriptors 736 * until we drain the queue, or use up all available transmit 737 * descriptors. 738 */ 739 while (sc->sc_txpending < FXP_NTXCB) { 740 /* 741 * Grab a packet off the queue. 742 */ 743 IFQ_POLL(&ifp->if_snd, m0); 744 if (m0 == NULL) 745 break; 746 m = NULL; 747 748 /* 749 * Get the next available transmit descriptor. 750 */ 751 nexttx = FXP_NEXTTX(sc->sc_txlast); 752 txd = FXP_CDTX(sc, nexttx); 753 txs = FXP_DSTX(sc, nexttx); 754 dmamap = txs->txs_dmamap; 755 756 /* 757 * Load the DMA map. If this fails, the packet either 758 * didn't fit in the allotted number of frags, or we were 759 * short on resources. In this case, we'll copy and try 760 * again. 761 */ 762 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 763 BUS_DMA_NOWAIT) != 0) { 764 MGETHDR(m, M_DONTWAIT, MT_DATA); 765 if (m == NULL) { 766 printf("%s: unable to allocate Tx mbuf\n", 767 sc->sc_dev.dv_xname); 768 break; 769 } 770 if (m0->m_pkthdr.len > MHLEN) { 771 MCLGET(m, M_DONTWAIT); 772 if ((m->m_flags & M_EXT) == 0) { 773 printf("%s: unable to allocate Tx " 774 "cluster\n", sc->sc_dev.dv_xname); 775 m_freem(m); 776 break; 777 } 778 } 779 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 780 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 781 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 782 m, BUS_DMA_NOWAIT); 783 if (error) { 784 printf("%s: unable to load Tx buffer, " 785 "error = %d\n", sc->sc_dev.dv_xname, error); 786 break; 787 } 788 } 789 790 IFQ_DEQUEUE(&ifp->if_snd, m0); 791 if (m != NULL) { 792 m_freem(m0); 793 m0 = m; 794 } 795 796 /* Initialize the fraglist. */ 797 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 798 txd->txd_tbd[seg].tb_addr = 799 htole32(dmamap->dm_segs[seg].ds_addr); 800 txd->txd_tbd[seg].tb_size = 801 htole32(dmamap->dm_segs[seg].ds_len); 802 } 803 804 /* Sync the DMA map. */ 805 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 806 BUS_DMASYNC_PREWRITE); 807 808 /* 809 * Store a pointer to the packet so we can free it later. 810 */ 811 txs->txs_mbuf = m0; 812 813 /* 814 * Initialize the transmit descriptor. 815 */ 816 /* BIG_ENDIAN: no need to swap to store 0 */ 817 txd->txd_txcb.cb_status = 0; 818 txd->txd_txcb.cb_command = 819 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 820 txd->txd_txcb.tx_threshold = tx_threshold; 821 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 822 823 FXP_CDTXSYNC(sc, nexttx, 824 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 825 826 /* Advance the tx pointer. */ 827 sc->sc_txpending++; 828 sc->sc_txlast = nexttx; 829 830 #if NBPFILTER > 0 831 /* 832 * Pass packet to bpf if there is a listener. 833 */ 834 if (ifp->if_bpf) 835 bpf_mtap(ifp->if_bpf, m0); 836 #endif 837 } 838 839 if (sc->sc_txpending == FXP_NTXCB) { 840 /* No more slots; notify upper layer. */ 841 ifp->if_flags |= IFF_OACTIVE; 842 } 843 844 if (sc->sc_txpending != opending) { 845 /* 846 * We enqueued packets. If the transmitter was idle, 847 * reset the txdirty pointer. 848 */ 849 if (opending == 0) 850 sc->sc_txdirty = FXP_NEXTTX(lasttx); 851 852 /* 853 * Cause the chip to interrupt and suspend command 854 * processing once the last packet we've enqueued 855 * has been transmitted. 856 */ 857 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 858 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 859 FXP_CDTXSYNC(sc, sc->sc_txlast, 860 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 861 862 /* 863 * The entire packet chain is set up. Clear the suspend bit 864 * on the command prior to the first packet we set up. 865 */ 866 FXP_CDTXSYNC(sc, lasttx, 867 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 868 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 869 htole16(~FXP_CB_COMMAND_S); 870 FXP_CDTXSYNC(sc, lasttx, 871 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 872 873 /* 874 * Issue a Resume command in case the chip was suspended. 875 */ 876 fxp_scb_wait(sc); 877 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 878 879 /* Set a watchdog timer in case the chip flakes out. */ 880 ifp->if_timer = 5; 881 } 882 } 883 884 /* 885 * Process interface interrupts. 886 */ 887 int 888 fxp_intr(void *arg) 889 { 890 struct fxp_softc *sc = arg; 891 struct ethercom *ec = &sc->sc_ethercom; 892 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 893 struct fxp_txdesc *txd; 894 struct fxp_txsoft *txs; 895 struct mbuf *m, *m0; 896 bus_dmamap_t rxmap; 897 struct fxp_rfa *rfa; 898 int i, claimed = 0; 899 u_int16_t len, rxstat, txstat; 900 u_int8_t statack; 901 902 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 903 return (0); 904 /* 905 * If the interface isn't running, don't try to 906 * service the interrupt.. just ack it and bail. 907 */ 908 if ((ifp->if_flags & IFF_RUNNING) == 0) { 909 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 910 if (statack) { 911 claimed = 1; 912 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 913 } 914 return (claimed); 915 } 916 917 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 918 claimed = 1; 919 920 /* 921 * First ACK all the interrupts in this pass. 922 */ 923 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 924 925 /* 926 * Process receiver interrupts. If a no-resource (RNR) 927 * condition exists, get whatever packets we can and 928 * re-start the receiver. 929 */ 930 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 931 rcvloop: 932 m = sc->sc_rxq.ifq_head; 933 rfa = FXP_MTORFA(m); 934 rxmap = M_GETCTX(m, bus_dmamap_t); 935 936 FXP_RFASYNC(sc, m, 937 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 938 939 rxstat = le16toh(rfa->rfa_status); 940 941 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 942 /* 943 * We have processed all of the 944 * receive buffers. 945 */ 946 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 947 goto do_transmit; 948 } 949 950 IF_DEQUEUE(&sc->sc_rxq, m); 951 952 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 953 954 len = le16toh(rfa->actual_size) & 955 (m->m_ext.ext_size - 1); 956 957 if (len < sizeof(struct ether_header)) { 958 /* 959 * Runt packet; drop it now. 960 */ 961 FXP_INIT_RFABUF(sc, m); 962 goto rcvloop; 963 } 964 965 /* 966 * If support for 802.1Q VLAN sized frames is 967 * enabled, we need to do some additional error 968 * checking (as we are saving bad frames, in 969 * order to receive the larger ones). 970 */ 971 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 972 (rxstat & (FXP_RFA_STATUS_OVERRUN| 973 FXP_RFA_STATUS_RNR| 974 FXP_RFA_STATUS_ALIGN| 975 FXP_RFA_STATUS_CRC)) != 0) { 976 FXP_INIT_RFABUF(sc, m); 977 goto rcvloop; 978 } 979 980 /* 981 * If the packet is small enough to fit in a 982 * single header mbuf, allocate one and copy 983 * the data into it. This greatly reduces 984 * memory consumption when we receive lots 985 * of small packets. 986 * 987 * Otherwise, we add a new buffer to the receive 988 * chain. If this fails, we drop the packet and 989 * recycle the old buffer. 990 */ 991 if (fxp_copy_small != 0 && len <= MHLEN) { 992 MGETHDR(m0, M_DONTWAIT, MT_DATA); 993 if (m == NULL) 994 goto dropit; 995 memcpy(mtod(m0, caddr_t), 996 mtod(m, caddr_t), len); 997 FXP_INIT_RFABUF(sc, m); 998 m = m0; 999 } else { 1000 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1001 dropit: 1002 ifp->if_ierrors++; 1003 FXP_INIT_RFABUF(sc, m); 1004 goto rcvloop; 1005 } 1006 } 1007 1008 m->m_pkthdr.rcvif = ifp; 1009 m->m_pkthdr.len = m->m_len = len; 1010 1011 #if NBPFILTER > 0 1012 /* 1013 * Pass this up to any BPF listeners, but only 1014 * pass it up the stack it its for us. 1015 */ 1016 if (ifp->if_bpf) 1017 bpf_mtap(ifp->if_bpf, m); 1018 #endif 1019 1020 /* Pass it on. */ 1021 (*ifp->if_input)(ifp, m); 1022 goto rcvloop; 1023 } 1024 1025 do_transmit: 1026 if (statack & FXP_SCB_STATACK_RNR) { 1027 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1028 fxp_scb_wait(sc); 1029 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1030 rxmap->dm_segs[0].ds_addr + 1031 RFA_ALIGNMENT_FUDGE); 1032 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1033 } 1034 1035 /* 1036 * Free any finished transmit mbuf chains. 1037 */ 1038 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1039 ifp->if_flags &= ~IFF_OACTIVE; 1040 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1041 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1042 txd = FXP_CDTX(sc, i); 1043 txs = FXP_DSTX(sc, i); 1044 1045 FXP_CDTXSYNC(sc, i, 1046 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1047 1048 txstat = le16toh(txd->txd_txcb.cb_status); 1049 1050 if ((txstat & FXP_CB_STATUS_C) == 0) 1051 break; 1052 1053 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1054 0, txs->txs_dmamap->dm_mapsize, 1055 BUS_DMASYNC_POSTWRITE); 1056 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1057 m_freem(txs->txs_mbuf); 1058 txs->txs_mbuf = NULL; 1059 } 1060 1061 /* Update the dirty transmit buffer pointer. */ 1062 sc->sc_txdirty = i; 1063 1064 /* 1065 * Cancel the watchdog timer if there are no pending 1066 * transmissions. 1067 */ 1068 if (sc->sc_txpending == 0) { 1069 ifp->if_timer = 0; 1070 1071 /* 1072 * If we want a re-init, do that now. 1073 */ 1074 if (sc->sc_flags & FXPF_WANTINIT) 1075 (void) fxp_init(ifp); 1076 } 1077 1078 /* 1079 * Try to get more packets going. 1080 */ 1081 fxp_start(ifp); 1082 } 1083 } 1084 1085 #if NRND > 0 1086 if (claimed) 1087 rnd_add_uint32(&sc->rnd_source, statack); 1088 #endif 1089 return (claimed); 1090 } 1091 1092 /* 1093 * Update packet in/out/collision statistics. The i82557 doesn't 1094 * allow you to access these counters without doing a fairly 1095 * expensive DMA to get _all_ of the statistics it maintains, so 1096 * we do this operation here only once per second. The statistics 1097 * counters in the kernel are updated from the previous dump-stats 1098 * DMA and then a new dump-stats DMA is started. The on-chip 1099 * counters are zeroed when the DMA completes. If we can't start 1100 * the DMA immediately, we don't wait - we just prepare to read 1101 * them again next time. 1102 */ 1103 void 1104 fxp_tick(void *arg) 1105 { 1106 struct fxp_softc *sc = arg; 1107 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1108 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1109 int s; 1110 1111 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1112 return; 1113 1114 s = splnet(); 1115 1116 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1117 1118 ifp->if_opackets += le32toh(sp->tx_good); 1119 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1120 if (sp->rx_good) { 1121 ifp->if_ipackets += le32toh(sp->rx_good); 1122 sc->sc_rxidle = 0; 1123 } else { 1124 sc->sc_rxidle++; 1125 } 1126 ifp->if_ierrors += 1127 le32toh(sp->rx_crc_errors) + 1128 le32toh(sp->rx_alignment_errors) + 1129 le32toh(sp->rx_rnr_errors) + 1130 le32toh(sp->rx_overrun_errors); 1131 /* 1132 * If any transmit underruns occured, bump up the transmit 1133 * threshold by another 512 bytes (64 * 8). 1134 */ 1135 if (sp->tx_underruns) { 1136 ifp->if_oerrors += le32toh(sp->tx_underruns); 1137 if (tx_threshold < 192) 1138 tx_threshold += 64; 1139 } 1140 1141 /* 1142 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1143 * then assume the receiver has locked up and attempt to clear 1144 * the condition by reprogramming the multicast filter (actually, 1145 * resetting the interface). This is a work-around for a bug in 1146 * the 82557 where the receiver locks up if it gets certain types 1147 * of garbage in the syncronization bits prior to the packet header. 1148 * This bug is supposed to only occur in 10Mbps mode, but has been 1149 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1150 * speed transition). 1151 */ 1152 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1153 (void) fxp_init(ifp); 1154 splx(s); 1155 return; 1156 } 1157 /* 1158 * If there is no pending command, start another stats 1159 * dump. Otherwise punt for now. 1160 */ 1161 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1162 /* 1163 * Start another stats dump. 1164 */ 1165 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1166 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1167 } else { 1168 /* 1169 * A previous command is still waiting to be accepted. 1170 * Just zero our copy of the stats and wait for the 1171 * next timer event to update them. 1172 */ 1173 /* BIG_ENDIAN: no swap required to store 0 */ 1174 sp->tx_good = 0; 1175 sp->tx_underruns = 0; 1176 sp->tx_total_collisions = 0; 1177 1178 sp->rx_good = 0; 1179 sp->rx_crc_errors = 0; 1180 sp->rx_alignment_errors = 0; 1181 sp->rx_rnr_errors = 0; 1182 sp->rx_overrun_errors = 0; 1183 } 1184 1185 if (sc->sc_flags & FXPF_MII) { 1186 /* Tick the MII clock. */ 1187 mii_tick(&sc->sc_mii); 1188 } 1189 1190 splx(s); 1191 1192 /* 1193 * Schedule another timeout one second from now. 1194 */ 1195 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1196 } 1197 1198 /* 1199 * Drain the receive queue. 1200 */ 1201 void 1202 fxp_rxdrain(struct fxp_softc *sc) 1203 { 1204 bus_dmamap_t rxmap; 1205 struct mbuf *m; 1206 1207 for (;;) { 1208 IF_DEQUEUE(&sc->sc_rxq, m); 1209 if (m == NULL) 1210 break; 1211 rxmap = M_GETCTX(m, bus_dmamap_t); 1212 bus_dmamap_unload(sc->sc_dmat, rxmap); 1213 FXP_RXMAP_PUT(sc, rxmap); 1214 m_freem(m); 1215 } 1216 } 1217 1218 /* 1219 * Stop the interface. Cancels the statistics updater and resets 1220 * the interface. 1221 */ 1222 void 1223 fxp_stop(struct ifnet *ifp, int disable) 1224 { 1225 struct fxp_softc *sc = ifp->if_softc; 1226 struct fxp_txsoft *txs; 1227 int i; 1228 1229 /* 1230 * Turn down interface (done early to avoid bad interactions 1231 * between panics, shutdown hooks, and the watchdog timer) 1232 */ 1233 ifp->if_timer = 0; 1234 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1235 1236 /* 1237 * Cancel stats updater. 1238 */ 1239 callout_stop(&sc->sc_callout); 1240 if (sc->sc_flags & FXPF_MII) { 1241 /* Down the MII. */ 1242 mii_down(&sc->sc_mii); 1243 } 1244 1245 /* 1246 * Issue software reset 1247 */ 1248 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1249 DELAY(10); 1250 1251 /* 1252 * Release any xmit buffers. 1253 */ 1254 for (i = 0; i < FXP_NTXCB; i++) { 1255 txs = FXP_DSTX(sc, i); 1256 if (txs->txs_mbuf != NULL) { 1257 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1258 m_freem(txs->txs_mbuf); 1259 txs->txs_mbuf = NULL; 1260 } 1261 } 1262 sc->sc_txpending = 0; 1263 1264 if (disable) { 1265 fxp_rxdrain(sc); 1266 fxp_disable(sc); 1267 } 1268 1269 } 1270 1271 /* 1272 * Watchdog/transmission transmit timeout handler. Called when a 1273 * transmission is started on the interface, but no interrupt is 1274 * received before the timeout. This usually indicates that the 1275 * card has wedged for some reason. 1276 */ 1277 void 1278 fxp_watchdog(struct ifnet *ifp) 1279 { 1280 struct fxp_softc *sc = ifp->if_softc; 1281 1282 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1283 ifp->if_oerrors++; 1284 1285 (void) fxp_init(ifp); 1286 } 1287 1288 /* 1289 * Initialize the interface. Must be called at splnet(). 1290 */ 1291 int 1292 fxp_init(struct ifnet *ifp) 1293 { 1294 struct fxp_softc *sc = ifp->if_softc; 1295 struct fxp_cb_config *cbp; 1296 struct fxp_cb_ias *cb_ias; 1297 struct fxp_txdesc *txd; 1298 bus_dmamap_t rxmap; 1299 int i, prm, save_bf, lrxen, allm, error = 0; 1300 1301 if ((error = fxp_enable(sc)) != 0) 1302 goto out; 1303 1304 /* 1305 * Cancel any pending I/O 1306 */ 1307 fxp_stop(ifp, 0); 1308 1309 /* 1310 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1311 * flag, and this prevents the MII from detaching resulting in 1312 * a panic. The flags field should perhaps be split in runtime 1313 * flags and more static information. For now, just clear the 1314 * only other flag set. 1315 */ 1316 1317 sc->sc_flags &= ~FXPF_WANTINIT; 1318 1319 /* 1320 * Initialize base of CBL and RFA memory. Loading with zero 1321 * sets it up for regular linear addressing. 1322 */ 1323 fxp_scb_wait(sc); 1324 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1325 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1326 1327 fxp_scb_wait(sc); 1328 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1329 1330 /* 1331 * Initialize the multicast filter. Do this now, since we might 1332 * have to setup the config block differently. 1333 */ 1334 fxp_mc_setup(sc); 1335 1336 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1337 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1338 1339 /* 1340 * In order to support receiving 802.1Q VLAN frames, we have to 1341 * enable "save bad frames", since they are 4 bytes larger than 1342 * the normal Ethernet maximum frame length. On i82558 and later, 1343 * we have a better mechanism for this. 1344 */ 1345 save_bf = 0; 1346 lrxen = 0; 1347 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1348 if (sc->sc_rev < FXP_REV_82558_A4) 1349 save_bf = 1; 1350 else 1351 lrxen = 1; 1352 } 1353 1354 /* 1355 * Initialize base of dump-stats buffer. 1356 */ 1357 fxp_scb_wait(sc); 1358 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1359 sc->sc_cddma + FXP_CDSTATSOFF); 1360 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1361 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1362 1363 cbp = &sc->sc_control_data->fcd_configcb; 1364 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1365 1366 /* 1367 * This copy is kind of disgusting, but there are a bunch of must be 1368 * zero and must be one bits in this structure and this is the easiest 1369 * way to initialize them all to proper values. 1370 */ 1371 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1372 1373 /* BIG_ENDIAN: no need to swap to store 0 */ 1374 cbp->cb_status = 0; 1375 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1376 FXP_CB_COMMAND_EL); 1377 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1378 cbp->link_addr = 0xffffffff; /* (no) next command */ 1379 cbp->byte_count = 22; /* (22) bytes to config */ 1380 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1381 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1382 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1383 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1384 cbp->type_enable = 0; /* actually reserved */ 1385 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1386 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1387 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1388 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1389 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1390 cbp->late_scb = 0; /* (don't) defer SCB update */ 1391 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1392 cbp->ci_int = 1; /* interrupt on CU idle */ 1393 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1394 cbp->ext_stats_dis = 1; /* disable extended counters */ 1395 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1396 cbp->save_bf = save_bf;/* save bad frames */ 1397 cbp->disc_short_rx = !prm; /* discard short packets */ 1398 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1399 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1400 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1401 /* interface mode */ 1402 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1403 cbp->csma_dis = 0; /* (don't) disable link */ 1404 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1405 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1406 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1407 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1408 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1409 cbp->nsai = 1; /* (don't) disable source addr insert */ 1410 cbp->preamble_length = 2; /* (7 byte) preamble */ 1411 cbp->loopback = 0; /* (don't) loopback */ 1412 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1413 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1414 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1415 cbp->promiscuous = prm; /* promiscuous mode */ 1416 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1417 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1418 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1419 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1420 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1421 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1422 cbp->padding = 1; /* (do) pad short tx packets */ 1423 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1424 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1425 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1426 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1427 /* must set wake_en in PMCSR also */ 1428 cbp->force_fdx = 0; /* (don't) force full duplex */ 1429 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1430 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1431 cbp->mc_all = allm; /* accept all multicasts */ 1432 1433 if (sc->sc_rev < FXP_REV_82558_A4) { 1434 /* 1435 * The i82557 has no hardware flow control, the values 1436 * here are the defaults for the chip. 1437 */ 1438 cbp->fc_delay_lsb = 0; 1439 cbp->fc_delay_msb = 0x40; 1440 cbp->pri_fc_thresh = 3; 1441 cbp->tx_fc_dis = 0; 1442 cbp->rx_fc_restop = 0; 1443 cbp->rx_fc_restart = 0; 1444 cbp->fc_filter = 0; 1445 cbp->pri_fc_loc = 1; 1446 } else { 1447 cbp->fc_delay_lsb = 0x1f; 1448 cbp->fc_delay_msb = 0x01; 1449 cbp->pri_fc_thresh = 3; 1450 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1451 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1452 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1453 cbp->fc_filter = !prm; /* drop FC frames to host */ 1454 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1455 } 1456 1457 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1458 1459 /* 1460 * Start the config command/DMA. 1461 */ 1462 fxp_scb_wait(sc); 1463 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1464 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1465 /* ...and wait for it to complete. */ 1466 i = 1000; 1467 do { 1468 FXP_CDCONFIGSYNC(sc, 1469 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1470 DELAY(1); 1471 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1472 if (i == 0) { 1473 printf("%s at line %d: dmasync timeout\n", 1474 sc->sc_dev.dv_xname, __LINE__); 1475 return ETIMEDOUT; 1476 } 1477 1478 /* 1479 * Initialize the station address. 1480 */ 1481 cb_ias = &sc->sc_control_data->fcd_iascb; 1482 /* BIG_ENDIAN: no need to swap to store 0 */ 1483 cb_ias->cb_status = 0; 1484 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1485 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1486 cb_ias->link_addr = 0xffffffff; 1487 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1488 1489 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1490 1491 /* 1492 * Start the IAS (Individual Address Setup) command/DMA. 1493 */ 1494 fxp_scb_wait(sc); 1495 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1496 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1497 /* ...and wait for it to complete. */ 1498 i = 1000; 1499 do { 1500 FXP_CDIASSYNC(sc, 1501 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1502 DELAY(1); 1503 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1504 if (i == 0) { 1505 printf("%s at line %d: dmasync timeout\n", 1506 sc->sc_dev.dv_xname, __LINE__); 1507 return ETIMEDOUT; 1508 } 1509 1510 /* 1511 * Initialize the transmit descriptor ring. txlast is initialized 1512 * to the end of the list so that it will wrap around to the first 1513 * descriptor when the first packet is transmitted. 1514 */ 1515 for (i = 0; i < FXP_NTXCB; i++) { 1516 txd = FXP_CDTX(sc, i); 1517 memset(txd, 0, sizeof(*txd)); 1518 txd->txd_txcb.cb_command = 1519 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1520 txd->txd_txcb.link_addr = 1521 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1522 if (sc->sc_flags & FXPF_EXT_TXCB) 1523 txd->txd_txcb.tbd_array_addr = 1524 htole32(FXP_CDTBDADDR(sc, i) + 1525 (2 * sizeof(struct fxp_tbd))); 1526 else 1527 txd->txd_txcb.tbd_array_addr = 1528 htole32(FXP_CDTBDADDR(sc, i)); 1529 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1530 } 1531 sc->sc_txpending = 0; 1532 sc->sc_txdirty = 0; 1533 sc->sc_txlast = FXP_NTXCB - 1; 1534 1535 /* 1536 * Initialize the receive buffer list. 1537 */ 1538 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1539 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1540 rxmap = FXP_RXMAP_GET(sc); 1541 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1542 printf("%s: unable to allocate or map rx " 1543 "buffer %d, error = %d\n", 1544 sc->sc_dev.dv_xname, 1545 sc->sc_rxq.ifq_len, error); 1546 /* 1547 * XXX Should attempt to run with fewer receive 1548 * XXX buffers instead of just failing. 1549 */ 1550 FXP_RXMAP_PUT(sc, rxmap); 1551 fxp_rxdrain(sc); 1552 goto out; 1553 } 1554 } 1555 sc->sc_rxidle = 0; 1556 1557 /* 1558 * Give the transmit ring to the chip. We do this by pointing 1559 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1560 * issuing a start command. It will execute the NOP and then 1561 * suspend, pointing at the first descriptor. 1562 */ 1563 fxp_scb_wait(sc); 1564 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1565 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1566 1567 /* 1568 * Initialize receiver buffer area - RFA. 1569 */ 1570 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1571 fxp_scb_wait(sc); 1572 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1573 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1574 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1575 1576 if (sc->sc_flags & FXPF_MII) { 1577 /* 1578 * Set current media. 1579 */ 1580 mii_mediachg(&sc->sc_mii); 1581 } 1582 1583 /* 1584 * ...all done! 1585 */ 1586 ifp->if_flags |= IFF_RUNNING; 1587 ifp->if_flags &= ~IFF_OACTIVE; 1588 1589 /* 1590 * Start the one second timer. 1591 */ 1592 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1593 1594 /* 1595 * Attempt to start output on the interface. 1596 */ 1597 fxp_start(ifp); 1598 1599 out: 1600 if (error) { 1601 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1602 ifp->if_timer = 0; 1603 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1604 } 1605 return (error); 1606 } 1607 1608 /* 1609 * Change media according to request. 1610 */ 1611 int 1612 fxp_mii_mediachange(struct ifnet *ifp) 1613 { 1614 struct fxp_softc *sc = ifp->if_softc; 1615 1616 if (ifp->if_flags & IFF_UP) 1617 mii_mediachg(&sc->sc_mii); 1618 return (0); 1619 } 1620 1621 /* 1622 * Notify the world which media we're using. 1623 */ 1624 void 1625 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1626 { 1627 struct fxp_softc *sc = ifp->if_softc; 1628 1629 if(sc->sc_enabled == 0) { 1630 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1631 ifmr->ifm_status = 0; 1632 return; 1633 } 1634 1635 mii_pollstat(&sc->sc_mii); 1636 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1637 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1638 } 1639 1640 int 1641 fxp_80c24_mediachange(struct ifnet *ifp) 1642 { 1643 1644 /* Nothing to do here. */ 1645 return (0); 1646 } 1647 1648 void 1649 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1650 { 1651 struct fxp_softc *sc = ifp->if_softc; 1652 1653 /* 1654 * Media is currently-selected media. We cannot determine 1655 * the link status. 1656 */ 1657 ifmr->ifm_status = 0; 1658 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1659 } 1660 1661 /* 1662 * Add a buffer to the end of the RFA buffer list. 1663 * Return 0 if successful, error code on failure. 1664 * 1665 * The RFA struct is stuck at the beginning of mbuf cluster and the 1666 * data pointer is fixed up to point just past it. 1667 */ 1668 int 1669 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1670 { 1671 struct mbuf *m; 1672 int error; 1673 1674 MGETHDR(m, M_DONTWAIT, MT_DATA); 1675 if (m == NULL) 1676 return (ENOBUFS); 1677 1678 MCLGET(m, M_DONTWAIT); 1679 if ((m->m_flags & M_EXT) == 0) { 1680 m_freem(m); 1681 return (ENOBUFS); 1682 } 1683 1684 if (unload) 1685 bus_dmamap_unload(sc->sc_dmat, rxmap); 1686 1687 M_SETCTX(m, rxmap); 1688 1689 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1690 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1691 if (error) { 1692 printf("%s: can't load rx DMA map %d, error = %d\n", 1693 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1694 panic("fxp_add_rfabuf"); /* XXX */ 1695 } 1696 1697 FXP_INIT_RFABUF(sc, m); 1698 1699 return (0); 1700 } 1701 1702 int 1703 fxp_mdi_read(struct device *self, int phy, int reg) 1704 { 1705 struct fxp_softc *sc = (struct fxp_softc *)self; 1706 int count = 10000; 1707 int value; 1708 1709 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1710 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1711 1712 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1713 && count--) 1714 DELAY(10); 1715 1716 if (count <= 0) 1717 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1718 1719 return (value & 0xffff); 1720 } 1721 1722 void 1723 fxp_statchg(struct device *self) 1724 { 1725 struct fxp_softc *sc = (void *) self; 1726 1727 /* 1728 * Determine whether or not we have to work-around the 1729 * Resume Bug. 1730 */ 1731 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1732 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1733 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1734 else 1735 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1736 } 1737 } 1738 1739 void 1740 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1741 { 1742 struct fxp_softc *sc = (struct fxp_softc *)self; 1743 int count = 10000; 1744 1745 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1746 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1747 (value & 0xffff)); 1748 1749 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1750 count--) 1751 DELAY(10); 1752 1753 if (count <= 0) 1754 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1755 } 1756 1757 int 1758 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1759 { 1760 struct fxp_softc *sc = ifp->if_softc; 1761 struct ifreq *ifr = (struct ifreq *)data; 1762 int s, error; 1763 1764 s = splnet(); 1765 1766 switch (cmd) { 1767 case SIOCSIFMEDIA: 1768 case SIOCGIFMEDIA: 1769 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1770 break; 1771 1772 default: 1773 error = ether_ioctl(ifp, cmd, data); 1774 if (error == ENETRESET) { 1775 if (sc->sc_enabled) { 1776 /* 1777 * Multicast list has changed; set the 1778 * hardware filter accordingly. 1779 */ 1780 if (sc->sc_txpending) { 1781 sc->sc_flags |= FXPF_WANTINIT; 1782 error = 0; 1783 } else 1784 error = fxp_init(ifp); 1785 } else 1786 error = 0; 1787 } 1788 break; 1789 } 1790 1791 /* Try to get more packets going. */ 1792 if (sc->sc_enabled) 1793 fxp_start(ifp); 1794 1795 splx(s); 1796 return (error); 1797 } 1798 1799 /* 1800 * Program the multicast filter. 1801 * 1802 * This function must be called at splnet(). 1803 */ 1804 void 1805 fxp_mc_setup(struct fxp_softc *sc) 1806 { 1807 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1808 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1809 struct ethercom *ec = &sc->sc_ethercom; 1810 struct ether_multi *enm; 1811 struct ether_multistep step; 1812 int count, nmcasts; 1813 1814 #ifdef DIAGNOSTIC 1815 if (sc->sc_txpending) 1816 panic("fxp_mc_setup: pending transmissions"); 1817 #endif 1818 1819 ifp->if_flags &= ~IFF_ALLMULTI; 1820 1821 /* 1822 * Initialize multicast setup descriptor. 1823 */ 1824 nmcasts = 0; 1825 ETHER_FIRST_MULTI(step, ec, enm); 1826 while (enm != NULL) { 1827 /* 1828 * Check for too many multicast addresses or if we're 1829 * listening to a range. Either way, we simply have 1830 * to accept all multicasts. 1831 */ 1832 if (nmcasts >= MAXMCADDR || 1833 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1834 ETHER_ADDR_LEN) != 0) { 1835 /* 1836 * Callers of this function must do the 1837 * right thing with this. If we're called 1838 * from outside fxp_init(), the caller must 1839 * detect if the state if IFF_ALLMULTI changes. 1840 * If it does, the caller must then call 1841 * fxp_init(), since allmulti is handled by 1842 * the config block. 1843 */ 1844 ifp->if_flags |= IFF_ALLMULTI; 1845 return; 1846 } 1847 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1848 ETHER_ADDR_LEN); 1849 nmcasts++; 1850 ETHER_NEXT_MULTI(step, enm); 1851 } 1852 1853 /* BIG_ENDIAN: no need to swap to store 0 */ 1854 mcsp->cb_status = 0; 1855 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1856 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1857 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1858 1859 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1860 1861 /* 1862 * Wait until the command unit is not active. This should never 1863 * happen since nothing is queued, but make sure anyway. 1864 */ 1865 count = 100; 1866 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1867 FXP_SCB_CUS_ACTIVE && --count) 1868 DELAY(1); 1869 if (count == 0) { 1870 printf("%s at line %d: command queue timeout\n", 1871 sc->sc_dev.dv_xname, __LINE__); 1872 return; 1873 } 1874 1875 /* 1876 * Start the multicast setup command/DMA. 1877 */ 1878 fxp_scb_wait(sc); 1879 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1880 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1881 1882 /* ...and wait for it to complete. */ 1883 count = 1000; 1884 do { 1885 FXP_CDMCSSYNC(sc, 1886 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1887 DELAY(1); 1888 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1889 if (count == 0) { 1890 printf("%s at line %d: dmasync timeout\n", 1891 sc->sc_dev.dv_xname, __LINE__); 1892 return; 1893 } 1894 } 1895 1896 int 1897 fxp_enable(struct fxp_softc *sc) 1898 { 1899 1900 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1901 if ((*sc->sc_enable)(sc) != 0) { 1902 printf("%s: device enable failed\n", 1903 sc->sc_dev.dv_xname); 1904 return (EIO); 1905 } 1906 } 1907 1908 sc->sc_enabled = 1; 1909 return (0); 1910 } 1911 1912 void 1913 fxp_disable(struct fxp_softc *sc) 1914 { 1915 1916 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1917 (*sc->sc_disable)(sc); 1918 sc->sc_enabled = 0; 1919 } 1920 } 1921 1922 /* 1923 * fxp_activate: 1924 * 1925 * Handle device activation/deactivation requests. 1926 */ 1927 int 1928 fxp_activate(struct device *self, enum devact act) 1929 { 1930 struct fxp_softc *sc = (void *) self; 1931 int s, error = 0; 1932 1933 s = splnet(); 1934 switch (act) { 1935 case DVACT_ACTIVATE: 1936 error = EOPNOTSUPP; 1937 break; 1938 1939 case DVACT_DEACTIVATE: 1940 if (sc->sc_flags & FXPF_MII) 1941 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1942 MII_OFFSET_ANY); 1943 if_deactivate(&sc->sc_ethercom.ec_if); 1944 break; 1945 } 1946 splx(s); 1947 1948 return (error); 1949 } 1950 1951 /* 1952 * fxp_detach: 1953 * 1954 * Detach an i82557 interface. 1955 */ 1956 int 1957 fxp_detach(struct fxp_softc *sc) 1958 { 1959 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1960 int i; 1961 1962 /* Succeed now if there's no work to do. */ 1963 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1964 return (0); 1965 1966 /* Unhook our tick handler. */ 1967 callout_stop(&sc->sc_callout); 1968 1969 if (sc->sc_flags & FXPF_MII) { 1970 /* Detach all PHYs */ 1971 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1972 } 1973 1974 /* Delete all remaining media. */ 1975 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1976 1977 #if NRND > 0 1978 rnd_detach_source(&sc->rnd_source); 1979 #endif 1980 ether_ifdetach(ifp); 1981 if_detach(ifp); 1982 1983 for (i = 0; i < FXP_NRFABUFS; i++) { 1984 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1985 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1986 } 1987 1988 for (i = 0; i < FXP_NTXCB; i++) { 1989 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1990 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1991 } 1992 1993 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1994 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1995 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1996 sizeof(struct fxp_control_data)); 1997 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 1998 1999 shutdownhook_disestablish(sc->sc_sdhook); 2000 powerhook_disestablish(sc->sc_powerhook); 2001 2002 return (0); 2003 } 2004
Indexes created Mon Sep 29 15:09:53 GMT 2025