i82557.c revision 1.54
1 /* $NetBSD: i82557.c,v 1.54 2001/06/12 22:32:50 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include "bpfilter.h" 76 #include "rnd.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 89 #include <machine/endian.h> 90 91 #include <uvm/uvm_extern.h> 92 93 #if NRND > 0 94 #include <sys/rnd.h> 95 #endif 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #if NBPFILTER > 0 103 #include <net/bpf.h> 104 #endif 105 106 #include <machine/bus.h> 107 #include <machine/intr.h> 108 109 #include <dev/mii/miivar.h> 110 111 #include <dev/ic/i82557reg.h> 112 #include <dev/ic/i82557var.h> 113 114 /* 115 * NOTE! On the Alpha, we have an alignment constraint. The 116 * card DMAs the packet immediately following the RFA. However, 117 * the first thing in the packet is a 14-byte Ethernet header. 118 * This means that the packet is misaligned. To compensate, 119 * we actually offset the RFA 2 bytes into the cluster. This 120 * alignes the packet after the Ethernet header at a 32-bit 121 * boundary. HOWEVER! This means that the RFA is misaligned! 122 */ 123 #define RFA_ALIGNMENT_FUDGE 2 124 125 /* 126 * The configuration byte map has several undefined fields which 127 * must be one or must be zero. Set up a template for these bits 128 * only (assuming an i82557 chip), leaving the actual configuration 129 * for fxp_init(). 130 * 131 * See the definition of struct fxp_cb_config for the bit definitions. 132 */ 133 const u_int8_t fxp_cb_config_template[] = { 134 0x0, 0x0, /* cb_status */ 135 0x0, 0x0, /* cb_command */ 136 0x0, 0x0, 0x0, 0x0, /* link_addr */ 137 0x0, /* 0 */ 138 0x0, /* 1 */ 139 0x0, /* 2 */ 140 0x0, /* 3 */ 141 0x0, /* 4 */ 142 0x0, /* 5 */ 143 0x32, /* 6 */ 144 0x0, /* 7 */ 145 0x0, /* 8 */ 146 0x0, /* 9 */ 147 0x6, /* 10 */ 148 0x0, /* 11 */ 149 0x0, /* 12 */ 150 0x0, /* 13 */ 151 0xf2, /* 14 */ 152 0x48, /* 15 */ 153 0x0, /* 16 */ 154 0x40, /* 17 */ 155 0xf0, /* 18 */ 156 0x0, /* 19 */ 157 0x3f, /* 20 */ 158 0x5, /* 21 */ 159 0x0, /* 22 */ 160 0x0, /* 23 */ 161 0x0, /* 24 */ 162 0x0, /* 25 */ 163 0x0, /* 26 */ 164 0x0, /* 27 */ 165 0x0, /* 28 */ 166 0x0, /* 29 */ 167 0x0, /* 30 */ 168 0x0, /* 31 */ 169 }; 170 171 void fxp_mii_initmedia(struct fxp_softc *); 172 int fxp_mii_mediachange(struct ifnet *); 173 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 174 175 void fxp_80c24_initmedia(struct fxp_softc *); 176 int fxp_80c24_mediachange(struct ifnet *); 177 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 178 179 void fxp_start(struct ifnet *); 180 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 181 void fxp_watchdog(struct ifnet *); 182 int fxp_init(struct ifnet *); 183 void fxp_stop(struct ifnet *, int); 184 185 void fxp_rxdrain(struct fxp_softc *); 186 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 187 int fxp_mdi_read(struct device *, int, int); 188 void fxp_statchg(struct device *); 189 void fxp_mdi_write(struct device *, int, int, int); 190 void fxp_autosize_eeprom(struct fxp_softc*); 191 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 192 void fxp_get_info(struct fxp_softc *, u_int8_t *); 193 void fxp_tick(void *); 194 void fxp_mc_setup(struct fxp_softc *); 195 196 void fxp_shutdown(void *); 197 void fxp_power(int, void *); 198 199 int fxp_copy_small = 0; 200 201 struct fxp_phytype { 202 int fp_phy; /* type of PHY, -1 for MII at the end. */ 203 void (*fp_init)(struct fxp_softc *); 204 } fxp_phytype_table[] = { 205 { FXP_PHY_80C24, fxp_80c24_initmedia }, 206 { -1, fxp_mii_initmedia }, 207 }; 208 209 /* 210 * Set initial transmit threshold at 64 (512 bytes). This is 211 * increased by 64 (512 bytes) at a time, to maximum of 192 212 * (1536 bytes), if an underrun occurs. 213 */ 214 static int tx_threshold = 64; 215 216 /* 217 * Wait for the previous command to be accepted (but not necessarily 218 * completed). 219 */ 220 static __inline void 221 fxp_scb_wait(struct fxp_softc *sc) 222 { 223 int i = 10000; 224 225 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 226 delay(2); 227 if (i == 0) 228 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 229 } 230 231 /* 232 * Submit a command to the i82557. 233 */ 234 static __inline void 235 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 236 { 237 238 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 239 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 240 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_NOP); 241 fxp_scb_wait(sc); 242 } 243 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 244 } 245 246 /* 247 * Finish attaching an i82557 interface. Called by bus-specific front-end. 248 */ 249 void 250 fxp_attach(struct fxp_softc *sc) 251 { 252 u_int8_t enaddr[ETHER_ADDR_LEN]; 253 struct ifnet *ifp; 254 bus_dma_segment_t seg; 255 int rseg, i, error; 256 struct fxp_phytype *fp; 257 258 callout_init(&sc->sc_callout); 259 260 /* Start out using the standard RFA. */ 261 sc->sc_rfa_size = RFA_SIZE; 262 263 /* 264 * Enable some good stuff on i82558 and later. 265 */ 266 if (sc->sc_rev >= FXP_REV_82558_A4) { 267 /* Enable the extended TxCB. */ 268 sc->sc_flags |= FXPF_EXT_TXCB; 269 } 270 271 /* 272 * Allocate the control data structures, and create and load the 273 * DMA map for it. 274 */ 275 if ((error = bus_dmamem_alloc(sc->sc_dmat, 276 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 277 0)) != 0) { 278 printf("%s: unable to allocate control data, error = %d\n", 279 sc->sc_dev.dv_xname, error); 280 goto fail_0; 281 } 282 283 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 284 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 285 BUS_DMA_COHERENT)) != 0) { 286 printf("%s: unable to map control data, error = %d\n", 287 sc->sc_dev.dv_xname, error); 288 goto fail_1; 289 } 290 sc->sc_cdseg = seg; 291 sc->sc_cdnseg = rseg; 292 293 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 294 295 if ((error = bus_dmamap_create(sc->sc_dmat, 296 sizeof(struct fxp_control_data), 1, 297 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 298 printf("%s: unable to create control data DMA map, " 299 "error = %d\n", sc->sc_dev.dv_xname, error); 300 goto fail_2; 301 } 302 303 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 304 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 305 0)) != 0) { 306 printf("%s: can't load control data DMA map, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_3; 309 } 310 311 /* 312 * Create the transmit buffer DMA maps. 313 */ 314 for (i = 0; i < FXP_NTXCB; i++) { 315 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 316 FXP_NTXSEG, MCLBYTES, 0, 0, 317 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 318 printf("%s: unable to create tx DMA map %d, " 319 "error = %d\n", sc->sc_dev.dv_xname, i, error); 320 goto fail_4; 321 } 322 } 323 324 /* 325 * Create the receive buffer DMA maps. 326 */ 327 for (i = 0; i < FXP_NRFABUFS; i++) { 328 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 329 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 330 printf("%s: unable to create rx DMA map %d, " 331 "error = %d\n", sc->sc_dev.dv_xname, i, error); 332 goto fail_5; 333 } 334 } 335 336 /* Initialize MAC address and media structures. */ 337 fxp_get_info(sc, enaddr); 338 339 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 340 ether_sprintf(enaddr)); 341 342 ifp = &sc->sc_ethercom.ec_if; 343 344 /* 345 * Get info about our media interface, and initialize it. Note 346 * the table terminates itself with a phy of -1, indicating 347 * that we're using MII. 348 */ 349 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 350 if (fp->fp_phy == sc->phy_primary_device) 351 break; 352 (*fp->fp_init)(sc); 353 354 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 355 ifp->if_softc = sc; 356 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 357 ifp->if_ioctl = fxp_ioctl; 358 ifp->if_start = fxp_start; 359 ifp->if_watchdog = fxp_watchdog; 360 ifp->if_init = fxp_init; 361 ifp->if_stop = fxp_stop; 362 IFQ_SET_READY(&ifp->if_snd); 363 364 /* 365 * We can support 802.1Q VLAN-sized frames. 366 */ 367 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 368 369 /* 370 * Attach the interface. 371 */ 372 if_attach(ifp); 373 ether_ifattach(ifp, enaddr); 374 #if NRND > 0 375 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 376 RND_TYPE_NET, 0); 377 #endif 378 379 /* 380 * Add shutdown hook so that DMA is disabled prior to reboot. Not 381 * doing do could allow DMA to corrupt kernel memory during the 382 * reboot before the driver initializes. 383 */ 384 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 385 if (sc->sc_sdhook == NULL) 386 printf("%s: WARNING: unable to establish shutdown hook\n", 387 sc->sc_dev.dv_xname); 388 /* 389 * Add suspend hook, for similar reasons.. 390 */ 391 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 392 if (sc->sc_powerhook == NULL) 393 printf("%s: WARNING: unable to establish power hook\n", 394 sc->sc_dev.dv_xname); 395 396 /* The attach is successful. */ 397 sc->sc_flags |= FXPF_ATTACHED; 398 399 return; 400 401 /* 402 * Free any resources we've allocated during the failed attach 403 * attempt. Do this in reverse order and fall though. 404 */ 405 fail_5: 406 for (i = 0; i < FXP_NRFABUFS; i++) { 407 if (sc->sc_rxmaps[i] != NULL) 408 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 409 } 410 fail_4: 411 for (i = 0; i < FXP_NTXCB; i++) { 412 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 413 bus_dmamap_destroy(sc->sc_dmat, 414 FXP_DSTX(sc, i)->txs_dmamap); 415 } 416 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 417 fail_3: 418 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 419 fail_2: 420 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 421 sizeof(struct fxp_control_data)); 422 fail_1: 423 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 424 fail_0: 425 return; 426 } 427 428 void 429 fxp_mii_initmedia(struct fxp_softc *sc) 430 { 431 432 sc->sc_flags |= FXPF_MII; 433 434 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 435 sc->sc_mii.mii_readreg = fxp_mdi_read; 436 sc->sc_mii.mii_writereg = fxp_mdi_write; 437 sc->sc_mii.mii_statchg = fxp_statchg; 438 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 439 fxp_mii_mediastatus); 440 /* 441 * The i82557 wedges if all of its PHYs are isolated! 442 */ 443 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 444 MII_OFFSET_ANY, MIIF_NOISOLATE); 445 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 446 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 447 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 448 } else 449 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 450 } 451 452 void 453 fxp_80c24_initmedia(struct fxp_softc *sc) 454 { 455 456 /* 457 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 458 * doesn't have a programming interface of any sort. The 459 * media is sensed automatically based on how the link partner 460 * is configured. This is, in essence, manual configuration. 461 */ 462 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 463 sc->sc_dev.dv_xname); 464 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 465 fxp_80c24_mediastatus); 466 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 467 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 468 } 469 470 /* 471 * Device shutdown routine. Called at system shutdown after sync. The 472 * main purpose of this routine is to shut off receiver DMA so that 473 * kernel memory doesn't get clobbered during warmboot. 474 */ 475 void 476 fxp_shutdown(void *arg) 477 { 478 struct fxp_softc *sc = arg; 479 480 /* 481 * Since the system's going to halt shortly, don't bother 482 * freeing mbufs. 483 */ 484 fxp_stop(&sc->sc_ethercom.ec_if, 0); 485 } 486 /* 487 * Power handler routine. Called when the system is transitioning 488 * into/out of power save modes. As with fxp_shutdown, the main 489 * purpose of this routine is to shut off receiver DMA so it doesn't 490 * clobber kernel memory at the wrong time. 491 */ 492 void 493 fxp_power(int why, void *arg) 494 { 495 struct fxp_softc *sc = arg; 496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 497 int s; 498 499 s = splnet(); 500 switch (why) { 501 case PWR_SUSPEND: 502 case PWR_STANDBY: 503 fxp_stop(ifp, 0); 504 break; 505 case PWR_RESUME: 506 if (ifp->if_flags & IFF_UP) 507 fxp_init(ifp); 508 break; 509 case PWR_SOFTSUSPEND: 510 case PWR_SOFTSTANDBY: 511 case PWR_SOFTRESUME: 512 break; 513 } 514 splx(s); 515 } 516 517 /* 518 * Initialize the interface media. 519 */ 520 void 521 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 522 { 523 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 524 525 /* 526 * Reset to a stable state. 527 */ 528 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 529 DELAY(10); 530 531 sc->sc_eeprom_size = 0; 532 fxp_autosize_eeprom(sc); 533 if(sc->sc_eeprom_size == 0) { 534 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 535 sc->sc_eeprom_size = 6; /* XXX panic here? */ 536 } 537 #ifdef DEBUG 538 printf("%s: detected %d word EEPROM\n", 539 sc->sc_dev.dv_xname, 540 1 << sc->sc_eeprom_size); 541 #endif 542 543 /* 544 * Get info about the primary PHY 545 */ 546 fxp_read_eeprom(sc, &data, 6, 1); 547 sc->phy_primary_device = 548 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 549 550 /* 551 * Read MAC address. 552 */ 553 fxp_read_eeprom(sc, myea, 0, 3); 554 enaddr[0] = myea[0] & 0xff; 555 enaddr[1] = myea[0] >> 8; 556 enaddr[2] = myea[1] & 0xff; 557 enaddr[3] = myea[1] >> 8; 558 enaddr[4] = myea[2] & 0xff; 559 enaddr[5] = myea[2] >> 8; 560 } 561 562 /* 563 * Figure out EEPROM size. 564 * 565 * 559's can have either 64-word or 256-word EEPROMs, the 558 566 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 567 * talks about the existance of 16 to 256 word EEPROMs. 568 * 569 * The only known sizes are 64 and 256, where the 256 version is used 570 * by CardBus cards to store CIS information. 571 * 572 * The address is shifted in msb-to-lsb, and after the last 573 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 574 * after which follows the actual data. We try to detect this zero, by 575 * probing the data-out bit in the EEPROM control register just after 576 * having shifted in a bit. If the bit is zero, we assume we've 577 * shifted enough address bits. The data-out should be tri-state, 578 * before this, which should translate to a logical one. 579 * 580 * Other ways to do this would be to try to read a register with known 581 * contents with a varying number of address bits, but no such 582 * register seem to be available. The high bits of register 10 are 01 583 * on the 558 and 559, but apparently not on the 557. 584 * 585 * The Linux driver computes a checksum on the EEPROM data, but the 586 * value of this checksum is not very well documented. 587 */ 588 589 void 590 fxp_autosize_eeprom(struct fxp_softc *sc) 591 { 592 u_int16_t reg; 593 int x; 594 595 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 596 /* 597 * Shift in read opcode. 598 */ 599 for (x = 3; x > 0; x--) { 600 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 601 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 602 } else { 603 reg = FXP_EEPROM_EECS; 604 } 605 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 606 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 607 reg | FXP_EEPROM_EESK); 608 DELAY(4); 609 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 610 DELAY(4); 611 } 612 /* 613 * Shift in address, wait for the dummy zero following a correct 614 * address shift. 615 */ 616 for (x = 1; x <= 8; x++) { 617 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 618 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 619 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 620 DELAY(4); 621 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 622 FXP_EEPROM_EEDO) == 0) 623 break; 624 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 625 DELAY(4); 626 } 627 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 628 DELAY(4); 629 if(x != 6 && x != 8) { 630 #ifdef DEBUG 631 printf("%s: strange EEPROM size (%d)\n", 632 sc->sc_dev.dv_xname, 1 << x); 633 #endif 634 } else 635 sc->sc_eeprom_size = x; 636 } 637 638 /* 639 * Read from the serial EEPROM. Basically, you manually shift in 640 * the read opcode (one bit at a time) and then shift in the address, 641 * and then you shift out the data (all of this one bit at a time). 642 * The word size is 16 bits, so you have to provide the address for 643 * every 16 bits of data. 644 */ 645 void 646 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 647 { 648 u_int16_t reg; 649 int i, x; 650 651 for (i = 0; i < words; i++) { 652 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 653 /* 654 * Shift in read opcode. 655 */ 656 for (x = 3; x > 0; x--) { 657 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 658 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 659 } else { 660 reg = FXP_EEPROM_EECS; 661 } 662 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 663 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 664 reg | FXP_EEPROM_EESK); 665 DELAY(4); 666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 667 DELAY(4); 668 } 669 /* 670 * Shift in address. 671 */ 672 for (x = sc->sc_eeprom_size; x > 0; x--) { 673 if ((i + offset) & (1 << (x - 1))) { 674 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 675 } else { 676 reg = FXP_EEPROM_EECS; 677 } 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 680 reg | FXP_EEPROM_EESK); 681 DELAY(4); 682 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 683 DELAY(4); 684 } 685 reg = FXP_EEPROM_EECS; 686 data[i] = 0; 687 /* 688 * Shift out data. 689 */ 690 for (x = 16; x > 0; x--) { 691 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 692 reg | FXP_EEPROM_EESK); 693 DELAY(4); 694 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 695 FXP_EEPROM_EEDO) 696 data[i] |= (1 << (x - 1)); 697 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 698 DELAY(4); 699 } 700 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 701 DELAY(4); 702 } 703 } 704 705 /* 706 * Start packet transmission on the interface. 707 */ 708 void 709 fxp_start(struct ifnet *ifp) 710 { 711 struct fxp_softc *sc = ifp->if_softc; 712 struct mbuf *m0, *m; 713 struct fxp_txdesc *txd; 714 struct fxp_txsoft *txs; 715 bus_dmamap_t dmamap; 716 int error, lasttx, nexttx, opending, seg; 717 718 /* 719 * If we want a re-init, bail out now. 720 */ 721 if (sc->sc_flags & FXPF_WANTINIT) { 722 ifp->if_flags |= IFF_OACTIVE; 723 return; 724 } 725 726 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 727 return; 728 729 /* 730 * Remember the previous txpending and the current lasttx. 731 */ 732 opending = sc->sc_txpending; 733 lasttx = sc->sc_txlast; 734 735 /* 736 * Loop through the send queue, setting up transmit descriptors 737 * until we drain the queue, or use up all available transmit 738 * descriptors. 739 */ 740 while (sc->sc_txpending < FXP_NTXCB) { 741 /* 742 * Grab a packet off the queue. 743 */ 744 IFQ_POLL(&ifp->if_snd, m0); 745 if (m0 == NULL) 746 break; 747 m = NULL; 748 749 /* 750 * Get the next available transmit descriptor. 751 */ 752 nexttx = FXP_NEXTTX(sc->sc_txlast); 753 txd = FXP_CDTX(sc, nexttx); 754 txs = FXP_DSTX(sc, nexttx); 755 dmamap = txs->txs_dmamap; 756 757 /* 758 * Load the DMA map. If this fails, the packet either 759 * didn't fit in the allotted number of frags, or we were 760 * short on resources. In this case, we'll copy and try 761 * again. 762 */ 763 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 764 BUS_DMA_NOWAIT) != 0) { 765 MGETHDR(m, M_DONTWAIT, MT_DATA); 766 if (m == NULL) { 767 printf("%s: unable to allocate Tx mbuf\n", 768 sc->sc_dev.dv_xname); 769 break; 770 } 771 if (m0->m_pkthdr.len > MHLEN) { 772 MCLGET(m, M_DONTWAIT); 773 if ((m->m_flags & M_EXT) == 0) { 774 printf("%s: unable to allocate Tx " 775 "cluster\n", sc->sc_dev.dv_xname); 776 m_freem(m); 777 break; 778 } 779 } 780 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 781 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 782 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 783 m, BUS_DMA_NOWAIT); 784 if (error) { 785 printf("%s: unable to load Tx buffer, " 786 "error = %d\n", sc->sc_dev.dv_xname, error); 787 break; 788 } 789 } 790 791 IFQ_DEQUEUE(&ifp->if_snd, m0); 792 if (m != NULL) { 793 m_freem(m0); 794 m0 = m; 795 } 796 797 /* Initialize the fraglist. */ 798 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 799 txd->txd_tbd[seg].tb_addr = 800 htole32(dmamap->dm_segs[seg].ds_addr); 801 txd->txd_tbd[seg].tb_size = 802 htole32(dmamap->dm_segs[seg].ds_len); 803 } 804 805 /* Sync the DMA map. */ 806 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 807 BUS_DMASYNC_PREWRITE); 808 809 /* 810 * Store a pointer to the packet so we can free it later. 811 */ 812 txs->txs_mbuf = m0; 813 814 /* 815 * Initialize the transmit descriptor. 816 */ 817 /* BIG_ENDIAN: no need to swap to store 0 */ 818 txd->txd_txcb.cb_status = 0; 819 txd->txd_txcb.cb_command = 820 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 821 txd->txd_txcb.tx_threshold = tx_threshold; 822 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 823 824 FXP_CDTXSYNC(sc, nexttx, 825 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 826 827 /* Advance the tx pointer. */ 828 sc->sc_txpending++; 829 sc->sc_txlast = nexttx; 830 831 #if NBPFILTER > 0 832 /* 833 * Pass packet to bpf if there is a listener. 834 */ 835 if (ifp->if_bpf) 836 bpf_mtap(ifp->if_bpf, m0); 837 #endif 838 } 839 840 if (sc->sc_txpending == FXP_NTXCB) { 841 /* No more slots; notify upper layer. */ 842 ifp->if_flags |= IFF_OACTIVE; 843 } 844 845 if (sc->sc_txpending != opending) { 846 /* 847 * We enqueued packets. If the transmitter was idle, 848 * reset the txdirty pointer. 849 */ 850 if (opending == 0) 851 sc->sc_txdirty = FXP_NEXTTX(lasttx); 852 853 /* 854 * Cause the chip to interrupt and suspend command 855 * processing once the last packet we've enqueued 856 * has been transmitted. 857 */ 858 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 859 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 860 FXP_CDTXSYNC(sc, sc->sc_txlast, 861 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 862 863 /* 864 * The entire packet chain is set up. Clear the suspend bit 865 * on the command prior to the first packet we set up. 866 */ 867 FXP_CDTXSYNC(sc, lasttx, 868 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 869 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 870 htole16(~FXP_CB_COMMAND_S); 871 FXP_CDTXSYNC(sc, lasttx, 872 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 873 874 /* 875 * Issue a Resume command in case the chip was suspended. 876 */ 877 fxp_scb_wait(sc); 878 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 879 880 /* Set a watchdog timer in case the chip flakes out. */ 881 ifp->if_timer = 5; 882 } 883 } 884 885 /* 886 * Process interface interrupts. 887 */ 888 int 889 fxp_intr(void *arg) 890 { 891 struct fxp_softc *sc = arg; 892 struct ethercom *ec = &sc->sc_ethercom; 893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 894 struct fxp_txdesc *txd; 895 struct fxp_txsoft *txs; 896 struct mbuf *m, *m0; 897 bus_dmamap_t rxmap; 898 struct fxp_rfa *rfa; 899 int i, claimed = 0; 900 u_int16_t len, rxstat, txstat; 901 u_int8_t statack; 902 903 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 904 return (0); 905 /* 906 * If the interface isn't running, don't try to 907 * service the interrupt.. just ack it and bail. 908 */ 909 if ((ifp->if_flags & IFF_RUNNING) == 0) { 910 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 911 if (statack) { 912 claimed = 1; 913 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 914 } 915 return (claimed); 916 } 917 918 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 919 claimed = 1; 920 921 /* 922 * First ACK all the interrupts in this pass. 923 */ 924 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 925 926 /* 927 * Process receiver interrupts. If a no-resource (RNR) 928 * condition exists, get whatever packets we can and 929 * re-start the receiver. 930 */ 931 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 932 rcvloop: 933 m = sc->sc_rxq.ifq_head; 934 rfa = FXP_MTORFA(m); 935 rxmap = M_GETCTX(m, bus_dmamap_t); 936 937 FXP_RFASYNC(sc, m, 938 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 939 940 rxstat = le16toh(rfa->rfa_status); 941 942 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 943 /* 944 * We have processed all of the 945 * receive buffers. 946 */ 947 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 948 goto do_transmit; 949 } 950 951 IF_DEQUEUE(&sc->sc_rxq, m); 952 953 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 954 955 len = le16toh(rfa->actual_size) & 956 (m->m_ext.ext_size - 1); 957 958 if (len < sizeof(struct ether_header)) { 959 /* 960 * Runt packet; drop it now. 961 */ 962 FXP_INIT_RFABUF(sc, m); 963 goto rcvloop; 964 } 965 966 /* 967 * If support for 802.1Q VLAN sized frames is 968 * enabled, we need to do some additional error 969 * checking (as we are saving bad frames, in 970 * order to receive the larger ones). 971 */ 972 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 973 (rxstat & (FXP_RFA_STATUS_OVERRUN| 974 FXP_RFA_STATUS_RNR| 975 FXP_RFA_STATUS_ALIGN| 976 FXP_RFA_STATUS_CRC)) != 0) { 977 FXP_INIT_RFABUF(sc, m); 978 goto rcvloop; 979 } 980 981 /* 982 * If the packet is small enough to fit in a 983 * single header mbuf, allocate one and copy 984 * the data into it. This greatly reduces 985 * memory consumption when we receive lots 986 * of small packets. 987 * 988 * Otherwise, we add a new buffer to the receive 989 * chain. If this fails, we drop the packet and 990 * recycle the old buffer. 991 */ 992 if (fxp_copy_small != 0 && len <= MHLEN) { 993 MGETHDR(m0, M_DONTWAIT, MT_DATA); 994 if (m == NULL) 995 goto dropit; 996 memcpy(mtod(m0, caddr_t), 997 mtod(m, caddr_t), len); 998 FXP_INIT_RFABUF(sc, m); 999 m = m0; 1000 } else { 1001 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1002 dropit: 1003 ifp->if_ierrors++; 1004 FXP_INIT_RFABUF(sc, m); 1005 goto rcvloop; 1006 } 1007 } 1008 1009 m->m_pkthdr.rcvif = ifp; 1010 m->m_pkthdr.len = m->m_len = len; 1011 1012 #if NBPFILTER > 0 1013 /* 1014 * Pass this up to any BPF listeners, but only 1015 * pass it up the stack it its for us. 1016 */ 1017 if (ifp->if_bpf) 1018 bpf_mtap(ifp->if_bpf, m); 1019 #endif 1020 1021 /* Pass it on. */ 1022 (*ifp->if_input)(ifp, m); 1023 goto rcvloop; 1024 } 1025 1026 do_transmit: 1027 if (statack & FXP_SCB_STATACK_RNR) { 1028 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1029 fxp_scb_wait(sc); 1030 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1031 rxmap->dm_segs[0].ds_addr + 1032 RFA_ALIGNMENT_FUDGE); 1033 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1034 } 1035 1036 /* 1037 * Free any finished transmit mbuf chains. 1038 */ 1039 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1040 ifp->if_flags &= ~IFF_OACTIVE; 1041 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1042 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1043 txd = FXP_CDTX(sc, i); 1044 txs = FXP_DSTX(sc, i); 1045 1046 FXP_CDTXSYNC(sc, i, 1047 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1048 1049 txstat = le16toh(txd->txd_txcb.cb_status); 1050 1051 if ((txstat & FXP_CB_STATUS_C) == 0) 1052 break; 1053 1054 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1055 0, txs->txs_dmamap->dm_mapsize, 1056 BUS_DMASYNC_POSTWRITE); 1057 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1058 m_freem(txs->txs_mbuf); 1059 txs->txs_mbuf = NULL; 1060 } 1061 1062 /* Update the dirty transmit buffer pointer. */ 1063 sc->sc_txdirty = i; 1064 1065 /* 1066 * Cancel the watchdog timer if there are no pending 1067 * transmissions. 1068 */ 1069 if (sc->sc_txpending == 0) { 1070 ifp->if_timer = 0; 1071 1072 /* 1073 * If we want a re-init, do that now. 1074 */ 1075 if (sc->sc_flags & FXPF_WANTINIT) 1076 (void) fxp_init(ifp); 1077 } 1078 1079 /* 1080 * Try to get more packets going. 1081 */ 1082 fxp_start(ifp); 1083 } 1084 } 1085 1086 #if NRND > 0 1087 if (claimed) 1088 rnd_add_uint32(&sc->rnd_source, statack); 1089 #endif 1090 return (claimed); 1091 } 1092 1093 /* 1094 * Update packet in/out/collision statistics. The i82557 doesn't 1095 * allow you to access these counters without doing a fairly 1096 * expensive DMA to get _all_ of the statistics it maintains, so 1097 * we do this operation here only once per second. The statistics 1098 * counters in the kernel are updated from the previous dump-stats 1099 * DMA and then a new dump-stats DMA is started. The on-chip 1100 * counters are zeroed when the DMA completes. If we can't start 1101 * the DMA immediately, we don't wait - we just prepare to read 1102 * them again next time. 1103 */ 1104 void 1105 fxp_tick(void *arg) 1106 { 1107 struct fxp_softc *sc = arg; 1108 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1109 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1110 int s; 1111 1112 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1113 return; 1114 1115 s = splnet(); 1116 1117 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1118 1119 ifp->if_opackets += le32toh(sp->tx_good); 1120 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1121 if (sp->rx_good) { 1122 ifp->if_ipackets += le32toh(sp->rx_good); 1123 sc->sc_rxidle = 0; 1124 } else { 1125 sc->sc_rxidle++; 1126 } 1127 ifp->if_ierrors += 1128 le32toh(sp->rx_crc_errors) + 1129 le32toh(sp->rx_alignment_errors) + 1130 le32toh(sp->rx_rnr_errors) + 1131 le32toh(sp->rx_overrun_errors); 1132 /* 1133 * If any transmit underruns occured, bump up the transmit 1134 * threshold by another 512 bytes (64 * 8). 1135 */ 1136 if (sp->tx_underruns) { 1137 ifp->if_oerrors += le32toh(sp->tx_underruns); 1138 if (tx_threshold < 192) 1139 tx_threshold += 64; 1140 } 1141 1142 /* 1143 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1144 * then assume the receiver has locked up and attempt to clear 1145 * the condition by reprogramming the multicast filter (actually, 1146 * resetting the interface). This is a work-around for a bug in 1147 * the 82557 where the receiver locks up if it gets certain types 1148 * of garbage in the syncronization bits prior to the packet header. 1149 * This bug is supposed to only occur in 10Mbps mode, but has been 1150 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1151 * speed transition). 1152 */ 1153 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1154 (void) fxp_init(ifp); 1155 splx(s); 1156 return; 1157 } 1158 /* 1159 * If there is no pending command, start another stats 1160 * dump. Otherwise punt for now. 1161 */ 1162 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1163 /* 1164 * Start another stats dump. 1165 */ 1166 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1168 } else { 1169 /* 1170 * A previous command is still waiting to be accepted. 1171 * Just zero our copy of the stats and wait for the 1172 * next timer event to update them. 1173 */ 1174 /* BIG_ENDIAN: no swap required to store 0 */ 1175 sp->tx_good = 0; 1176 sp->tx_underruns = 0; 1177 sp->tx_total_collisions = 0; 1178 1179 sp->rx_good = 0; 1180 sp->rx_crc_errors = 0; 1181 sp->rx_alignment_errors = 0; 1182 sp->rx_rnr_errors = 0; 1183 sp->rx_overrun_errors = 0; 1184 } 1185 1186 if (sc->sc_flags & FXPF_MII) { 1187 /* Tick the MII clock. */ 1188 mii_tick(&sc->sc_mii); 1189 } 1190 1191 splx(s); 1192 1193 /* 1194 * Schedule another timeout one second from now. 1195 */ 1196 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1197 } 1198 1199 /* 1200 * Drain the receive queue. 1201 */ 1202 void 1203 fxp_rxdrain(struct fxp_softc *sc) 1204 { 1205 bus_dmamap_t rxmap; 1206 struct mbuf *m; 1207 1208 for (;;) { 1209 IF_DEQUEUE(&sc->sc_rxq, m); 1210 if (m == NULL) 1211 break; 1212 rxmap = M_GETCTX(m, bus_dmamap_t); 1213 bus_dmamap_unload(sc->sc_dmat, rxmap); 1214 FXP_RXMAP_PUT(sc, rxmap); 1215 m_freem(m); 1216 } 1217 } 1218 1219 /* 1220 * Stop the interface. Cancels the statistics updater and resets 1221 * the interface. 1222 */ 1223 void 1224 fxp_stop(struct ifnet *ifp, int disable) 1225 { 1226 struct fxp_softc *sc = ifp->if_softc; 1227 struct fxp_txsoft *txs; 1228 int i; 1229 1230 /* 1231 * Turn down interface (done early to avoid bad interactions 1232 * between panics, shutdown hooks, and the watchdog timer) 1233 */ 1234 ifp->if_timer = 0; 1235 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1236 1237 /* 1238 * Cancel stats updater. 1239 */ 1240 callout_stop(&sc->sc_callout); 1241 if (sc->sc_flags & FXPF_MII) { 1242 /* Down the MII. */ 1243 mii_down(&sc->sc_mii); 1244 } 1245 1246 /* 1247 * Issue software reset 1248 */ 1249 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1250 DELAY(10); 1251 1252 /* 1253 * Release any xmit buffers. 1254 */ 1255 for (i = 0; i < FXP_NTXCB; i++) { 1256 txs = FXP_DSTX(sc, i); 1257 if (txs->txs_mbuf != NULL) { 1258 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1259 m_freem(txs->txs_mbuf); 1260 txs->txs_mbuf = NULL; 1261 } 1262 } 1263 sc->sc_txpending = 0; 1264 1265 if (disable) { 1266 fxp_rxdrain(sc); 1267 fxp_disable(sc); 1268 } 1269 1270 } 1271 1272 /* 1273 * Watchdog/transmission transmit timeout handler. Called when a 1274 * transmission is started on the interface, but no interrupt is 1275 * received before the timeout. This usually indicates that the 1276 * card has wedged for some reason. 1277 */ 1278 void 1279 fxp_watchdog(struct ifnet *ifp) 1280 { 1281 struct fxp_softc *sc = ifp->if_softc; 1282 1283 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1284 ifp->if_oerrors++; 1285 1286 (void) fxp_init(ifp); 1287 } 1288 1289 /* 1290 * Initialize the interface. Must be called at splnet(). 1291 */ 1292 int 1293 fxp_init(struct ifnet *ifp) 1294 { 1295 struct fxp_softc *sc = ifp->if_softc; 1296 struct fxp_cb_config *cbp; 1297 struct fxp_cb_ias *cb_ias; 1298 struct fxp_txdesc *txd; 1299 bus_dmamap_t rxmap; 1300 int i, prm, save_bf, lrxen, allm, error = 0; 1301 1302 if ((error = fxp_enable(sc)) != 0) 1303 goto out; 1304 1305 /* 1306 * Cancel any pending I/O 1307 */ 1308 fxp_stop(ifp, 0); 1309 1310 /* 1311 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1312 * flag, and this prevents the MII from detaching resulting in 1313 * a panic. The flags field should perhaps be split in runtime 1314 * flags and more static information. For now, just clear the 1315 * only other flag set. 1316 */ 1317 1318 sc->sc_flags &= ~FXPF_WANTINIT; 1319 1320 /* 1321 * Initialize base of CBL and RFA memory. Loading with zero 1322 * sets it up for regular linear addressing. 1323 */ 1324 fxp_scb_wait(sc); 1325 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1326 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1327 1328 fxp_scb_wait(sc); 1329 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1330 1331 /* 1332 * Initialize the multicast filter. Do this now, since we might 1333 * have to setup the config block differently. 1334 */ 1335 fxp_mc_setup(sc); 1336 1337 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1338 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1339 1340 /* 1341 * In order to support receiving 802.1Q VLAN frames, we have to 1342 * enable "save bad frames", since they are 4 bytes larger than 1343 * the normal Ethernet maximum frame length. On i82558 and later, 1344 * we have a better mechanism for this. 1345 */ 1346 save_bf = 0; 1347 lrxen = 0; 1348 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1349 if (sc->sc_rev < FXP_REV_82558_A4) 1350 save_bf = 1; 1351 else 1352 lrxen = 1; 1353 } 1354 1355 /* 1356 * Initialize base of dump-stats buffer. 1357 */ 1358 fxp_scb_wait(sc); 1359 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1360 sc->sc_cddma + FXP_CDSTATSOFF); 1361 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1362 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1363 1364 cbp = &sc->sc_control_data->fcd_configcb; 1365 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1366 1367 /* 1368 * This copy is kind of disgusting, but there are a bunch of must be 1369 * zero and must be one bits in this structure and this is the easiest 1370 * way to initialize them all to proper values. 1371 */ 1372 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1373 1374 /* BIG_ENDIAN: no need to swap to store 0 */ 1375 cbp->cb_status = 0; 1376 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1377 FXP_CB_COMMAND_EL); 1378 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1379 cbp->link_addr = 0xffffffff; /* (no) next command */ 1380 /* bytes in config block */ 1381 cbp->byte_count = FXP_CONFIG_LEN; 1382 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1383 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1384 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1385 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1386 cbp->type_enable = 0; /* actually reserved */ 1387 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1388 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1389 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1390 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1391 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1392 cbp->late_scb = 0; /* (don't) defer SCB update */ 1393 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1394 cbp->ci_int = 1; /* interrupt on CU idle */ 1395 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1396 cbp->ext_stats_dis = 1; /* disable extended counters */ 1397 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1398 cbp->save_bf = save_bf;/* save bad frames */ 1399 cbp->disc_short_rx = !prm; /* discard short packets */ 1400 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1401 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1402 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1403 /* interface mode */ 1404 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1405 cbp->csma_dis = 0; /* (don't) disable link */ 1406 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1407 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1408 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1409 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1410 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1411 cbp->nsai = 1; /* (don't) disable source addr insert */ 1412 cbp->preamble_length = 2; /* (7 byte) preamble */ 1413 cbp->loopback = 0; /* (don't) loopback */ 1414 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1415 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1416 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1417 cbp->promiscuous = prm; /* promiscuous mode */ 1418 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1419 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1420 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1421 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1422 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1423 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1424 cbp->padding = 1; /* (do) pad short tx packets */ 1425 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1426 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1427 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1428 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1429 /* must set wake_en in PMCSR also */ 1430 cbp->force_fdx = 0; /* (don't) force full duplex */ 1431 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1432 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1433 cbp->mc_all = allm; /* accept all multicasts */ 1434 1435 if (sc->sc_rev < FXP_REV_82558_A4) { 1436 /* 1437 * The i82557 has no hardware flow control, the values 1438 * here are the defaults for the chip. 1439 */ 1440 cbp->fc_delay_lsb = 0; 1441 cbp->fc_delay_msb = 0x40; 1442 cbp->pri_fc_thresh = 3; 1443 cbp->tx_fc_dis = 0; 1444 cbp->rx_fc_restop = 0; 1445 cbp->rx_fc_restart = 0; 1446 cbp->fc_filter = 0; 1447 cbp->pri_fc_loc = 1; 1448 } else { 1449 cbp->fc_delay_lsb = 0x1f; 1450 cbp->fc_delay_msb = 0x01; 1451 cbp->pri_fc_thresh = 3; 1452 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1453 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1454 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1455 cbp->fc_filter = !prm; /* drop FC frames to host */ 1456 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1457 } 1458 1459 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1460 1461 /* 1462 * Start the config command/DMA. 1463 */ 1464 fxp_scb_wait(sc); 1465 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1466 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1467 /* ...and wait for it to complete. */ 1468 i = 1000; 1469 do { 1470 FXP_CDCONFIGSYNC(sc, 1471 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1472 DELAY(1); 1473 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1474 if (i == 0) { 1475 printf("%s at line %d: dmasync timeout\n", 1476 sc->sc_dev.dv_xname, __LINE__); 1477 return ETIMEDOUT; 1478 } 1479 1480 /* 1481 * Initialize the station address. 1482 */ 1483 cb_ias = &sc->sc_control_data->fcd_iascb; 1484 /* BIG_ENDIAN: no need to swap to store 0 */ 1485 cb_ias->cb_status = 0; 1486 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1487 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1488 cb_ias->link_addr = 0xffffffff; 1489 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1490 1491 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1492 1493 /* 1494 * Start the IAS (Individual Address Setup) command/DMA. 1495 */ 1496 fxp_scb_wait(sc); 1497 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1498 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1499 /* ...and wait for it to complete. */ 1500 i = 1000; 1501 do { 1502 FXP_CDIASSYNC(sc, 1503 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1504 DELAY(1); 1505 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1506 if (i == 0) { 1507 printf("%s at line %d: dmasync timeout\n", 1508 sc->sc_dev.dv_xname, __LINE__); 1509 return ETIMEDOUT; 1510 } 1511 1512 /* 1513 * Initialize the transmit descriptor ring. txlast is initialized 1514 * to the end of the list so that it will wrap around to the first 1515 * descriptor when the first packet is transmitted. 1516 */ 1517 for (i = 0; i < FXP_NTXCB; i++) { 1518 txd = FXP_CDTX(sc, i); 1519 memset(txd, 0, sizeof(*txd)); 1520 txd->txd_txcb.cb_command = 1521 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1522 txd->txd_txcb.link_addr = 1523 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1524 if (sc->sc_flags & FXPF_EXT_TXCB) 1525 txd->txd_txcb.tbd_array_addr = 1526 htole32(FXP_CDTBDADDR(sc, i) + 1527 (2 * sizeof(struct fxp_tbd))); 1528 else 1529 txd->txd_txcb.tbd_array_addr = 1530 htole32(FXP_CDTBDADDR(sc, i)); 1531 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1532 } 1533 sc->sc_txpending = 0; 1534 sc->sc_txdirty = 0; 1535 sc->sc_txlast = FXP_NTXCB - 1; 1536 1537 /* 1538 * Initialize the receive buffer list. 1539 */ 1540 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1541 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1542 rxmap = FXP_RXMAP_GET(sc); 1543 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1544 printf("%s: unable to allocate or map rx " 1545 "buffer %d, error = %d\n", 1546 sc->sc_dev.dv_xname, 1547 sc->sc_rxq.ifq_len, error); 1548 /* 1549 * XXX Should attempt to run with fewer receive 1550 * XXX buffers instead of just failing. 1551 */ 1552 FXP_RXMAP_PUT(sc, rxmap); 1553 fxp_rxdrain(sc); 1554 goto out; 1555 } 1556 } 1557 sc->sc_rxidle = 0; 1558 1559 /* 1560 * Give the transmit ring to the chip. We do this by pointing 1561 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1562 * issuing a start command. It will execute the NOP and then 1563 * suspend, pointing at the first descriptor. 1564 */ 1565 fxp_scb_wait(sc); 1566 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1567 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1568 1569 /* 1570 * Initialize receiver buffer area - RFA. 1571 */ 1572 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1573 fxp_scb_wait(sc); 1574 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1575 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1576 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1577 1578 if (sc->sc_flags & FXPF_MII) { 1579 /* 1580 * Set current media. 1581 */ 1582 mii_mediachg(&sc->sc_mii); 1583 } 1584 1585 /* 1586 * ...all done! 1587 */ 1588 ifp->if_flags |= IFF_RUNNING; 1589 ifp->if_flags &= ~IFF_OACTIVE; 1590 1591 /* 1592 * Start the one second timer. 1593 */ 1594 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1595 1596 /* 1597 * Attempt to start output on the interface. 1598 */ 1599 fxp_start(ifp); 1600 1601 out: 1602 if (error) { 1603 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1604 ifp->if_timer = 0; 1605 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1606 } 1607 return (error); 1608 } 1609 1610 /* 1611 * Change media according to request. 1612 */ 1613 int 1614 fxp_mii_mediachange(struct ifnet *ifp) 1615 { 1616 struct fxp_softc *sc = ifp->if_softc; 1617 1618 if (ifp->if_flags & IFF_UP) 1619 mii_mediachg(&sc->sc_mii); 1620 return (0); 1621 } 1622 1623 /* 1624 * Notify the world which media we're using. 1625 */ 1626 void 1627 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1628 { 1629 struct fxp_softc *sc = ifp->if_softc; 1630 1631 if(sc->sc_enabled == 0) { 1632 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1633 ifmr->ifm_status = 0; 1634 return; 1635 } 1636 1637 mii_pollstat(&sc->sc_mii); 1638 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1639 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1640 } 1641 1642 int 1643 fxp_80c24_mediachange(struct ifnet *ifp) 1644 { 1645 1646 /* Nothing to do here. */ 1647 return (0); 1648 } 1649 1650 void 1651 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1652 { 1653 struct fxp_softc *sc = ifp->if_softc; 1654 1655 /* 1656 * Media is currently-selected media. We cannot determine 1657 * the link status. 1658 */ 1659 ifmr->ifm_status = 0; 1660 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1661 } 1662 1663 /* 1664 * Add a buffer to the end of the RFA buffer list. 1665 * Return 0 if successful, error code on failure. 1666 * 1667 * The RFA struct is stuck at the beginning of mbuf cluster and the 1668 * data pointer is fixed up to point just past it. 1669 */ 1670 int 1671 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1672 { 1673 struct mbuf *m; 1674 int error; 1675 1676 MGETHDR(m, M_DONTWAIT, MT_DATA); 1677 if (m == NULL) 1678 return (ENOBUFS); 1679 1680 MCLGET(m, M_DONTWAIT); 1681 if ((m->m_flags & M_EXT) == 0) { 1682 m_freem(m); 1683 return (ENOBUFS); 1684 } 1685 1686 if (unload) 1687 bus_dmamap_unload(sc->sc_dmat, rxmap); 1688 1689 M_SETCTX(m, rxmap); 1690 1691 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1692 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1693 if (error) { 1694 printf("%s: can't load rx DMA map %d, error = %d\n", 1695 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1696 panic("fxp_add_rfabuf"); /* XXX */ 1697 } 1698 1699 FXP_INIT_RFABUF(sc, m); 1700 1701 return (0); 1702 } 1703 1704 int 1705 fxp_mdi_read(struct device *self, int phy, int reg) 1706 { 1707 struct fxp_softc *sc = (struct fxp_softc *)self; 1708 int count = 10000; 1709 int value; 1710 1711 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1712 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1713 1714 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1715 && count--) 1716 DELAY(10); 1717 1718 if (count <= 0) 1719 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1720 1721 return (value & 0xffff); 1722 } 1723 1724 void 1725 fxp_statchg(struct device *self) 1726 { 1727 struct fxp_softc *sc = (void *) self; 1728 1729 /* 1730 * Determine whether or not we have to work-around the 1731 * Resume Bug. 1732 */ 1733 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1734 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1735 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1736 else 1737 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1738 } 1739 } 1740 1741 void 1742 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1743 { 1744 struct fxp_softc *sc = (struct fxp_softc *)self; 1745 int count = 10000; 1746 1747 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1748 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1749 (value & 0xffff)); 1750 1751 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1752 count--) 1753 DELAY(10); 1754 1755 if (count <= 0) 1756 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1757 } 1758 1759 int 1760 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1761 { 1762 struct fxp_softc *sc = ifp->if_softc; 1763 struct ifreq *ifr = (struct ifreq *)data; 1764 int s, error; 1765 1766 s = splnet(); 1767 1768 switch (cmd) { 1769 case SIOCSIFMEDIA: 1770 case SIOCGIFMEDIA: 1771 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1772 break; 1773 1774 default: 1775 error = ether_ioctl(ifp, cmd, data); 1776 if (error == ENETRESET) { 1777 if (sc->sc_enabled) { 1778 /* 1779 * Multicast list has changed; set the 1780 * hardware filter accordingly. 1781 */ 1782 if (sc->sc_txpending) { 1783 sc->sc_flags |= FXPF_WANTINIT; 1784 error = 0; 1785 } else 1786 error = fxp_init(ifp); 1787 } else 1788 error = 0; 1789 } 1790 break; 1791 } 1792 1793 /* Try to get more packets going. */ 1794 if (sc->sc_enabled) 1795 fxp_start(ifp); 1796 1797 splx(s); 1798 return (error); 1799 } 1800 1801 /* 1802 * Program the multicast filter. 1803 * 1804 * This function must be called at splnet(). 1805 */ 1806 void 1807 fxp_mc_setup(struct fxp_softc *sc) 1808 { 1809 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1810 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1811 struct ethercom *ec = &sc->sc_ethercom; 1812 struct ether_multi *enm; 1813 struct ether_multistep step; 1814 int count, nmcasts; 1815 1816 #ifdef DIAGNOSTIC 1817 if (sc->sc_txpending) 1818 panic("fxp_mc_setup: pending transmissions"); 1819 #endif 1820 1821 ifp->if_flags &= ~IFF_ALLMULTI; 1822 1823 /* 1824 * Initialize multicast setup descriptor. 1825 */ 1826 nmcasts = 0; 1827 ETHER_FIRST_MULTI(step, ec, enm); 1828 while (enm != NULL) { 1829 /* 1830 * Check for too many multicast addresses or if we're 1831 * listening to a range. Either way, we simply have 1832 * to accept all multicasts. 1833 */ 1834 if (nmcasts >= MAXMCADDR || 1835 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1836 ETHER_ADDR_LEN) != 0) { 1837 /* 1838 * Callers of this function must do the 1839 * right thing with this. If we're called 1840 * from outside fxp_init(), the caller must 1841 * detect if the state if IFF_ALLMULTI changes. 1842 * If it does, the caller must then call 1843 * fxp_init(), since allmulti is handled by 1844 * the config block. 1845 */ 1846 ifp->if_flags |= IFF_ALLMULTI; 1847 return; 1848 } 1849 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1850 ETHER_ADDR_LEN); 1851 nmcasts++; 1852 ETHER_NEXT_MULTI(step, enm); 1853 } 1854 1855 /* BIG_ENDIAN: no need to swap to store 0 */ 1856 mcsp->cb_status = 0; 1857 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1858 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1859 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1860 1861 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1862 1863 /* 1864 * Wait until the command unit is not active. This should never 1865 * happen since nothing is queued, but make sure anyway. 1866 */ 1867 count = 100; 1868 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1869 FXP_SCB_CUS_ACTIVE && --count) 1870 DELAY(1); 1871 if (count == 0) { 1872 printf("%s at line %d: command queue timeout\n", 1873 sc->sc_dev.dv_xname, __LINE__); 1874 return; 1875 } 1876 1877 /* 1878 * Start the multicast setup command/DMA. 1879 */ 1880 fxp_scb_wait(sc); 1881 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1882 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1883 1884 /* ...and wait for it to complete. */ 1885 count = 1000; 1886 do { 1887 FXP_CDMCSSYNC(sc, 1888 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1889 DELAY(1); 1890 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1891 if (count == 0) { 1892 printf("%s at line %d: dmasync timeout\n", 1893 sc->sc_dev.dv_xname, __LINE__); 1894 return; 1895 } 1896 } 1897 1898 int 1899 fxp_enable(struct fxp_softc *sc) 1900 { 1901 1902 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1903 if ((*sc->sc_enable)(sc) != 0) { 1904 printf("%s: device enable failed\n", 1905 sc->sc_dev.dv_xname); 1906 return (EIO); 1907 } 1908 } 1909 1910 sc->sc_enabled = 1; 1911 return (0); 1912 } 1913 1914 void 1915 fxp_disable(struct fxp_softc *sc) 1916 { 1917 1918 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1919 (*sc->sc_disable)(sc); 1920 sc->sc_enabled = 0; 1921 } 1922 } 1923 1924 /* 1925 * fxp_activate: 1926 * 1927 * Handle device activation/deactivation requests. 1928 */ 1929 int 1930 fxp_activate(struct device *self, enum devact act) 1931 { 1932 struct fxp_softc *sc = (void *) self; 1933 int s, error = 0; 1934 1935 s = splnet(); 1936 switch (act) { 1937 case DVACT_ACTIVATE: 1938 error = EOPNOTSUPP; 1939 break; 1940 1941 case DVACT_DEACTIVATE: 1942 if (sc->sc_flags & FXPF_MII) 1943 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1944 MII_OFFSET_ANY); 1945 if_deactivate(&sc->sc_ethercom.ec_if); 1946 break; 1947 } 1948 splx(s); 1949 1950 return (error); 1951 } 1952 1953 /* 1954 * fxp_detach: 1955 * 1956 * Detach an i82557 interface. 1957 */ 1958 int 1959 fxp_detach(struct fxp_softc *sc) 1960 { 1961 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1962 int i; 1963 1964 /* Succeed now if there's no work to do. */ 1965 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 1966 return (0); 1967 1968 /* Unhook our tick handler. */ 1969 callout_stop(&sc->sc_callout); 1970 1971 if (sc->sc_flags & FXPF_MII) { 1972 /* Detach all PHYs */ 1973 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1974 } 1975 1976 /* Delete all remaining media. */ 1977 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1978 1979 #if NRND > 0 1980 rnd_detach_source(&sc->rnd_source); 1981 #endif 1982 ether_ifdetach(ifp); 1983 if_detach(ifp); 1984 1985 for (i = 0; i < FXP_NRFABUFS; i++) { 1986 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 1987 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 1988 } 1989 1990 for (i = 0; i < FXP_NTXCB; i++) { 1991 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1992 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 1993 } 1994 1995 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 1996 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 1997 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1998 sizeof(struct fxp_control_data)); 1999 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2000 2001 shutdownhook_disestablish(sc->sc_sdhook); 2002 powerhook_disestablish(sc->sc_powerhook); 2003 2004 return (0); 2005 } 2006
Indexes created Wed Oct 29 12:09:47 GMT 2025