i82557.c revision 1.55
1 /* $NetBSD: i82557.c,v 1.55 2001/06/15 22:16:00 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include "bpfilter.h" 76 #include "rnd.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 89 #include <machine/endian.h> 90 91 #include <uvm/uvm_extern.h> 92 93 #if NRND > 0 94 #include <sys/rnd.h> 95 #endif 96 97 #include <net/if.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_ether.h> 101 102 #if NBPFILTER > 0 103 #include <net/bpf.h> 104 #endif 105 106 #include <machine/bus.h> 107 #include <machine/intr.h> 108 109 #include <dev/mii/miivar.h> 110 111 #include <dev/ic/i82557reg.h> 112 #include <dev/ic/i82557var.h> 113 114 /* 115 * NOTE! On the Alpha, we have an alignment constraint. The 116 * card DMAs the packet immediately following the RFA. However, 117 * the first thing in the packet is a 14-byte Ethernet header. 118 * This means that the packet is misaligned. To compensate, 119 * we actually offset the RFA 2 bytes into the cluster. This 120 * alignes the packet after the Ethernet header at a 32-bit 121 * boundary. HOWEVER! This means that the RFA is misaligned! 122 */ 123 #define RFA_ALIGNMENT_FUDGE 2 124 125 /* 126 * The configuration byte map has several undefined fields which 127 * must be one or must be zero. Set up a template for these bits 128 * only (assuming an i82557 chip), leaving the actual configuration 129 * for fxp_init(). 130 * 131 * See the definition of struct fxp_cb_config for the bit definitions. 132 */ 133 const u_int8_t fxp_cb_config_template[] = { 134 0x0, 0x0, /* cb_status */ 135 0x0, 0x0, /* cb_command */ 136 0x0, 0x0, 0x0, 0x0, /* link_addr */ 137 0x0, /* 0 */ 138 0x0, /* 1 */ 139 0x0, /* 2 */ 140 0x0, /* 3 */ 141 0x0, /* 4 */ 142 0x0, /* 5 */ 143 0x32, /* 6 */ 144 0x0, /* 7 */ 145 0x0, /* 8 */ 146 0x0, /* 9 */ 147 0x6, /* 10 */ 148 0x0, /* 11 */ 149 0x0, /* 12 */ 150 0x0, /* 13 */ 151 0xf2, /* 14 */ 152 0x48, /* 15 */ 153 0x0, /* 16 */ 154 0x40, /* 17 */ 155 0xf0, /* 18 */ 156 0x0, /* 19 */ 157 0x3f, /* 20 */ 158 0x5, /* 21 */ 159 0x0, /* 22 */ 160 0x0, /* 23 */ 161 0x0, /* 24 */ 162 0x0, /* 25 */ 163 0x0, /* 26 */ 164 0x0, /* 27 */ 165 0x0, /* 28 */ 166 0x0, /* 29 */ 167 0x0, /* 30 */ 168 0x0, /* 31 */ 169 }; 170 171 void fxp_mii_initmedia(struct fxp_softc *); 172 int fxp_mii_mediachange(struct ifnet *); 173 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 174 175 void fxp_80c24_initmedia(struct fxp_softc *); 176 int fxp_80c24_mediachange(struct ifnet *); 177 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 178 179 void fxp_start(struct ifnet *); 180 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 181 void fxp_watchdog(struct ifnet *); 182 int fxp_init(struct ifnet *); 183 void fxp_stop(struct ifnet *, int); 184 185 void fxp_txintr(struct fxp_softc *); 186 void fxp_rxintr(struct fxp_softc *); 187 188 void fxp_rxdrain(struct fxp_softc *); 189 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 190 int fxp_mdi_read(struct device *, int, int); 191 void fxp_statchg(struct device *); 192 void fxp_mdi_write(struct device *, int, int, int); 193 void fxp_autosize_eeprom(struct fxp_softc*); 194 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 195 void fxp_get_info(struct fxp_softc *, u_int8_t *); 196 void fxp_tick(void *); 197 void fxp_mc_setup(struct fxp_softc *); 198 199 void fxp_shutdown(void *); 200 void fxp_power(int, void *); 201 202 int fxp_copy_small = 0; 203 204 struct fxp_phytype { 205 int fp_phy; /* type of PHY, -1 for MII at the end. */ 206 void (*fp_init)(struct fxp_softc *); 207 } fxp_phytype_table[] = { 208 { FXP_PHY_80C24, fxp_80c24_initmedia }, 209 { -1, fxp_mii_initmedia }, 210 }; 211 212 /* 213 * Set initial transmit threshold at 64 (512 bytes). This is 214 * increased by 64 (512 bytes) at a time, to maximum of 192 215 * (1536 bytes), if an underrun occurs. 216 */ 217 static int tx_threshold = 64; 218 219 /* 220 * Wait for the previous command to be accepted (but not necessarily 221 * completed). 222 */ 223 static __inline void 224 fxp_scb_wait(struct fxp_softc *sc) 225 { 226 int i = 10000; 227 228 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 229 delay(2); 230 if (i == 0) 231 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 232 } 233 234 /* 235 * Submit a command to the i82557. 236 */ 237 static __inline void 238 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 239 { 240 241 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 242 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 243 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_NOP); 244 fxp_scb_wait(sc); 245 } 246 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 247 } 248 249 /* 250 * Finish attaching an i82557 interface. Called by bus-specific front-end. 251 */ 252 void 253 fxp_attach(struct fxp_softc *sc) 254 { 255 u_int8_t enaddr[ETHER_ADDR_LEN]; 256 struct ifnet *ifp; 257 bus_dma_segment_t seg; 258 int rseg, i, error; 259 struct fxp_phytype *fp; 260 261 callout_init(&sc->sc_callout); 262 263 /* Start out using the standard RFA. */ 264 sc->sc_rfa_size = RFA_SIZE; 265 266 /* 267 * Enable some good stuff on i82558 and later. 268 */ 269 if (sc->sc_rev >= FXP_REV_82558_A4) { 270 /* Enable the extended TxCB. */ 271 sc->sc_flags |= FXPF_EXT_TXCB; 272 } 273 274 /* 275 * Allocate the control data structures, and create and load the 276 * DMA map for it. 277 */ 278 if ((error = bus_dmamem_alloc(sc->sc_dmat, 279 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 280 0)) != 0) { 281 printf("%s: unable to allocate control data, error = %d\n", 282 sc->sc_dev.dv_xname, error); 283 goto fail_0; 284 } 285 286 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 287 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 288 BUS_DMA_COHERENT)) != 0) { 289 printf("%s: unable to map control data, error = %d\n", 290 sc->sc_dev.dv_xname, error); 291 goto fail_1; 292 } 293 sc->sc_cdseg = seg; 294 sc->sc_cdnseg = rseg; 295 296 bzero(sc->sc_control_data, sizeof(struct fxp_control_data)); 297 298 if ((error = bus_dmamap_create(sc->sc_dmat, 299 sizeof(struct fxp_control_data), 1, 300 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 301 printf("%s: unable to create control data DMA map, " 302 "error = %d\n", sc->sc_dev.dv_xname, error); 303 goto fail_2; 304 } 305 306 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 307 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 308 0)) != 0) { 309 printf("%s: can't load control data DMA map, error = %d\n", 310 sc->sc_dev.dv_xname, error); 311 goto fail_3; 312 } 313 314 /* 315 * Create the transmit buffer DMA maps. 316 */ 317 for (i = 0; i < FXP_NTXCB; i++) { 318 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 319 FXP_NTXSEG, MCLBYTES, 0, 0, 320 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 321 printf("%s: unable to create tx DMA map %d, " 322 "error = %d\n", sc->sc_dev.dv_xname, i, error); 323 goto fail_4; 324 } 325 } 326 327 /* 328 * Create the receive buffer DMA maps. 329 */ 330 for (i = 0; i < FXP_NRFABUFS; i++) { 331 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 332 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 333 printf("%s: unable to create rx DMA map %d, " 334 "error = %d\n", sc->sc_dev.dv_xname, i, error); 335 goto fail_5; 336 } 337 } 338 339 /* Initialize MAC address and media structures. */ 340 fxp_get_info(sc, enaddr); 341 342 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 343 ether_sprintf(enaddr)); 344 345 ifp = &sc->sc_ethercom.ec_if; 346 347 /* 348 * Get info about our media interface, and initialize it. Note 349 * the table terminates itself with a phy of -1, indicating 350 * that we're using MII. 351 */ 352 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 353 if (fp->fp_phy == sc->phy_primary_device) 354 break; 355 (*fp->fp_init)(sc); 356 357 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 358 ifp->if_softc = sc; 359 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 360 ifp->if_ioctl = fxp_ioctl; 361 ifp->if_start = fxp_start; 362 ifp->if_watchdog = fxp_watchdog; 363 ifp->if_init = fxp_init; 364 ifp->if_stop = fxp_stop; 365 IFQ_SET_READY(&ifp->if_snd); 366 367 /* 368 * We can support 802.1Q VLAN-sized frames. 369 */ 370 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 371 372 /* 373 * Attach the interface. 374 */ 375 if_attach(ifp); 376 ether_ifattach(ifp, enaddr); 377 #if NRND > 0 378 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 379 RND_TYPE_NET, 0); 380 #endif 381 382 #ifdef FXP_EVENT_COUNTERS 383 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 384 NULL, sc->sc_dev.dv_xname, "txstall"); 385 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 386 NULL, sc->sc_dev.dv_xname, "txintr"); 387 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 388 NULL, sc->sc_dev.dv_xname, "rxintr"); 389 #endif /* FXP_EVENT_COUNTERS */ 390 391 /* 392 * Add shutdown hook so that DMA is disabled prior to reboot. Not 393 * doing do could allow DMA to corrupt kernel memory during the 394 * reboot before the driver initializes. 395 */ 396 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 397 if (sc->sc_sdhook == NULL) 398 printf("%s: WARNING: unable to establish shutdown hook\n", 399 sc->sc_dev.dv_xname); 400 /* 401 * Add suspend hook, for similar reasons.. 402 */ 403 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 404 if (sc->sc_powerhook == NULL) 405 printf("%s: WARNING: unable to establish power hook\n", 406 sc->sc_dev.dv_xname); 407 408 /* The attach is successful. */ 409 sc->sc_flags |= FXPF_ATTACHED; 410 411 return; 412 413 /* 414 * Free any resources we've allocated during the failed attach 415 * attempt. Do this in reverse order and fall though. 416 */ 417 fail_5: 418 for (i = 0; i < FXP_NRFABUFS; i++) { 419 if (sc->sc_rxmaps[i] != NULL) 420 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 421 } 422 fail_4: 423 for (i = 0; i < FXP_NTXCB; i++) { 424 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 425 bus_dmamap_destroy(sc->sc_dmat, 426 FXP_DSTX(sc, i)->txs_dmamap); 427 } 428 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 429 fail_3: 430 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 431 fail_2: 432 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 433 sizeof(struct fxp_control_data)); 434 fail_1: 435 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 436 fail_0: 437 return; 438 } 439 440 void 441 fxp_mii_initmedia(struct fxp_softc *sc) 442 { 443 444 sc->sc_flags |= FXPF_MII; 445 446 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 447 sc->sc_mii.mii_readreg = fxp_mdi_read; 448 sc->sc_mii.mii_writereg = fxp_mdi_write; 449 sc->sc_mii.mii_statchg = fxp_statchg; 450 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 451 fxp_mii_mediastatus); 452 /* 453 * The i82557 wedges if all of its PHYs are isolated! 454 */ 455 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 456 MII_OFFSET_ANY, MIIF_NOISOLATE); 457 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 458 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 459 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 460 } else 461 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 462 } 463 464 void 465 fxp_80c24_initmedia(struct fxp_softc *sc) 466 { 467 468 /* 469 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 470 * doesn't have a programming interface of any sort. The 471 * media is sensed automatically based on how the link partner 472 * is configured. This is, in essence, manual configuration. 473 */ 474 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 475 sc->sc_dev.dv_xname); 476 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 477 fxp_80c24_mediastatus); 478 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 479 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 480 } 481 482 /* 483 * Device shutdown routine. Called at system shutdown after sync. The 484 * main purpose of this routine is to shut off receiver DMA so that 485 * kernel memory doesn't get clobbered during warmboot. 486 */ 487 void 488 fxp_shutdown(void *arg) 489 { 490 struct fxp_softc *sc = arg; 491 492 /* 493 * Since the system's going to halt shortly, don't bother 494 * freeing mbufs. 495 */ 496 fxp_stop(&sc->sc_ethercom.ec_if, 0); 497 } 498 /* 499 * Power handler routine. Called when the system is transitioning 500 * into/out of power save modes. As with fxp_shutdown, the main 501 * purpose of this routine is to shut off receiver DMA so it doesn't 502 * clobber kernel memory at the wrong time. 503 */ 504 void 505 fxp_power(int why, void *arg) 506 { 507 struct fxp_softc *sc = arg; 508 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 509 int s; 510 511 s = splnet(); 512 switch (why) { 513 case PWR_SUSPEND: 514 case PWR_STANDBY: 515 fxp_stop(ifp, 0); 516 break; 517 case PWR_RESUME: 518 if (ifp->if_flags & IFF_UP) 519 fxp_init(ifp); 520 break; 521 case PWR_SOFTSUSPEND: 522 case PWR_SOFTSTANDBY: 523 case PWR_SOFTRESUME: 524 break; 525 } 526 splx(s); 527 } 528 529 /* 530 * Initialize the interface media. 531 */ 532 void 533 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 534 { 535 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 536 537 /* 538 * Reset to a stable state. 539 */ 540 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 541 DELAY(10); 542 543 sc->sc_eeprom_size = 0; 544 fxp_autosize_eeprom(sc); 545 if(sc->sc_eeprom_size == 0) { 546 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 547 sc->sc_eeprom_size = 6; /* XXX panic here? */ 548 } 549 #ifdef DEBUG 550 printf("%s: detected %d word EEPROM\n", 551 sc->sc_dev.dv_xname, 552 1 << sc->sc_eeprom_size); 553 #endif 554 555 /* 556 * Get info about the primary PHY 557 */ 558 fxp_read_eeprom(sc, &data, 6, 1); 559 sc->phy_primary_device = 560 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 561 562 /* 563 * Read MAC address. 564 */ 565 fxp_read_eeprom(sc, myea, 0, 3); 566 enaddr[0] = myea[0] & 0xff; 567 enaddr[1] = myea[0] >> 8; 568 enaddr[2] = myea[1] & 0xff; 569 enaddr[3] = myea[1] >> 8; 570 enaddr[4] = myea[2] & 0xff; 571 enaddr[5] = myea[2] >> 8; 572 } 573 574 /* 575 * Figure out EEPROM size. 576 * 577 * 559's can have either 64-word or 256-word EEPROMs, the 558 578 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 579 * talks about the existance of 16 to 256 word EEPROMs. 580 * 581 * The only known sizes are 64 and 256, where the 256 version is used 582 * by CardBus cards to store CIS information. 583 * 584 * The address is shifted in msb-to-lsb, and after the last 585 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 586 * after which follows the actual data. We try to detect this zero, by 587 * probing the data-out bit in the EEPROM control register just after 588 * having shifted in a bit. If the bit is zero, we assume we've 589 * shifted enough address bits. The data-out should be tri-state, 590 * before this, which should translate to a logical one. 591 * 592 * Other ways to do this would be to try to read a register with known 593 * contents with a varying number of address bits, but no such 594 * register seem to be available. The high bits of register 10 are 01 595 * on the 558 and 559, but apparently not on the 557. 596 * 597 * The Linux driver computes a checksum on the EEPROM data, but the 598 * value of this checksum is not very well documented. 599 */ 600 601 void 602 fxp_autosize_eeprom(struct fxp_softc *sc) 603 { 604 u_int16_t reg; 605 int x; 606 607 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 608 /* 609 * Shift in read opcode. 610 */ 611 for (x = 3; x > 0; x--) { 612 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 613 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 614 } else { 615 reg = FXP_EEPROM_EECS; 616 } 617 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 618 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 619 reg | FXP_EEPROM_EESK); 620 DELAY(4); 621 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 622 DELAY(4); 623 } 624 /* 625 * Shift in address, wait for the dummy zero following a correct 626 * address shift. 627 */ 628 for (x = 1; x <= 8; x++) { 629 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 630 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 631 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 632 DELAY(4); 633 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 634 FXP_EEPROM_EEDO) == 0) 635 break; 636 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 637 DELAY(4); 638 } 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 640 DELAY(4); 641 if(x != 6 && x != 8) { 642 #ifdef DEBUG 643 printf("%s: strange EEPROM size (%d)\n", 644 sc->sc_dev.dv_xname, 1 << x); 645 #endif 646 } else 647 sc->sc_eeprom_size = x; 648 } 649 650 /* 651 * Read from the serial EEPROM. Basically, you manually shift in 652 * the read opcode (one bit at a time) and then shift in the address, 653 * and then you shift out the data (all of this one bit at a time). 654 * The word size is 16 bits, so you have to provide the address for 655 * every 16 bits of data. 656 */ 657 void 658 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 659 { 660 u_int16_t reg; 661 int i, x; 662 663 for (i = 0; i < words; i++) { 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 665 /* 666 * Shift in read opcode. 667 */ 668 for (x = 3; x > 0; x--) { 669 if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) { 670 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 671 } else { 672 reg = FXP_EEPROM_EECS; 673 } 674 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 676 reg | FXP_EEPROM_EESK); 677 DELAY(4); 678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 679 DELAY(4); 680 } 681 /* 682 * Shift in address. 683 */ 684 for (x = sc->sc_eeprom_size; x > 0; x--) { 685 if ((i + offset) & (1 << (x - 1))) { 686 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 687 } else { 688 reg = FXP_EEPROM_EECS; 689 } 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 691 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 692 reg | FXP_EEPROM_EESK); 693 DELAY(4); 694 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 695 DELAY(4); 696 } 697 reg = FXP_EEPROM_EECS; 698 data[i] = 0; 699 /* 700 * Shift out data. 701 */ 702 for (x = 16; x > 0; x--) { 703 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 704 reg | FXP_EEPROM_EESK); 705 DELAY(4); 706 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 707 FXP_EEPROM_EEDO) 708 data[i] |= (1 << (x - 1)); 709 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 710 DELAY(4); 711 } 712 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 713 DELAY(4); 714 } 715 } 716 717 /* 718 * Start packet transmission on the interface. 719 */ 720 void 721 fxp_start(struct ifnet *ifp) 722 { 723 struct fxp_softc *sc = ifp->if_softc; 724 struct mbuf *m0, *m; 725 struct fxp_txdesc *txd; 726 struct fxp_txsoft *txs; 727 bus_dmamap_t dmamap; 728 int error, lasttx, nexttx, opending, seg; 729 730 /* 731 * If we want a re-init, bail out now. 732 */ 733 if (sc->sc_flags & FXPF_WANTINIT) { 734 ifp->if_flags |= IFF_OACTIVE; 735 return; 736 } 737 738 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 739 return; 740 741 /* 742 * Remember the previous txpending and the current lasttx. 743 */ 744 opending = sc->sc_txpending; 745 lasttx = sc->sc_txlast; 746 747 /* 748 * Loop through the send queue, setting up transmit descriptors 749 * until we drain the queue, or use up all available transmit 750 * descriptors. 751 */ 752 for (;;) { 753 /* 754 * Grab a packet off the queue. 755 */ 756 IFQ_POLL(&ifp->if_snd, m0); 757 if (m0 == NULL) 758 break; 759 m = NULL; 760 761 if (sc->sc_txpending == FXP_NTXCB) { 762 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 763 break; 764 } 765 766 /* 767 * Get the next available transmit descriptor. 768 */ 769 nexttx = FXP_NEXTTX(sc->sc_txlast); 770 txd = FXP_CDTX(sc, nexttx); 771 txs = FXP_DSTX(sc, nexttx); 772 dmamap = txs->txs_dmamap; 773 774 /* 775 * Load the DMA map. If this fails, the packet either 776 * didn't fit in the allotted number of frags, or we were 777 * short on resources. In this case, we'll copy and try 778 * again. 779 */ 780 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 781 BUS_DMA_NOWAIT) != 0) { 782 MGETHDR(m, M_DONTWAIT, MT_DATA); 783 if (m == NULL) { 784 printf("%s: unable to allocate Tx mbuf\n", 785 sc->sc_dev.dv_xname); 786 break; 787 } 788 if (m0->m_pkthdr.len > MHLEN) { 789 MCLGET(m, M_DONTWAIT); 790 if ((m->m_flags & M_EXT) == 0) { 791 printf("%s: unable to allocate Tx " 792 "cluster\n", sc->sc_dev.dv_xname); 793 m_freem(m); 794 break; 795 } 796 } 797 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 798 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 799 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 800 m, BUS_DMA_NOWAIT); 801 if (error) { 802 printf("%s: unable to load Tx buffer, " 803 "error = %d\n", sc->sc_dev.dv_xname, error); 804 break; 805 } 806 } 807 808 IFQ_DEQUEUE(&ifp->if_snd, m0); 809 if (m != NULL) { 810 m_freem(m0); 811 m0 = m; 812 } 813 814 /* Initialize the fraglist. */ 815 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 816 txd->txd_tbd[seg].tb_addr = 817 htole32(dmamap->dm_segs[seg].ds_addr); 818 txd->txd_tbd[seg].tb_size = 819 htole32(dmamap->dm_segs[seg].ds_len); 820 } 821 822 /* Sync the DMA map. */ 823 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 824 BUS_DMASYNC_PREWRITE); 825 826 /* 827 * Store a pointer to the packet so we can free it later. 828 */ 829 txs->txs_mbuf = m0; 830 831 /* 832 * Initialize the transmit descriptor. 833 */ 834 /* BIG_ENDIAN: no need to swap to store 0 */ 835 txd->txd_txcb.cb_status = 0; 836 txd->txd_txcb.cb_command = 837 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 838 txd->txd_txcb.tx_threshold = tx_threshold; 839 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 840 841 FXP_CDTXSYNC(sc, nexttx, 842 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 843 844 /* Advance the tx pointer. */ 845 sc->sc_txpending++; 846 sc->sc_txlast = nexttx; 847 848 #if NBPFILTER > 0 849 /* 850 * Pass packet to bpf if there is a listener. 851 */ 852 if (ifp->if_bpf) 853 bpf_mtap(ifp->if_bpf, m0); 854 #endif 855 } 856 857 if (sc->sc_txpending == FXP_NTXCB) { 858 /* No more slots; notify upper layer. */ 859 ifp->if_flags |= IFF_OACTIVE; 860 } 861 862 if (sc->sc_txpending != opending) { 863 /* 864 * We enqueued packets. If the transmitter was idle, 865 * reset the txdirty pointer. 866 */ 867 if (opending == 0) 868 sc->sc_txdirty = FXP_NEXTTX(lasttx); 869 870 /* 871 * Cause the chip to interrupt and suspend command 872 * processing once the last packet we've enqueued 873 * has been transmitted. 874 */ 875 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 876 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 877 FXP_CDTXSYNC(sc, sc->sc_txlast, 878 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 879 880 /* 881 * The entire packet chain is set up. Clear the suspend bit 882 * on the command prior to the first packet we set up. 883 */ 884 FXP_CDTXSYNC(sc, lasttx, 885 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 886 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 887 htole16(~FXP_CB_COMMAND_S); 888 FXP_CDTXSYNC(sc, lasttx, 889 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 890 891 /* 892 * Issue a Resume command in case the chip was suspended. 893 */ 894 fxp_scb_wait(sc); 895 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 896 897 /* Set a watchdog timer in case the chip flakes out. */ 898 ifp->if_timer = 5; 899 } 900 } 901 902 /* 903 * Process interface interrupts. 904 */ 905 int 906 fxp_intr(void *arg) 907 { 908 struct fxp_softc *sc = arg; 909 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 910 bus_dmamap_t rxmap; 911 int claimed = 0; 912 u_int8_t statack; 913 914 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 915 return (0); 916 /* 917 * If the interface isn't running, don't try to 918 * service the interrupt.. just ack it and bail. 919 */ 920 if ((ifp->if_flags & IFF_RUNNING) == 0) { 921 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 922 if (statack) { 923 claimed = 1; 924 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 925 } 926 return (claimed); 927 } 928 929 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 930 claimed = 1; 931 932 /* 933 * First ACK all the interrupts in this pass. 934 */ 935 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 936 937 /* 938 * Process receiver interrupts. If a no-resource (RNR) 939 * condition exists, get whatever packets we can and 940 * re-start the receiver. 941 */ 942 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 943 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 944 fxp_rxintr(sc); 945 } 946 947 if (statack & FXP_SCB_STATACK_RNR) { 948 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 949 fxp_scb_wait(sc); 950 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 951 rxmap->dm_segs[0].ds_addr + 952 RFA_ALIGNMENT_FUDGE); 953 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 954 } 955 956 /* 957 * Free any finished transmit mbuf chains. 958 */ 959 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 960 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 961 fxp_txintr(sc); 962 963 /* 964 * Try to get more packets going. 965 */ 966 fxp_start(ifp); 967 968 if (sc->sc_txpending == 0) { 969 /* 970 * If we want a re-init, do that now. 971 */ 972 if (sc->sc_flags & FXPF_WANTINIT) 973 (void) fxp_init(ifp); 974 } 975 } 976 } 977 978 #if NRND > 0 979 if (claimed) 980 rnd_add_uint32(&sc->rnd_source, statack); 981 #endif 982 return (claimed); 983 } 984 985 /* 986 * Handle transmit completion interrupts. 987 */ 988 void 989 fxp_txintr(struct fxp_softc *sc) 990 { 991 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 992 struct fxp_txdesc *txd; 993 struct fxp_txsoft *txs; 994 int i; 995 u_int16_t txstat; 996 997 ifp->if_flags &= ~IFF_OACTIVE; 998 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 999 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1000 txd = FXP_CDTX(sc, i); 1001 txs = FXP_DSTX(sc, i); 1002 1003 FXP_CDTXSYNC(sc, i, 1004 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1005 1006 txstat = le16toh(txd->txd_txcb.cb_status); 1007 1008 if ((txstat & FXP_CB_STATUS_C) == 0) 1009 break; 1010 1011 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1012 0, txs->txs_dmamap->dm_mapsize, 1013 BUS_DMASYNC_POSTWRITE); 1014 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1015 m_freem(txs->txs_mbuf); 1016 txs->txs_mbuf = NULL; 1017 } 1018 1019 /* Update the dirty transmit buffer pointer. */ 1020 sc->sc_txdirty = i; 1021 1022 /* 1023 * Cancel the watchdog timer if there are no pending 1024 * transmissions. 1025 */ 1026 if (sc->sc_txpending == 0) 1027 ifp->if_timer = 0; 1028 } 1029 1030 /* 1031 * Handle receive interrupts. 1032 */ 1033 void 1034 fxp_rxintr(struct fxp_softc *sc) 1035 { 1036 struct ethercom *ec = &sc->sc_ethercom; 1037 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1038 struct mbuf *m, *m0; 1039 bus_dmamap_t rxmap; 1040 struct fxp_rfa *rfa; 1041 u_int16_t len, rxstat; 1042 1043 for (;;) { 1044 m = sc->sc_rxq.ifq_head; 1045 rfa = FXP_MTORFA(m); 1046 rxmap = M_GETCTX(m, bus_dmamap_t); 1047 1048 FXP_RFASYNC(sc, m, 1049 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1050 1051 rxstat = le16toh(rfa->rfa_status); 1052 1053 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1054 /* 1055 * We have processed all of the 1056 * receive buffers. 1057 */ 1058 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1059 return; 1060 } 1061 1062 IF_DEQUEUE(&sc->sc_rxq, m); 1063 1064 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1065 1066 len = le16toh(rfa->actual_size) & 1067 (m->m_ext.ext_size - 1); 1068 1069 if (len < sizeof(struct ether_header)) { 1070 /* 1071 * Runt packet; drop it now. 1072 */ 1073 FXP_INIT_RFABUF(sc, m); 1074 continue; 1075 } 1076 1077 /* 1078 * If support for 802.1Q VLAN sized frames is 1079 * enabled, we need to do some additional error 1080 * checking (as we are saving bad frames, in 1081 * order to receive the larger ones). 1082 */ 1083 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1084 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1085 FXP_RFA_STATUS_RNR| 1086 FXP_RFA_STATUS_ALIGN| 1087 FXP_RFA_STATUS_CRC)) != 0) { 1088 FXP_INIT_RFABUF(sc, m); 1089 continue; 1090 } 1091 1092 /* 1093 * If the packet is small enough to fit in a 1094 * single header mbuf, allocate one and copy 1095 * the data into it. This greatly reduces 1096 * memory consumption when we receive lots 1097 * of small packets. 1098 * 1099 * Otherwise, we add a new buffer to the receive 1100 * chain. If this fails, we drop the packet and 1101 * recycle the old buffer. 1102 */ 1103 if (fxp_copy_small != 0 && len <= MHLEN) { 1104 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1105 if (m == NULL) 1106 goto dropit; 1107 memcpy(mtod(m0, caddr_t), 1108 mtod(m, caddr_t), len); 1109 FXP_INIT_RFABUF(sc, m); 1110 m = m0; 1111 } else { 1112 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1113 dropit: 1114 ifp->if_ierrors++; 1115 FXP_INIT_RFABUF(sc, m); 1116 continue; 1117 } 1118 } 1119 1120 m->m_pkthdr.rcvif = ifp; 1121 m->m_pkthdr.len = m->m_len = len; 1122 1123 #if NBPFILTER > 0 1124 /* 1125 * Pass this up to any BPF listeners, but only 1126 * pass it up the stack it its for us. 1127 */ 1128 if (ifp->if_bpf) 1129 bpf_mtap(ifp->if_bpf, m); 1130 #endif 1131 1132 /* Pass it on. */ 1133 (*ifp->if_input)(ifp, m); 1134 } 1135 } 1136 1137 /* 1138 * Update packet in/out/collision statistics. The i82557 doesn't 1139 * allow you to access these counters without doing a fairly 1140 * expensive DMA to get _all_ of the statistics it maintains, so 1141 * we do this operation here only once per second. The statistics 1142 * counters in the kernel are updated from the previous dump-stats 1143 * DMA and then a new dump-stats DMA is started. The on-chip 1144 * counters are zeroed when the DMA completes. If we can't start 1145 * the DMA immediately, we don't wait - we just prepare to read 1146 * them again next time. 1147 */ 1148 void 1149 fxp_tick(void *arg) 1150 { 1151 struct fxp_softc *sc = arg; 1152 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1153 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1154 int s; 1155 1156 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1157 return; 1158 1159 s = splnet(); 1160 1161 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1162 1163 ifp->if_opackets += le32toh(sp->tx_good); 1164 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1165 if (sp->rx_good) { 1166 ifp->if_ipackets += le32toh(sp->rx_good); 1167 sc->sc_rxidle = 0; 1168 } else { 1169 sc->sc_rxidle++; 1170 } 1171 ifp->if_ierrors += 1172 le32toh(sp->rx_crc_errors) + 1173 le32toh(sp->rx_alignment_errors) + 1174 le32toh(sp->rx_rnr_errors) + 1175 le32toh(sp->rx_overrun_errors); 1176 /* 1177 * If any transmit underruns occured, bump up the transmit 1178 * threshold by another 512 bytes (64 * 8). 1179 */ 1180 if (sp->tx_underruns) { 1181 ifp->if_oerrors += le32toh(sp->tx_underruns); 1182 if (tx_threshold < 192) 1183 tx_threshold += 64; 1184 } 1185 1186 /* 1187 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1188 * then assume the receiver has locked up and attempt to clear 1189 * the condition by reprogramming the multicast filter (actually, 1190 * resetting the interface). This is a work-around for a bug in 1191 * the 82557 where the receiver locks up if it gets certain types 1192 * of garbage in the syncronization bits prior to the packet header. 1193 * This bug is supposed to only occur in 10Mbps mode, but has been 1194 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1195 * speed transition). 1196 */ 1197 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1198 (void) fxp_init(ifp); 1199 splx(s); 1200 return; 1201 } 1202 /* 1203 * If there is no pending command, start another stats 1204 * dump. Otherwise punt for now. 1205 */ 1206 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1207 /* 1208 * Start another stats dump. 1209 */ 1210 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1211 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1212 } else { 1213 /* 1214 * A previous command is still waiting to be accepted. 1215 * Just zero our copy of the stats and wait for the 1216 * next timer event to update them. 1217 */ 1218 /* BIG_ENDIAN: no swap required to store 0 */ 1219 sp->tx_good = 0; 1220 sp->tx_underruns = 0; 1221 sp->tx_total_collisions = 0; 1222 1223 sp->rx_good = 0; 1224 sp->rx_crc_errors = 0; 1225 sp->rx_alignment_errors = 0; 1226 sp->rx_rnr_errors = 0; 1227 sp->rx_overrun_errors = 0; 1228 } 1229 1230 if (sc->sc_flags & FXPF_MII) { 1231 /* Tick the MII clock. */ 1232 mii_tick(&sc->sc_mii); 1233 } 1234 1235 splx(s); 1236 1237 /* 1238 * Schedule another timeout one second from now. 1239 */ 1240 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1241 } 1242 1243 /* 1244 * Drain the receive queue. 1245 */ 1246 void 1247 fxp_rxdrain(struct fxp_softc *sc) 1248 { 1249 bus_dmamap_t rxmap; 1250 struct mbuf *m; 1251 1252 for (;;) { 1253 IF_DEQUEUE(&sc->sc_rxq, m); 1254 if (m == NULL) 1255 break; 1256 rxmap = M_GETCTX(m, bus_dmamap_t); 1257 bus_dmamap_unload(sc->sc_dmat, rxmap); 1258 FXP_RXMAP_PUT(sc, rxmap); 1259 m_freem(m); 1260 } 1261 } 1262 1263 /* 1264 * Stop the interface. Cancels the statistics updater and resets 1265 * the interface. 1266 */ 1267 void 1268 fxp_stop(struct ifnet *ifp, int disable) 1269 { 1270 struct fxp_softc *sc = ifp->if_softc; 1271 struct fxp_txsoft *txs; 1272 int i; 1273 1274 /* 1275 * Turn down interface (done early to avoid bad interactions 1276 * between panics, shutdown hooks, and the watchdog timer) 1277 */ 1278 ifp->if_timer = 0; 1279 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1280 1281 /* 1282 * Cancel stats updater. 1283 */ 1284 callout_stop(&sc->sc_callout); 1285 if (sc->sc_flags & FXPF_MII) { 1286 /* Down the MII. */ 1287 mii_down(&sc->sc_mii); 1288 } 1289 1290 /* 1291 * Issue software reset 1292 */ 1293 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1294 DELAY(10); 1295 1296 /* 1297 * Release any xmit buffers. 1298 */ 1299 for (i = 0; i < FXP_NTXCB; i++) { 1300 txs = FXP_DSTX(sc, i); 1301 if (txs->txs_mbuf != NULL) { 1302 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1303 m_freem(txs->txs_mbuf); 1304 txs->txs_mbuf = NULL; 1305 } 1306 } 1307 sc->sc_txpending = 0; 1308 1309 if (disable) { 1310 fxp_rxdrain(sc); 1311 fxp_disable(sc); 1312 } 1313 1314 } 1315 1316 /* 1317 * Watchdog/transmission transmit timeout handler. Called when a 1318 * transmission is started on the interface, but no interrupt is 1319 * received before the timeout. This usually indicates that the 1320 * card has wedged for some reason. 1321 */ 1322 void 1323 fxp_watchdog(struct ifnet *ifp) 1324 { 1325 struct fxp_softc *sc = ifp->if_softc; 1326 1327 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1328 ifp->if_oerrors++; 1329 1330 (void) fxp_init(ifp); 1331 } 1332 1333 /* 1334 * Initialize the interface. Must be called at splnet(). 1335 */ 1336 int 1337 fxp_init(struct ifnet *ifp) 1338 { 1339 struct fxp_softc *sc = ifp->if_softc; 1340 struct fxp_cb_config *cbp; 1341 struct fxp_cb_ias *cb_ias; 1342 struct fxp_txdesc *txd; 1343 bus_dmamap_t rxmap; 1344 int i, prm, save_bf, lrxen, allm, error = 0; 1345 1346 if ((error = fxp_enable(sc)) != 0) 1347 goto out; 1348 1349 /* 1350 * Cancel any pending I/O 1351 */ 1352 fxp_stop(ifp, 0); 1353 1354 /* 1355 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1356 * flag, and this prevents the MII from detaching resulting in 1357 * a panic. The flags field should perhaps be split in runtime 1358 * flags and more static information. For now, just clear the 1359 * only other flag set. 1360 */ 1361 1362 sc->sc_flags &= ~FXPF_WANTINIT; 1363 1364 /* 1365 * Initialize base of CBL and RFA memory. Loading with zero 1366 * sets it up for regular linear addressing. 1367 */ 1368 fxp_scb_wait(sc); 1369 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1370 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1371 1372 fxp_scb_wait(sc); 1373 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1374 1375 /* 1376 * Initialize the multicast filter. Do this now, since we might 1377 * have to setup the config block differently. 1378 */ 1379 fxp_mc_setup(sc); 1380 1381 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1382 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1383 1384 /* 1385 * In order to support receiving 802.1Q VLAN frames, we have to 1386 * enable "save bad frames", since they are 4 bytes larger than 1387 * the normal Ethernet maximum frame length. On i82558 and later, 1388 * we have a better mechanism for this. 1389 */ 1390 save_bf = 0; 1391 lrxen = 0; 1392 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1393 if (sc->sc_rev < FXP_REV_82558_A4) 1394 save_bf = 1; 1395 else 1396 lrxen = 1; 1397 } 1398 1399 /* 1400 * Initialize base of dump-stats buffer. 1401 */ 1402 fxp_scb_wait(sc); 1403 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1404 sc->sc_cddma + FXP_CDSTATSOFF); 1405 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1406 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1407 1408 cbp = &sc->sc_control_data->fcd_configcb; 1409 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1410 1411 /* 1412 * This copy is kind of disgusting, but there are a bunch of must be 1413 * zero and must be one bits in this structure and this is the easiest 1414 * way to initialize them all to proper values. 1415 */ 1416 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1417 1418 /* BIG_ENDIAN: no need to swap to store 0 */ 1419 cbp->cb_status = 0; 1420 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1421 FXP_CB_COMMAND_EL); 1422 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1423 cbp->link_addr = 0xffffffff; /* (no) next command */ 1424 /* bytes in config block */ 1425 cbp->byte_count = FXP_CONFIG_LEN; 1426 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1427 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1428 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1429 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1430 cbp->type_enable = 0; /* actually reserved */ 1431 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1432 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1433 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1434 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1435 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1436 cbp->late_scb = 0; /* (don't) defer SCB update */ 1437 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1438 cbp->ci_int = 1; /* interrupt on CU idle */ 1439 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1440 cbp->ext_stats_dis = 1; /* disable extended counters */ 1441 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1442 cbp->save_bf = save_bf;/* save bad frames */ 1443 cbp->disc_short_rx = !prm; /* discard short packets */ 1444 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1445 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1446 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1447 /* interface mode */ 1448 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1449 cbp->csma_dis = 0; /* (don't) disable link */ 1450 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1451 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1452 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1453 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1454 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1455 cbp->nsai = 1; /* (don't) disable source addr insert */ 1456 cbp->preamble_length = 2; /* (7 byte) preamble */ 1457 cbp->loopback = 0; /* (don't) loopback */ 1458 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1459 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1460 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1461 cbp->promiscuous = prm; /* promiscuous mode */ 1462 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1463 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1464 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1465 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1466 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1467 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1468 cbp->padding = 1; /* (do) pad short tx packets */ 1469 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1470 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1471 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1472 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1473 /* must set wake_en in PMCSR also */ 1474 cbp->force_fdx = 0; /* (don't) force full duplex */ 1475 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1476 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1477 cbp->mc_all = allm; /* accept all multicasts */ 1478 1479 if (sc->sc_rev < FXP_REV_82558_A4) { 1480 /* 1481 * The i82557 has no hardware flow control, the values 1482 * here are the defaults for the chip. 1483 */ 1484 cbp->fc_delay_lsb = 0; 1485 cbp->fc_delay_msb = 0x40; 1486 cbp->pri_fc_thresh = 3; 1487 cbp->tx_fc_dis = 0; 1488 cbp->rx_fc_restop = 0; 1489 cbp->rx_fc_restart = 0; 1490 cbp->fc_filter = 0; 1491 cbp->pri_fc_loc = 1; 1492 } else { 1493 cbp->fc_delay_lsb = 0x1f; 1494 cbp->fc_delay_msb = 0x01; 1495 cbp->pri_fc_thresh = 3; 1496 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1497 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1498 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1499 cbp->fc_filter = !prm; /* drop FC frames to host */ 1500 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1501 } 1502 1503 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1504 1505 /* 1506 * Start the config command/DMA. 1507 */ 1508 fxp_scb_wait(sc); 1509 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1510 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1511 /* ...and wait for it to complete. */ 1512 i = 1000; 1513 do { 1514 FXP_CDCONFIGSYNC(sc, 1515 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1516 DELAY(1); 1517 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1518 if (i == 0) { 1519 printf("%s at line %d: dmasync timeout\n", 1520 sc->sc_dev.dv_xname, __LINE__); 1521 return ETIMEDOUT; 1522 } 1523 1524 /* 1525 * Initialize the station address. 1526 */ 1527 cb_ias = &sc->sc_control_data->fcd_iascb; 1528 /* BIG_ENDIAN: no need to swap to store 0 */ 1529 cb_ias->cb_status = 0; 1530 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1531 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1532 cb_ias->link_addr = 0xffffffff; 1533 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1534 1535 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1536 1537 /* 1538 * Start the IAS (Individual Address Setup) command/DMA. 1539 */ 1540 fxp_scb_wait(sc); 1541 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1542 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1543 /* ...and wait for it to complete. */ 1544 i = 1000; 1545 do { 1546 FXP_CDIASSYNC(sc, 1547 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1548 DELAY(1); 1549 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1550 if (i == 0) { 1551 printf("%s at line %d: dmasync timeout\n", 1552 sc->sc_dev.dv_xname, __LINE__); 1553 return ETIMEDOUT; 1554 } 1555 1556 /* 1557 * Initialize the transmit descriptor ring. txlast is initialized 1558 * to the end of the list so that it will wrap around to the first 1559 * descriptor when the first packet is transmitted. 1560 */ 1561 for (i = 0; i < FXP_NTXCB; i++) { 1562 txd = FXP_CDTX(sc, i); 1563 memset(txd, 0, sizeof(*txd)); 1564 txd->txd_txcb.cb_command = 1565 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1566 txd->txd_txcb.link_addr = 1567 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1568 if (sc->sc_flags & FXPF_EXT_TXCB) 1569 txd->txd_txcb.tbd_array_addr = 1570 htole32(FXP_CDTBDADDR(sc, i) + 1571 (2 * sizeof(struct fxp_tbd))); 1572 else 1573 txd->txd_txcb.tbd_array_addr = 1574 htole32(FXP_CDTBDADDR(sc, i)); 1575 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1576 } 1577 sc->sc_txpending = 0; 1578 sc->sc_txdirty = 0; 1579 sc->sc_txlast = FXP_NTXCB - 1; 1580 1581 /* 1582 * Initialize the receive buffer list. 1583 */ 1584 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1585 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1586 rxmap = FXP_RXMAP_GET(sc); 1587 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1588 printf("%s: unable to allocate or map rx " 1589 "buffer %d, error = %d\n", 1590 sc->sc_dev.dv_xname, 1591 sc->sc_rxq.ifq_len, error); 1592 /* 1593 * XXX Should attempt to run with fewer receive 1594 * XXX buffers instead of just failing. 1595 */ 1596 FXP_RXMAP_PUT(sc, rxmap); 1597 fxp_rxdrain(sc); 1598 goto out; 1599 } 1600 } 1601 sc->sc_rxidle = 0; 1602 1603 /* 1604 * Give the transmit ring to the chip. We do this by pointing 1605 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1606 * issuing a start command. It will execute the NOP and then 1607 * suspend, pointing at the first descriptor. 1608 */ 1609 fxp_scb_wait(sc); 1610 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1611 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1612 1613 /* 1614 * Initialize receiver buffer area - RFA. 1615 */ 1616 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1617 fxp_scb_wait(sc); 1618 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1619 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1620 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1621 1622 if (sc->sc_flags & FXPF_MII) { 1623 /* 1624 * Set current media. 1625 */ 1626 mii_mediachg(&sc->sc_mii); 1627 } 1628 1629 /* 1630 * ...all done! 1631 */ 1632 ifp->if_flags |= IFF_RUNNING; 1633 ifp->if_flags &= ~IFF_OACTIVE; 1634 1635 /* 1636 * Start the one second timer. 1637 */ 1638 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1639 1640 /* 1641 * Attempt to start output on the interface. 1642 */ 1643 fxp_start(ifp); 1644 1645 out: 1646 if (error) { 1647 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1648 ifp->if_timer = 0; 1649 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1650 } 1651 return (error); 1652 } 1653 1654 /* 1655 * Change media according to request. 1656 */ 1657 int 1658 fxp_mii_mediachange(struct ifnet *ifp) 1659 { 1660 struct fxp_softc *sc = ifp->if_softc; 1661 1662 if (ifp->if_flags & IFF_UP) 1663 mii_mediachg(&sc->sc_mii); 1664 return (0); 1665 } 1666 1667 /* 1668 * Notify the world which media we're using. 1669 */ 1670 void 1671 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1672 { 1673 struct fxp_softc *sc = ifp->if_softc; 1674 1675 if(sc->sc_enabled == 0) { 1676 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1677 ifmr->ifm_status = 0; 1678 return; 1679 } 1680 1681 mii_pollstat(&sc->sc_mii); 1682 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1683 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1684 } 1685 1686 int 1687 fxp_80c24_mediachange(struct ifnet *ifp) 1688 { 1689 1690 /* Nothing to do here. */ 1691 return (0); 1692 } 1693 1694 void 1695 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1696 { 1697 struct fxp_softc *sc = ifp->if_softc; 1698 1699 /* 1700 * Media is currently-selected media. We cannot determine 1701 * the link status. 1702 */ 1703 ifmr->ifm_status = 0; 1704 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1705 } 1706 1707 /* 1708 * Add a buffer to the end of the RFA buffer list. 1709 * Return 0 if successful, error code on failure. 1710 * 1711 * The RFA struct is stuck at the beginning of mbuf cluster and the 1712 * data pointer is fixed up to point just past it. 1713 */ 1714 int 1715 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1716 { 1717 struct mbuf *m; 1718 int error; 1719 1720 MGETHDR(m, M_DONTWAIT, MT_DATA); 1721 if (m == NULL) 1722 return (ENOBUFS); 1723 1724 MCLGET(m, M_DONTWAIT); 1725 if ((m->m_flags & M_EXT) == 0) { 1726 m_freem(m); 1727 return (ENOBUFS); 1728 } 1729 1730 if (unload) 1731 bus_dmamap_unload(sc->sc_dmat, rxmap); 1732 1733 M_SETCTX(m, rxmap); 1734 1735 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1736 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1737 if (error) { 1738 printf("%s: can't load rx DMA map %d, error = %d\n", 1739 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1740 panic("fxp_add_rfabuf"); /* XXX */ 1741 } 1742 1743 FXP_INIT_RFABUF(sc, m); 1744 1745 return (0); 1746 } 1747 1748 int 1749 fxp_mdi_read(struct device *self, int phy, int reg) 1750 { 1751 struct fxp_softc *sc = (struct fxp_softc *)self; 1752 int count = 10000; 1753 int value; 1754 1755 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1756 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1757 1758 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1759 && count--) 1760 DELAY(10); 1761 1762 if (count <= 0) 1763 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1764 1765 return (value & 0xffff); 1766 } 1767 1768 void 1769 fxp_statchg(struct device *self) 1770 { 1771 struct fxp_softc *sc = (void *) self; 1772 1773 /* 1774 * Determine whether or not we have to work-around the 1775 * Resume Bug. 1776 */ 1777 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1778 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1779 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1780 else 1781 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1782 } 1783 } 1784 1785 void 1786 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1787 { 1788 struct fxp_softc *sc = (struct fxp_softc *)self; 1789 int count = 10000; 1790 1791 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1792 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1793 (value & 0xffff)); 1794 1795 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1796 count--) 1797 DELAY(10); 1798 1799 if (count <= 0) 1800 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1801 } 1802 1803 int 1804 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1805 { 1806 struct fxp_softc *sc = ifp->if_softc; 1807 struct ifreq *ifr = (struct ifreq *)data; 1808 int s, error; 1809 1810 s = splnet(); 1811 1812 switch (cmd) { 1813 case SIOCSIFMEDIA: 1814 case SIOCGIFMEDIA: 1815 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1816 break; 1817 1818 default: 1819 error = ether_ioctl(ifp, cmd, data); 1820 if (error == ENETRESET) { 1821 if (sc->sc_enabled) { 1822 /* 1823 * Multicast list has changed; set the 1824 * hardware filter accordingly. 1825 */ 1826 if (sc->sc_txpending) { 1827 sc->sc_flags |= FXPF_WANTINIT; 1828 error = 0; 1829 } else 1830 error = fxp_init(ifp); 1831 } else 1832 error = 0; 1833 } 1834 break; 1835 } 1836 1837 /* Try to get more packets going. */ 1838 if (sc->sc_enabled) 1839 fxp_start(ifp); 1840 1841 splx(s); 1842 return (error); 1843 } 1844 1845 /* 1846 * Program the multicast filter. 1847 * 1848 * This function must be called at splnet(). 1849 */ 1850 void 1851 fxp_mc_setup(struct fxp_softc *sc) 1852 { 1853 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1854 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1855 struct ethercom *ec = &sc->sc_ethercom; 1856 struct ether_multi *enm; 1857 struct ether_multistep step; 1858 int count, nmcasts; 1859 1860 #ifdef DIAGNOSTIC 1861 if (sc->sc_txpending) 1862 panic("fxp_mc_setup: pending transmissions"); 1863 #endif 1864 1865 ifp->if_flags &= ~IFF_ALLMULTI; 1866 1867 /* 1868 * Initialize multicast setup descriptor. 1869 */ 1870 nmcasts = 0; 1871 ETHER_FIRST_MULTI(step, ec, enm); 1872 while (enm != NULL) { 1873 /* 1874 * Check for too many multicast addresses or if we're 1875 * listening to a range. Either way, we simply have 1876 * to accept all multicasts. 1877 */ 1878 if (nmcasts >= MAXMCADDR || 1879 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1880 ETHER_ADDR_LEN) != 0) { 1881 /* 1882 * Callers of this function must do the 1883 * right thing with this. If we're called 1884 * from outside fxp_init(), the caller must 1885 * detect if the state if IFF_ALLMULTI changes. 1886 * If it does, the caller must then call 1887 * fxp_init(), since allmulti is handled by 1888 * the config block. 1889 */ 1890 ifp->if_flags |= IFF_ALLMULTI; 1891 return; 1892 } 1893 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1894 ETHER_ADDR_LEN); 1895 nmcasts++; 1896 ETHER_NEXT_MULTI(step, enm); 1897 } 1898 1899 /* BIG_ENDIAN: no need to swap to store 0 */ 1900 mcsp->cb_status = 0; 1901 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1902 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 1903 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 1904 1905 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1906 1907 /* 1908 * Wait until the command unit is not active. This should never 1909 * happen since nothing is queued, but make sure anyway. 1910 */ 1911 count = 100; 1912 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 1913 FXP_SCB_CUS_ACTIVE && --count) 1914 DELAY(1); 1915 if (count == 0) { 1916 printf("%s at line %d: command queue timeout\n", 1917 sc->sc_dev.dv_xname, __LINE__); 1918 return; 1919 } 1920 1921 /* 1922 * Start the multicast setup command/DMA. 1923 */ 1924 fxp_scb_wait(sc); 1925 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 1926 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1927 1928 /* ...and wait for it to complete. */ 1929 count = 1000; 1930 do { 1931 FXP_CDMCSSYNC(sc, 1932 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1933 DELAY(1); 1934 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 1935 if (count == 0) { 1936 printf("%s at line %d: dmasync timeout\n", 1937 sc->sc_dev.dv_xname, __LINE__); 1938 return; 1939 } 1940 } 1941 1942 int 1943 fxp_enable(struct fxp_softc *sc) 1944 { 1945 1946 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 1947 if ((*sc->sc_enable)(sc) != 0) { 1948 printf("%s: device enable failed\n", 1949 sc->sc_dev.dv_xname); 1950 return (EIO); 1951 } 1952 } 1953 1954 sc->sc_enabled = 1; 1955 return (0); 1956 } 1957 1958 void 1959 fxp_disable(struct fxp_softc *sc) 1960 { 1961 1962 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 1963 (*sc->sc_disable)(sc); 1964 sc->sc_enabled = 0; 1965 } 1966 } 1967 1968 /* 1969 * fxp_activate: 1970 * 1971 * Handle device activation/deactivation requests. 1972 */ 1973 int 1974 fxp_activate(struct device *self, enum devact act) 1975 { 1976 struct fxp_softc *sc = (void *) self; 1977 int s, error = 0; 1978 1979 s = splnet(); 1980 switch (act) { 1981 case DVACT_ACTIVATE: 1982 error = EOPNOTSUPP; 1983 break; 1984 1985 case DVACT_DEACTIVATE: 1986 if (sc->sc_flags & FXPF_MII) 1987 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 1988 MII_OFFSET_ANY); 1989 if_deactivate(&sc->sc_ethercom.ec_if); 1990 break; 1991 } 1992 splx(s); 1993 1994 return (error); 1995 } 1996 1997 /* 1998 * fxp_detach: 1999 * 2000 * Detach an i82557 interface. 2001 */ 2002 int 2003 fxp_detach(struct fxp_softc *sc) 2004 { 2005 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2006 int i; 2007 2008 /* Succeed now if there's no work to do. */ 2009 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2010 return (0); 2011 2012 /* Unhook our tick handler. */ 2013 callout_stop(&sc->sc_callout); 2014 2015 if (sc->sc_flags & FXPF_MII) { 2016 /* Detach all PHYs */ 2017 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2018 } 2019 2020 /* Delete all remaining media. */ 2021 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2022 2023 #if NRND > 0 2024 rnd_detach_source(&sc->rnd_source); 2025 #endif 2026 ether_ifdetach(ifp); 2027 if_detach(ifp); 2028 2029 for (i = 0; i < FXP_NRFABUFS; i++) { 2030 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2031 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2032 } 2033 2034 for (i = 0; i < FXP_NTXCB; i++) { 2035 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2036 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2037 } 2038 2039 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2040 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2041 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2042 sizeof(struct fxp_control_data)); 2043 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2044 2045 shutdownhook_disestablish(sc->sc_sdhook); 2046 powerhook_disestablish(sc->sc_powerhook); 2047 2048 return (0); 2049 } 2050
Indexes created Mon Sep 29 03:10:08 GMT 2025