i82557.c revision 1.63
1 /* $NetBSD: i82557.c,v 1.63 2002/04/04 23:15:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.63 2002/04/04 23:15:43 thorpej Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 /* 118 * NOTE! On the Alpha, we have an alignment constraint. The 119 * card DMAs the packet immediately following the RFA. However, 120 * the first thing in the packet is a 14-byte Ethernet header. 121 * This means that the packet is misaligned. To compensate, 122 * we actually offset the RFA 2 bytes into the cluster. This 123 * alignes the packet after the Ethernet header at a 32-bit 124 * boundary. HOWEVER! This means that the RFA is misaligned! 125 */ 126 #define RFA_ALIGNMENT_FUDGE 2 127 128 /* 129 * The configuration byte map has several undefined fields which 130 * must be one or must be zero. Set up a template for these bits 131 * only (assuming an i82557 chip), leaving the actual configuration 132 * for fxp_init(). 133 * 134 * See the definition of struct fxp_cb_config for the bit definitions. 135 */ 136 const u_int8_t fxp_cb_config_template[] = { 137 0x0, 0x0, /* cb_status */ 138 0x0, 0x0, /* cb_command */ 139 0x0, 0x0, 0x0, 0x0, /* link_addr */ 140 0x0, /* 0 */ 141 0x0, /* 1 */ 142 0x0, /* 2 */ 143 0x0, /* 3 */ 144 0x0, /* 4 */ 145 0x0, /* 5 */ 146 0x32, /* 6 */ 147 0x0, /* 7 */ 148 0x0, /* 8 */ 149 0x0, /* 9 */ 150 0x6, /* 10 */ 151 0x0, /* 11 */ 152 0x0, /* 12 */ 153 0x0, /* 13 */ 154 0xf2, /* 14 */ 155 0x48, /* 15 */ 156 0x0, /* 16 */ 157 0x40, /* 17 */ 158 0xf0, /* 18 */ 159 0x0, /* 19 */ 160 0x3f, /* 20 */ 161 0x5, /* 21 */ 162 0x0, /* 22 */ 163 0x0, /* 23 */ 164 0x0, /* 24 */ 165 0x0, /* 25 */ 166 0x0, /* 26 */ 167 0x0, /* 27 */ 168 0x0, /* 28 */ 169 0x0, /* 29 */ 170 0x0, /* 30 */ 171 0x0, /* 31 */ 172 }; 173 174 void fxp_mii_initmedia(struct fxp_softc *); 175 int fxp_mii_mediachange(struct ifnet *); 176 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 177 178 void fxp_80c24_initmedia(struct fxp_softc *); 179 int fxp_80c24_mediachange(struct ifnet *); 180 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 181 182 void fxp_start(struct ifnet *); 183 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 184 void fxp_watchdog(struct ifnet *); 185 int fxp_init(struct ifnet *); 186 void fxp_stop(struct ifnet *, int); 187 188 void fxp_txintr(struct fxp_softc *); 189 void fxp_rxintr(struct fxp_softc *); 190 191 void fxp_rxdrain(struct fxp_softc *); 192 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 193 int fxp_mdi_read(struct device *, int, int); 194 void fxp_statchg(struct device *); 195 void fxp_mdi_write(struct device *, int, int, int); 196 void fxp_autosize_eeprom(struct fxp_softc*); 197 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 198 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 199 void fxp_eeprom_update_cksum(struct fxp_softc *); 200 void fxp_get_info(struct fxp_softc *, u_int8_t *); 201 void fxp_tick(void *); 202 void fxp_mc_setup(struct fxp_softc *); 203 204 void fxp_shutdown(void *); 205 void fxp_power(int, void *); 206 207 int fxp_copy_small = 0; 208 209 struct fxp_phytype { 210 int fp_phy; /* type of PHY, -1 for MII at the end. */ 211 void (*fp_init)(struct fxp_softc *); 212 } fxp_phytype_table[] = { 213 { FXP_PHY_80C24, fxp_80c24_initmedia }, 214 { -1, fxp_mii_initmedia }, 215 }; 216 217 /* 218 * Set initial transmit threshold at 64 (512 bytes). This is 219 * increased by 64 (512 bytes) at a time, to maximum of 192 220 * (1536 bytes), if an underrun occurs. 221 */ 222 static int tx_threshold = 64; 223 224 /* 225 * Wait for the previous command to be accepted (but not necessarily 226 * completed). 227 */ 228 static __inline void 229 fxp_scb_wait(struct fxp_softc *sc) 230 { 231 int i = 10000; 232 233 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 234 delay(2); 235 if (i == 0) 236 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 237 } 238 239 /* 240 * Submit a command to the i82557. 241 */ 242 static __inline void 243 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 244 { 245 246 if (cmd == FXP_SCB_COMMAND_CU_RESUME && 247 (sc->sc_flags & FXPF_FIX_RESUME_BUG) != 0) { 248 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_NOP); 249 fxp_scb_wait(sc); 250 } 251 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 252 } 253 254 /* 255 * Finish attaching an i82557 interface. Called by bus-specific front-end. 256 */ 257 void 258 fxp_attach(struct fxp_softc *sc) 259 { 260 u_int8_t enaddr[ETHER_ADDR_LEN]; 261 struct ifnet *ifp; 262 bus_dma_segment_t seg; 263 int rseg, i, error; 264 struct fxp_phytype *fp; 265 266 callout_init(&sc->sc_callout); 267 268 /* Start out using the standard RFA. */ 269 sc->sc_rfa_size = RFA_SIZE; 270 271 /* 272 * Enable some good stuff on i82558 and later. 273 */ 274 if (sc->sc_rev >= FXP_REV_82558_A4) { 275 /* Enable the extended TxCB. */ 276 sc->sc_flags |= FXPF_EXT_TXCB; 277 } 278 279 /* 280 * Allocate the control data structures, and create and load the 281 * DMA map for it. 282 */ 283 if ((error = bus_dmamem_alloc(sc->sc_dmat, 284 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 285 0)) != 0) { 286 printf("%s: unable to allocate control data, error = %d\n", 287 sc->sc_dev.dv_xname, error); 288 goto fail_0; 289 } 290 291 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 292 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 293 BUS_DMA_COHERENT)) != 0) { 294 printf("%s: unable to map control data, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 goto fail_1; 297 } 298 sc->sc_cdseg = seg; 299 sc->sc_cdnseg = rseg; 300 301 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 302 303 if ((error = bus_dmamap_create(sc->sc_dmat, 304 sizeof(struct fxp_control_data), 1, 305 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 306 printf("%s: unable to create control data DMA map, " 307 "error = %d\n", sc->sc_dev.dv_xname, error); 308 goto fail_2; 309 } 310 311 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 312 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 313 0)) != 0) { 314 printf("%s: can't load control data DMA map, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_3; 317 } 318 319 /* 320 * Create the transmit buffer DMA maps. 321 */ 322 for (i = 0; i < FXP_NTXCB; i++) { 323 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 324 FXP_NTXSEG, MCLBYTES, 0, 0, 325 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 326 printf("%s: unable to create tx DMA map %d, " 327 "error = %d\n", sc->sc_dev.dv_xname, i, error); 328 goto fail_4; 329 } 330 } 331 332 /* 333 * Create the receive buffer DMA maps. 334 */ 335 for (i = 0; i < FXP_NRFABUFS; i++) { 336 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 337 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 338 printf("%s: unable to create rx DMA map %d, " 339 "error = %d\n", sc->sc_dev.dv_xname, i, error); 340 goto fail_5; 341 } 342 } 343 344 /* Initialize MAC address and media structures. */ 345 fxp_get_info(sc, enaddr); 346 347 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 348 ether_sprintf(enaddr)); 349 350 ifp = &sc->sc_ethercom.ec_if; 351 352 /* 353 * Get info about our media interface, and initialize it. Note 354 * the table terminates itself with a phy of -1, indicating 355 * that we're using MII. 356 */ 357 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 358 if (fp->fp_phy == sc->phy_primary_device) 359 break; 360 (*fp->fp_init)(sc); 361 362 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 363 ifp->if_softc = sc; 364 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 365 ifp->if_ioctl = fxp_ioctl; 366 ifp->if_start = fxp_start; 367 ifp->if_watchdog = fxp_watchdog; 368 ifp->if_init = fxp_init; 369 ifp->if_stop = fxp_stop; 370 IFQ_SET_READY(&ifp->if_snd); 371 372 /* 373 * We can support 802.1Q VLAN-sized frames. 374 */ 375 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 376 377 /* 378 * Attach the interface. 379 */ 380 if_attach(ifp); 381 ether_ifattach(ifp, enaddr); 382 #if NRND > 0 383 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 384 RND_TYPE_NET, 0); 385 #endif 386 387 #ifdef FXP_EVENT_COUNTERS 388 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 389 NULL, sc->sc_dev.dv_xname, "txstall"); 390 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 391 NULL, sc->sc_dev.dv_xname, "txintr"); 392 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 393 NULL, sc->sc_dev.dv_xname, "rxintr"); 394 #endif /* FXP_EVENT_COUNTERS */ 395 396 /* 397 * Add shutdown hook so that DMA is disabled prior to reboot. Not 398 * doing do could allow DMA to corrupt kernel memory during the 399 * reboot before the driver initializes. 400 */ 401 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 402 if (sc->sc_sdhook == NULL) 403 printf("%s: WARNING: unable to establish shutdown hook\n", 404 sc->sc_dev.dv_xname); 405 /* 406 * Add suspend hook, for similar reasons.. 407 */ 408 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 409 if (sc->sc_powerhook == NULL) 410 printf("%s: WARNING: unable to establish power hook\n", 411 sc->sc_dev.dv_xname); 412 413 /* The attach is successful. */ 414 sc->sc_flags |= FXPF_ATTACHED; 415 416 return; 417 418 /* 419 * Free any resources we've allocated during the failed attach 420 * attempt. Do this in reverse order and fall though. 421 */ 422 fail_5: 423 for (i = 0; i < FXP_NRFABUFS; i++) { 424 if (sc->sc_rxmaps[i] != NULL) 425 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 426 } 427 fail_4: 428 for (i = 0; i < FXP_NTXCB; i++) { 429 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 430 bus_dmamap_destroy(sc->sc_dmat, 431 FXP_DSTX(sc, i)->txs_dmamap); 432 } 433 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 434 fail_3: 435 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 436 fail_2: 437 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 438 sizeof(struct fxp_control_data)); 439 fail_1: 440 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 441 fail_0: 442 return; 443 } 444 445 void 446 fxp_mii_initmedia(struct fxp_softc *sc) 447 { 448 int flags; 449 450 sc->sc_flags |= FXPF_MII; 451 452 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 453 sc->sc_mii.mii_readreg = fxp_mdi_read; 454 sc->sc_mii.mii_writereg = fxp_mdi_write; 455 sc->sc_mii.mii_statchg = fxp_statchg; 456 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_mii_mediachange, 457 fxp_mii_mediastatus); 458 459 flags = MIIF_NOISOLATE; 460 if (sc->sc_rev >= FXP_REV_82558_A4) 461 flags |= MIIF_DOPAUSE; 462 /* 463 * The i82557 wedges if all of its PHYs are isolated! 464 */ 465 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 466 MII_OFFSET_ANY, flags); 467 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 468 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 469 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 470 } else 471 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 472 } 473 474 void 475 fxp_80c24_initmedia(struct fxp_softc *sc) 476 { 477 478 /* 479 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 480 * doesn't have a programming interface of any sort. The 481 * media is sensed automatically based on how the link partner 482 * is configured. This is, in essence, manual configuration. 483 */ 484 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 485 sc->sc_dev.dv_xname); 486 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 487 fxp_80c24_mediastatus); 488 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 489 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 490 } 491 492 /* 493 * Device shutdown routine. Called at system shutdown after sync. The 494 * main purpose of this routine is to shut off receiver DMA so that 495 * kernel memory doesn't get clobbered during warmboot. 496 */ 497 void 498 fxp_shutdown(void *arg) 499 { 500 struct fxp_softc *sc = arg; 501 502 /* 503 * Since the system's going to halt shortly, don't bother 504 * freeing mbufs. 505 */ 506 fxp_stop(&sc->sc_ethercom.ec_if, 0); 507 } 508 /* 509 * Power handler routine. Called when the system is transitioning 510 * into/out of power save modes. As with fxp_shutdown, the main 511 * purpose of this routine is to shut off receiver DMA so it doesn't 512 * clobber kernel memory at the wrong time. 513 */ 514 void 515 fxp_power(int why, void *arg) 516 { 517 struct fxp_softc *sc = arg; 518 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 519 int s; 520 521 s = splnet(); 522 switch (why) { 523 case PWR_SUSPEND: 524 case PWR_STANDBY: 525 fxp_stop(ifp, 0); 526 break; 527 case PWR_RESUME: 528 if (ifp->if_flags & IFF_UP) 529 fxp_init(ifp); 530 break; 531 case PWR_SOFTSUSPEND: 532 case PWR_SOFTSTANDBY: 533 case PWR_SOFTRESUME: 534 break; 535 } 536 splx(s); 537 } 538 539 /* 540 * Initialize the interface media. 541 */ 542 void 543 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 544 { 545 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 546 547 /* 548 * Reset to a stable state. 549 */ 550 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 551 DELAY(10); 552 553 sc->sc_eeprom_size = 0; 554 fxp_autosize_eeprom(sc); 555 if(sc->sc_eeprom_size == 0) { 556 printf("%s: failed to detect EEPROM size\n", sc->sc_dev.dv_xname); 557 sc->sc_eeprom_size = 6; /* XXX panic here? */ 558 } 559 #ifdef DEBUG 560 printf("%s: detected %d word EEPROM\n", 561 sc->sc_dev.dv_xname, 562 1 << sc->sc_eeprom_size); 563 #endif 564 565 /* 566 * Get info about the primary PHY 567 */ 568 fxp_read_eeprom(sc, &data, 6, 1); 569 sc->phy_primary_device = 570 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 571 572 /* 573 * Read MAC address. 574 */ 575 fxp_read_eeprom(sc, myea, 0, 3); 576 enaddr[0] = myea[0] & 0xff; 577 enaddr[1] = myea[0] >> 8; 578 enaddr[2] = myea[1] & 0xff; 579 enaddr[3] = myea[1] >> 8; 580 enaddr[4] = myea[2] & 0xff; 581 enaddr[5] = myea[2] >> 8; 582 583 /* 584 * Systems based on the ICH2/ICH2-M chip from Intel, as well 585 * as some i82559 designs, have a defect where the chip can 586 * cause a PCI protocol violation if it receives a CU_RESUME 587 * command when it is entering the IDLE state. 588 * 589 * The work-around is to disable Dynamic Standby Mode, so that 590 * the chip never deasserts #CLKRUN, and always remains in the 591 * active state. 592 * 593 * Unfortunately, the only way to disable Dynamic Standby is 594 * to frob an EEPROM setting and reboot (the EEPROM setting 595 * is only consulted when the PCI bus comes out of reset). 596 * 597 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 598 */ 599 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 600 fxp_read_eeprom(sc, &data, 10, 1); 601 if (data & 0x02) { /* STB enable */ 602 printf("%s: disabling Dynamic Standby Mode in EEPROM\n", 603 sc->sc_dev.dv_xname); 604 data &= ~0x02; 605 fxp_write_eeprom(sc, &data, 10, 1); 606 printf("%s: new EEPROM ID: 0x%04x\n", 607 sc->sc_dev.dv_xname, data); 608 fxp_eeprom_update_cksum(sc); 609 printf("%s: PLEASE RESET YOUR SYSTEM FOR CHANGE TO " 610 "TAKE EFFECT!\n", sc->sc_dev.dv_xname); 611 } else { 612 #if 1 613 /* 614 * If Dynamic Standby Mode is disabled, we don't 615 * need to work around the Resume bug anymore. 616 */ 617 sc->sc_flags &= ~FXPF_HAS_RESUME_BUG; 618 #endif 619 } 620 } 621 } 622 623 static void 624 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 625 { 626 uint16_t reg; 627 int x; 628 629 for (x = 1 << (len - 1); x != 0; x >>= 1) { 630 if (data & x) 631 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 632 else 633 reg = FXP_EEPROM_EECS; 634 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 635 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 636 reg | FXP_EEPROM_EESK); 637 DELAY(4); 638 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 639 DELAY(4); 640 } 641 } 642 643 /* 644 * Figure out EEPROM size. 645 * 646 * 559's can have either 64-word or 256-word EEPROMs, the 558 647 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 648 * talks about the existance of 16 to 256 word EEPROMs. 649 * 650 * The only known sizes are 64 and 256, where the 256 version is used 651 * by CardBus cards to store CIS information. 652 * 653 * The address is shifted in msb-to-lsb, and after the last 654 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 655 * after which follows the actual data. We try to detect this zero, by 656 * probing the data-out bit in the EEPROM control register just after 657 * having shifted in a bit. If the bit is zero, we assume we've 658 * shifted enough address bits. The data-out should be tri-state, 659 * before this, which should translate to a logical one. 660 * 661 * Other ways to do this would be to try to read a register with known 662 * contents with a varying number of address bits, but no such 663 * register seem to be available. The high bits of register 10 are 01 664 * on the 558 and 559, but apparently not on the 557. 665 * 666 * The Linux driver computes a checksum on the EEPROM data, but the 667 * value of this checksum is not very well documented. 668 */ 669 670 void 671 fxp_autosize_eeprom(struct fxp_softc *sc) 672 { 673 int x; 674 675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 676 677 /* Shift in read opcode. */ 678 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 679 680 /* 681 * Shift in address, wait for the dummy zero following a correct 682 * address shift. 683 */ 684 for (x = 1; x <= 8; x++) { 685 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 686 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 687 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 688 DELAY(4); 689 if((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 690 FXP_EEPROM_EEDO) == 0) 691 break; 692 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 693 DELAY(4); 694 } 695 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 696 DELAY(4); 697 if(x != 6 && x != 8) { 698 #ifdef DEBUG 699 printf("%s: strange EEPROM size (%d)\n", 700 sc->sc_dev.dv_xname, 1 << x); 701 #endif 702 } else 703 sc->sc_eeprom_size = x; 704 } 705 706 /* 707 * Read from the serial EEPROM. Basically, you manually shift in 708 * the read opcode (one bit at a time) and then shift in the address, 709 * and then you shift out the data (all of this one bit at a time). 710 * The word size is 16 bits, so you have to provide the address for 711 * every 16 bits of data. 712 */ 713 void 714 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 715 { 716 u_int16_t reg; 717 int i, x; 718 719 for (i = 0; i < words; i++) { 720 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 721 722 /* Shift in read opcode. */ 723 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 724 725 /* Shift in address. */ 726 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 727 728 reg = FXP_EEPROM_EECS; 729 data[i] = 0; 730 731 /* Shift out data. */ 732 for (x = 16; x > 0; x--) { 733 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 734 reg | FXP_EEPROM_EESK); 735 DELAY(4); 736 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 737 FXP_EEPROM_EEDO) 738 data[i] |= (1 << (x - 1)); 739 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 740 DELAY(4); 741 } 742 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 743 DELAY(4); 744 } 745 } 746 747 /* 748 * Write data to the serial EEPROM. 749 */ 750 void 751 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 752 { 753 int i, j; 754 755 for (i = 0; i < words; i++) { 756 /* Erase/write enable. */ 757 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 758 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 759 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 760 sc->sc_eeprom_size); 761 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 762 DELAY(4); 763 764 /* Shift in write opcode, address, data. */ 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 766 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 767 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 768 fxp_eeprom_shiftin(sc, data[i], 16); 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 770 DELAY(4); 771 772 /* Wait for the EEPROM to finish up. */ 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 774 DELAY(4); 775 for (j = 0; j < 1000; j++) { 776 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 777 FXP_EEPROM_EEDO) 778 break; 779 DELAY(50); 780 } 781 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 782 DELAY(4); 783 784 /* Erase/write disable. */ 785 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 786 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 787 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 788 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 789 DELAY(4); 790 } 791 } 792 793 /* 794 * Update the checksum of the EEPROM. 795 */ 796 void 797 fxp_eeprom_update_cksum(struct fxp_softc *sc) 798 { 799 int i; 800 uint16_t data, cksum; 801 802 cksum = 0; 803 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 804 fxp_read_eeprom(sc, &data, i, 1); 805 cksum += data; 806 } 807 i = (1 << sc->sc_eeprom_size) - 1; 808 cksum = 0xbaba - cksum; 809 fxp_read_eeprom(sc, &data, i, 1); 810 fxp_write_eeprom(sc, &cksum, i, 1); 811 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 812 sc->sc_dev.dv_xname, i, data, cksum); 813 } 814 815 /* 816 * Start packet transmission on the interface. 817 */ 818 void 819 fxp_start(struct ifnet *ifp) 820 { 821 struct fxp_softc *sc = ifp->if_softc; 822 struct mbuf *m0, *m; 823 struct fxp_txdesc *txd; 824 struct fxp_txsoft *txs; 825 bus_dmamap_t dmamap; 826 int error, lasttx, nexttx, opending, seg; 827 828 /* 829 * If we want a re-init, bail out now. 830 */ 831 if (sc->sc_flags & FXPF_WANTINIT) { 832 ifp->if_flags |= IFF_OACTIVE; 833 return; 834 } 835 836 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 837 return; 838 839 /* 840 * Remember the previous txpending and the current lasttx. 841 */ 842 opending = sc->sc_txpending; 843 lasttx = sc->sc_txlast; 844 845 /* 846 * Loop through the send queue, setting up transmit descriptors 847 * until we drain the queue, or use up all available transmit 848 * descriptors. 849 */ 850 for (;;) { 851 /* 852 * Grab a packet off the queue. 853 */ 854 IFQ_POLL(&ifp->if_snd, m0); 855 if (m0 == NULL) 856 break; 857 m = NULL; 858 859 if (sc->sc_txpending == FXP_NTXCB) { 860 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 861 break; 862 } 863 864 /* 865 * Get the next available transmit descriptor. 866 */ 867 nexttx = FXP_NEXTTX(sc->sc_txlast); 868 txd = FXP_CDTX(sc, nexttx); 869 txs = FXP_DSTX(sc, nexttx); 870 dmamap = txs->txs_dmamap; 871 872 /* 873 * Load the DMA map. If this fails, the packet either 874 * didn't fit in the allotted number of frags, or we were 875 * short on resources. In this case, we'll copy and try 876 * again. 877 */ 878 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 879 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 880 MGETHDR(m, M_DONTWAIT, MT_DATA); 881 if (m == NULL) { 882 printf("%s: unable to allocate Tx mbuf\n", 883 sc->sc_dev.dv_xname); 884 break; 885 } 886 if (m0->m_pkthdr.len > MHLEN) { 887 MCLGET(m, M_DONTWAIT); 888 if ((m->m_flags & M_EXT) == 0) { 889 printf("%s: unable to allocate Tx " 890 "cluster\n", sc->sc_dev.dv_xname); 891 m_freem(m); 892 break; 893 } 894 } 895 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 896 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 897 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 898 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 899 if (error) { 900 printf("%s: unable to load Tx buffer, " 901 "error = %d\n", sc->sc_dev.dv_xname, error); 902 break; 903 } 904 } 905 906 IFQ_DEQUEUE(&ifp->if_snd, m0); 907 if (m != NULL) { 908 m_freem(m0); 909 m0 = m; 910 } 911 912 /* Initialize the fraglist. */ 913 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 914 txd->txd_tbd[seg].tb_addr = 915 htole32(dmamap->dm_segs[seg].ds_addr); 916 txd->txd_tbd[seg].tb_size = 917 htole32(dmamap->dm_segs[seg].ds_len); 918 } 919 920 /* Sync the DMA map. */ 921 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 922 BUS_DMASYNC_PREWRITE); 923 924 /* 925 * Store a pointer to the packet so we can free it later. 926 */ 927 txs->txs_mbuf = m0; 928 929 /* 930 * Initialize the transmit descriptor. 931 */ 932 /* BIG_ENDIAN: no need to swap to store 0 */ 933 txd->txd_txcb.cb_status = 0; 934 txd->txd_txcb.cb_command = 935 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 936 txd->txd_txcb.tx_threshold = tx_threshold; 937 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 938 939 FXP_CDTXSYNC(sc, nexttx, 940 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 941 942 /* Advance the tx pointer. */ 943 sc->sc_txpending++; 944 sc->sc_txlast = nexttx; 945 946 #if NBPFILTER > 0 947 /* 948 * Pass packet to bpf if there is a listener. 949 */ 950 if (ifp->if_bpf) 951 bpf_mtap(ifp->if_bpf, m0); 952 #endif 953 } 954 955 if (sc->sc_txpending == FXP_NTXCB) { 956 /* No more slots; notify upper layer. */ 957 ifp->if_flags |= IFF_OACTIVE; 958 } 959 960 if (sc->sc_txpending != opending) { 961 /* 962 * We enqueued packets. If the transmitter was idle, 963 * reset the txdirty pointer. 964 */ 965 if (opending == 0) 966 sc->sc_txdirty = FXP_NEXTTX(lasttx); 967 968 /* 969 * Cause the chip to interrupt and suspend command 970 * processing once the last packet we've enqueued 971 * has been transmitted. 972 */ 973 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 974 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 975 FXP_CDTXSYNC(sc, sc->sc_txlast, 976 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 977 978 /* 979 * The entire packet chain is set up. Clear the suspend bit 980 * on the command prior to the first packet we set up. 981 */ 982 FXP_CDTXSYNC(sc, lasttx, 983 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 984 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 985 htole16(~FXP_CB_COMMAND_S); 986 FXP_CDTXSYNC(sc, lasttx, 987 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 988 989 /* 990 * Issue a Resume command in case the chip was suspended. 991 */ 992 fxp_scb_wait(sc); 993 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 994 995 /* Set a watchdog timer in case the chip flakes out. */ 996 ifp->if_timer = 5; 997 } 998 } 999 1000 /* 1001 * Process interface interrupts. 1002 */ 1003 int 1004 fxp_intr(void *arg) 1005 { 1006 struct fxp_softc *sc = arg; 1007 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1008 bus_dmamap_t rxmap; 1009 int claimed = 0; 1010 u_int8_t statack; 1011 1012 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1013 return (0); 1014 /* 1015 * If the interface isn't running, don't try to 1016 * service the interrupt.. just ack it and bail. 1017 */ 1018 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1019 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1020 if (statack) { 1021 claimed = 1; 1022 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1023 } 1024 return (claimed); 1025 } 1026 1027 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1028 claimed = 1; 1029 1030 /* 1031 * First ACK all the interrupts in this pass. 1032 */ 1033 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1034 1035 /* 1036 * Process receiver interrupts. If a no-resource (RNR) 1037 * condition exists, get whatever packets we can and 1038 * re-start the receiver. 1039 */ 1040 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1041 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1042 fxp_rxintr(sc); 1043 } 1044 1045 if (statack & FXP_SCB_STATACK_RNR) { 1046 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1047 fxp_scb_wait(sc); 1048 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1049 rxmap->dm_segs[0].ds_addr + 1050 RFA_ALIGNMENT_FUDGE); 1051 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1052 } 1053 1054 /* 1055 * Free any finished transmit mbuf chains. 1056 */ 1057 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1058 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1059 fxp_txintr(sc); 1060 1061 /* 1062 * Try to get more packets going. 1063 */ 1064 fxp_start(ifp); 1065 1066 if (sc->sc_txpending == 0) { 1067 /* 1068 * If we want a re-init, do that now. 1069 */ 1070 if (sc->sc_flags & FXPF_WANTINIT) 1071 (void) fxp_init(ifp); 1072 } 1073 } 1074 } 1075 1076 #if NRND > 0 1077 if (claimed) 1078 rnd_add_uint32(&sc->rnd_source, statack); 1079 #endif 1080 return (claimed); 1081 } 1082 1083 /* 1084 * Handle transmit completion interrupts. 1085 */ 1086 void 1087 fxp_txintr(struct fxp_softc *sc) 1088 { 1089 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1090 struct fxp_txdesc *txd; 1091 struct fxp_txsoft *txs; 1092 int i; 1093 u_int16_t txstat; 1094 1095 ifp->if_flags &= ~IFF_OACTIVE; 1096 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1097 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1098 txd = FXP_CDTX(sc, i); 1099 txs = FXP_DSTX(sc, i); 1100 1101 FXP_CDTXSYNC(sc, i, 1102 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1103 1104 txstat = le16toh(txd->txd_txcb.cb_status); 1105 1106 if ((txstat & FXP_CB_STATUS_C) == 0) 1107 break; 1108 1109 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1110 0, txs->txs_dmamap->dm_mapsize, 1111 BUS_DMASYNC_POSTWRITE); 1112 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1113 m_freem(txs->txs_mbuf); 1114 txs->txs_mbuf = NULL; 1115 } 1116 1117 /* Update the dirty transmit buffer pointer. */ 1118 sc->sc_txdirty = i; 1119 1120 /* 1121 * Cancel the watchdog timer if there are no pending 1122 * transmissions. 1123 */ 1124 if (sc->sc_txpending == 0) 1125 ifp->if_timer = 0; 1126 } 1127 1128 /* 1129 * Handle receive interrupts. 1130 */ 1131 void 1132 fxp_rxintr(struct fxp_softc *sc) 1133 { 1134 struct ethercom *ec = &sc->sc_ethercom; 1135 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1136 struct mbuf *m, *m0; 1137 bus_dmamap_t rxmap; 1138 struct fxp_rfa *rfa; 1139 u_int16_t len, rxstat; 1140 1141 for (;;) { 1142 m = sc->sc_rxq.ifq_head; 1143 rfa = FXP_MTORFA(m); 1144 rxmap = M_GETCTX(m, bus_dmamap_t); 1145 1146 FXP_RFASYNC(sc, m, 1147 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1148 1149 rxstat = le16toh(rfa->rfa_status); 1150 1151 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1152 /* 1153 * We have processed all of the 1154 * receive buffers. 1155 */ 1156 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1157 return; 1158 } 1159 1160 IF_DEQUEUE(&sc->sc_rxq, m); 1161 1162 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1163 1164 len = le16toh(rfa->actual_size) & 1165 (m->m_ext.ext_size - 1); 1166 1167 if (len < sizeof(struct ether_header)) { 1168 /* 1169 * Runt packet; drop it now. 1170 */ 1171 FXP_INIT_RFABUF(sc, m); 1172 continue; 1173 } 1174 1175 /* 1176 * If support for 802.1Q VLAN sized frames is 1177 * enabled, we need to do some additional error 1178 * checking (as we are saving bad frames, in 1179 * order to receive the larger ones). 1180 */ 1181 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1182 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1183 FXP_RFA_STATUS_RNR| 1184 FXP_RFA_STATUS_ALIGN| 1185 FXP_RFA_STATUS_CRC)) != 0) { 1186 FXP_INIT_RFABUF(sc, m); 1187 continue; 1188 } 1189 1190 /* 1191 * If the packet is small enough to fit in a 1192 * single header mbuf, allocate one and copy 1193 * the data into it. This greatly reduces 1194 * memory consumption when we receive lots 1195 * of small packets. 1196 * 1197 * Otherwise, we add a new buffer to the receive 1198 * chain. If this fails, we drop the packet and 1199 * recycle the old buffer. 1200 */ 1201 if (fxp_copy_small != 0 && len <= MHLEN) { 1202 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1203 if (m == NULL) 1204 goto dropit; 1205 memcpy(mtod(m0, caddr_t), 1206 mtod(m, caddr_t), len); 1207 FXP_INIT_RFABUF(sc, m); 1208 m = m0; 1209 } else { 1210 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1211 dropit: 1212 ifp->if_ierrors++; 1213 FXP_INIT_RFABUF(sc, m); 1214 continue; 1215 } 1216 } 1217 1218 m->m_pkthdr.rcvif = ifp; 1219 m->m_pkthdr.len = m->m_len = len; 1220 1221 #if NBPFILTER > 0 1222 /* 1223 * Pass this up to any BPF listeners, but only 1224 * pass it up the stack it its for us. 1225 */ 1226 if (ifp->if_bpf) 1227 bpf_mtap(ifp->if_bpf, m); 1228 #endif 1229 1230 /* Pass it on. */ 1231 (*ifp->if_input)(ifp, m); 1232 } 1233 } 1234 1235 /* 1236 * Update packet in/out/collision statistics. The i82557 doesn't 1237 * allow you to access these counters without doing a fairly 1238 * expensive DMA to get _all_ of the statistics it maintains, so 1239 * we do this operation here only once per second. The statistics 1240 * counters in the kernel are updated from the previous dump-stats 1241 * DMA and then a new dump-stats DMA is started. The on-chip 1242 * counters are zeroed when the DMA completes. If we can't start 1243 * the DMA immediately, we don't wait - we just prepare to read 1244 * them again next time. 1245 */ 1246 void 1247 fxp_tick(void *arg) 1248 { 1249 struct fxp_softc *sc = arg; 1250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1251 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1252 int s; 1253 1254 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1255 return; 1256 1257 s = splnet(); 1258 1259 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1260 1261 ifp->if_opackets += le32toh(sp->tx_good); 1262 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1263 if (sp->rx_good) { 1264 ifp->if_ipackets += le32toh(sp->rx_good); 1265 sc->sc_rxidle = 0; 1266 } else { 1267 sc->sc_rxidle++; 1268 } 1269 ifp->if_ierrors += 1270 le32toh(sp->rx_crc_errors) + 1271 le32toh(sp->rx_alignment_errors) + 1272 le32toh(sp->rx_rnr_errors) + 1273 le32toh(sp->rx_overrun_errors); 1274 /* 1275 * If any transmit underruns occurred, bump up the transmit 1276 * threshold by another 512 bytes (64 * 8). 1277 */ 1278 if (sp->tx_underruns) { 1279 ifp->if_oerrors += le32toh(sp->tx_underruns); 1280 if (tx_threshold < 192) 1281 tx_threshold += 64; 1282 } 1283 1284 /* 1285 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1286 * then assume the receiver has locked up and attempt to clear 1287 * the condition by reprogramming the multicast filter (actually, 1288 * resetting the interface). This is a work-around for a bug in 1289 * the 82557 where the receiver locks up if it gets certain types 1290 * of garbage in the syncronization bits prior to the packet header. 1291 * This bug is supposed to only occur in 10Mbps mode, but has been 1292 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1293 * speed transition). 1294 */ 1295 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1296 (void) fxp_init(ifp); 1297 splx(s); 1298 return; 1299 } 1300 /* 1301 * If there is no pending command, start another stats 1302 * dump. Otherwise punt for now. 1303 */ 1304 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1305 /* 1306 * Start another stats dump. 1307 */ 1308 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1309 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1310 } else { 1311 /* 1312 * A previous command is still waiting to be accepted. 1313 * Just zero our copy of the stats and wait for the 1314 * next timer event to update them. 1315 */ 1316 /* BIG_ENDIAN: no swap required to store 0 */ 1317 sp->tx_good = 0; 1318 sp->tx_underruns = 0; 1319 sp->tx_total_collisions = 0; 1320 1321 sp->rx_good = 0; 1322 sp->rx_crc_errors = 0; 1323 sp->rx_alignment_errors = 0; 1324 sp->rx_rnr_errors = 0; 1325 sp->rx_overrun_errors = 0; 1326 } 1327 1328 if (sc->sc_flags & FXPF_MII) { 1329 /* Tick the MII clock. */ 1330 mii_tick(&sc->sc_mii); 1331 } 1332 1333 splx(s); 1334 1335 /* 1336 * Schedule another timeout one second from now. 1337 */ 1338 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1339 } 1340 1341 /* 1342 * Drain the receive queue. 1343 */ 1344 void 1345 fxp_rxdrain(struct fxp_softc *sc) 1346 { 1347 bus_dmamap_t rxmap; 1348 struct mbuf *m; 1349 1350 for (;;) { 1351 IF_DEQUEUE(&sc->sc_rxq, m); 1352 if (m == NULL) 1353 break; 1354 rxmap = M_GETCTX(m, bus_dmamap_t); 1355 bus_dmamap_unload(sc->sc_dmat, rxmap); 1356 FXP_RXMAP_PUT(sc, rxmap); 1357 m_freem(m); 1358 } 1359 } 1360 1361 /* 1362 * Stop the interface. Cancels the statistics updater and resets 1363 * the interface. 1364 */ 1365 void 1366 fxp_stop(struct ifnet *ifp, int disable) 1367 { 1368 struct fxp_softc *sc = ifp->if_softc; 1369 struct fxp_txsoft *txs; 1370 int i; 1371 1372 /* 1373 * Turn down interface (done early to avoid bad interactions 1374 * between panics, shutdown hooks, and the watchdog timer) 1375 */ 1376 ifp->if_timer = 0; 1377 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1378 1379 /* 1380 * Cancel stats updater. 1381 */ 1382 callout_stop(&sc->sc_callout); 1383 if (sc->sc_flags & FXPF_MII) { 1384 /* Down the MII. */ 1385 mii_down(&sc->sc_mii); 1386 } 1387 1388 /* 1389 * Issue software reset 1390 */ 1391 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1392 DELAY(10); 1393 1394 /* 1395 * Release any xmit buffers. 1396 */ 1397 for (i = 0; i < FXP_NTXCB; i++) { 1398 txs = FXP_DSTX(sc, i); 1399 if (txs->txs_mbuf != NULL) { 1400 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1401 m_freem(txs->txs_mbuf); 1402 txs->txs_mbuf = NULL; 1403 } 1404 } 1405 sc->sc_txpending = 0; 1406 1407 if (disable) { 1408 fxp_rxdrain(sc); 1409 fxp_disable(sc); 1410 } 1411 1412 } 1413 1414 /* 1415 * Watchdog/transmission transmit timeout handler. Called when a 1416 * transmission is started on the interface, but no interrupt is 1417 * received before the timeout. This usually indicates that the 1418 * card has wedged for some reason. 1419 */ 1420 void 1421 fxp_watchdog(struct ifnet *ifp) 1422 { 1423 struct fxp_softc *sc = ifp->if_softc; 1424 1425 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1426 ifp->if_oerrors++; 1427 1428 (void) fxp_init(ifp); 1429 } 1430 1431 /* 1432 * Initialize the interface. Must be called at splnet(). 1433 */ 1434 int 1435 fxp_init(struct ifnet *ifp) 1436 { 1437 struct fxp_softc *sc = ifp->if_softc; 1438 struct fxp_cb_config *cbp; 1439 struct fxp_cb_ias *cb_ias; 1440 struct fxp_txdesc *txd; 1441 bus_dmamap_t rxmap; 1442 int i, prm, save_bf, lrxen, allm, error = 0; 1443 1444 if ((error = fxp_enable(sc)) != 0) 1445 goto out; 1446 1447 /* 1448 * Cancel any pending I/O 1449 */ 1450 fxp_stop(ifp, 0); 1451 1452 /* 1453 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1454 * flag, and this prevents the MII from detaching resulting in 1455 * a panic. The flags field should perhaps be split in runtime 1456 * flags and more static information. For now, just clear the 1457 * only other flag set. 1458 */ 1459 1460 sc->sc_flags &= ~FXPF_WANTINIT; 1461 1462 /* 1463 * Initialize base of CBL and RFA memory. Loading with zero 1464 * sets it up for regular linear addressing. 1465 */ 1466 fxp_scb_wait(sc); 1467 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1468 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1469 1470 fxp_scb_wait(sc); 1471 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1472 1473 /* 1474 * Initialize the multicast filter. Do this now, since we might 1475 * have to setup the config block differently. 1476 */ 1477 fxp_mc_setup(sc); 1478 1479 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1480 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1481 1482 /* 1483 * In order to support receiving 802.1Q VLAN frames, we have to 1484 * enable "save bad frames", since they are 4 bytes larger than 1485 * the normal Ethernet maximum frame length. On i82558 and later, 1486 * we have a better mechanism for this. 1487 */ 1488 save_bf = 0; 1489 lrxen = 0; 1490 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1491 if (sc->sc_rev < FXP_REV_82558_A4) 1492 save_bf = 1; 1493 else 1494 lrxen = 1; 1495 } 1496 1497 /* 1498 * Initialize base of dump-stats buffer. 1499 */ 1500 fxp_scb_wait(sc); 1501 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1502 sc->sc_cddma + FXP_CDSTATSOFF); 1503 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1504 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1505 1506 cbp = &sc->sc_control_data->fcd_configcb; 1507 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1508 1509 /* 1510 * This copy is kind of disgusting, but there are a bunch of must be 1511 * zero and must be one bits in this structure and this is the easiest 1512 * way to initialize them all to proper values. 1513 */ 1514 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1515 1516 /* BIG_ENDIAN: no need to swap to store 0 */ 1517 cbp->cb_status = 0; 1518 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1519 FXP_CB_COMMAND_EL); 1520 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1521 cbp->link_addr = 0xffffffff; /* (no) next command */ 1522 /* bytes in config block */ 1523 cbp->byte_count = FXP_CONFIG_LEN; 1524 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1525 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1526 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1527 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1528 cbp->type_enable = 0; /* actually reserved */ 1529 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1530 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1531 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1532 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1533 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1534 cbp->late_scb = 0; /* (don't) defer SCB update */ 1535 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1536 cbp->ci_int = 1; /* interrupt on CU idle */ 1537 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1538 cbp->ext_stats_dis = 1; /* disable extended counters */ 1539 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1540 cbp->save_bf = save_bf;/* save bad frames */ 1541 cbp->disc_short_rx = !prm; /* discard short packets */ 1542 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1543 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1544 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1545 /* interface mode */ 1546 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1547 cbp->csma_dis = 0; /* (don't) disable link */ 1548 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1549 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1550 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1551 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1552 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1553 cbp->nsai = 1; /* (don't) disable source addr insert */ 1554 cbp->preamble_length = 2; /* (7 byte) preamble */ 1555 cbp->loopback = 0; /* (don't) loopback */ 1556 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1557 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1558 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1559 cbp->promiscuous = prm; /* promiscuous mode */ 1560 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1561 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1562 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1563 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1564 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1565 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1566 cbp->padding = 1; /* (do) pad short tx packets */ 1567 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1568 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1569 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1570 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1571 /* must set wake_en in PMCSR also */ 1572 cbp->force_fdx = 0; /* (don't) force full duplex */ 1573 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1574 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1575 cbp->mc_all = allm; /* accept all multicasts */ 1576 1577 if (sc->sc_rev < FXP_REV_82558_A4) { 1578 /* 1579 * The i82557 has no hardware flow control, the values 1580 * here are the defaults for the chip. 1581 */ 1582 cbp->fc_delay_lsb = 0; 1583 cbp->fc_delay_msb = 0x40; 1584 cbp->pri_fc_thresh = 3; 1585 cbp->tx_fc_dis = 0; 1586 cbp->rx_fc_restop = 0; 1587 cbp->rx_fc_restart = 0; 1588 cbp->fc_filter = 0; 1589 cbp->pri_fc_loc = 1; 1590 } else { 1591 cbp->fc_delay_lsb = 0x1f; 1592 cbp->fc_delay_msb = 0x01; 1593 cbp->pri_fc_thresh = 3; 1594 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1595 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1596 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1597 cbp->fc_filter = !prm; /* drop FC frames to host */ 1598 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1599 } 1600 1601 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1602 1603 /* 1604 * Start the config command/DMA. 1605 */ 1606 fxp_scb_wait(sc); 1607 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1608 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1609 /* ...and wait for it to complete. */ 1610 i = 1000; 1611 do { 1612 FXP_CDCONFIGSYNC(sc, 1613 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1614 DELAY(1); 1615 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1616 if (i == 0) { 1617 printf("%s at line %d: dmasync timeout\n", 1618 sc->sc_dev.dv_xname, __LINE__); 1619 return ETIMEDOUT; 1620 } 1621 1622 /* 1623 * Initialize the station address. 1624 */ 1625 cb_ias = &sc->sc_control_data->fcd_iascb; 1626 /* BIG_ENDIAN: no need to swap to store 0 */ 1627 cb_ias->cb_status = 0; 1628 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1629 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1630 cb_ias->link_addr = 0xffffffff; 1631 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1632 1633 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1634 1635 /* 1636 * Start the IAS (Individual Address Setup) command/DMA. 1637 */ 1638 fxp_scb_wait(sc); 1639 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1640 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1641 /* ...and wait for it to complete. */ 1642 i = 1000; 1643 do { 1644 FXP_CDIASSYNC(sc, 1645 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1646 DELAY(1); 1647 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1648 if (i == 0) { 1649 printf("%s at line %d: dmasync timeout\n", 1650 sc->sc_dev.dv_xname, __LINE__); 1651 return ETIMEDOUT; 1652 } 1653 1654 /* 1655 * Initialize the transmit descriptor ring. txlast is initialized 1656 * to the end of the list so that it will wrap around to the first 1657 * descriptor when the first packet is transmitted. 1658 */ 1659 for (i = 0; i < FXP_NTXCB; i++) { 1660 txd = FXP_CDTX(sc, i); 1661 memset(txd, 0, sizeof(*txd)); 1662 txd->txd_txcb.cb_command = 1663 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1664 txd->txd_txcb.link_addr = 1665 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1666 if (sc->sc_flags & FXPF_EXT_TXCB) 1667 txd->txd_txcb.tbd_array_addr = 1668 htole32(FXP_CDTBDADDR(sc, i) + 1669 (2 * sizeof(struct fxp_tbd))); 1670 else 1671 txd->txd_txcb.tbd_array_addr = 1672 htole32(FXP_CDTBDADDR(sc, i)); 1673 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1674 } 1675 sc->sc_txpending = 0; 1676 sc->sc_txdirty = 0; 1677 sc->sc_txlast = FXP_NTXCB - 1; 1678 1679 /* 1680 * Initialize the receive buffer list. 1681 */ 1682 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1683 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1684 rxmap = FXP_RXMAP_GET(sc); 1685 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1686 printf("%s: unable to allocate or map rx " 1687 "buffer %d, error = %d\n", 1688 sc->sc_dev.dv_xname, 1689 sc->sc_rxq.ifq_len, error); 1690 /* 1691 * XXX Should attempt to run with fewer receive 1692 * XXX buffers instead of just failing. 1693 */ 1694 FXP_RXMAP_PUT(sc, rxmap); 1695 fxp_rxdrain(sc); 1696 goto out; 1697 } 1698 } 1699 sc->sc_rxidle = 0; 1700 1701 /* 1702 * Give the transmit ring to the chip. We do this by pointing 1703 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1704 * issuing a start command. It will execute the NOP and then 1705 * suspend, pointing at the first descriptor. 1706 */ 1707 fxp_scb_wait(sc); 1708 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1709 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1710 1711 /* 1712 * Initialize receiver buffer area - RFA. 1713 */ 1714 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1715 fxp_scb_wait(sc); 1716 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1717 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1718 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1719 1720 if (sc->sc_flags & FXPF_MII) { 1721 /* 1722 * Set current media. 1723 */ 1724 mii_mediachg(&sc->sc_mii); 1725 } 1726 1727 /* 1728 * ...all done! 1729 */ 1730 ifp->if_flags |= IFF_RUNNING; 1731 ifp->if_flags &= ~IFF_OACTIVE; 1732 1733 /* 1734 * Start the one second timer. 1735 */ 1736 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1737 1738 /* 1739 * Attempt to start output on the interface. 1740 */ 1741 fxp_start(ifp); 1742 1743 out: 1744 if (error) { 1745 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1746 ifp->if_timer = 0; 1747 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1748 } 1749 return (error); 1750 } 1751 1752 /* 1753 * Change media according to request. 1754 */ 1755 int 1756 fxp_mii_mediachange(struct ifnet *ifp) 1757 { 1758 struct fxp_softc *sc = ifp->if_softc; 1759 1760 if (ifp->if_flags & IFF_UP) 1761 mii_mediachg(&sc->sc_mii); 1762 return (0); 1763 } 1764 1765 /* 1766 * Notify the world which media we're using. 1767 */ 1768 void 1769 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1770 { 1771 struct fxp_softc *sc = ifp->if_softc; 1772 1773 if(sc->sc_enabled == 0) { 1774 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1775 ifmr->ifm_status = 0; 1776 return; 1777 } 1778 1779 mii_pollstat(&sc->sc_mii); 1780 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1781 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1782 } 1783 1784 int 1785 fxp_80c24_mediachange(struct ifnet *ifp) 1786 { 1787 1788 /* Nothing to do here. */ 1789 return (0); 1790 } 1791 1792 void 1793 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1794 { 1795 struct fxp_softc *sc = ifp->if_softc; 1796 1797 /* 1798 * Media is currently-selected media. We cannot determine 1799 * the link status. 1800 */ 1801 ifmr->ifm_status = 0; 1802 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1803 } 1804 1805 /* 1806 * Add a buffer to the end of the RFA buffer list. 1807 * Return 0 if successful, error code on failure. 1808 * 1809 * The RFA struct is stuck at the beginning of mbuf cluster and the 1810 * data pointer is fixed up to point just past it. 1811 */ 1812 int 1813 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1814 { 1815 struct mbuf *m; 1816 int error; 1817 1818 MGETHDR(m, M_DONTWAIT, MT_DATA); 1819 if (m == NULL) 1820 return (ENOBUFS); 1821 1822 MCLGET(m, M_DONTWAIT); 1823 if ((m->m_flags & M_EXT) == 0) { 1824 m_freem(m); 1825 return (ENOBUFS); 1826 } 1827 1828 if (unload) 1829 bus_dmamap_unload(sc->sc_dmat, rxmap); 1830 1831 M_SETCTX(m, rxmap); 1832 1833 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1834 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1835 BUS_DMA_READ|BUS_DMA_NOWAIT); 1836 if (error) { 1837 printf("%s: can't load rx DMA map %d, error = %d\n", 1838 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1839 panic("fxp_add_rfabuf"); /* XXX */ 1840 } 1841 1842 FXP_INIT_RFABUF(sc, m); 1843 1844 return (0); 1845 } 1846 1847 int 1848 fxp_mdi_read(struct device *self, int phy, int reg) 1849 { 1850 struct fxp_softc *sc = (struct fxp_softc *)self; 1851 int count = 10000; 1852 int value; 1853 1854 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1855 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1856 1857 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1858 && count--) 1859 DELAY(10); 1860 1861 if (count <= 0) 1862 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1863 1864 return (value & 0xffff); 1865 } 1866 1867 void 1868 fxp_statchg(struct device *self) 1869 { 1870 struct fxp_softc *sc = (void *) self; 1871 1872 /* 1873 * Determine whether or not we have to work-around the 1874 * Resume Bug. 1875 */ 1876 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 1877 if (IFM_TYPE(sc->sc_mii.mii_media_active) == IFM_10_T) 1878 sc->sc_flags |= FXPF_FIX_RESUME_BUG; 1879 else 1880 sc->sc_flags &= ~FXPF_FIX_RESUME_BUG; 1881 } 1882 } 1883 1884 void 1885 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1886 { 1887 struct fxp_softc *sc = (struct fxp_softc *)self; 1888 int count = 10000; 1889 1890 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1891 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1892 (value & 0xffff)); 1893 1894 while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1895 count--) 1896 DELAY(10); 1897 1898 if (count <= 0) 1899 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1900 } 1901 1902 int 1903 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1904 { 1905 struct fxp_softc *sc = ifp->if_softc; 1906 struct ifreq *ifr = (struct ifreq *)data; 1907 int s, error; 1908 1909 s = splnet(); 1910 1911 switch (cmd) { 1912 case SIOCSIFMEDIA: 1913 case SIOCGIFMEDIA: 1914 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1915 break; 1916 1917 default: 1918 error = ether_ioctl(ifp, cmd, data); 1919 if (error == ENETRESET) { 1920 if (sc->sc_enabled) { 1921 /* 1922 * Multicast list has changed; set the 1923 * hardware filter accordingly. 1924 */ 1925 if (sc->sc_txpending) { 1926 sc->sc_flags |= FXPF_WANTINIT; 1927 error = 0; 1928 } else 1929 error = fxp_init(ifp); 1930 } else 1931 error = 0; 1932 } 1933 break; 1934 } 1935 1936 /* Try to get more packets going. */ 1937 if (sc->sc_enabled) 1938 fxp_start(ifp); 1939 1940 splx(s); 1941 return (error); 1942 } 1943 1944 /* 1945 * Program the multicast filter. 1946 * 1947 * This function must be called at splnet(). 1948 */ 1949 void 1950 fxp_mc_setup(struct fxp_softc *sc) 1951 { 1952 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1953 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1954 struct ethercom *ec = &sc->sc_ethercom; 1955 struct ether_multi *enm; 1956 struct ether_multistep step; 1957 int count, nmcasts; 1958 1959 #ifdef DIAGNOSTIC 1960 if (sc->sc_txpending) 1961 panic("fxp_mc_setup: pending transmissions"); 1962 #endif 1963 1964 ifp->if_flags &= ~IFF_ALLMULTI; 1965 1966 /* 1967 * Initialize multicast setup descriptor. 1968 */ 1969 nmcasts = 0; 1970 ETHER_FIRST_MULTI(step, ec, enm); 1971 while (enm != NULL) { 1972 /* 1973 * Check for too many multicast addresses or if we're 1974 * listening to a range. Either way, we simply have 1975 * to accept all multicasts. 1976 */ 1977 if (nmcasts >= MAXMCADDR || 1978 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1979 ETHER_ADDR_LEN) != 0) { 1980 /* 1981 * Callers of this function must do the 1982 * right thing with this. If we're called 1983 * from outside fxp_init(), the caller must 1984 * detect if the state if IFF_ALLMULTI changes. 1985 * If it does, the caller must then call 1986 * fxp_init(), since allmulti is handled by 1987 * the config block. 1988 */ 1989 ifp->if_flags |= IFF_ALLMULTI; 1990 return; 1991 } 1992 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1993 ETHER_ADDR_LEN); 1994 nmcasts++; 1995 ETHER_NEXT_MULTI(step, enm); 1996 } 1997 1998 /* BIG_ENDIAN: no need to swap to store 0 */ 1999 mcsp->cb_status = 0; 2000 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2001 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2002 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2003 2004 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2005 2006 /* 2007 * Wait until the command unit is not active. This should never 2008 * happen since nothing is queued, but make sure anyway. 2009 */ 2010 count = 100; 2011 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2012 FXP_SCB_CUS_ACTIVE && --count) 2013 DELAY(1); 2014 if (count == 0) { 2015 printf("%s at line %d: command queue timeout\n", 2016 sc->sc_dev.dv_xname, __LINE__); 2017 return; 2018 } 2019 2020 /* 2021 * Start the multicast setup command/DMA. 2022 */ 2023 fxp_scb_wait(sc); 2024 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2025 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2026 2027 /* ...and wait for it to complete. */ 2028 count = 1000; 2029 do { 2030 FXP_CDMCSSYNC(sc, 2031 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2032 DELAY(1); 2033 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2034 if (count == 0) { 2035 printf("%s at line %d: dmasync timeout\n", 2036 sc->sc_dev.dv_xname, __LINE__); 2037 return; 2038 } 2039 } 2040 2041 int 2042 fxp_enable(struct fxp_softc *sc) 2043 { 2044 2045 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2046 if ((*sc->sc_enable)(sc) != 0) { 2047 printf("%s: device enable failed\n", 2048 sc->sc_dev.dv_xname); 2049 return (EIO); 2050 } 2051 } 2052 2053 sc->sc_enabled = 1; 2054 return (0); 2055 } 2056 2057 void 2058 fxp_disable(struct fxp_softc *sc) 2059 { 2060 2061 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2062 (*sc->sc_disable)(sc); 2063 sc->sc_enabled = 0; 2064 } 2065 } 2066 2067 /* 2068 * fxp_activate: 2069 * 2070 * Handle device activation/deactivation requests. 2071 */ 2072 int 2073 fxp_activate(struct device *self, enum devact act) 2074 { 2075 struct fxp_softc *sc = (void *) self; 2076 int s, error = 0; 2077 2078 s = splnet(); 2079 switch (act) { 2080 case DVACT_ACTIVATE: 2081 error = EOPNOTSUPP; 2082 break; 2083 2084 case DVACT_DEACTIVATE: 2085 if (sc->sc_flags & FXPF_MII) 2086 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2087 MII_OFFSET_ANY); 2088 if_deactivate(&sc->sc_ethercom.ec_if); 2089 break; 2090 } 2091 splx(s); 2092 2093 return (error); 2094 } 2095 2096 /* 2097 * fxp_detach: 2098 * 2099 * Detach an i82557 interface. 2100 */ 2101 int 2102 fxp_detach(struct fxp_softc *sc) 2103 { 2104 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2105 int i; 2106 2107 /* Succeed now if there's no work to do. */ 2108 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2109 return (0); 2110 2111 /* Unhook our tick handler. */ 2112 callout_stop(&sc->sc_callout); 2113 2114 if (sc->sc_flags & FXPF_MII) { 2115 /* Detach all PHYs */ 2116 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2117 } 2118 2119 /* Delete all remaining media. */ 2120 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2121 2122 #if NRND > 0 2123 rnd_detach_source(&sc->rnd_source); 2124 #endif 2125 ether_ifdetach(ifp); 2126 if_detach(ifp); 2127 2128 for (i = 0; i < FXP_NRFABUFS; i++) { 2129 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2130 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2131 } 2132 2133 for (i = 0; i < FXP_NTXCB; i++) { 2134 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2135 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2136 } 2137 2138 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2139 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2140 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2141 sizeof(struct fxp_control_data)); 2142 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2143 2144 shutdownhook_disestablish(sc->sc_sdhook); 2145 powerhook_disestablish(sc->sc_powerhook); 2146 2147 return (0); 2148 } 2149
Indexes created Tue Sep 30 11:09:46 GMT 2025