i82557.c revision 1.70
1 /* $NetBSD: i82557.c,v 1.70 2003/01/06 13:10:28 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.70 2003/01/06 13:10:28 wiz Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 void fxp_rxdrain(struct fxp_softc *); 194 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 195 int fxp_mdi_read(struct device *, int, int); 196 void fxp_statchg(struct device *); 197 void fxp_mdi_write(struct device *, int, int, int); 198 void fxp_autosize_eeprom(struct fxp_softc*); 199 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 200 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 201 void fxp_eeprom_update_cksum(struct fxp_softc *); 202 void fxp_get_info(struct fxp_softc *, u_int8_t *); 203 void fxp_tick(void *); 204 void fxp_mc_setup(struct fxp_softc *); 205 void fxp_load_ucode(struct fxp_softc *); 206 207 void fxp_shutdown(void *); 208 void fxp_power(int, void *); 209 210 int fxp_copy_small = 0; 211 212 /* 213 * Variables for interrupt mitigating microcode. 214 */ 215 int fxp_int_delay = 1000; /* usec */ 216 int fxp_bundle_max = 6; /* packets */ 217 218 struct fxp_phytype { 219 int fp_phy; /* type of PHY, -1 for MII at the end. */ 220 void (*fp_init)(struct fxp_softc *); 221 } fxp_phytype_table[] = { 222 { FXP_PHY_80C24, fxp_80c24_initmedia }, 223 { -1, fxp_mii_initmedia }, 224 }; 225 226 /* 227 * Set initial transmit threshold at 64 (512 bytes). This is 228 * increased by 64 (512 bytes) at a time, to maximum of 192 229 * (1536 bytes), if an underrun occurs. 230 */ 231 static int tx_threshold = 64; 232 233 /* 234 * Wait for the previous command to be accepted (but not necessarily 235 * completed). 236 */ 237 static __inline void 238 fxp_scb_wait(struct fxp_softc *sc) 239 { 240 int i = 10000; 241 242 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 243 delay(2); 244 if (i == 0) 245 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 246 } 247 248 /* 249 * Submit a command to the i82557. 250 */ 251 static __inline void 252 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253 { 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256 } 257 258 /* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261 void 262 fxp_attach(struct fxp_softc *sc) 263 { 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout); 271 272 /* Start out using the standard RFA. */ 273 sc->sc_rfa_size = RFA_SIZE; 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Allocate the control data structures, and create and load the 285 * DMA map for it. 286 */ 287 if ((error = bus_dmamem_alloc(sc->sc_dmat, 288 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 289 0)) != 0) { 290 printf("%s: unable to allocate control data, error = %d\n", 291 sc->sc_dev.dv_xname, error); 292 goto fail_0; 293 } 294 295 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 296 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 297 BUS_DMA_COHERENT)) != 0) { 298 printf("%s: unable to map control data, error = %d\n", 299 sc->sc_dev.dv_xname, error); 300 goto fail_1; 301 } 302 sc->sc_cdseg = seg; 303 sc->sc_cdnseg = rseg; 304 305 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 306 307 if ((error = bus_dmamap_create(sc->sc_dmat, 308 sizeof(struct fxp_control_data), 1, 309 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 310 printf("%s: unable to create control data DMA map, " 311 "error = %d\n", sc->sc_dev.dv_xname, error); 312 goto fail_2; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 316 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 317 0)) != 0) { 318 printf("%s: can't load control data DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail_3; 321 } 322 323 /* 324 * Create the transmit buffer DMA maps. 325 */ 326 for (i = 0; i < FXP_NTXCB; i++) { 327 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 328 FXP_NTXSEG, MCLBYTES, 0, 0, 329 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 330 printf("%s: unable to create tx DMA map %d, " 331 "error = %d\n", sc->sc_dev.dv_xname, i, error); 332 goto fail_4; 333 } 334 } 335 336 /* 337 * Create the receive buffer DMA maps. 338 */ 339 for (i = 0; i < FXP_NRFABUFS; i++) { 340 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 341 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 342 printf("%s: unable to create rx DMA map %d, " 343 "error = %d\n", sc->sc_dev.dv_xname, i, error); 344 goto fail_5; 345 } 346 } 347 348 /* Initialize MAC address and media structures. */ 349 fxp_get_info(sc, enaddr); 350 351 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 352 ether_sprintf(enaddr)); 353 354 ifp = &sc->sc_ethercom.ec_if; 355 356 /* 357 * Get info about our media interface, and initialize it. Note 358 * the table terminates itself with a phy of -1, indicating 359 * that we're using MII. 360 */ 361 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 362 if (fp->fp_phy == sc->phy_primary_device) 363 break; 364 (*fp->fp_init)(sc); 365 366 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = fxp_ioctl; 370 ifp->if_start = fxp_start; 371 ifp->if_watchdog = fxp_watchdog; 372 ifp->if_init = fxp_init; 373 ifp->if_stop = fxp_stop; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 /* 377 * We can support 802.1Q VLAN-sized frames. 378 */ 379 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 380 381 /* 382 * Attach the interface. 383 */ 384 if_attach(ifp); 385 ether_ifattach(ifp, enaddr); 386 #if NRND > 0 387 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 388 RND_TYPE_NET, 0); 389 #endif 390 391 #ifdef FXP_EVENT_COUNTERS 392 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 393 NULL, sc->sc_dev.dv_xname, "txstall"); 394 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 395 NULL, sc->sc_dev.dv_xname, "txintr"); 396 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 397 NULL, sc->sc_dev.dv_xname, "rxintr"); 398 #endif /* FXP_EVENT_COUNTERS */ 399 400 /* 401 * Add shutdown hook so that DMA is disabled prior to reboot. Not 402 * doing do could allow DMA to corrupt kernel memory during the 403 * reboot before the driver initializes. 404 */ 405 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 406 if (sc->sc_sdhook == NULL) 407 printf("%s: WARNING: unable to establish shutdown hook\n", 408 sc->sc_dev.dv_xname); 409 /* 410 * Add suspend hook, for similar reasons.. 411 */ 412 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 413 if (sc->sc_powerhook == NULL) 414 printf("%s: WARNING: unable to establish power hook\n", 415 sc->sc_dev.dv_xname); 416 417 /* The attach is successful. */ 418 sc->sc_flags |= FXPF_ATTACHED; 419 420 return; 421 422 /* 423 * Free any resources we've allocated during the failed attach 424 * attempt. Do this in reverse order and fall though. 425 */ 426 fail_5: 427 for (i = 0; i < FXP_NRFABUFS; i++) { 428 if (sc->sc_rxmaps[i] != NULL) 429 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 430 } 431 fail_4: 432 for (i = 0; i < FXP_NTXCB; i++) { 433 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 434 bus_dmamap_destroy(sc->sc_dmat, 435 FXP_DSTX(sc, i)->txs_dmamap); 436 } 437 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 438 fail_3: 439 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 440 fail_2: 441 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 442 sizeof(struct fxp_control_data)); 443 fail_1: 444 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 445 fail_0: 446 return; 447 } 448 449 void 450 fxp_mii_initmedia(struct fxp_softc *sc) 451 { 452 int flags; 453 454 sc->sc_flags |= FXPF_MII; 455 456 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 457 sc->sc_mii.mii_readreg = fxp_mdi_read; 458 sc->sc_mii.mii_writereg = fxp_mdi_write; 459 sc->sc_mii.mii_statchg = fxp_statchg; 460 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 461 fxp_mii_mediastatus); 462 463 flags = MIIF_NOISOLATE; 464 if (sc->sc_rev >= FXP_REV_82558_A4) 465 flags |= MIIF_DOPAUSE; 466 /* 467 * The i82557 wedges if all of its PHYs are isolated! 468 */ 469 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 470 MII_OFFSET_ANY, flags); 471 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 472 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 473 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 474 } else 475 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 476 } 477 478 void 479 fxp_80c24_initmedia(struct fxp_softc *sc) 480 { 481 482 /* 483 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 484 * doesn't have a programming interface of any sort. The 485 * media is sensed automatically based on how the link partner 486 * is configured. This is, in essence, manual configuration. 487 */ 488 printf("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 489 sc->sc_dev.dv_xname); 490 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 491 fxp_80c24_mediastatus); 492 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 493 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 494 } 495 496 /* 497 * Device shutdown routine. Called at system shutdown after sync. The 498 * main purpose of this routine is to shut off receiver DMA so that 499 * kernel memory doesn't get clobbered during warmboot. 500 */ 501 void 502 fxp_shutdown(void *arg) 503 { 504 struct fxp_softc *sc = arg; 505 506 /* 507 * Since the system's going to halt shortly, don't bother 508 * freeing mbufs. 509 */ 510 fxp_stop(&sc->sc_ethercom.ec_if, 0); 511 } 512 /* 513 * Power handler routine. Called when the system is transitioning 514 * into/out of power save modes. As with fxp_shutdown, the main 515 * purpose of this routine is to shut off receiver DMA so it doesn't 516 * clobber kernel memory at the wrong time. 517 */ 518 void 519 fxp_power(int why, void *arg) 520 { 521 struct fxp_softc *sc = arg; 522 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 523 int s; 524 525 s = splnet(); 526 switch (why) { 527 case PWR_SUSPEND: 528 case PWR_STANDBY: 529 fxp_stop(ifp, 0); 530 break; 531 case PWR_RESUME: 532 if (ifp->if_flags & IFF_UP) 533 fxp_init(ifp); 534 break; 535 case PWR_SOFTSUSPEND: 536 case PWR_SOFTSTANDBY: 537 case PWR_SOFTRESUME: 538 break; 539 } 540 splx(s); 541 } 542 543 /* 544 * Initialize the interface media. 545 */ 546 void 547 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 548 { 549 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 550 551 /* 552 * Reset to a stable state. 553 */ 554 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 555 DELAY(10); 556 557 sc->sc_eeprom_size = 0; 558 fxp_autosize_eeprom(sc); 559 if (sc->sc_eeprom_size == 0) { 560 printf("%s: failed to detect EEPROM size\n", 561 sc->sc_dev.dv_xname); 562 sc->sc_eeprom_size = 6; /* XXX panic here? */ 563 } 564 #ifdef DEBUG 565 printf("%s: detected %d word EEPROM\n", 566 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 567 #endif 568 569 /* 570 * Get info about the primary PHY 571 */ 572 fxp_read_eeprom(sc, &data, 6, 1); 573 sc->phy_primary_device = 574 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 575 576 /* 577 * Read MAC address. 578 */ 579 fxp_read_eeprom(sc, myea, 0, 3); 580 enaddr[0] = myea[0] & 0xff; 581 enaddr[1] = myea[0] >> 8; 582 enaddr[2] = myea[1] & 0xff; 583 enaddr[3] = myea[1] >> 8; 584 enaddr[4] = myea[2] & 0xff; 585 enaddr[5] = myea[2] >> 8; 586 587 /* 588 * Systems based on the ICH2/ICH2-M chip from Intel, as well 589 * as some i82559 designs, have a defect where the chip can 590 * cause a PCI protocol violation if it receives a CU_RESUME 591 * command when it is entering the IDLE state. 592 * 593 * The work-around is to disable Dynamic Standby Mode, so that 594 * the chip never deasserts #CLKRUN, and always remains in the 595 * active state. 596 * 597 * Unfortunately, the only way to disable Dynamic Standby is 598 * to frob an EEPROM setting and reboot (the EEPROM setting 599 * is only consulted when the PCI bus comes out of reset). 600 * 601 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 602 */ 603 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 604 fxp_read_eeprom(sc, &data, 10, 1); 605 if (data & 0x02) { /* STB enable */ 606 printf("%s: WARNING: " 607 "Disabling dynamic standby mode in EEPROM " 608 "to work around a\n", 609 sc->sc_dev.dv_xname); 610 printf("%s: WARNING: hardware bug. You must reset " 611 "the system before using this\n", 612 sc->sc_dev.dv_xname); 613 printf("%s: WARNING: interface.\n", 614 sc->sc_dev.dv_xname); 615 data &= ~0x02; 616 fxp_write_eeprom(sc, &data, 10, 1); 617 printf("%s: new EEPROM ID: 0x%04x\n", 618 sc->sc_dev.dv_xname, data); 619 fxp_eeprom_update_cksum(sc); 620 } 621 } 622 } 623 624 static void 625 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 626 { 627 uint16_t reg; 628 int x; 629 630 for (x = 1 << (len - 1); x != 0; x >>= 1) { 631 if (data & x) 632 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 633 else 634 reg = FXP_EEPROM_EECS; 635 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 636 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 637 reg | FXP_EEPROM_EESK); 638 DELAY(4); 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 640 DELAY(4); 641 } 642 } 643 644 /* 645 * Figure out EEPROM size. 646 * 647 * 559's can have either 64-word or 256-word EEPROMs, the 558 648 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 649 * talks about the existance of 16 to 256 word EEPROMs. 650 * 651 * The only known sizes are 64 and 256, where the 256 version is used 652 * by CardBus cards to store CIS information. 653 * 654 * The address is shifted in msb-to-lsb, and after the last 655 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 656 * after which follows the actual data. We try to detect this zero, by 657 * probing the data-out bit in the EEPROM control register just after 658 * having shifted in a bit. If the bit is zero, we assume we've 659 * shifted enough address bits. The data-out should be tri-state, 660 * before this, which should translate to a logical one. 661 * 662 * Other ways to do this would be to try to read a register with known 663 * contents with a varying number of address bits, but no such 664 * register seem to be available. The high bits of register 10 are 01 665 * on the 558 and 559, but apparently not on the 557. 666 * 667 * The Linux driver computes a checksum on the EEPROM data, but the 668 * value of this checksum is not very well documented. 669 */ 670 671 void 672 fxp_autosize_eeprom(struct fxp_softc *sc) 673 { 674 int x; 675 676 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 677 678 /* Shift in read opcode. */ 679 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 680 681 /* 682 * Shift in address, wait for the dummy zero following a correct 683 * address shift. 684 */ 685 for (x = 1; x <= 8; x++) { 686 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 687 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 688 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 689 DELAY(4); 690 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 691 FXP_EEPROM_EEDO) == 0) 692 break; 693 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 694 DELAY(4); 695 } 696 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 697 DELAY(4); 698 if (x != 6 && x != 8) { 699 #ifdef DEBUG 700 printf("%s: strange EEPROM size (%d)\n", 701 sc->sc_dev.dv_xname, 1 << x); 702 #endif 703 } else 704 sc->sc_eeprom_size = x; 705 } 706 707 /* 708 * Read from the serial EEPROM. Basically, you manually shift in 709 * the read opcode (one bit at a time) and then shift in the address, 710 * and then you shift out the data (all of this one bit at a time). 711 * The word size is 16 bits, so you have to provide the address for 712 * every 16 bits of data. 713 */ 714 void 715 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 716 { 717 u_int16_t reg; 718 int i, x; 719 720 for (i = 0; i < words; i++) { 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 722 723 /* Shift in read opcode. */ 724 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 725 726 /* Shift in address. */ 727 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 728 729 reg = FXP_EEPROM_EECS; 730 data[i] = 0; 731 732 /* Shift out data. */ 733 for (x = 16; x > 0; x--) { 734 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 735 reg | FXP_EEPROM_EESK); 736 DELAY(4); 737 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 738 FXP_EEPROM_EEDO) 739 data[i] |= (1 << (x - 1)); 740 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 741 DELAY(4); 742 } 743 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 744 DELAY(4); 745 } 746 } 747 748 /* 749 * Write data to the serial EEPROM. 750 */ 751 void 752 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 753 { 754 int i, j; 755 756 for (i = 0; i < words; i++) { 757 /* Erase/write enable. */ 758 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 759 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 760 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 761 sc->sc_eeprom_size); 762 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 763 DELAY(4); 764 765 /* Shift in write opcode, address, data. */ 766 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 767 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 768 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 769 fxp_eeprom_shiftin(sc, data[i], 16); 770 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 771 DELAY(4); 772 773 /* Wait for the EEPROM to finish up. */ 774 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 775 DELAY(4); 776 for (j = 0; j < 1000; j++) { 777 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 778 FXP_EEPROM_EEDO) 779 break; 780 DELAY(50); 781 } 782 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 783 DELAY(4); 784 785 /* Erase/write disable. */ 786 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 787 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 788 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 789 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 790 DELAY(4); 791 } 792 } 793 794 /* 795 * Update the checksum of the EEPROM. 796 */ 797 void 798 fxp_eeprom_update_cksum(struct fxp_softc *sc) 799 { 800 int i; 801 uint16_t data, cksum; 802 803 cksum = 0; 804 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 805 fxp_read_eeprom(sc, &data, i, 1); 806 cksum += data; 807 } 808 i = (1 << sc->sc_eeprom_size) - 1; 809 cksum = 0xbaba - cksum; 810 fxp_read_eeprom(sc, &data, i, 1); 811 fxp_write_eeprom(sc, &cksum, i, 1); 812 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 813 sc->sc_dev.dv_xname, i, data, cksum); 814 } 815 816 /* 817 * Start packet transmission on the interface. 818 */ 819 void 820 fxp_start(struct ifnet *ifp) 821 { 822 struct fxp_softc *sc = ifp->if_softc; 823 struct mbuf *m0, *m; 824 struct fxp_txdesc *txd; 825 struct fxp_txsoft *txs; 826 bus_dmamap_t dmamap; 827 int error, lasttx, nexttx, opending, seg; 828 829 /* 830 * If we want a re-init, bail out now. 831 */ 832 if (sc->sc_flags & FXPF_WANTINIT) { 833 ifp->if_flags |= IFF_OACTIVE; 834 return; 835 } 836 837 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 838 return; 839 840 /* 841 * Remember the previous txpending and the current lasttx. 842 */ 843 opending = sc->sc_txpending; 844 lasttx = sc->sc_txlast; 845 846 /* 847 * Loop through the send queue, setting up transmit descriptors 848 * until we drain the queue, or use up all available transmit 849 * descriptors. 850 */ 851 for (;;) { 852 /* 853 * Grab a packet off the queue. 854 */ 855 IFQ_POLL(&ifp->if_snd, m0); 856 if (m0 == NULL) 857 break; 858 m = NULL; 859 860 if (sc->sc_txpending == FXP_NTXCB) { 861 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 862 break; 863 } 864 865 /* 866 * Get the next available transmit descriptor. 867 */ 868 nexttx = FXP_NEXTTX(sc->sc_txlast); 869 txd = FXP_CDTX(sc, nexttx); 870 txs = FXP_DSTX(sc, nexttx); 871 dmamap = txs->txs_dmamap; 872 873 /* 874 * Load the DMA map. If this fails, the packet either 875 * didn't fit in the allotted number of frags, or we were 876 * short on resources. In this case, we'll copy and try 877 * again. 878 */ 879 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 880 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 881 MGETHDR(m, M_DONTWAIT, MT_DATA); 882 if (m == NULL) { 883 printf("%s: unable to allocate Tx mbuf\n", 884 sc->sc_dev.dv_xname); 885 break; 886 } 887 if (m0->m_pkthdr.len > MHLEN) { 888 MCLGET(m, M_DONTWAIT); 889 if ((m->m_flags & M_EXT) == 0) { 890 printf("%s: unable to allocate Tx " 891 "cluster\n", sc->sc_dev.dv_xname); 892 m_freem(m); 893 break; 894 } 895 } 896 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 897 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 898 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 899 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 900 if (error) { 901 printf("%s: unable to load Tx buffer, " 902 "error = %d\n", sc->sc_dev.dv_xname, error); 903 break; 904 } 905 } 906 907 IFQ_DEQUEUE(&ifp->if_snd, m0); 908 if (m != NULL) { 909 m_freem(m0); 910 m0 = m; 911 } 912 913 /* Initialize the fraglist. */ 914 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 915 txd->txd_tbd[seg].tb_addr = 916 htole32(dmamap->dm_segs[seg].ds_addr); 917 txd->txd_tbd[seg].tb_size = 918 htole32(dmamap->dm_segs[seg].ds_len); 919 } 920 921 /* Sync the DMA map. */ 922 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 923 BUS_DMASYNC_PREWRITE); 924 925 /* 926 * Store a pointer to the packet so we can free it later. 927 */ 928 txs->txs_mbuf = m0; 929 930 /* 931 * Initialize the transmit descriptor. 932 */ 933 /* BIG_ENDIAN: no need to swap to store 0 */ 934 txd->txd_txcb.cb_status = 0; 935 txd->txd_txcb.cb_command = 936 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 937 txd->txd_txcb.tx_threshold = tx_threshold; 938 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 939 940 FXP_CDTXSYNC(sc, nexttx, 941 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 942 943 /* Advance the tx pointer. */ 944 sc->sc_txpending++; 945 sc->sc_txlast = nexttx; 946 947 #if NBPFILTER > 0 948 /* 949 * Pass packet to bpf if there is a listener. 950 */ 951 if (ifp->if_bpf) 952 bpf_mtap(ifp->if_bpf, m0); 953 #endif 954 } 955 956 if (sc->sc_txpending == FXP_NTXCB) { 957 /* No more slots; notify upper layer. */ 958 ifp->if_flags |= IFF_OACTIVE; 959 } 960 961 if (sc->sc_txpending != opending) { 962 /* 963 * We enqueued packets. If the transmitter was idle, 964 * reset the txdirty pointer. 965 */ 966 if (opending == 0) 967 sc->sc_txdirty = FXP_NEXTTX(lasttx); 968 969 /* 970 * Cause the chip to interrupt and suspend command 971 * processing once the last packet we've enqueued 972 * has been transmitted. 973 */ 974 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 975 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 976 FXP_CDTXSYNC(sc, sc->sc_txlast, 977 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 978 979 /* 980 * The entire packet chain is set up. Clear the suspend bit 981 * on the command prior to the first packet we set up. 982 */ 983 FXP_CDTXSYNC(sc, lasttx, 984 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 985 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 986 htole16(~FXP_CB_COMMAND_S); 987 FXP_CDTXSYNC(sc, lasttx, 988 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 989 990 /* 991 * Issue a Resume command in case the chip was suspended. 992 */ 993 fxp_scb_wait(sc); 994 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 995 996 /* Set a watchdog timer in case the chip flakes out. */ 997 ifp->if_timer = 5; 998 } 999 } 1000 1001 /* 1002 * Process interface interrupts. 1003 */ 1004 int 1005 fxp_intr(void *arg) 1006 { 1007 struct fxp_softc *sc = arg; 1008 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1009 bus_dmamap_t rxmap; 1010 int claimed = 0; 1011 u_int8_t statack; 1012 1013 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1014 return (0); 1015 /* 1016 * If the interface isn't running, don't try to 1017 * service the interrupt.. just ack it and bail. 1018 */ 1019 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1020 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1021 if (statack) { 1022 claimed = 1; 1023 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1024 } 1025 return (claimed); 1026 } 1027 1028 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1029 claimed = 1; 1030 1031 /* 1032 * First ACK all the interrupts in this pass. 1033 */ 1034 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1035 1036 /* 1037 * Process receiver interrupts. If a no-resource (RNR) 1038 * condition exists, get whatever packets we can and 1039 * re-start the receiver. 1040 */ 1041 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1042 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1043 fxp_rxintr(sc); 1044 } 1045 1046 if (statack & FXP_SCB_STATACK_RNR) { 1047 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1048 fxp_scb_wait(sc); 1049 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1050 rxmap->dm_segs[0].ds_addr + 1051 RFA_ALIGNMENT_FUDGE); 1052 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1053 } 1054 1055 /* 1056 * Free any finished transmit mbuf chains. 1057 */ 1058 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1059 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1060 fxp_txintr(sc); 1061 1062 /* 1063 * Try to get more packets going. 1064 */ 1065 fxp_start(ifp); 1066 1067 if (sc->sc_txpending == 0) { 1068 /* 1069 * If we want a re-init, do that now. 1070 */ 1071 if (sc->sc_flags & FXPF_WANTINIT) 1072 (void) fxp_init(ifp); 1073 } 1074 } 1075 } 1076 1077 #if NRND > 0 1078 if (claimed) 1079 rnd_add_uint32(&sc->rnd_source, statack); 1080 #endif 1081 return (claimed); 1082 } 1083 1084 /* 1085 * Handle transmit completion interrupts. 1086 */ 1087 void 1088 fxp_txintr(struct fxp_softc *sc) 1089 { 1090 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1091 struct fxp_txdesc *txd; 1092 struct fxp_txsoft *txs; 1093 int i; 1094 u_int16_t txstat; 1095 1096 ifp->if_flags &= ~IFF_OACTIVE; 1097 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1098 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1099 txd = FXP_CDTX(sc, i); 1100 txs = FXP_DSTX(sc, i); 1101 1102 FXP_CDTXSYNC(sc, i, 1103 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1104 1105 txstat = le16toh(txd->txd_txcb.cb_status); 1106 1107 if ((txstat & FXP_CB_STATUS_C) == 0) 1108 break; 1109 1110 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1111 0, txs->txs_dmamap->dm_mapsize, 1112 BUS_DMASYNC_POSTWRITE); 1113 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1114 m_freem(txs->txs_mbuf); 1115 txs->txs_mbuf = NULL; 1116 } 1117 1118 /* Update the dirty transmit buffer pointer. */ 1119 sc->sc_txdirty = i; 1120 1121 /* 1122 * Cancel the watchdog timer if there are no pending 1123 * transmissions. 1124 */ 1125 if (sc->sc_txpending == 0) 1126 ifp->if_timer = 0; 1127 } 1128 1129 /* 1130 * Handle receive interrupts. 1131 */ 1132 void 1133 fxp_rxintr(struct fxp_softc *sc) 1134 { 1135 struct ethercom *ec = &sc->sc_ethercom; 1136 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1137 struct mbuf *m, *m0; 1138 bus_dmamap_t rxmap; 1139 struct fxp_rfa *rfa; 1140 u_int16_t len, rxstat; 1141 1142 for (;;) { 1143 m = sc->sc_rxq.ifq_head; 1144 rfa = FXP_MTORFA(m); 1145 rxmap = M_GETCTX(m, bus_dmamap_t); 1146 1147 FXP_RFASYNC(sc, m, 1148 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1149 1150 rxstat = le16toh(rfa->rfa_status); 1151 1152 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1153 /* 1154 * We have processed all of the 1155 * receive buffers. 1156 */ 1157 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1158 return; 1159 } 1160 1161 IF_DEQUEUE(&sc->sc_rxq, m); 1162 1163 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1164 1165 len = le16toh(rfa->actual_size) & 1166 (m->m_ext.ext_size - 1); 1167 1168 if (len < sizeof(struct ether_header)) { 1169 /* 1170 * Runt packet; drop it now. 1171 */ 1172 FXP_INIT_RFABUF(sc, m); 1173 continue; 1174 } 1175 1176 /* 1177 * If support for 802.1Q VLAN sized frames is 1178 * enabled, we need to do some additional error 1179 * checking (as we are saving bad frames, in 1180 * order to receive the larger ones). 1181 */ 1182 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1183 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1184 FXP_RFA_STATUS_RNR| 1185 FXP_RFA_STATUS_ALIGN| 1186 FXP_RFA_STATUS_CRC)) != 0) { 1187 FXP_INIT_RFABUF(sc, m); 1188 continue; 1189 } 1190 1191 /* 1192 * If the packet is small enough to fit in a 1193 * single header mbuf, allocate one and copy 1194 * the data into it. This greatly reduces 1195 * memory consumption when we receive lots 1196 * of small packets. 1197 * 1198 * Otherwise, we add a new buffer to the receive 1199 * chain. If this fails, we drop the packet and 1200 * recycle the old buffer. 1201 */ 1202 if (fxp_copy_small != 0 && len <= MHLEN) { 1203 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1204 if (m == NULL) 1205 goto dropit; 1206 memcpy(mtod(m0, caddr_t), 1207 mtod(m, caddr_t), len); 1208 FXP_INIT_RFABUF(sc, m); 1209 m = m0; 1210 } else { 1211 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1212 dropit: 1213 ifp->if_ierrors++; 1214 FXP_INIT_RFABUF(sc, m); 1215 continue; 1216 } 1217 } 1218 1219 m->m_pkthdr.rcvif = ifp; 1220 m->m_pkthdr.len = m->m_len = len; 1221 1222 #if NBPFILTER > 0 1223 /* 1224 * Pass this up to any BPF listeners, but only 1225 * pass it up the stack it its for us. 1226 */ 1227 if (ifp->if_bpf) 1228 bpf_mtap(ifp->if_bpf, m); 1229 #endif 1230 1231 /* Pass it on. */ 1232 (*ifp->if_input)(ifp, m); 1233 } 1234 } 1235 1236 /* 1237 * Update packet in/out/collision statistics. The i82557 doesn't 1238 * allow you to access these counters without doing a fairly 1239 * expensive DMA to get _all_ of the statistics it maintains, so 1240 * we do this operation here only once per second. The statistics 1241 * counters in the kernel are updated from the previous dump-stats 1242 * DMA and then a new dump-stats DMA is started. The on-chip 1243 * counters are zeroed when the DMA completes. If we can't start 1244 * the DMA immediately, we don't wait - we just prepare to read 1245 * them again next time. 1246 */ 1247 void 1248 fxp_tick(void *arg) 1249 { 1250 struct fxp_softc *sc = arg; 1251 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1252 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1253 int s; 1254 1255 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1256 return; 1257 1258 s = splnet(); 1259 1260 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1261 1262 ifp->if_opackets += le32toh(sp->tx_good); 1263 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1264 if (sp->rx_good) { 1265 ifp->if_ipackets += le32toh(sp->rx_good); 1266 sc->sc_rxidle = 0; 1267 } else { 1268 sc->sc_rxidle++; 1269 } 1270 ifp->if_ierrors += 1271 le32toh(sp->rx_crc_errors) + 1272 le32toh(sp->rx_alignment_errors) + 1273 le32toh(sp->rx_rnr_errors) + 1274 le32toh(sp->rx_overrun_errors); 1275 /* 1276 * If any transmit underruns occurred, bump up the transmit 1277 * threshold by another 512 bytes (64 * 8). 1278 */ 1279 if (sp->tx_underruns) { 1280 ifp->if_oerrors += le32toh(sp->tx_underruns); 1281 if (tx_threshold < 192) 1282 tx_threshold += 64; 1283 } 1284 1285 /* 1286 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1287 * then assume the receiver has locked up and attempt to clear 1288 * the condition by reprogramming the multicast filter (actually, 1289 * resetting the interface). This is a work-around for a bug in 1290 * the 82557 where the receiver locks up if it gets certain types 1291 * of garbage in the synchronization bits prior to the packet header. 1292 * This bug is supposed to only occur in 10Mbps mode, but has been 1293 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1294 * speed transition). 1295 */ 1296 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1297 (void) fxp_init(ifp); 1298 splx(s); 1299 return; 1300 } 1301 /* 1302 * If there is no pending command, start another stats 1303 * dump. Otherwise punt for now. 1304 */ 1305 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1306 /* 1307 * Start another stats dump. 1308 */ 1309 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1310 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1311 } else { 1312 /* 1313 * A previous command is still waiting to be accepted. 1314 * Just zero our copy of the stats and wait for the 1315 * next timer event to update them. 1316 */ 1317 /* BIG_ENDIAN: no swap required to store 0 */ 1318 sp->tx_good = 0; 1319 sp->tx_underruns = 0; 1320 sp->tx_total_collisions = 0; 1321 1322 sp->rx_good = 0; 1323 sp->rx_crc_errors = 0; 1324 sp->rx_alignment_errors = 0; 1325 sp->rx_rnr_errors = 0; 1326 sp->rx_overrun_errors = 0; 1327 } 1328 1329 if (sc->sc_flags & FXPF_MII) { 1330 /* Tick the MII clock. */ 1331 mii_tick(&sc->sc_mii); 1332 } 1333 1334 splx(s); 1335 1336 /* 1337 * Schedule another timeout one second from now. 1338 */ 1339 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1340 } 1341 1342 /* 1343 * Drain the receive queue. 1344 */ 1345 void 1346 fxp_rxdrain(struct fxp_softc *sc) 1347 { 1348 bus_dmamap_t rxmap; 1349 struct mbuf *m; 1350 1351 for (;;) { 1352 IF_DEQUEUE(&sc->sc_rxq, m); 1353 if (m == NULL) 1354 break; 1355 rxmap = M_GETCTX(m, bus_dmamap_t); 1356 bus_dmamap_unload(sc->sc_dmat, rxmap); 1357 FXP_RXMAP_PUT(sc, rxmap); 1358 m_freem(m); 1359 } 1360 } 1361 1362 /* 1363 * Stop the interface. Cancels the statistics updater and resets 1364 * the interface. 1365 */ 1366 void 1367 fxp_stop(struct ifnet *ifp, int disable) 1368 { 1369 struct fxp_softc *sc = ifp->if_softc; 1370 struct fxp_txsoft *txs; 1371 int i; 1372 1373 /* 1374 * Turn down interface (done early to avoid bad interactions 1375 * between panics, shutdown hooks, and the watchdog timer) 1376 */ 1377 ifp->if_timer = 0; 1378 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1379 1380 /* 1381 * Cancel stats updater. 1382 */ 1383 callout_stop(&sc->sc_callout); 1384 if (sc->sc_flags & FXPF_MII) { 1385 /* Down the MII. */ 1386 mii_down(&sc->sc_mii); 1387 } 1388 1389 /* 1390 * Issue software reset. This unloads any microcode that 1391 * might already be loaded. 1392 */ 1393 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1394 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1395 DELAY(50); 1396 1397 /* 1398 * Release any xmit buffers. 1399 */ 1400 for (i = 0; i < FXP_NTXCB; i++) { 1401 txs = FXP_DSTX(sc, i); 1402 if (txs->txs_mbuf != NULL) { 1403 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1404 m_freem(txs->txs_mbuf); 1405 txs->txs_mbuf = NULL; 1406 } 1407 } 1408 sc->sc_txpending = 0; 1409 1410 if (disable) { 1411 fxp_rxdrain(sc); 1412 fxp_disable(sc); 1413 } 1414 1415 } 1416 1417 /* 1418 * Watchdog/transmission transmit timeout handler. Called when a 1419 * transmission is started on the interface, but no interrupt is 1420 * received before the timeout. This usually indicates that the 1421 * card has wedged for some reason. 1422 */ 1423 void 1424 fxp_watchdog(struct ifnet *ifp) 1425 { 1426 struct fxp_softc *sc = ifp->if_softc; 1427 1428 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1429 ifp->if_oerrors++; 1430 1431 (void) fxp_init(ifp); 1432 } 1433 1434 /* 1435 * Initialize the interface. Must be called at splnet(). 1436 */ 1437 int 1438 fxp_init(struct ifnet *ifp) 1439 { 1440 struct fxp_softc *sc = ifp->if_softc; 1441 struct fxp_cb_config *cbp; 1442 struct fxp_cb_ias *cb_ias; 1443 struct fxp_txdesc *txd; 1444 bus_dmamap_t rxmap; 1445 int i, prm, save_bf, lrxen, allm, error = 0; 1446 1447 if ((error = fxp_enable(sc)) != 0) 1448 goto out; 1449 1450 /* 1451 * Cancel any pending I/O 1452 */ 1453 fxp_stop(ifp, 0); 1454 1455 /* 1456 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1457 * flag, and this prevents the MII from detaching resulting in 1458 * a panic. The flags field should perhaps be split in runtime 1459 * flags and more static information. For now, just clear the 1460 * only other flag set. 1461 */ 1462 1463 sc->sc_flags &= ~FXPF_WANTINIT; 1464 1465 /* 1466 * Initialize base of CBL and RFA memory. Loading with zero 1467 * sets it up for regular linear addressing. 1468 */ 1469 fxp_scb_wait(sc); 1470 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1471 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1472 1473 fxp_scb_wait(sc); 1474 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1475 1476 /* 1477 * Initialize the multicast filter. Do this now, since we might 1478 * have to setup the config block differently. 1479 */ 1480 fxp_mc_setup(sc); 1481 1482 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1483 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1484 1485 /* 1486 * In order to support receiving 802.1Q VLAN frames, we have to 1487 * enable "save bad frames", since they are 4 bytes larger than 1488 * the normal Ethernet maximum frame length. On i82558 and later, 1489 * we have a better mechanism for this. 1490 */ 1491 save_bf = 0; 1492 lrxen = 0; 1493 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1494 if (sc->sc_rev < FXP_REV_82558_A4) 1495 save_bf = 1; 1496 else 1497 lrxen = 1; 1498 } 1499 1500 /* 1501 * Initialize base of dump-stats buffer. 1502 */ 1503 fxp_scb_wait(sc); 1504 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1505 sc->sc_cddma + FXP_CDSTATSOFF); 1506 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1507 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1508 1509 cbp = &sc->sc_control_data->fcd_configcb; 1510 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1511 1512 /* 1513 * Load microcode for this controller. 1514 */ 1515 fxp_load_ucode(sc); 1516 1517 /* 1518 * This copy is kind of disgusting, but there are a bunch of must be 1519 * zero and must be one bits in this structure and this is the easiest 1520 * way to initialize them all to proper values. 1521 */ 1522 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1523 1524 /* BIG_ENDIAN: no need to swap to store 0 */ 1525 cbp->cb_status = 0; 1526 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1527 FXP_CB_COMMAND_EL); 1528 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1529 cbp->link_addr = 0xffffffff; /* (no) next command */ 1530 /* bytes in config block */ 1531 cbp->byte_count = FXP_CONFIG_LEN; 1532 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1533 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1534 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1535 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1536 cbp->type_enable = 0; /* actually reserved */ 1537 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1538 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1539 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1540 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1541 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1542 cbp->late_scb = 0; /* (don't) defer SCB update */ 1543 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1544 cbp->ci_int = 1; /* interrupt on CU idle */ 1545 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1546 cbp->ext_stats_dis = 1; /* disable extended counters */ 1547 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1548 cbp->save_bf = save_bf;/* save bad frames */ 1549 cbp->disc_short_rx = !prm; /* discard short packets */ 1550 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1551 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1552 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1553 /* interface mode */ 1554 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1555 cbp->csma_dis = 0; /* (don't) disable link */ 1556 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1557 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1558 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1559 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1560 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1561 cbp->nsai = 1; /* (don't) disable source addr insert */ 1562 cbp->preamble_length = 2; /* (7 byte) preamble */ 1563 cbp->loopback = 0; /* (don't) loopback */ 1564 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1565 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1566 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1567 cbp->promiscuous = prm; /* promiscuous mode */ 1568 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1569 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1570 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1571 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1572 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1573 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1574 cbp->padding = 1; /* (do) pad short tx packets */ 1575 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1576 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1577 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1578 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1579 /* must set wake_en in PMCSR also */ 1580 cbp->force_fdx = 0; /* (don't) force full duplex */ 1581 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1582 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1583 cbp->mc_all = allm; /* accept all multicasts */ 1584 1585 if (sc->sc_rev < FXP_REV_82558_A4) { 1586 /* 1587 * The i82557 has no hardware flow control, the values 1588 * here are the defaults for the chip. 1589 */ 1590 cbp->fc_delay_lsb = 0; 1591 cbp->fc_delay_msb = 0x40; 1592 cbp->pri_fc_thresh = 3; 1593 cbp->tx_fc_dis = 0; 1594 cbp->rx_fc_restop = 0; 1595 cbp->rx_fc_restart = 0; 1596 cbp->fc_filter = 0; 1597 cbp->pri_fc_loc = 1; 1598 } else { 1599 cbp->fc_delay_lsb = 0x1f; 1600 cbp->fc_delay_msb = 0x01; 1601 cbp->pri_fc_thresh = 3; 1602 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1603 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1604 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1605 cbp->fc_filter = !prm; /* drop FC frames to host */ 1606 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1607 } 1608 1609 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1610 1611 /* 1612 * Start the config command/DMA. 1613 */ 1614 fxp_scb_wait(sc); 1615 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1616 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1617 /* ...and wait for it to complete. */ 1618 i = 1000; 1619 do { 1620 FXP_CDCONFIGSYNC(sc, 1621 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1622 DELAY(1); 1623 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1624 if (i == 0) { 1625 printf("%s at line %d: dmasync timeout\n", 1626 sc->sc_dev.dv_xname, __LINE__); 1627 return (ETIMEDOUT); 1628 } 1629 1630 /* 1631 * Initialize the station address. 1632 */ 1633 cb_ias = &sc->sc_control_data->fcd_iascb; 1634 /* BIG_ENDIAN: no need to swap to store 0 */ 1635 cb_ias->cb_status = 0; 1636 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1637 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1638 cb_ias->link_addr = 0xffffffff; 1639 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1640 1641 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1642 1643 /* 1644 * Start the IAS (Individual Address Setup) command/DMA. 1645 */ 1646 fxp_scb_wait(sc); 1647 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1648 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1649 /* ...and wait for it to complete. */ 1650 i = 1000; 1651 do { 1652 FXP_CDIASSYNC(sc, 1653 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1654 DELAY(1); 1655 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1656 if (i == 0) { 1657 printf("%s at line %d: dmasync timeout\n", 1658 sc->sc_dev.dv_xname, __LINE__); 1659 return (ETIMEDOUT); 1660 } 1661 1662 /* 1663 * Initialize the transmit descriptor ring. txlast is initialized 1664 * to the end of the list so that it will wrap around to the first 1665 * descriptor when the first packet is transmitted. 1666 */ 1667 for (i = 0; i < FXP_NTXCB; i++) { 1668 txd = FXP_CDTX(sc, i); 1669 memset(txd, 0, sizeof(*txd)); 1670 txd->txd_txcb.cb_command = 1671 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1672 txd->txd_txcb.link_addr = 1673 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1674 if (sc->sc_flags & FXPF_EXT_TXCB) 1675 txd->txd_txcb.tbd_array_addr = 1676 htole32(FXP_CDTBDADDR(sc, i) + 1677 (2 * sizeof(struct fxp_tbd))); 1678 else 1679 txd->txd_txcb.tbd_array_addr = 1680 htole32(FXP_CDTBDADDR(sc, i)); 1681 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1682 } 1683 sc->sc_txpending = 0; 1684 sc->sc_txdirty = 0; 1685 sc->sc_txlast = FXP_NTXCB - 1; 1686 1687 /* 1688 * Initialize the receive buffer list. 1689 */ 1690 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1691 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1692 rxmap = FXP_RXMAP_GET(sc); 1693 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1694 printf("%s: unable to allocate or map rx " 1695 "buffer %d, error = %d\n", 1696 sc->sc_dev.dv_xname, 1697 sc->sc_rxq.ifq_len, error); 1698 /* 1699 * XXX Should attempt to run with fewer receive 1700 * XXX buffers instead of just failing. 1701 */ 1702 FXP_RXMAP_PUT(sc, rxmap); 1703 fxp_rxdrain(sc); 1704 goto out; 1705 } 1706 } 1707 sc->sc_rxidle = 0; 1708 1709 /* 1710 * Give the transmit ring to the chip. We do this by pointing 1711 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1712 * issuing a start command. It will execute the NOP and then 1713 * suspend, pointing at the first descriptor. 1714 */ 1715 fxp_scb_wait(sc); 1716 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1717 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1718 1719 /* 1720 * Initialize receiver buffer area - RFA. 1721 */ 1722 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1723 fxp_scb_wait(sc); 1724 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1725 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1726 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1727 1728 if (sc->sc_flags & FXPF_MII) { 1729 /* 1730 * Set current media. 1731 */ 1732 mii_mediachg(&sc->sc_mii); 1733 } 1734 1735 /* 1736 * ...all done! 1737 */ 1738 ifp->if_flags |= IFF_RUNNING; 1739 ifp->if_flags &= ~IFF_OACTIVE; 1740 1741 /* 1742 * Start the one second timer. 1743 */ 1744 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1745 1746 /* 1747 * Attempt to start output on the interface. 1748 */ 1749 fxp_start(ifp); 1750 1751 out: 1752 if (error) { 1753 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1754 ifp->if_timer = 0; 1755 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1756 } 1757 return (error); 1758 } 1759 1760 /* 1761 * Change media according to request. 1762 */ 1763 int 1764 fxp_mii_mediachange(struct ifnet *ifp) 1765 { 1766 struct fxp_softc *sc = ifp->if_softc; 1767 1768 if (ifp->if_flags & IFF_UP) 1769 mii_mediachg(&sc->sc_mii); 1770 return (0); 1771 } 1772 1773 /* 1774 * Notify the world which media we're using. 1775 */ 1776 void 1777 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1778 { 1779 struct fxp_softc *sc = ifp->if_softc; 1780 1781 if (sc->sc_enabled == 0) { 1782 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1783 ifmr->ifm_status = 0; 1784 return; 1785 } 1786 1787 mii_pollstat(&sc->sc_mii); 1788 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1789 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1790 } 1791 1792 int 1793 fxp_80c24_mediachange(struct ifnet *ifp) 1794 { 1795 1796 /* Nothing to do here. */ 1797 return (0); 1798 } 1799 1800 void 1801 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1802 { 1803 struct fxp_softc *sc = ifp->if_softc; 1804 1805 /* 1806 * Media is currently-selected media. We cannot determine 1807 * the link status. 1808 */ 1809 ifmr->ifm_status = 0; 1810 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1811 } 1812 1813 /* 1814 * Add a buffer to the end of the RFA buffer list. 1815 * Return 0 if successful, error code on failure. 1816 * 1817 * The RFA struct is stuck at the beginning of mbuf cluster and the 1818 * data pointer is fixed up to point just past it. 1819 */ 1820 int 1821 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1822 { 1823 struct mbuf *m; 1824 int error; 1825 1826 MGETHDR(m, M_DONTWAIT, MT_DATA); 1827 if (m == NULL) 1828 return (ENOBUFS); 1829 1830 MCLGET(m, M_DONTWAIT); 1831 if ((m->m_flags & M_EXT) == 0) { 1832 m_freem(m); 1833 return (ENOBUFS); 1834 } 1835 1836 if (unload) 1837 bus_dmamap_unload(sc->sc_dmat, rxmap); 1838 1839 M_SETCTX(m, rxmap); 1840 1841 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1842 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1843 BUS_DMA_READ|BUS_DMA_NOWAIT); 1844 if (error) { 1845 printf("%s: can't load rx DMA map %d, error = %d\n", 1846 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1847 panic("fxp_add_rfabuf"); /* XXX */ 1848 } 1849 1850 FXP_INIT_RFABUF(sc, m); 1851 1852 return (0); 1853 } 1854 1855 int 1856 fxp_mdi_read(struct device *self, int phy, int reg) 1857 { 1858 struct fxp_softc *sc = (struct fxp_softc *)self; 1859 int count = 10000; 1860 int value; 1861 1862 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1863 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1864 1865 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 1866 0x10000000) == 0 && count--) 1867 DELAY(10); 1868 1869 if (count <= 0) 1870 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1871 1872 return (value & 0xffff); 1873 } 1874 1875 void 1876 fxp_statchg(struct device *self) 1877 { 1878 1879 /* Nothing to do. */ 1880 } 1881 1882 void 1883 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1884 { 1885 struct fxp_softc *sc = (struct fxp_softc *)self; 1886 int count = 10000; 1887 1888 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1889 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1890 (value & 0xffff)); 1891 1892 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1893 count--) 1894 DELAY(10); 1895 1896 if (count <= 0) 1897 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1898 } 1899 1900 int 1901 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1902 { 1903 struct fxp_softc *sc = ifp->if_softc; 1904 struct ifreq *ifr = (struct ifreq *)data; 1905 int s, error; 1906 1907 s = splnet(); 1908 1909 switch (cmd) { 1910 case SIOCSIFMEDIA: 1911 case SIOCGIFMEDIA: 1912 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1913 break; 1914 1915 default: 1916 error = ether_ioctl(ifp, cmd, data); 1917 if (error == ENETRESET) { 1918 if (sc->sc_enabled) { 1919 /* 1920 * Multicast list has changed; set the 1921 * hardware filter accordingly. 1922 */ 1923 if (sc->sc_txpending) { 1924 sc->sc_flags |= FXPF_WANTINIT; 1925 error = 0; 1926 } else 1927 error = fxp_init(ifp); 1928 } else 1929 error = 0; 1930 } 1931 break; 1932 } 1933 1934 /* Try to get more packets going. */ 1935 if (sc->sc_enabled) 1936 fxp_start(ifp); 1937 1938 splx(s); 1939 return (error); 1940 } 1941 1942 /* 1943 * Program the multicast filter. 1944 * 1945 * This function must be called at splnet(). 1946 */ 1947 void 1948 fxp_mc_setup(struct fxp_softc *sc) 1949 { 1950 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1951 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1952 struct ethercom *ec = &sc->sc_ethercom; 1953 struct ether_multi *enm; 1954 struct ether_multistep step; 1955 int count, nmcasts; 1956 1957 #ifdef DIAGNOSTIC 1958 if (sc->sc_txpending) 1959 panic("fxp_mc_setup: pending transmissions"); 1960 #endif 1961 1962 ifp->if_flags &= ~IFF_ALLMULTI; 1963 1964 /* 1965 * Initialize multicast setup descriptor. 1966 */ 1967 nmcasts = 0; 1968 ETHER_FIRST_MULTI(step, ec, enm); 1969 while (enm != NULL) { 1970 /* 1971 * Check for too many multicast addresses or if we're 1972 * listening to a range. Either way, we simply have 1973 * to accept all multicasts. 1974 */ 1975 if (nmcasts >= MAXMCADDR || 1976 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1977 ETHER_ADDR_LEN) != 0) { 1978 /* 1979 * Callers of this function must do the 1980 * right thing with this. If we're called 1981 * from outside fxp_init(), the caller must 1982 * detect if the state if IFF_ALLMULTI changes. 1983 * If it does, the caller must then call 1984 * fxp_init(), since allmulti is handled by 1985 * the config block. 1986 */ 1987 ifp->if_flags |= IFF_ALLMULTI; 1988 return; 1989 } 1990 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1991 ETHER_ADDR_LEN); 1992 nmcasts++; 1993 ETHER_NEXT_MULTI(step, enm); 1994 } 1995 1996 /* BIG_ENDIAN: no need to swap to store 0 */ 1997 mcsp->cb_status = 0; 1998 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 1999 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2000 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2001 2002 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2003 2004 /* 2005 * Wait until the command unit is not active. This should never 2006 * happen since nothing is queued, but make sure anyway. 2007 */ 2008 count = 100; 2009 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2010 FXP_SCB_CUS_ACTIVE && --count) 2011 DELAY(1); 2012 if (count == 0) { 2013 printf("%s at line %d: command queue timeout\n", 2014 sc->sc_dev.dv_xname, __LINE__); 2015 return; 2016 } 2017 2018 /* 2019 * Start the multicast setup command/DMA. 2020 */ 2021 fxp_scb_wait(sc); 2022 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2023 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2024 2025 /* ...and wait for it to complete. */ 2026 count = 1000; 2027 do { 2028 FXP_CDMCSSYNC(sc, 2029 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2030 DELAY(1); 2031 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2032 if (count == 0) { 2033 printf("%s at line %d: dmasync timeout\n", 2034 sc->sc_dev.dv_xname, __LINE__); 2035 return; 2036 } 2037 } 2038 2039 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2040 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2041 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2042 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2043 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2044 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2045 2046 #define UCODE(x) x, sizeof(x) 2047 2048 static const struct ucode { 2049 int32_t revision; 2050 const uint32_t *ucode; 2051 size_t length; 2052 uint16_t int_delay_offset; 2053 uint16_t bundle_max_offset; 2054 } ucode_table[] = { 2055 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2056 D101_CPUSAVER_DWORD, 0 }, 2057 2058 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2059 D101_CPUSAVER_DWORD, 0 }, 2060 2061 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2062 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2063 2064 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2065 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2066 2067 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2068 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2069 2070 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2071 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2072 2073 { 0, NULL, 0, 0, 0 } 2074 }; 2075 2076 void 2077 fxp_load_ucode(struct fxp_softc *sc) 2078 { 2079 const struct ucode *uc; 2080 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2081 int count; 2082 2083 if (sc->sc_flags & FXPF_UCODE_LOADED) 2084 return; 2085 2086 /* 2087 * Only load the uCode if the user has requested that 2088 * we do so. 2089 */ 2090 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2091 sc->sc_int_delay = 0; 2092 sc->sc_bundle_max = 0; 2093 return; 2094 } 2095 2096 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2097 if (sc->sc_rev == uc->revision) 2098 break; 2099 } 2100 if (uc->ucode == NULL) 2101 return; 2102 2103 /* BIG ENDIAN: no need to swap to store 0 */ 2104 cbp->cb_status = 0; 2105 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2106 cbp->link_addr = 0xffffffff; /* (no) next command */ 2107 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2108 2109 if (uc->int_delay_offset) 2110 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2111 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2112 2113 if (uc->bundle_max_offset) 2114 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2115 htole16(fxp_bundle_max); 2116 2117 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2118 2119 /* 2120 * Download the uCode to the chip. 2121 */ 2122 fxp_scb_wait(sc); 2123 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2124 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2125 2126 /* ...and wait for it to complete. */ 2127 count = 10000; 2128 do { 2129 FXP_CDUCODESYNC(sc, 2130 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2131 DELAY(2); 2132 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2133 if (count == 0) { 2134 sc->sc_int_delay = 0; 2135 sc->sc_bundle_max = 0; 2136 printf("%s: timeout loading microcode\n", 2137 sc->sc_dev.dv_xname); 2138 return; 2139 } 2140 2141 if (sc->sc_int_delay != fxp_int_delay || 2142 sc->sc_bundle_max != fxp_bundle_max) { 2143 sc->sc_int_delay = fxp_int_delay; 2144 sc->sc_bundle_max = fxp_bundle_max; 2145 printf("%s: Microcode loaded: int delay: %d usec, " 2146 "max bundle: %d\n", sc->sc_dev.dv_xname, 2147 sc->sc_int_delay, 2148 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2149 } 2150 2151 sc->sc_flags |= FXPF_UCODE_LOADED; 2152 } 2153 2154 int 2155 fxp_enable(struct fxp_softc *sc) 2156 { 2157 2158 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2159 if ((*sc->sc_enable)(sc) != 0) { 2160 printf("%s: device enable failed\n", 2161 sc->sc_dev.dv_xname); 2162 return (EIO); 2163 } 2164 } 2165 2166 sc->sc_enabled = 1; 2167 return (0); 2168 } 2169 2170 void 2171 fxp_disable(struct fxp_softc *sc) 2172 { 2173 2174 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2175 (*sc->sc_disable)(sc); 2176 sc->sc_enabled = 0; 2177 } 2178 } 2179 2180 /* 2181 * fxp_activate: 2182 * 2183 * Handle device activation/deactivation requests. 2184 */ 2185 int 2186 fxp_activate(struct device *self, enum devact act) 2187 { 2188 struct fxp_softc *sc = (void *) self; 2189 int s, error = 0; 2190 2191 s = splnet(); 2192 switch (act) { 2193 case DVACT_ACTIVATE: 2194 error = EOPNOTSUPP; 2195 break; 2196 2197 case DVACT_DEACTIVATE: 2198 if (sc->sc_flags & FXPF_MII) 2199 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2200 MII_OFFSET_ANY); 2201 if_deactivate(&sc->sc_ethercom.ec_if); 2202 break; 2203 } 2204 splx(s); 2205 2206 return (error); 2207 } 2208 2209 /* 2210 * fxp_detach: 2211 * 2212 * Detach an i82557 interface. 2213 */ 2214 int 2215 fxp_detach(struct fxp_softc *sc) 2216 { 2217 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2218 int i; 2219 2220 /* Succeed now if there's no work to do. */ 2221 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2222 return (0); 2223 2224 /* Unhook our tick handler. */ 2225 callout_stop(&sc->sc_callout); 2226 2227 if (sc->sc_flags & FXPF_MII) { 2228 /* Detach all PHYs */ 2229 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2230 } 2231 2232 /* Delete all remaining media. */ 2233 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2234 2235 #if NRND > 0 2236 rnd_detach_source(&sc->rnd_source); 2237 #endif 2238 ether_ifdetach(ifp); 2239 if_detach(ifp); 2240 2241 for (i = 0; i < FXP_NRFABUFS; i++) { 2242 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2243 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2244 } 2245 2246 for (i = 0; i < FXP_NTXCB; i++) { 2247 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2248 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2249 } 2250 2251 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2252 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2253 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2254 sizeof(struct fxp_control_data)); 2255 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2256 2257 shutdownhook_disestablish(sc->sc_sdhook); 2258 powerhook_disestablish(sc->sc_powerhook); 2259 2260 return (0); 2261 } 2262
Indexes created Sun Sep 28 16:09:52 GMT 2025