i82557.c revision 1.74
1 /* $NetBSD: i82557.c,v 1.74 2003/05/25 15:10:23 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.74 2003/05/25 15:10:23 yamt Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 void fxp_rxdrain(struct fxp_softc *); 194 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 195 int fxp_mdi_read(struct device *, int, int); 196 void fxp_statchg(struct device *); 197 void fxp_mdi_write(struct device *, int, int, int); 198 void fxp_autosize_eeprom(struct fxp_softc*); 199 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 200 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 201 void fxp_eeprom_update_cksum(struct fxp_softc *); 202 void fxp_get_info(struct fxp_softc *, u_int8_t *); 203 void fxp_tick(void *); 204 void fxp_mc_setup(struct fxp_softc *); 205 void fxp_load_ucode(struct fxp_softc *); 206 207 void fxp_shutdown(void *); 208 void fxp_power(int, void *); 209 210 int fxp_copy_small = 0; 211 212 /* 213 * Variables for interrupt mitigating microcode. 214 */ 215 int fxp_int_delay = 1000; /* usec */ 216 int fxp_bundle_max = 6; /* packets */ 217 218 struct fxp_phytype { 219 int fp_phy; /* type of PHY, -1 for MII at the end. */ 220 void (*fp_init)(struct fxp_softc *); 221 } fxp_phytype_table[] = { 222 { FXP_PHY_80C24, fxp_80c24_initmedia }, 223 { -1, fxp_mii_initmedia }, 224 }; 225 226 /* 227 * Set initial transmit threshold at 64 (512 bytes). This is 228 * increased by 64 (512 bytes) at a time, to maximum of 192 229 * (1536 bytes), if an underrun occurs. 230 */ 231 static int tx_threshold = 64; 232 233 /* 234 * Wait for the previous command to be accepted (but not necessarily 235 * completed). 236 */ 237 static __inline void 238 fxp_scb_wait(struct fxp_softc *sc) 239 { 240 int i = 10000; 241 242 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 243 delay(2); 244 if (i == 0) 245 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 246 } 247 248 /* 249 * Submit a command to the i82557. 250 */ 251 static __inline void 252 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 253 { 254 255 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 256 } 257 258 /* 259 * Finish attaching an i82557 interface. Called by bus-specific front-end. 260 */ 261 void 262 fxp_attach(struct fxp_softc *sc) 263 { 264 u_int8_t enaddr[ETHER_ADDR_LEN]; 265 struct ifnet *ifp; 266 bus_dma_segment_t seg; 267 int rseg, i, error; 268 struct fxp_phytype *fp; 269 270 callout_init(&sc->sc_callout); 271 272 /* Start out using the standard RFA. */ 273 sc->sc_rfa_size = RFA_SIZE; 274 275 /* 276 * Enable some good stuff on i82558 and later. 277 */ 278 if (sc->sc_rev >= FXP_REV_82558_A4) { 279 /* Enable the extended TxCB. */ 280 sc->sc_flags |= FXPF_EXT_TXCB; 281 } 282 283 /* 284 * Allocate the control data structures, and create and load the 285 * DMA map for it. 286 */ 287 if ((error = bus_dmamem_alloc(sc->sc_dmat, 288 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 289 0)) != 0) { 290 aprint_error( 291 "%s: unable to allocate control data, error = %d\n", 292 sc->sc_dev.dv_xname, error); 293 goto fail_0; 294 } 295 296 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 297 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 298 BUS_DMA_COHERENT)) != 0) { 299 aprint_error("%s: unable to map control data, error = %d\n", 300 sc->sc_dev.dv_xname, error); 301 goto fail_1; 302 } 303 sc->sc_cdseg = seg; 304 sc->sc_cdnseg = rseg; 305 306 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 307 308 if ((error = bus_dmamap_create(sc->sc_dmat, 309 sizeof(struct fxp_control_data), 1, 310 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 311 aprint_error("%s: unable to create control data DMA map, " 312 "error = %d\n", sc->sc_dev.dv_xname, error); 313 goto fail_2; 314 } 315 316 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 317 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 318 0)) != 0) { 319 aprint_error( 320 "%s: can't load control data DMA map, error = %d\n", 321 sc->sc_dev.dv_xname, error); 322 goto fail_3; 323 } 324 325 /* 326 * Create the transmit buffer DMA maps. 327 */ 328 for (i = 0; i < FXP_NTXCB; i++) { 329 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 330 FXP_NTXSEG, MCLBYTES, 0, 0, 331 &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 332 aprint_error("%s: unable to create tx DMA map %d, " 333 "error = %d\n", sc->sc_dev.dv_xname, i, error); 334 goto fail_4; 335 } 336 } 337 338 /* 339 * Create the receive buffer DMA maps. 340 */ 341 for (i = 0; i < FXP_NRFABUFS; i++) { 342 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 343 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 344 aprint_error("%s: unable to create rx DMA map %d, " 345 "error = %d\n", sc->sc_dev.dv_xname, i, error); 346 goto fail_5; 347 } 348 } 349 350 /* Initialize MAC address and media structures. */ 351 fxp_get_info(sc, enaddr); 352 353 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 354 ether_sprintf(enaddr)); 355 356 ifp = &sc->sc_ethercom.ec_if; 357 358 /* 359 * Get info about our media interface, and initialize it. Note 360 * the table terminates itself with a phy of -1, indicating 361 * that we're using MII. 362 */ 363 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 364 if (fp->fp_phy == sc->phy_primary_device) 365 break; 366 (*fp->fp_init)(sc); 367 368 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 369 ifp->if_softc = sc; 370 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 371 ifp->if_ioctl = fxp_ioctl; 372 ifp->if_start = fxp_start; 373 ifp->if_watchdog = fxp_watchdog; 374 ifp->if_init = fxp_init; 375 ifp->if_stop = fxp_stop; 376 IFQ_SET_READY(&ifp->if_snd); 377 378 /* 379 * We can support 802.1Q VLAN-sized frames. 380 */ 381 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 382 383 /* 384 * Attach the interface. 385 */ 386 if_attach(ifp); 387 ether_ifattach(ifp, enaddr); 388 #if NRND > 0 389 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 390 RND_TYPE_NET, 0); 391 #endif 392 393 #ifdef FXP_EVENT_COUNTERS 394 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 395 NULL, sc->sc_dev.dv_xname, "txstall"); 396 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 397 NULL, sc->sc_dev.dv_xname, "txintr"); 398 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 399 NULL, sc->sc_dev.dv_xname, "rxintr"); 400 #endif /* FXP_EVENT_COUNTERS */ 401 402 /* 403 * Add shutdown hook so that DMA is disabled prior to reboot. Not 404 * doing do could allow DMA to corrupt kernel memory during the 405 * reboot before the driver initializes. 406 */ 407 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 408 if (sc->sc_sdhook == NULL) 409 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 410 sc->sc_dev.dv_xname); 411 /* 412 * Add suspend hook, for similar reasons.. 413 */ 414 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 415 if (sc->sc_powerhook == NULL) 416 aprint_error("%s: WARNING: unable to establish power hook\n", 417 sc->sc_dev.dv_xname); 418 419 /* The attach is successful. */ 420 sc->sc_flags |= FXPF_ATTACHED; 421 422 return; 423 424 /* 425 * Free any resources we've allocated during the failed attach 426 * attempt. Do this in reverse order and fall though. 427 */ 428 fail_5: 429 for (i = 0; i < FXP_NRFABUFS; i++) { 430 if (sc->sc_rxmaps[i] != NULL) 431 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 432 } 433 fail_4: 434 for (i = 0; i < FXP_NTXCB; i++) { 435 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 436 bus_dmamap_destroy(sc->sc_dmat, 437 FXP_DSTX(sc, i)->txs_dmamap); 438 } 439 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 440 fail_3: 441 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 442 fail_2: 443 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 444 sizeof(struct fxp_control_data)); 445 fail_1: 446 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 447 fail_0: 448 return; 449 } 450 451 void 452 fxp_mii_initmedia(struct fxp_softc *sc) 453 { 454 int flags; 455 456 sc->sc_flags |= FXPF_MII; 457 458 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 459 sc->sc_mii.mii_readreg = fxp_mdi_read; 460 sc->sc_mii.mii_writereg = fxp_mdi_write; 461 sc->sc_mii.mii_statchg = fxp_statchg; 462 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 463 fxp_mii_mediastatus); 464 465 flags = MIIF_NOISOLATE; 466 if (sc->sc_rev >= FXP_REV_82558_A4) 467 flags |= MIIF_DOPAUSE; 468 /* 469 * The i82557 wedges if all of its PHYs are isolated! 470 */ 471 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 472 MII_OFFSET_ANY, flags); 473 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 474 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 475 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 476 } else 477 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 478 } 479 480 void 481 fxp_80c24_initmedia(struct fxp_softc *sc) 482 { 483 484 /* 485 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 486 * doesn't have a programming interface of any sort. The 487 * media is sensed automatically based on how the link partner 488 * is configured. This is, in essence, manual configuration. 489 */ 490 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 491 sc->sc_dev.dv_xname); 492 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 493 fxp_80c24_mediastatus); 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 495 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 496 } 497 498 /* 499 * Device shutdown routine. Called at system shutdown after sync. The 500 * main purpose of this routine is to shut off receiver DMA so that 501 * kernel memory doesn't get clobbered during warmboot. 502 */ 503 void 504 fxp_shutdown(void *arg) 505 { 506 struct fxp_softc *sc = arg; 507 508 /* 509 * Since the system's going to halt shortly, don't bother 510 * freeing mbufs. 511 */ 512 fxp_stop(&sc->sc_ethercom.ec_if, 0); 513 } 514 /* 515 * Power handler routine. Called when the system is transitioning 516 * into/out of power save modes. As with fxp_shutdown, the main 517 * purpose of this routine is to shut off receiver DMA so it doesn't 518 * clobber kernel memory at the wrong time. 519 */ 520 void 521 fxp_power(int why, void *arg) 522 { 523 struct fxp_softc *sc = arg; 524 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 525 int s; 526 527 s = splnet(); 528 switch (why) { 529 case PWR_SUSPEND: 530 case PWR_STANDBY: 531 fxp_stop(ifp, 0); 532 break; 533 case PWR_RESUME: 534 if (ifp->if_flags & IFF_UP) 535 fxp_init(ifp); 536 break; 537 case PWR_SOFTSUSPEND: 538 case PWR_SOFTSTANDBY: 539 case PWR_SOFTRESUME: 540 break; 541 } 542 splx(s); 543 } 544 545 /* 546 * Initialize the interface media. 547 */ 548 void 549 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 550 { 551 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 552 553 /* 554 * Reset to a stable state. 555 */ 556 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 557 DELAY(10); 558 559 sc->sc_eeprom_size = 0; 560 fxp_autosize_eeprom(sc); 561 if (sc->sc_eeprom_size == 0) { 562 aprint_error("%s: failed to detect EEPROM size\n", 563 sc->sc_dev.dv_xname); 564 sc->sc_eeprom_size = 6; /* XXX panic here? */ 565 } 566 #ifdef DEBUG 567 aprint_debug("%s: detected %d word EEPROM\n", 568 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 569 #endif 570 571 /* 572 * Get info about the primary PHY 573 */ 574 fxp_read_eeprom(sc, &data, 6, 1); 575 sc->phy_primary_device = 576 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 577 578 /* 579 * Read MAC address. 580 */ 581 fxp_read_eeprom(sc, myea, 0, 3); 582 enaddr[0] = myea[0] & 0xff; 583 enaddr[1] = myea[0] >> 8; 584 enaddr[2] = myea[1] & 0xff; 585 enaddr[3] = myea[1] >> 8; 586 enaddr[4] = myea[2] & 0xff; 587 enaddr[5] = myea[2] >> 8; 588 589 /* 590 * Systems based on the ICH2/ICH2-M chip from Intel, as well 591 * as some i82559 designs, have a defect where the chip can 592 * cause a PCI protocol violation if it receives a CU_RESUME 593 * command when it is entering the IDLE state. 594 * 595 * The work-around is to disable Dynamic Standby Mode, so that 596 * the chip never deasserts #CLKRUN, and always remains in the 597 * active state. 598 * 599 * Unfortunately, the only way to disable Dynamic Standby is 600 * to frob an EEPROM setting and reboot (the EEPROM setting 601 * is only consulted when the PCI bus comes out of reset). 602 * 603 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 604 */ 605 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 606 fxp_read_eeprom(sc, &data, 10, 1); 607 if (data & 0x02) { /* STB enable */ 608 aprint_error("%s: WARNING: " 609 "Disabling dynamic standby mode in EEPROM " 610 "to work around a\n", 611 sc->sc_dev.dv_xname); 612 aprint_normal( 613 "%s: WARNING: hardware bug. You must reset " 614 "the system before using this\n", 615 sc->sc_dev.dv_xname); 616 aprint_normal("%s: WARNING: interface.\n", 617 sc->sc_dev.dv_xname); 618 data &= ~0x02; 619 fxp_write_eeprom(sc, &data, 10, 1); 620 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 621 sc->sc_dev.dv_xname, data); 622 fxp_eeprom_update_cksum(sc); 623 } 624 } 625 } 626 627 static void 628 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 629 { 630 uint16_t reg; 631 int x; 632 633 for (x = 1 << (len - 1); x != 0; x >>= 1) { 634 if (data & x) 635 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 636 else 637 reg = FXP_EEPROM_EECS; 638 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 639 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 640 reg | FXP_EEPROM_EESK); 641 DELAY(4); 642 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 643 DELAY(4); 644 } 645 } 646 647 /* 648 * Figure out EEPROM size. 649 * 650 * 559's can have either 64-word or 256-word EEPROMs, the 558 651 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 652 * talks about the existance of 16 to 256 word EEPROMs. 653 * 654 * The only known sizes are 64 and 256, where the 256 version is used 655 * by CardBus cards to store CIS information. 656 * 657 * The address is shifted in msb-to-lsb, and after the last 658 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 659 * after which follows the actual data. We try to detect this zero, by 660 * probing the data-out bit in the EEPROM control register just after 661 * having shifted in a bit. If the bit is zero, we assume we've 662 * shifted enough address bits. The data-out should be tri-state, 663 * before this, which should translate to a logical one. 664 * 665 * Other ways to do this would be to try to read a register with known 666 * contents with a varying number of address bits, but no such 667 * register seem to be available. The high bits of register 10 are 01 668 * on the 558 and 559, but apparently not on the 557. 669 * 670 * The Linux driver computes a checksum on the EEPROM data, but the 671 * value of this checksum is not very well documented. 672 */ 673 674 void 675 fxp_autosize_eeprom(struct fxp_softc *sc) 676 { 677 int x; 678 679 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 680 681 /* Shift in read opcode. */ 682 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 683 684 /* 685 * Shift in address, wait for the dummy zero following a correct 686 * address shift. 687 */ 688 for (x = 1; x <= 8; x++) { 689 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 690 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 691 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 692 DELAY(4); 693 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 694 FXP_EEPROM_EEDO) == 0) 695 break; 696 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 697 DELAY(4); 698 } 699 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 700 DELAY(4); 701 if (x != 6 && x != 8) { 702 #ifdef DEBUG 703 printf("%s: strange EEPROM size (%d)\n", 704 sc->sc_dev.dv_xname, 1 << x); 705 #endif 706 } else 707 sc->sc_eeprom_size = x; 708 } 709 710 /* 711 * Read from the serial EEPROM. Basically, you manually shift in 712 * the read opcode (one bit at a time) and then shift in the address, 713 * and then you shift out the data (all of this one bit at a time). 714 * The word size is 16 bits, so you have to provide the address for 715 * every 16 bits of data. 716 */ 717 void 718 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 719 { 720 u_int16_t reg; 721 int i, x; 722 723 for (i = 0; i < words; i++) { 724 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 725 726 /* Shift in read opcode. */ 727 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 728 729 /* Shift in address. */ 730 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 731 732 reg = FXP_EEPROM_EECS; 733 data[i] = 0; 734 735 /* Shift out data. */ 736 for (x = 16; x > 0; x--) { 737 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 738 reg | FXP_EEPROM_EESK); 739 DELAY(4); 740 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 741 FXP_EEPROM_EEDO) 742 data[i] |= (1 << (x - 1)); 743 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 744 DELAY(4); 745 } 746 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 747 DELAY(4); 748 } 749 } 750 751 /* 752 * Write data to the serial EEPROM. 753 */ 754 void 755 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 756 { 757 int i, j; 758 759 for (i = 0; i < words; i++) { 760 /* Erase/write enable. */ 761 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 762 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 763 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 764 sc->sc_eeprom_size); 765 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 766 DELAY(4); 767 768 /* Shift in write opcode, address, data. */ 769 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 770 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 771 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 772 fxp_eeprom_shiftin(sc, data[i], 16); 773 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 774 DELAY(4); 775 776 /* Wait for the EEPROM to finish up. */ 777 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 778 DELAY(4); 779 for (j = 0; j < 1000; j++) { 780 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 781 FXP_EEPROM_EEDO) 782 break; 783 DELAY(50); 784 } 785 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 786 DELAY(4); 787 788 /* Erase/write disable. */ 789 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 790 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 791 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 792 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 793 DELAY(4); 794 } 795 } 796 797 /* 798 * Update the checksum of the EEPROM. 799 */ 800 void 801 fxp_eeprom_update_cksum(struct fxp_softc *sc) 802 { 803 int i; 804 uint16_t data, cksum; 805 806 cksum = 0; 807 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 808 fxp_read_eeprom(sc, &data, i, 1); 809 cksum += data; 810 } 811 i = (1 << sc->sc_eeprom_size) - 1; 812 cksum = 0xbaba - cksum; 813 fxp_read_eeprom(sc, &data, i, 1); 814 fxp_write_eeprom(sc, &cksum, i, 1); 815 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 816 sc->sc_dev.dv_xname, i, data, cksum); 817 } 818 819 /* 820 * Start packet transmission on the interface. 821 */ 822 void 823 fxp_start(struct ifnet *ifp) 824 { 825 struct fxp_softc *sc = ifp->if_softc; 826 struct mbuf *m0, *m; 827 struct fxp_txdesc *txd; 828 struct fxp_txsoft *txs; 829 bus_dmamap_t dmamap; 830 int error, lasttx, nexttx, opending, seg; 831 832 /* 833 * If we want a re-init, bail out now. 834 */ 835 if (sc->sc_flags & FXPF_WANTINIT) { 836 ifp->if_flags |= IFF_OACTIVE; 837 return; 838 } 839 840 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 841 return; 842 843 /* 844 * Remember the previous txpending and the current lasttx. 845 */ 846 opending = sc->sc_txpending; 847 lasttx = sc->sc_txlast; 848 849 /* 850 * Loop through the send queue, setting up transmit descriptors 851 * until we drain the queue, or use up all available transmit 852 * descriptors. 853 */ 854 for (;;) { 855 /* 856 * Grab a packet off the queue. 857 */ 858 IFQ_POLL(&ifp->if_snd, m0); 859 if (m0 == NULL) 860 break; 861 m = NULL; 862 863 if (sc->sc_txpending == FXP_NTXCB) { 864 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 865 break; 866 } 867 868 /* 869 * Get the next available transmit descriptor. 870 */ 871 nexttx = FXP_NEXTTX(sc->sc_txlast); 872 txd = FXP_CDTX(sc, nexttx); 873 txs = FXP_DSTX(sc, nexttx); 874 dmamap = txs->txs_dmamap; 875 876 /* 877 * Load the DMA map. If this fails, the packet either 878 * didn't fit in the allotted number of frags, or we were 879 * short on resources. In this case, we'll copy and try 880 * again. 881 */ 882 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 883 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 884 MGETHDR(m, M_DONTWAIT, MT_DATA); 885 if (m == NULL) { 886 printf("%s: unable to allocate Tx mbuf\n", 887 sc->sc_dev.dv_xname); 888 break; 889 } 890 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 891 if (m0->m_pkthdr.len > MHLEN) { 892 MCLGET(m, M_DONTWAIT); 893 if ((m->m_flags & M_EXT) == 0) { 894 printf("%s: unable to allocate Tx " 895 "cluster\n", sc->sc_dev.dv_xname); 896 m_freem(m); 897 break; 898 } 899 } 900 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 901 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 902 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 903 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 904 if (error) { 905 printf("%s: unable to load Tx buffer, " 906 "error = %d\n", sc->sc_dev.dv_xname, error); 907 break; 908 } 909 } 910 911 IFQ_DEQUEUE(&ifp->if_snd, m0); 912 if (m != NULL) { 913 m_freem(m0); 914 m0 = m; 915 } 916 917 /* Initialize the fraglist. */ 918 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 919 txd->txd_tbd[seg].tb_addr = 920 htole32(dmamap->dm_segs[seg].ds_addr); 921 txd->txd_tbd[seg].tb_size = 922 htole32(dmamap->dm_segs[seg].ds_len); 923 } 924 925 /* Sync the DMA map. */ 926 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 927 BUS_DMASYNC_PREWRITE); 928 929 /* 930 * Store a pointer to the packet so we can free it later. 931 */ 932 txs->txs_mbuf = m0; 933 934 /* 935 * Initialize the transmit descriptor. 936 */ 937 /* BIG_ENDIAN: no need to swap to store 0 */ 938 txd->txd_txcb.cb_status = 0; 939 txd->txd_txcb.cb_command = 940 htole16(FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF); 941 txd->txd_txcb.tx_threshold = tx_threshold; 942 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 943 944 FXP_CDTXSYNC(sc, nexttx, 945 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 946 947 /* Advance the tx pointer. */ 948 sc->sc_txpending++; 949 sc->sc_txlast = nexttx; 950 951 #if NBPFILTER > 0 952 /* 953 * Pass packet to bpf if there is a listener. 954 */ 955 if (ifp->if_bpf) 956 bpf_mtap(ifp->if_bpf, m0); 957 #endif 958 } 959 960 if (sc->sc_txpending == FXP_NTXCB) { 961 /* No more slots; notify upper layer. */ 962 ifp->if_flags |= IFF_OACTIVE; 963 } 964 965 if (sc->sc_txpending != opending) { 966 /* 967 * We enqueued packets. If the transmitter was idle, 968 * reset the txdirty pointer. 969 */ 970 if (opending == 0) 971 sc->sc_txdirty = FXP_NEXTTX(lasttx); 972 973 /* 974 * Cause the chip to interrupt and suspend command 975 * processing once the last packet we've enqueued 976 * has been transmitted. 977 */ 978 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 979 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 980 FXP_CDTXSYNC(sc, sc->sc_txlast, 981 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 982 983 /* 984 * The entire packet chain is set up. Clear the suspend bit 985 * on the command prior to the first packet we set up. 986 */ 987 FXP_CDTXSYNC(sc, lasttx, 988 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 989 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 990 htole16(~FXP_CB_COMMAND_S); 991 FXP_CDTXSYNC(sc, lasttx, 992 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 993 994 /* 995 * Issue a Resume command in case the chip was suspended. 996 */ 997 fxp_scb_wait(sc); 998 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 999 1000 /* Set a watchdog timer in case the chip flakes out. */ 1001 ifp->if_timer = 5; 1002 } 1003 } 1004 1005 /* 1006 * Process interface interrupts. 1007 */ 1008 int 1009 fxp_intr(void *arg) 1010 { 1011 struct fxp_softc *sc = arg; 1012 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1013 bus_dmamap_t rxmap; 1014 int claimed = 0; 1015 u_int8_t statack; 1016 1017 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1018 return (0); 1019 /* 1020 * If the interface isn't running, don't try to 1021 * service the interrupt.. just ack it and bail. 1022 */ 1023 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1024 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1025 if (statack) { 1026 claimed = 1; 1027 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1028 } 1029 return (claimed); 1030 } 1031 1032 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1033 claimed = 1; 1034 1035 /* 1036 * First ACK all the interrupts in this pass. 1037 */ 1038 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1039 1040 /* 1041 * Process receiver interrupts. If a no-resource (RNR) 1042 * condition exists, get whatever packets we can and 1043 * re-start the receiver. 1044 */ 1045 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1046 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1047 fxp_rxintr(sc); 1048 } 1049 1050 if (statack & FXP_SCB_STATACK_RNR) { 1051 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1052 fxp_scb_wait(sc); 1053 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1054 rxmap->dm_segs[0].ds_addr + 1055 RFA_ALIGNMENT_FUDGE); 1056 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1057 } 1058 1059 /* 1060 * Free any finished transmit mbuf chains. 1061 */ 1062 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1063 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1064 fxp_txintr(sc); 1065 1066 /* 1067 * Try to get more packets going. 1068 */ 1069 fxp_start(ifp); 1070 1071 if (sc->sc_txpending == 0) { 1072 /* 1073 * If we want a re-init, do that now. 1074 */ 1075 if (sc->sc_flags & FXPF_WANTINIT) 1076 (void) fxp_init(ifp); 1077 } 1078 } 1079 } 1080 1081 #if NRND > 0 1082 if (claimed) 1083 rnd_add_uint32(&sc->rnd_source, statack); 1084 #endif 1085 return (claimed); 1086 } 1087 1088 /* 1089 * Handle transmit completion interrupts. 1090 */ 1091 void 1092 fxp_txintr(struct fxp_softc *sc) 1093 { 1094 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1095 struct fxp_txdesc *txd; 1096 struct fxp_txsoft *txs; 1097 int i; 1098 u_int16_t txstat; 1099 1100 ifp->if_flags &= ~IFF_OACTIVE; 1101 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1102 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1103 txd = FXP_CDTX(sc, i); 1104 txs = FXP_DSTX(sc, i); 1105 1106 FXP_CDTXSYNC(sc, i, 1107 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1108 1109 txstat = le16toh(txd->txd_txcb.cb_status); 1110 1111 if ((txstat & FXP_CB_STATUS_C) == 0) 1112 break; 1113 1114 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1115 0, txs->txs_dmamap->dm_mapsize, 1116 BUS_DMASYNC_POSTWRITE); 1117 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1118 m_freem(txs->txs_mbuf); 1119 txs->txs_mbuf = NULL; 1120 } 1121 1122 /* Update the dirty transmit buffer pointer. */ 1123 sc->sc_txdirty = i; 1124 1125 /* 1126 * Cancel the watchdog timer if there are no pending 1127 * transmissions. 1128 */ 1129 if (sc->sc_txpending == 0) 1130 ifp->if_timer = 0; 1131 } 1132 1133 /* 1134 * Handle receive interrupts. 1135 */ 1136 void 1137 fxp_rxintr(struct fxp_softc *sc) 1138 { 1139 struct ethercom *ec = &sc->sc_ethercom; 1140 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1141 struct mbuf *m, *m0; 1142 bus_dmamap_t rxmap; 1143 struct fxp_rfa *rfa; 1144 u_int16_t len, rxstat; 1145 1146 for (;;) { 1147 m = sc->sc_rxq.ifq_head; 1148 rfa = FXP_MTORFA(m); 1149 rxmap = M_GETCTX(m, bus_dmamap_t); 1150 1151 FXP_RFASYNC(sc, m, 1152 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1153 1154 rxstat = le16toh(rfa->rfa_status); 1155 1156 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1157 /* 1158 * We have processed all of the 1159 * receive buffers. 1160 */ 1161 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1162 return; 1163 } 1164 1165 IF_DEQUEUE(&sc->sc_rxq, m); 1166 1167 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1168 1169 len = le16toh(rfa->actual_size) & 1170 (m->m_ext.ext_size - 1); 1171 1172 if (len < sizeof(struct ether_header)) { 1173 /* 1174 * Runt packet; drop it now. 1175 */ 1176 FXP_INIT_RFABUF(sc, m); 1177 continue; 1178 } 1179 1180 /* 1181 * If support for 802.1Q VLAN sized frames is 1182 * enabled, we need to do some additional error 1183 * checking (as we are saving bad frames, in 1184 * order to receive the larger ones). 1185 */ 1186 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1187 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1188 FXP_RFA_STATUS_RNR| 1189 FXP_RFA_STATUS_ALIGN| 1190 FXP_RFA_STATUS_CRC)) != 0) { 1191 FXP_INIT_RFABUF(sc, m); 1192 continue; 1193 } 1194 1195 /* 1196 * If the packet is small enough to fit in a 1197 * single header mbuf, allocate one and copy 1198 * the data into it. This greatly reduces 1199 * memory consumption when we receive lots 1200 * of small packets. 1201 * 1202 * Otherwise, we add a new buffer to the receive 1203 * chain. If this fails, we drop the packet and 1204 * recycle the old buffer. 1205 */ 1206 if (fxp_copy_small != 0 && len <= MHLEN) { 1207 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1208 if (m0 == NULL) 1209 goto dropit; 1210 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1211 memcpy(mtod(m0, caddr_t), 1212 mtod(m, caddr_t), len); 1213 FXP_INIT_RFABUF(sc, m); 1214 m = m0; 1215 } else { 1216 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1217 dropit: 1218 ifp->if_ierrors++; 1219 FXP_INIT_RFABUF(sc, m); 1220 continue; 1221 } 1222 } 1223 1224 m->m_pkthdr.rcvif = ifp; 1225 m->m_pkthdr.len = m->m_len = len; 1226 1227 #if NBPFILTER > 0 1228 /* 1229 * Pass this up to any BPF listeners, but only 1230 * pass it up the stack it its for us. 1231 */ 1232 if (ifp->if_bpf) 1233 bpf_mtap(ifp->if_bpf, m); 1234 #endif 1235 1236 /* Pass it on. */ 1237 (*ifp->if_input)(ifp, m); 1238 } 1239 } 1240 1241 /* 1242 * Update packet in/out/collision statistics. The i82557 doesn't 1243 * allow you to access these counters without doing a fairly 1244 * expensive DMA to get _all_ of the statistics it maintains, so 1245 * we do this operation here only once per second. The statistics 1246 * counters in the kernel are updated from the previous dump-stats 1247 * DMA and then a new dump-stats DMA is started. The on-chip 1248 * counters are zeroed when the DMA completes. If we can't start 1249 * the DMA immediately, we don't wait - we just prepare to read 1250 * them again next time. 1251 */ 1252 void 1253 fxp_tick(void *arg) 1254 { 1255 struct fxp_softc *sc = arg; 1256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1257 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1258 int s; 1259 1260 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1261 return; 1262 1263 s = splnet(); 1264 1265 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1266 1267 ifp->if_opackets += le32toh(sp->tx_good); 1268 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1269 if (sp->rx_good) { 1270 ifp->if_ipackets += le32toh(sp->rx_good); 1271 sc->sc_rxidle = 0; 1272 } else { 1273 sc->sc_rxidle++; 1274 } 1275 ifp->if_ierrors += 1276 le32toh(sp->rx_crc_errors) + 1277 le32toh(sp->rx_alignment_errors) + 1278 le32toh(sp->rx_rnr_errors) + 1279 le32toh(sp->rx_overrun_errors); 1280 /* 1281 * If any transmit underruns occurred, bump up the transmit 1282 * threshold by another 512 bytes (64 * 8). 1283 */ 1284 if (sp->tx_underruns) { 1285 ifp->if_oerrors += le32toh(sp->tx_underruns); 1286 if (tx_threshold < 192) 1287 tx_threshold += 64; 1288 } 1289 1290 /* 1291 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1292 * then assume the receiver has locked up and attempt to clear 1293 * the condition by reprogramming the multicast filter (actually, 1294 * resetting the interface). This is a work-around for a bug in 1295 * the 82557 where the receiver locks up if it gets certain types 1296 * of garbage in the synchronization bits prior to the packet header. 1297 * This bug is supposed to only occur in 10Mbps mode, but has been 1298 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1299 * speed transition). 1300 */ 1301 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1302 (void) fxp_init(ifp); 1303 splx(s); 1304 return; 1305 } 1306 /* 1307 * If there is no pending command, start another stats 1308 * dump. Otherwise punt for now. 1309 */ 1310 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1311 /* 1312 * Start another stats dump. 1313 */ 1314 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1315 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1316 } else { 1317 /* 1318 * A previous command is still waiting to be accepted. 1319 * Just zero our copy of the stats and wait for the 1320 * next timer event to update them. 1321 */ 1322 /* BIG_ENDIAN: no swap required to store 0 */ 1323 sp->tx_good = 0; 1324 sp->tx_underruns = 0; 1325 sp->tx_total_collisions = 0; 1326 1327 sp->rx_good = 0; 1328 sp->rx_crc_errors = 0; 1329 sp->rx_alignment_errors = 0; 1330 sp->rx_rnr_errors = 0; 1331 sp->rx_overrun_errors = 0; 1332 } 1333 1334 if (sc->sc_flags & FXPF_MII) { 1335 /* Tick the MII clock. */ 1336 mii_tick(&sc->sc_mii); 1337 } 1338 1339 splx(s); 1340 1341 /* 1342 * Schedule another timeout one second from now. 1343 */ 1344 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1345 } 1346 1347 /* 1348 * Drain the receive queue. 1349 */ 1350 void 1351 fxp_rxdrain(struct fxp_softc *sc) 1352 { 1353 bus_dmamap_t rxmap; 1354 struct mbuf *m; 1355 1356 for (;;) { 1357 IF_DEQUEUE(&sc->sc_rxq, m); 1358 if (m == NULL) 1359 break; 1360 rxmap = M_GETCTX(m, bus_dmamap_t); 1361 bus_dmamap_unload(sc->sc_dmat, rxmap); 1362 FXP_RXMAP_PUT(sc, rxmap); 1363 m_freem(m); 1364 } 1365 } 1366 1367 /* 1368 * Stop the interface. Cancels the statistics updater and resets 1369 * the interface. 1370 */ 1371 void 1372 fxp_stop(struct ifnet *ifp, int disable) 1373 { 1374 struct fxp_softc *sc = ifp->if_softc; 1375 struct fxp_txsoft *txs; 1376 int i; 1377 1378 /* 1379 * Turn down interface (done early to avoid bad interactions 1380 * between panics, shutdown hooks, and the watchdog timer) 1381 */ 1382 ifp->if_timer = 0; 1383 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1384 1385 /* 1386 * Cancel stats updater. 1387 */ 1388 callout_stop(&sc->sc_callout); 1389 if (sc->sc_flags & FXPF_MII) { 1390 /* Down the MII. */ 1391 mii_down(&sc->sc_mii); 1392 } 1393 1394 /* 1395 * Issue software reset. This unloads any microcode that 1396 * might already be loaded. 1397 */ 1398 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1399 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1400 DELAY(50); 1401 1402 /* 1403 * Release any xmit buffers. 1404 */ 1405 for (i = 0; i < FXP_NTXCB; i++) { 1406 txs = FXP_DSTX(sc, i); 1407 if (txs->txs_mbuf != NULL) { 1408 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1409 m_freem(txs->txs_mbuf); 1410 txs->txs_mbuf = NULL; 1411 } 1412 } 1413 sc->sc_txpending = 0; 1414 1415 if (disable) { 1416 fxp_rxdrain(sc); 1417 fxp_disable(sc); 1418 } 1419 1420 } 1421 1422 /* 1423 * Watchdog/transmission transmit timeout handler. Called when a 1424 * transmission is started on the interface, but no interrupt is 1425 * received before the timeout. This usually indicates that the 1426 * card has wedged for some reason. 1427 */ 1428 void 1429 fxp_watchdog(struct ifnet *ifp) 1430 { 1431 struct fxp_softc *sc = ifp->if_softc; 1432 1433 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1434 ifp->if_oerrors++; 1435 1436 (void) fxp_init(ifp); 1437 } 1438 1439 /* 1440 * Initialize the interface. Must be called at splnet(). 1441 */ 1442 int 1443 fxp_init(struct ifnet *ifp) 1444 { 1445 struct fxp_softc *sc = ifp->if_softc; 1446 struct fxp_cb_config *cbp; 1447 struct fxp_cb_ias *cb_ias; 1448 struct fxp_txdesc *txd; 1449 bus_dmamap_t rxmap; 1450 int i, prm, save_bf, lrxen, allm, error = 0; 1451 1452 if ((error = fxp_enable(sc)) != 0) 1453 goto out; 1454 1455 /* 1456 * Cancel any pending I/O 1457 */ 1458 fxp_stop(ifp, 0); 1459 1460 /* 1461 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1462 * flag, and this prevents the MII from detaching resulting in 1463 * a panic. The flags field should perhaps be split in runtime 1464 * flags and more static information. For now, just clear the 1465 * only other flag set. 1466 */ 1467 1468 sc->sc_flags &= ~FXPF_WANTINIT; 1469 1470 /* 1471 * Initialize base of CBL and RFA memory. Loading with zero 1472 * sets it up for regular linear addressing. 1473 */ 1474 fxp_scb_wait(sc); 1475 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1476 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1477 1478 fxp_scb_wait(sc); 1479 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1480 1481 /* 1482 * Initialize the multicast filter. Do this now, since we might 1483 * have to setup the config block differently. 1484 */ 1485 fxp_mc_setup(sc); 1486 1487 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1488 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1489 1490 /* 1491 * In order to support receiving 802.1Q VLAN frames, we have to 1492 * enable "save bad frames", since they are 4 bytes larger than 1493 * the normal Ethernet maximum frame length. On i82558 and later, 1494 * we have a better mechanism for this. 1495 */ 1496 save_bf = 0; 1497 lrxen = 0; 1498 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1499 if (sc->sc_rev < FXP_REV_82558_A4) 1500 save_bf = 1; 1501 else 1502 lrxen = 1; 1503 } 1504 1505 /* 1506 * Initialize base of dump-stats buffer. 1507 */ 1508 fxp_scb_wait(sc); 1509 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1510 sc->sc_cddma + FXP_CDSTATSOFF); 1511 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1512 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1513 1514 cbp = &sc->sc_control_data->fcd_configcb; 1515 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1516 1517 /* 1518 * Load microcode for this controller. 1519 */ 1520 fxp_load_ucode(sc); 1521 1522 /* 1523 * This copy is kind of disgusting, but there are a bunch of must be 1524 * zero and must be one bits in this structure and this is the easiest 1525 * way to initialize them all to proper values. 1526 */ 1527 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1528 1529 /* BIG_ENDIAN: no need to swap to store 0 */ 1530 cbp->cb_status = 0; 1531 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1532 FXP_CB_COMMAND_EL); 1533 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1534 cbp->link_addr = 0xffffffff; /* (no) next command */ 1535 /* bytes in config block */ 1536 cbp->byte_count = FXP_CONFIG_LEN; 1537 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1538 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1539 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1540 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1541 cbp->type_enable = 0; /* actually reserved */ 1542 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1543 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1544 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1545 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1546 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1547 cbp->late_scb = 0; /* (don't) defer SCB update */ 1548 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1549 cbp->ci_int = 1; /* interrupt on CU idle */ 1550 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1551 cbp->ext_stats_dis = 1; /* disable extended counters */ 1552 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1553 cbp->save_bf = save_bf;/* save bad frames */ 1554 cbp->disc_short_rx = !prm; /* discard short packets */ 1555 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1556 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1557 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1558 /* interface mode */ 1559 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1560 cbp->csma_dis = 0; /* (don't) disable link */ 1561 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1562 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1563 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1564 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1565 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1566 cbp->nsai = 1; /* (don't) disable source addr insert */ 1567 cbp->preamble_length = 2; /* (7 byte) preamble */ 1568 cbp->loopback = 0; /* (don't) loopback */ 1569 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1570 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1571 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1572 cbp->promiscuous = prm; /* promiscuous mode */ 1573 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1574 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1575 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1576 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1577 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1578 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1579 cbp->padding = 1; /* (do) pad short tx packets */ 1580 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1581 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1582 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1583 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1584 /* must set wake_en in PMCSR also */ 1585 cbp->force_fdx = 0; /* (don't) force full duplex */ 1586 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1587 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1588 cbp->mc_all = allm; /* accept all multicasts */ 1589 1590 if (sc->sc_rev < FXP_REV_82558_A4) { 1591 /* 1592 * The i82557 has no hardware flow control, the values 1593 * here are the defaults for the chip. 1594 */ 1595 cbp->fc_delay_lsb = 0; 1596 cbp->fc_delay_msb = 0x40; 1597 cbp->pri_fc_thresh = 3; 1598 cbp->tx_fc_dis = 0; 1599 cbp->rx_fc_restop = 0; 1600 cbp->rx_fc_restart = 0; 1601 cbp->fc_filter = 0; 1602 cbp->pri_fc_loc = 1; 1603 } else { 1604 cbp->fc_delay_lsb = 0x1f; 1605 cbp->fc_delay_msb = 0x01; 1606 cbp->pri_fc_thresh = 3; 1607 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1608 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1609 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1610 cbp->fc_filter = !prm; /* drop FC frames to host */ 1611 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1612 } 1613 1614 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1615 1616 /* 1617 * Start the config command/DMA. 1618 */ 1619 fxp_scb_wait(sc); 1620 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1621 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1622 /* ...and wait for it to complete. */ 1623 i = 1000; 1624 do { 1625 FXP_CDCONFIGSYNC(sc, 1626 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1627 DELAY(1); 1628 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1629 if (i == 0) { 1630 printf("%s at line %d: dmasync timeout\n", 1631 sc->sc_dev.dv_xname, __LINE__); 1632 return (ETIMEDOUT); 1633 } 1634 1635 /* 1636 * Initialize the station address. 1637 */ 1638 cb_ias = &sc->sc_control_data->fcd_iascb; 1639 /* BIG_ENDIAN: no need to swap to store 0 */ 1640 cb_ias->cb_status = 0; 1641 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1642 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1643 cb_ias->link_addr = 0xffffffff; 1644 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1645 1646 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1647 1648 /* 1649 * Start the IAS (Individual Address Setup) command/DMA. 1650 */ 1651 fxp_scb_wait(sc); 1652 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1653 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1654 /* ...and wait for it to complete. */ 1655 i = 1000; 1656 do { 1657 FXP_CDIASSYNC(sc, 1658 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1659 DELAY(1); 1660 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1661 if (i == 0) { 1662 printf("%s at line %d: dmasync timeout\n", 1663 sc->sc_dev.dv_xname, __LINE__); 1664 return (ETIMEDOUT); 1665 } 1666 1667 /* 1668 * Initialize the transmit descriptor ring. txlast is initialized 1669 * to the end of the list so that it will wrap around to the first 1670 * descriptor when the first packet is transmitted. 1671 */ 1672 for (i = 0; i < FXP_NTXCB; i++) { 1673 txd = FXP_CDTX(sc, i); 1674 memset(txd, 0, sizeof(*txd)); 1675 txd->txd_txcb.cb_command = 1676 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1677 txd->txd_txcb.link_addr = 1678 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1679 if (sc->sc_flags & FXPF_EXT_TXCB) 1680 txd->txd_txcb.tbd_array_addr = 1681 htole32(FXP_CDTBDADDR(sc, i) + 1682 (2 * sizeof(struct fxp_tbd))); 1683 else 1684 txd->txd_txcb.tbd_array_addr = 1685 htole32(FXP_CDTBDADDR(sc, i)); 1686 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1687 } 1688 sc->sc_txpending = 0; 1689 sc->sc_txdirty = 0; 1690 sc->sc_txlast = FXP_NTXCB - 1; 1691 1692 /* 1693 * Initialize the receive buffer list. 1694 */ 1695 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1696 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1697 rxmap = FXP_RXMAP_GET(sc); 1698 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1699 printf("%s: unable to allocate or map rx " 1700 "buffer %d, error = %d\n", 1701 sc->sc_dev.dv_xname, 1702 sc->sc_rxq.ifq_len, error); 1703 /* 1704 * XXX Should attempt to run with fewer receive 1705 * XXX buffers instead of just failing. 1706 */ 1707 FXP_RXMAP_PUT(sc, rxmap); 1708 fxp_rxdrain(sc); 1709 goto out; 1710 } 1711 } 1712 sc->sc_rxidle = 0; 1713 1714 /* 1715 * Give the transmit ring to the chip. We do this by pointing 1716 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1717 * issuing a start command. It will execute the NOP and then 1718 * suspend, pointing at the first descriptor. 1719 */ 1720 fxp_scb_wait(sc); 1721 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1722 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1723 1724 /* 1725 * Initialize receiver buffer area - RFA. 1726 */ 1727 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1728 fxp_scb_wait(sc); 1729 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1730 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1731 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1732 1733 if (sc->sc_flags & FXPF_MII) { 1734 /* 1735 * Set current media. 1736 */ 1737 mii_mediachg(&sc->sc_mii); 1738 } 1739 1740 /* 1741 * ...all done! 1742 */ 1743 ifp->if_flags |= IFF_RUNNING; 1744 ifp->if_flags &= ~IFF_OACTIVE; 1745 1746 /* 1747 * Start the one second timer. 1748 */ 1749 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1750 1751 /* 1752 * Attempt to start output on the interface. 1753 */ 1754 fxp_start(ifp); 1755 1756 out: 1757 if (error) { 1758 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1759 ifp->if_timer = 0; 1760 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1761 } 1762 return (error); 1763 } 1764 1765 /* 1766 * Change media according to request. 1767 */ 1768 int 1769 fxp_mii_mediachange(struct ifnet *ifp) 1770 { 1771 struct fxp_softc *sc = ifp->if_softc; 1772 1773 if (ifp->if_flags & IFF_UP) 1774 mii_mediachg(&sc->sc_mii); 1775 return (0); 1776 } 1777 1778 /* 1779 * Notify the world which media we're using. 1780 */ 1781 void 1782 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1783 { 1784 struct fxp_softc *sc = ifp->if_softc; 1785 1786 if (sc->sc_enabled == 0) { 1787 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1788 ifmr->ifm_status = 0; 1789 return; 1790 } 1791 1792 mii_pollstat(&sc->sc_mii); 1793 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1794 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1795 } 1796 1797 int 1798 fxp_80c24_mediachange(struct ifnet *ifp) 1799 { 1800 1801 /* Nothing to do here. */ 1802 return (0); 1803 } 1804 1805 void 1806 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1807 { 1808 struct fxp_softc *sc = ifp->if_softc; 1809 1810 /* 1811 * Media is currently-selected media. We cannot determine 1812 * the link status. 1813 */ 1814 ifmr->ifm_status = 0; 1815 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1816 } 1817 1818 /* 1819 * Add a buffer to the end of the RFA buffer list. 1820 * Return 0 if successful, error code on failure. 1821 * 1822 * The RFA struct is stuck at the beginning of mbuf cluster and the 1823 * data pointer is fixed up to point just past it. 1824 */ 1825 int 1826 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1827 { 1828 struct mbuf *m; 1829 int error; 1830 1831 MGETHDR(m, M_DONTWAIT, MT_DATA); 1832 if (m == NULL) 1833 return (ENOBUFS); 1834 1835 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1836 MCLGET(m, M_DONTWAIT); 1837 if ((m->m_flags & M_EXT) == 0) { 1838 m_freem(m); 1839 return (ENOBUFS); 1840 } 1841 1842 if (unload) 1843 bus_dmamap_unload(sc->sc_dmat, rxmap); 1844 1845 M_SETCTX(m, rxmap); 1846 1847 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1848 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 1849 BUS_DMA_READ|BUS_DMA_NOWAIT); 1850 if (error) { 1851 printf("%s: can't load rx DMA map %d, error = %d\n", 1852 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1853 panic("fxp_add_rfabuf"); /* XXX */ 1854 } 1855 1856 FXP_INIT_RFABUF(sc, m); 1857 1858 return (0); 1859 } 1860 1861 int 1862 fxp_mdi_read(struct device *self, int phy, int reg) 1863 { 1864 struct fxp_softc *sc = (struct fxp_softc *)self; 1865 int count = 10000; 1866 int value; 1867 1868 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1869 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1870 1871 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 1872 0x10000000) == 0 && count--) 1873 DELAY(10); 1874 1875 if (count <= 0) 1876 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1877 1878 return (value & 0xffff); 1879 } 1880 1881 void 1882 fxp_statchg(struct device *self) 1883 { 1884 1885 /* Nothing to do. */ 1886 } 1887 1888 void 1889 fxp_mdi_write(struct device *self, int phy, int reg, int value) 1890 { 1891 struct fxp_softc *sc = (struct fxp_softc *)self; 1892 int count = 10000; 1893 1894 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1895 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1896 (value & 0xffff)); 1897 1898 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1899 count--) 1900 DELAY(10); 1901 1902 if (count <= 0) 1903 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 1904 } 1905 1906 int 1907 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1908 { 1909 struct fxp_softc *sc = ifp->if_softc; 1910 struct ifreq *ifr = (struct ifreq *)data; 1911 int s, error; 1912 1913 s = splnet(); 1914 1915 switch (cmd) { 1916 case SIOCSIFMEDIA: 1917 case SIOCGIFMEDIA: 1918 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1919 break; 1920 1921 default: 1922 error = ether_ioctl(ifp, cmd, data); 1923 if (error == ENETRESET) { 1924 if (sc->sc_enabled) { 1925 /* 1926 * Multicast list has changed; set the 1927 * hardware filter accordingly. 1928 */ 1929 if (sc->sc_txpending) { 1930 sc->sc_flags |= FXPF_WANTINIT; 1931 error = 0; 1932 } else 1933 error = fxp_init(ifp); 1934 } else 1935 error = 0; 1936 } 1937 break; 1938 } 1939 1940 /* Try to get more packets going. */ 1941 if (sc->sc_enabled) 1942 fxp_start(ifp); 1943 1944 splx(s); 1945 return (error); 1946 } 1947 1948 /* 1949 * Program the multicast filter. 1950 * 1951 * This function must be called at splnet(). 1952 */ 1953 void 1954 fxp_mc_setup(struct fxp_softc *sc) 1955 { 1956 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 1957 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1958 struct ethercom *ec = &sc->sc_ethercom; 1959 struct ether_multi *enm; 1960 struct ether_multistep step; 1961 int count, nmcasts; 1962 1963 #ifdef DIAGNOSTIC 1964 if (sc->sc_txpending) 1965 panic("fxp_mc_setup: pending transmissions"); 1966 #endif 1967 1968 ifp->if_flags &= ~IFF_ALLMULTI; 1969 1970 /* 1971 * Initialize multicast setup descriptor. 1972 */ 1973 nmcasts = 0; 1974 ETHER_FIRST_MULTI(step, ec, enm); 1975 while (enm != NULL) { 1976 /* 1977 * Check for too many multicast addresses or if we're 1978 * listening to a range. Either way, we simply have 1979 * to accept all multicasts. 1980 */ 1981 if (nmcasts >= MAXMCADDR || 1982 memcmp(enm->enm_addrlo, enm->enm_addrhi, 1983 ETHER_ADDR_LEN) != 0) { 1984 /* 1985 * Callers of this function must do the 1986 * right thing with this. If we're called 1987 * from outside fxp_init(), the caller must 1988 * detect if the state if IFF_ALLMULTI changes. 1989 * If it does, the caller must then call 1990 * fxp_init(), since allmulti is handled by 1991 * the config block. 1992 */ 1993 ifp->if_flags |= IFF_ALLMULTI; 1994 return; 1995 } 1996 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 1997 ETHER_ADDR_LEN); 1998 nmcasts++; 1999 ETHER_NEXT_MULTI(step, enm); 2000 } 2001 2002 /* BIG_ENDIAN: no need to swap to store 0 */ 2003 mcsp->cb_status = 0; 2004 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2005 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2006 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2007 2008 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2009 2010 /* 2011 * Wait until the command unit is not active. This should never 2012 * happen since nothing is queued, but make sure anyway. 2013 */ 2014 count = 100; 2015 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2016 FXP_SCB_CUS_ACTIVE && --count) 2017 DELAY(1); 2018 if (count == 0) { 2019 printf("%s at line %d: command queue timeout\n", 2020 sc->sc_dev.dv_xname, __LINE__); 2021 return; 2022 } 2023 2024 /* 2025 * Start the multicast setup command/DMA. 2026 */ 2027 fxp_scb_wait(sc); 2028 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2029 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2030 2031 /* ...and wait for it to complete. */ 2032 count = 1000; 2033 do { 2034 FXP_CDMCSSYNC(sc, 2035 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2036 DELAY(1); 2037 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2038 if (count == 0) { 2039 printf("%s at line %d: dmasync timeout\n", 2040 sc->sc_dev.dv_xname, __LINE__); 2041 return; 2042 } 2043 } 2044 2045 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2046 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2047 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2048 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2049 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2050 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2051 2052 #define UCODE(x) x, sizeof(x) 2053 2054 static const struct ucode { 2055 int32_t revision; 2056 const uint32_t *ucode; 2057 size_t length; 2058 uint16_t int_delay_offset; 2059 uint16_t bundle_max_offset; 2060 } ucode_table[] = { 2061 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2062 D101_CPUSAVER_DWORD, 0 }, 2063 2064 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2065 D101_CPUSAVER_DWORD, 0 }, 2066 2067 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2068 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2069 2070 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2071 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2072 2073 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2074 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2075 2076 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2077 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2078 2079 { 0, NULL, 0, 0, 0 } 2080 }; 2081 2082 void 2083 fxp_load_ucode(struct fxp_softc *sc) 2084 { 2085 const struct ucode *uc; 2086 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2087 int count; 2088 2089 if (sc->sc_flags & FXPF_UCODE_LOADED) 2090 return; 2091 2092 /* 2093 * Only load the uCode if the user has requested that 2094 * we do so. 2095 */ 2096 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2097 sc->sc_int_delay = 0; 2098 sc->sc_bundle_max = 0; 2099 return; 2100 } 2101 2102 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2103 if (sc->sc_rev == uc->revision) 2104 break; 2105 } 2106 if (uc->ucode == NULL) 2107 return; 2108 2109 /* BIG ENDIAN: no need to swap to store 0 */ 2110 cbp->cb_status = 0; 2111 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2112 cbp->link_addr = 0xffffffff; /* (no) next command */ 2113 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2114 2115 if (uc->int_delay_offset) 2116 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2117 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2118 2119 if (uc->bundle_max_offset) 2120 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2121 htole16(fxp_bundle_max); 2122 2123 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2124 2125 /* 2126 * Download the uCode to the chip. 2127 */ 2128 fxp_scb_wait(sc); 2129 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2130 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2131 2132 /* ...and wait for it to complete. */ 2133 count = 10000; 2134 do { 2135 FXP_CDUCODESYNC(sc, 2136 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2137 DELAY(2); 2138 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2139 if (count == 0) { 2140 sc->sc_int_delay = 0; 2141 sc->sc_bundle_max = 0; 2142 printf("%s: timeout loading microcode\n", 2143 sc->sc_dev.dv_xname); 2144 return; 2145 } 2146 2147 if (sc->sc_int_delay != fxp_int_delay || 2148 sc->sc_bundle_max != fxp_bundle_max) { 2149 sc->sc_int_delay = fxp_int_delay; 2150 sc->sc_bundle_max = fxp_bundle_max; 2151 printf("%s: Microcode loaded: int delay: %d usec, " 2152 "max bundle: %d\n", sc->sc_dev.dv_xname, 2153 sc->sc_int_delay, 2154 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2155 } 2156 2157 sc->sc_flags |= FXPF_UCODE_LOADED; 2158 } 2159 2160 int 2161 fxp_enable(struct fxp_softc *sc) 2162 { 2163 2164 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2165 if ((*sc->sc_enable)(sc) != 0) { 2166 printf("%s: device enable failed\n", 2167 sc->sc_dev.dv_xname); 2168 return (EIO); 2169 } 2170 } 2171 2172 sc->sc_enabled = 1; 2173 return (0); 2174 } 2175 2176 void 2177 fxp_disable(struct fxp_softc *sc) 2178 { 2179 2180 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2181 (*sc->sc_disable)(sc); 2182 sc->sc_enabled = 0; 2183 } 2184 } 2185 2186 /* 2187 * fxp_activate: 2188 * 2189 * Handle device activation/deactivation requests. 2190 */ 2191 int 2192 fxp_activate(struct device *self, enum devact act) 2193 { 2194 struct fxp_softc *sc = (void *) self; 2195 int s, error = 0; 2196 2197 s = splnet(); 2198 switch (act) { 2199 case DVACT_ACTIVATE: 2200 error = EOPNOTSUPP; 2201 break; 2202 2203 case DVACT_DEACTIVATE: 2204 if (sc->sc_flags & FXPF_MII) 2205 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2206 MII_OFFSET_ANY); 2207 if_deactivate(&sc->sc_ethercom.ec_if); 2208 break; 2209 } 2210 splx(s); 2211 2212 return (error); 2213 } 2214 2215 /* 2216 * fxp_detach: 2217 * 2218 * Detach an i82557 interface. 2219 */ 2220 int 2221 fxp_detach(struct fxp_softc *sc) 2222 { 2223 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2224 int i; 2225 2226 /* Succeed now if there's no work to do. */ 2227 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2228 return (0); 2229 2230 /* Unhook our tick handler. */ 2231 callout_stop(&sc->sc_callout); 2232 2233 if (sc->sc_flags & FXPF_MII) { 2234 /* Detach all PHYs */ 2235 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2236 } 2237 2238 /* Delete all remaining media. */ 2239 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2240 2241 #if NRND > 0 2242 rnd_detach_source(&sc->rnd_source); 2243 #endif 2244 ether_ifdetach(ifp); 2245 if_detach(ifp); 2246 2247 for (i = 0; i < FXP_NRFABUFS; i++) { 2248 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2249 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2250 } 2251 2252 for (i = 0; i < FXP_NTXCB; i++) { 2253 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2254 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2255 } 2256 2257 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2258 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2259 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2260 sizeof(struct fxp_control_data)); 2261 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2262 2263 shutdownhook_disestablish(sc->sc_sdhook); 2264 powerhook_disestablish(sc->sc_powerhook); 2265 2266 return (0); 2267 } 2268
Indexes created Tue Sep 30 20:09:53 GMT 2025