i82557.c revision 1.75
1 /* $NetBSD: i82557.c,v 1.75 2003/05/26 16:14:49 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 1999, 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, David Greenman 42 * Copyright (c) 2001 Jonathan Lemon <jlemon (at) freebsd.org> 43 * All rights reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice unmodified, this list of conditions, and the following 50 * disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * Id: if_fxp.c,v 1.113 2001/05/17 23:50:24 jlemon 68 */ 69 70 /* 71 * Device driver for the Intel i82557 fast Ethernet controller, 72 * and its successors, the i82558 and i82559. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.75 2003/05/26 16:14:49 yamt Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 92 #include <machine/endian.h> 93 94 #include <uvm/uvm_extern.h> 95 96 #if NRND > 0 97 #include <sys/rnd.h> 98 #endif 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 112 #include <dev/mii/miivar.h> 113 114 #include <dev/ic/i82557reg.h> 115 #include <dev/ic/i82557var.h> 116 117 #include <dev/microcode/i8255x/rcvbundl.h> 118 119 /* 120 * NOTE! On the Alpha, we have an alignment constraint. The 121 * card DMAs the packet immediately following the RFA. However, 122 * the first thing in the packet is a 14-byte Ethernet header. 123 * This means that the packet is misaligned. To compensate, 124 * we actually offset the RFA 2 bytes into the cluster. This 125 * alignes the packet after the Ethernet header at a 32-bit 126 * boundary. HOWEVER! This means that the RFA is misaligned! 127 */ 128 #define RFA_ALIGNMENT_FUDGE 2 129 130 /* 131 * The configuration byte map has several undefined fields which 132 * must be one or must be zero. Set up a template for these bits 133 * only (assuming an i82557 chip), leaving the actual configuration 134 * for fxp_init(). 135 * 136 * See the definition of struct fxp_cb_config for the bit definitions. 137 */ 138 const u_int8_t fxp_cb_config_template[] = { 139 0x0, 0x0, /* cb_status */ 140 0x0, 0x0, /* cb_command */ 141 0x0, 0x0, 0x0, 0x0, /* link_addr */ 142 0x0, /* 0 */ 143 0x0, /* 1 */ 144 0x0, /* 2 */ 145 0x0, /* 3 */ 146 0x0, /* 4 */ 147 0x0, /* 5 */ 148 0x32, /* 6 */ 149 0x0, /* 7 */ 150 0x0, /* 8 */ 151 0x0, /* 9 */ 152 0x6, /* 10 */ 153 0x0, /* 11 */ 154 0x0, /* 12 */ 155 0x0, /* 13 */ 156 0xf2, /* 14 */ 157 0x48, /* 15 */ 158 0x0, /* 16 */ 159 0x40, /* 17 */ 160 0xf0, /* 18 */ 161 0x0, /* 19 */ 162 0x3f, /* 20 */ 163 0x5, /* 21 */ 164 0x0, /* 22 */ 165 0x0, /* 23 */ 166 0x0, /* 24 */ 167 0x0, /* 25 */ 168 0x0, /* 26 */ 169 0x0, /* 27 */ 170 0x0, /* 28 */ 171 0x0, /* 29 */ 172 0x0, /* 30 */ 173 0x0, /* 31 */ 174 }; 175 176 void fxp_mii_initmedia(struct fxp_softc *); 177 int fxp_mii_mediachange(struct ifnet *); 178 void fxp_mii_mediastatus(struct ifnet *, struct ifmediareq *); 179 180 void fxp_80c24_initmedia(struct fxp_softc *); 181 int fxp_80c24_mediachange(struct ifnet *); 182 void fxp_80c24_mediastatus(struct ifnet *, struct ifmediareq *); 183 184 void fxp_start(struct ifnet *); 185 int fxp_ioctl(struct ifnet *, u_long, caddr_t); 186 void fxp_watchdog(struct ifnet *); 187 int fxp_init(struct ifnet *); 188 void fxp_stop(struct ifnet *, int); 189 190 void fxp_txintr(struct fxp_softc *); 191 void fxp_rxintr(struct fxp_softc *); 192 193 void fxp_rx_hwcksum(struct mbuf *, const struct fxp_rfa *); 194 195 void fxp_rxdrain(struct fxp_softc *); 196 int fxp_add_rfabuf(struct fxp_softc *, bus_dmamap_t, int); 197 int fxp_mdi_read(struct device *, int, int); 198 void fxp_statchg(struct device *); 199 void fxp_mdi_write(struct device *, int, int, int); 200 void fxp_autosize_eeprom(struct fxp_softc*); 201 void fxp_read_eeprom(struct fxp_softc *, u_int16_t *, int, int); 202 void fxp_write_eeprom(struct fxp_softc *, u_int16_t *, int, int); 203 void fxp_eeprom_update_cksum(struct fxp_softc *); 204 void fxp_get_info(struct fxp_softc *, u_int8_t *); 205 void fxp_tick(void *); 206 void fxp_mc_setup(struct fxp_softc *); 207 void fxp_load_ucode(struct fxp_softc *); 208 209 void fxp_shutdown(void *); 210 void fxp_power(int, void *); 211 212 int fxp_copy_small = 0; 213 214 /* 215 * Variables for interrupt mitigating microcode. 216 */ 217 int fxp_int_delay = 1000; /* usec */ 218 int fxp_bundle_max = 6; /* packets */ 219 220 struct fxp_phytype { 221 int fp_phy; /* type of PHY, -1 for MII at the end. */ 222 void (*fp_init)(struct fxp_softc *); 223 } fxp_phytype_table[] = { 224 { FXP_PHY_80C24, fxp_80c24_initmedia }, 225 { -1, fxp_mii_initmedia }, 226 }; 227 228 /* 229 * Set initial transmit threshold at 64 (512 bytes). This is 230 * increased by 64 (512 bytes) at a time, to maximum of 192 231 * (1536 bytes), if an underrun occurs. 232 */ 233 static int tx_threshold = 64; 234 235 /* 236 * Wait for the previous command to be accepted (but not necessarily 237 * completed). 238 */ 239 static __inline void 240 fxp_scb_wait(struct fxp_softc *sc) 241 { 242 int i = 10000; 243 244 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 245 delay(2); 246 if (i == 0) 247 printf("%s: WARNING: SCB timed out!\n", sc->sc_dev.dv_xname); 248 } 249 250 /* 251 * Submit a command to the i82557. 252 */ 253 static __inline void 254 fxp_scb_cmd(struct fxp_softc *sc, u_int8_t cmd) 255 { 256 257 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 258 } 259 260 /* 261 * Finish attaching an i82557 interface. Called by bus-specific front-end. 262 */ 263 void 264 fxp_attach(struct fxp_softc *sc) 265 { 266 u_int8_t enaddr[ETHER_ADDR_LEN]; 267 struct ifnet *ifp; 268 bus_dma_segment_t seg; 269 int rseg, i, error; 270 struct fxp_phytype *fp; 271 272 callout_init(&sc->sc_callout); 273 274 /* 275 * Enable some good stuff on i82558 and later. 276 */ 277 if (sc->sc_rev >= FXP_REV_82558_A4) { 278 /* Enable the extended TxCB. */ 279 sc->sc_flags |= FXPF_EXT_TXCB; 280 } 281 282 /* 283 * Enable use of extended RFDs and TCBs for 82550 284 * and later chips. Note: we need extended TXCB support 285 * too, but that's already enabled by the code above. 286 * Be careful to do this only on the right devices. 287 */ 288 if (sc->sc_rev == FXP_REV_82550 || sc->sc_rev == FXP_REV_82550_C) { 289 sc->sc_flags |= FXPF_EXT_RFA | FXPF_IPCB; 290 sc->sc_txcmd = htole16(FXP_CB_COMMAND_IPCBXMIT); 291 } else { 292 sc->sc_txcmd = htole16(FXP_CB_COMMAND_XMIT); 293 } 294 295 sc->sc_rfa_size = 296 (sc->sc_flags & FXPF_EXT_RFA) ? RFA_EXT_SIZE : RFA_SIZE; 297 298 /* 299 * Allocate the control data structures, and create and load the 300 * DMA map for it. 301 */ 302 if ((error = bus_dmamem_alloc(sc->sc_dmat, 303 sizeof(struct fxp_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 304 0)) != 0) { 305 aprint_error( 306 "%s: unable to allocate control data, error = %d\n", 307 sc->sc_dev.dv_xname, error); 308 goto fail_0; 309 } 310 311 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 312 sizeof(struct fxp_control_data), (caddr_t *)&sc->sc_control_data, 313 BUS_DMA_COHERENT)) != 0) { 314 aprint_error("%s: unable to map control data, error = %d\n", 315 sc->sc_dev.dv_xname, error); 316 goto fail_1; 317 } 318 sc->sc_cdseg = seg; 319 sc->sc_cdnseg = rseg; 320 321 memset(sc->sc_control_data, 0, sizeof(struct fxp_control_data)); 322 323 if ((error = bus_dmamap_create(sc->sc_dmat, 324 sizeof(struct fxp_control_data), 1, 325 sizeof(struct fxp_control_data), 0, 0, &sc->sc_dmamap)) != 0) { 326 aprint_error("%s: unable to create control data DMA map, " 327 "error = %d\n", sc->sc_dev.dv_xname, error); 328 goto fail_2; 329 } 330 331 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 332 sc->sc_control_data, sizeof(struct fxp_control_data), NULL, 333 0)) != 0) { 334 aprint_error( 335 "%s: can't load control data DMA map, error = %d\n", 336 sc->sc_dev.dv_xname, error); 337 goto fail_3; 338 } 339 340 /* 341 * Create the transmit buffer DMA maps. 342 */ 343 for (i = 0; i < FXP_NTXCB; i++) { 344 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 345 (sc->sc_flags & FXPF_IPCB) ? FXP_IPCB_NTXSEG : FXP_NTXSEG, 346 MCLBYTES, 0, 0, &FXP_DSTX(sc, i)->txs_dmamap)) != 0) { 347 aprint_error("%s: unable to create tx DMA map %d, " 348 "error = %d\n", sc->sc_dev.dv_xname, i, error); 349 goto fail_4; 350 } 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < FXP_NRFABUFS; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxmaps[i])) != 0) { 359 aprint_error("%s: unable to create rx DMA map %d, " 360 "error = %d\n", sc->sc_dev.dv_xname, i, error); 361 goto fail_5; 362 } 363 } 364 365 /* Initialize MAC address and media structures. */ 366 fxp_get_info(sc, enaddr); 367 368 aprint_normal("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 369 ether_sprintf(enaddr)); 370 371 ifp = &sc->sc_ethercom.ec_if; 372 373 /* 374 * Get info about our media interface, and initialize it. Note 375 * the table terminates itself with a phy of -1, indicating 376 * that we're using MII. 377 */ 378 for (fp = fxp_phytype_table; fp->fp_phy != -1; fp++) 379 if (fp->fp_phy == sc->phy_primary_device) 380 break; 381 (*fp->fp_init)(sc); 382 383 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 384 ifp->if_softc = sc; 385 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 386 ifp->if_ioctl = fxp_ioctl; 387 ifp->if_start = fxp_start; 388 ifp->if_watchdog = fxp_watchdog; 389 ifp->if_init = fxp_init; 390 ifp->if_stop = fxp_stop; 391 IFQ_SET_READY(&ifp->if_snd); 392 393 /* 394 * XXX we should have separate IFCAP flags for transmit and receive. 395 * XXX it isn't problem for this paticular driver, though. 396 */ 397 if (sc->sc_flags & FXPF_IPCB) { 398 KASSERT(sc->sc_flags & FXPF_EXT_RFA); /* we have both or none */ 399 ifp->if_capabilities = 400 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 401 } 402 403 /* 404 * We can support 802.1Q VLAN-sized frames. 405 */ 406 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 407 408 /* 409 * Attach the interface. 410 */ 411 if_attach(ifp); 412 ether_ifattach(ifp, enaddr); 413 #if NRND > 0 414 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 415 RND_TYPE_NET, 0); 416 #endif 417 418 #ifdef FXP_EVENT_COUNTERS 419 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 420 NULL, sc->sc_dev.dv_xname, "txstall"); 421 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 422 NULL, sc->sc_dev.dv_xname, "txintr"); 423 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 424 NULL, sc->sc_dev.dv_xname, "rxintr"); 425 #endif /* FXP_EVENT_COUNTERS */ 426 427 /* 428 * Add shutdown hook so that DMA is disabled prior to reboot. Not 429 * doing do could allow DMA to corrupt kernel memory during the 430 * reboot before the driver initializes. 431 */ 432 sc->sc_sdhook = shutdownhook_establish(fxp_shutdown, sc); 433 if (sc->sc_sdhook == NULL) 434 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 435 sc->sc_dev.dv_xname); 436 /* 437 * Add suspend hook, for similar reasons.. 438 */ 439 sc->sc_powerhook = powerhook_establish(fxp_power, sc); 440 if (sc->sc_powerhook == NULL) 441 aprint_error("%s: WARNING: unable to establish power hook\n", 442 sc->sc_dev.dv_xname); 443 444 /* The attach is successful. */ 445 sc->sc_flags |= FXPF_ATTACHED; 446 447 return; 448 449 /* 450 * Free any resources we've allocated during the failed attach 451 * attempt. Do this in reverse order and fall though. 452 */ 453 fail_5: 454 for (i = 0; i < FXP_NRFABUFS; i++) { 455 if (sc->sc_rxmaps[i] != NULL) 456 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 457 } 458 fail_4: 459 for (i = 0; i < FXP_NTXCB; i++) { 460 if (FXP_DSTX(sc, i)->txs_dmamap != NULL) 461 bus_dmamap_destroy(sc->sc_dmat, 462 FXP_DSTX(sc, i)->txs_dmamap); 463 } 464 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 465 fail_3: 466 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 467 fail_2: 468 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 469 sizeof(struct fxp_control_data)); 470 fail_1: 471 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 472 fail_0: 473 return; 474 } 475 476 void 477 fxp_mii_initmedia(struct fxp_softc *sc) 478 { 479 int flags; 480 481 sc->sc_flags |= FXPF_MII; 482 483 sc->sc_mii.mii_ifp = &sc->sc_ethercom.ec_if; 484 sc->sc_mii.mii_readreg = fxp_mdi_read; 485 sc->sc_mii.mii_writereg = fxp_mdi_write; 486 sc->sc_mii.mii_statchg = fxp_statchg; 487 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, fxp_mii_mediachange, 488 fxp_mii_mediastatus); 489 490 flags = MIIF_NOISOLATE; 491 if (sc->sc_rev >= FXP_REV_82558_A4) 492 flags |= MIIF_DOPAUSE; 493 /* 494 * The i82557 wedges if all of its PHYs are isolated! 495 */ 496 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 497 MII_OFFSET_ANY, flags); 498 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 499 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 500 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 501 } else 502 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 503 } 504 505 void 506 fxp_80c24_initmedia(struct fxp_softc *sc) 507 { 508 509 /* 510 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 511 * doesn't have a programming interface of any sort. The 512 * media is sensed automatically based on how the link partner 513 * is configured. This is, in essence, manual configuration. 514 */ 515 aprint_normal("%s: Seeq 80c24 AutoDUPLEX media interface present\n", 516 sc->sc_dev.dv_xname); 517 ifmedia_init(&sc->sc_mii.mii_media, 0, fxp_80c24_mediachange, 518 fxp_80c24_mediastatus); 519 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 520 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 521 } 522 523 /* 524 * Device shutdown routine. Called at system shutdown after sync. The 525 * main purpose of this routine is to shut off receiver DMA so that 526 * kernel memory doesn't get clobbered during warmboot. 527 */ 528 void 529 fxp_shutdown(void *arg) 530 { 531 struct fxp_softc *sc = arg; 532 533 /* 534 * Since the system's going to halt shortly, don't bother 535 * freeing mbufs. 536 */ 537 fxp_stop(&sc->sc_ethercom.ec_if, 0); 538 } 539 /* 540 * Power handler routine. Called when the system is transitioning 541 * into/out of power save modes. As with fxp_shutdown, the main 542 * purpose of this routine is to shut off receiver DMA so it doesn't 543 * clobber kernel memory at the wrong time. 544 */ 545 void 546 fxp_power(int why, void *arg) 547 { 548 struct fxp_softc *sc = arg; 549 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 550 int s; 551 552 s = splnet(); 553 switch (why) { 554 case PWR_SUSPEND: 555 case PWR_STANDBY: 556 fxp_stop(ifp, 0); 557 break; 558 case PWR_RESUME: 559 if (ifp->if_flags & IFF_UP) 560 fxp_init(ifp); 561 break; 562 case PWR_SOFTSUSPEND: 563 case PWR_SOFTSTANDBY: 564 case PWR_SOFTRESUME: 565 break; 566 } 567 splx(s); 568 } 569 570 /* 571 * Initialize the interface media. 572 */ 573 void 574 fxp_get_info(struct fxp_softc *sc, u_int8_t *enaddr) 575 { 576 u_int16_t data, myea[ETHER_ADDR_LEN / 2]; 577 578 /* 579 * Reset to a stable state. 580 */ 581 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 582 DELAY(10); 583 584 sc->sc_eeprom_size = 0; 585 fxp_autosize_eeprom(sc); 586 if (sc->sc_eeprom_size == 0) { 587 aprint_error("%s: failed to detect EEPROM size\n", 588 sc->sc_dev.dv_xname); 589 sc->sc_eeprom_size = 6; /* XXX panic here? */ 590 } 591 #ifdef DEBUG 592 aprint_debug("%s: detected %d word EEPROM\n", 593 sc->sc_dev.dv_xname, 1 << sc->sc_eeprom_size); 594 #endif 595 596 /* 597 * Get info about the primary PHY 598 */ 599 fxp_read_eeprom(sc, &data, 6, 1); 600 sc->phy_primary_device = 601 (data & FXP_PHY_DEVICE_MASK) >> FXP_PHY_DEVICE_SHIFT; 602 603 /* 604 * Read MAC address. 605 */ 606 fxp_read_eeprom(sc, myea, 0, 3); 607 enaddr[0] = myea[0] & 0xff; 608 enaddr[1] = myea[0] >> 8; 609 enaddr[2] = myea[1] & 0xff; 610 enaddr[3] = myea[1] >> 8; 611 enaddr[4] = myea[2] & 0xff; 612 enaddr[5] = myea[2] >> 8; 613 614 /* 615 * Systems based on the ICH2/ICH2-M chip from Intel, as well 616 * as some i82559 designs, have a defect where the chip can 617 * cause a PCI protocol violation if it receives a CU_RESUME 618 * command when it is entering the IDLE state. 619 * 620 * The work-around is to disable Dynamic Standby Mode, so that 621 * the chip never deasserts #CLKRUN, and always remains in the 622 * active state. 623 * 624 * Unfortunately, the only way to disable Dynamic Standby is 625 * to frob an EEPROM setting and reboot (the EEPROM setting 626 * is only consulted when the PCI bus comes out of reset). 627 * 628 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 629 */ 630 if (sc->sc_flags & FXPF_HAS_RESUME_BUG) { 631 fxp_read_eeprom(sc, &data, 10, 1); 632 if (data & 0x02) { /* STB enable */ 633 aprint_error("%s: WARNING: " 634 "Disabling dynamic standby mode in EEPROM " 635 "to work around a\n", 636 sc->sc_dev.dv_xname); 637 aprint_normal( 638 "%s: WARNING: hardware bug. You must reset " 639 "the system before using this\n", 640 sc->sc_dev.dv_xname); 641 aprint_normal("%s: WARNING: interface.\n", 642 sc->sc_dev.dv_xname); 643 data &= ~0x02; 644 fxp_write_eeprom(sc, &data, 10, 1); 645 aprint_normal("%s: new EEPROM ID: 0x%04x\n", 646 sc->sc_dev.dv_xname, data); 647 fxp_eeprom_update_cksum(sc); 648 } 649 } 650 } 651 652 static void 653 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int len) 654 { 655 uint16_t reg; 656 int x; 657 658 for (x = 1 << (len - 1); x != 0; x >>= 1) { 659 if (data & x) 660 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 661 else 662 reg = FXP_EEPROM_EECS; 663 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 664 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 665 reg | FXP_EEPROM_EESK); 666 DELAY(4); 667 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 668 DELAY(4); 669 } 670 } 671 672 /* 673 * Figure out EEPROM size. 674 * 675 * 559's can have either 64-word or 256-word EEPROMs, the 558 676 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 677 * talks about the existance of 16 to 256 word EEPROMs. 678 * 679 * The only known sizes are 64 and 256, where the 256 version is used 680 * by CardBus cards to store CIS information. 681 * 682 * The address is shifted in msb-to-lsb, and after the last 683 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 684 * after which follows the actual data. We try to detect this zero, by 685 * probing the data-out bit in the EEPROM control register just after 686 * having shifted in a bit. If the bit is zero, we assume we've 687 * shifted enough address bits. The data-out should be tri-state, 688 * before this, which should translate to a logical one. 689 * 690 * Other ways to do this would be to try to read a register with known 691 * contents with a varying number of address bits, but no such 692 * register seem to be available. The high bits of register 10 are 01 693 * on the 558 and 559, but apparently not on the 557. 694 * 695 * The Linux driver computes a checksum on the EEPROM data, but the 696 * value of this checksum is not very well documented. 697 */ 698 699 void 700 fxp_autosize_eeprom(struct fxp_softc *sc) 701 { 702 int x; 703 704 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 705 706 /* Shift in read opcode. */ 707 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 708 709 /* 710 * Shift in address, wait for the dummy zero following a correct 711 * address shift. 712 */ 713 for (x = 1; x <= 8; x++) { 714 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 715 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 716 FXP_EEPROM_EECS | FXP_EEPROM_EESK); 717 DELAY(4); 718 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 719 FXP_EEPROM_EEDO) == 0) 720 break; 721 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 722 DELAY(4); 723 } 724 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 725 DELAY(4); 726 if (x != 6 && x != 8) { 727 #ifdef DEBUG 728 printf("%s: strange EEPROM size (%d)\n", 729 sc->sc_dev.dv_xname, 1 << x); 730 #endif 731 } else 732 sc->sc_eeprom_size = x; 733 } 734 735 /* 736 * Read from the serial EEPROM. Basically, you manually shift in 737 * the read opcode (one bit at a time) and then shift in the address, 738 * and then you shift out the data (all of this one bit at a time). 739 * The word size is 16 bits, so you have to provide the address for 740 * every 16 bits of data. 741 */ 742 void 743 fxp_read_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 744 { 745 u_int16_t reg; 746 int i, x; 747 748 for (i = 0; i < words; i++) { 749 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 750 751 /* Shift in read opcode. */ 752 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 753 754 /* Shift in address. */ 755 fxp_eeprom_shiftin(sc, i + offset, sc->sc_eeprom_size); 756 757 reg = FXP_EEPROM_EECS; 758 data[i] = 0; 759 760 /* Shift out data. */ 761 for (x = 16; x > 0; x--) { 762 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 763 reg | FXP_EEPROM_EESK); 764 DELAY(4); 765 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 766 FXP_EEPROM_EEDO) 767 data[i] |= (1 << (x - 1)); 768 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 769 DELAY(4); 770 } 771 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 772 DELAY(4); 773 } 774 } 775 776 /* 777 * Write data to the serial EEPROM. 778 */ 779 void 780 fxp_write_eeprom(struct fxp_softc *sc, u_int16_t *data, int offset, int words) 781 { 782 int i, j; 783 784 for (i = 0; i < words; i++) { 785 /* Erase/write enable. */ 786 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 787 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 788 fxp_eeprom_shiftin(sc, 0x3 << (sc->sc_eeprom_size - 2), 789 sc->sc_eeprom_size); 790 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 791 DELAY(4); 792 793 /* Shift in write opcode, address, data. */ 794 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 795 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 796 fxp_eeprom_shiftin(sc, offset, sc->sc_eeprom_size); 797 fxp_eeprom_shiftin(sc, data[i], 16); 798 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 799 DELAY(4); 800 801 /* Wait for the EEPROM to finish up. */ 802 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 803 DELAY(4); 804 for (j = 0; j < 1000; j++) { 805 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & 806 FXP_EEPROM_EEDO) 807 break; 808 DELAY(50); 809 } 810 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 811 DELAY(4); 812 813 /* Erase/write disable. */ 814 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 815 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_ERASE, 3); 816 fxp_eeprom_shiftin(sc, 0, sc->sc_eeprom_size); 817 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 818 DELAY(4); 819 } 820 } 821 822 /* 823 * Update the checksum of the EEPROM. 824 */ 825 void 826 fxp_eeprom_update_cksum(struct fxp_softc *sc) 827 { 828 int i; 829 uint16_t data, cksum; 830 831 cksum = 0; 832 for (i = 0; i < (1 << sc->sc_eeprom_size) - 1; i++) { 833 fxp_read_eeprom(sc, &data, i, 1); 834 cksum += data; 835 } 836 i = (1 << sc->sc_eeprom_size) - 1; 837 cksum = 0xbaba - cksum; 838 fxp_read_eeprom(sc, &data, i, 1); 839 fxp_write_eeprom(sc, &cksum, i, 1); 840 printf("%s: EEPROM checksum @ 0x%x: 0x%04x -> 0x%04x\n", 841 sc->sc_dev.dv_xname, i, data, cksum); 842 } 843 844 /* 845 * Start packet transmission on the interface. 846 */ 847 void 848 fxp_start(struct ifnet *ifp) 849 { 850 struct fxp_softc *sc = ifp->if_softc; 851 struct mbuf *m0, *m; 852 struct fxp_txdesc *txd; 853 struct fxp_txsoft *txs; 854 bus_dmamap_t dmamap; 855 int error, lasttx, nexttx, opending, seg; 856 857 /* 858 * If we want a re-init, bail out now. 859 */ 860 if (sc->sc_flags & FXPF_WANTINIT) { 861 ifp->if_flags |= IFF_OACTIVE; 862 return; 863 } 864 865 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 866 return; 867 868 /* 869 * Remember the previous txpending and the current lasttx. 870 */ 871 opending = sc->sc_txpending; 872 lasttx = sc->sc_txlast; 873 874 /* 875 * Loop through the send queue, setting up transmit descriptors 876 * until we drain the queue, or use up all available transmit 877 * descriptors. 878 */ 879 for (;;) { 880 struct fxp_tbd *tbdp; 881 int csum_flags; 882 883 /* 884 * Grab a packet off the queue. 885 */ 886 IFQ_POLL(&ifp->if_snd, m0); 887 if (m0 == NULL) 888 break; 889 m = NULL; 890 891 if (sc->sc_txpending == FXP_NTXCB) { 892 FXP_EVCNT_INCR(&sc->sc_ev_txstall); 893 break; 894 } 895 896 /* 897 * Get the next available transmit descriptor. 898 */ 899 nexttx = FXP_NEXTTX(sc->sc_txlast); 900 txd = FXP_CDTX(sc, nexttx); 901 txs = FXP_DSTX(sc, nexttx); 902 dmamap = txs->txs_dmamap; 903 904 /* 905 * Load the DMA map. If this fails, the packet either 906 * didn't fit in the allotted number of frags, or we were 907 * short on resources. In this case, we'll copy and try 908 * again. 909 */ 910 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 911 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 912 MGETHDR(m, M_DONTWAIT, MT_DATA); 913 if (m == NULL) { 914 printf("%s: unable to allocate Tx mbuf\n", 915 sc->sc_dev.dv_xname); 916 break; 917 } 918 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 919 if (m0->m_pkthdr.len > MHLEN) { 920 MCLGET(m, M_DONTWAIT); 921 if ((m->m_flags & M_EXT) == 0) { 922 printf("%s: unable to allocate Tx " 923 "cluster\n", sc->sc_dev.dv_xname); 924 m_freem(m); 925 break; 926 } 927 } 928 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 929 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 930 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 931 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 932 if (error) { 933 printf("%s: unable to load Tx buffer, " 934 "error = %d\n", sc->sc_dev.dv_xname, error); 935 break; 936 } 937 } 938 939 IFQ_DEQUEUE(&ifp->if_snd, m0); 940 csum_flags = m0->m_pkthdr.csum_flags; 941 if (m != NULL) { 942 m_freem(m0); 943 m0 = m; 944 } 945 946 /* Initialize the fraglist. */ 947 tbdp = txd->txd_tbd; 948 if (sc->sc_flags & FXPF_IPCB) 949 tbdp++; 950 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 951 tbdp[seg].tb_addr = 952 htole32(dmamap->dm_segs[seg].ds_addr); 953 tbdp[seg].tb_size = 954 htole32(dmamap->dm_segs[seg].ds_len); 955 } 956 957 /* Sync the DMA map. */ 958 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 959 BUS_DMASYNC_PREWRITE); 960 961 /* 962 * Store a pointer to the packet so we can free it later. 963 */ 964 txs->txs_mbuf = m0; 965 966 /* 967 * Initialize the transmit descriptor. 968 */ 969 /* BIG_ENDIAN: no need to swap to store 0 */ 970 txd->txd_txcb.cb_status = 0; 971 txd->txd_txcb.cb_command = 972 sc->sc_txcmd | htole16(FXP_CB_COMMAND_SF); 973 txd->txd_txcb.tx_threshold = tx_threshold; 974 txd->txd_txcb.tbd_number = dmamap->dm_nsegs; 975 976 KASSERT((csum_flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) == 0); 977 if (sc->sc_flags & FXPF_IPCB) { 978 struct fxp_ipcb *ipcb; 979 /* 980 * Deal with TCP/IP checksum offload. Note that 981 * in order for TCP checksum offload to work, 982 * the pseudo header checksum must have already 983 * been computed and stored in the checksum field 984 * in the TCP header. The stack should have 985 * already done this for us. 986 */ 987 ipcb = &txd->txd_u.txdu_ipcb; 988 memset(ipcb, 0, sizeof(*ipcb)); 989 /* 990 * always do hardware parsing. 991 */ 992 ipcb->ipcb_ip_activation_high = 993 FXP_IPCB_HARDWAREPARSING_ENABLE; 994 /* 995 * ip checksum offloading. 996 */ 997 if (csum_flags & M_CSUM_IPv4) { 998 ipcb->ipcb_ip_schedule |= 999 FXP_IPCB_IP_CHECKSUM_ENABLE; 1000 } 1001 /* 1002 * TCP/UDP checksum offloading. 1003 */ 1004 if (csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1005 ipcb->ipcb_ip_schedule |= 1006 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; 1007 } 1008 } else { 1009 KASSERT((csum_flags & 1010 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1011 } 1012 1013 FXP_CDTXSYNC(sc, nexttx, 1014 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1015 1016 /* Advance the tx pointer. */ 1017 sc->sc_txpending++; 1018 sc->sc_txlast = nexttx; 1019 1020 #if NBPFILTER > 0 1021 /* 1022 * Pass packet to bpf if there is a listener. 1023 */ 1024 if (ifp->if_bpf) 1025 bpf_mtap(ifp->if_bpf, m0); 1026 #endif 1027 } 1028 1029 if (sc->sc_txpending == FXP_NTXCB) { 1030 /* No more slots; notify upper layer. */ 1031 ifp->if_flags |= IFF_OACTIVE; 1032 } 1033 1034 if (sc->sc_txpending != opending) { 1035 /* 1036 * We enqueued packets. If the transmitter was idle, 1037 * reset the txdirty pointer. 1038 */ 1039 if (opending == 0) 1040 sc->sc_txdirty = FXP_NEXTTX(lasttx); 1041 1042 /* 1043 * Cause the chip to interrupt and suspend command 1044 * processing once the last packet we've enqueued 1045 * has been transmitted. 1046 */ 1047 FXP_CDTX(sc, sc->sc_txlast)->txd_txcb.cb_command |= 1048 htole16(FXP_CB_COMMAND_I | FXP_CB_COMMAND_S); 1049 FXP_CDTXSYNC(sc, sc->sc_txlast, 1050 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1051 1052 /* 1053 * The entire packet chain is set up. Clear the suspend bit 1054 * on the command prior to the first packet we set up. 1055 */ 1056 FXP_CDTXSYNC(sc, lasttx, 1057 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1058 FXP_CDTX(sc, lasttx)->txd_txcb.cb_command &= 1059 htole16(~FXP_CB_COMMAND_S); 1060 FXP_CDTXSYNC(sc, lasttx, 1061 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1062 1063 /* 1064 * Issue a Resume command in case the chip was suspended. 1065 */ 1066 fxp_scb_wait(sc); 1067 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1068 1069 /* Set a watchdog timer in case the chip flakes out. */ 1070 ifp->if_timer = 5; 1071 } 1072 } 1073 1074 /* 1075 * Process interface interrupts. 1076 */ 1077 int 1078 fxp_intr(void *arg) 1079 { 1080 struct fxp_softc *sc = arg; 1081 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1082 bus_dmamap_t rxmap; 1083 int claimed = 0; 1084 u_int8_t statack; 1085 1086 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1087 return (0); 1088 /* 1089 * If the interface isn't running, don't try to 1090 * service the interrupt.. just ack it and bail. 1091 */ 1092 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1093 statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1094 if (statack) { 1095 claimed = 1; 1096 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1097 } 1098 return (claimed); 1099 } 1100 1101 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1102 claimed = 1; 1103 1104 /* 1105 * First ACK all the interrupts in this pass. 1106 */ 1107 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1108 1109 /* 1110 * Process receiver interrupts. If a no-resource (RNR) 1111 * condition exists, get whatever packets we can and 1112 * re-start the receiver. 1113 */ 1114 if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { 1115 FXP_EVCNT_INCR(&sc->sc_ev_rxintr); 1116 fxp_rxintr(sc); 1117 } 1118 1119 if (statack & FXP_SCB_STATACK_RNR) { 1120 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1121 fxp_scb_wait(sc); 1122 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1123 rxmap->dm_segs[0].ds_addr + 1124 RFA_ALIGNMENT_FUDGE); 1125 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1126 } 1127 1128 /* 1129 * Free any finished transmit mbuf chains. 1130 */ 1131 if (statack & (FXP_SCB_STATACK_CXTNO|FXP_SCB_STATACK_CNA)) { 1132 FXP_EVCNT_INCR(&sc->sc_ev_txintr); 1133 fxp_txintr(sc); 1134 1135 /* 1136 * Try to get more packets going. 1137 */ 1138 fxp_start(ifp); 1139 1140 if (sc->sc_txpending == 0) { 1141 /* 1142 * If we want a re-init, do that now. 1143 */ 1144 if (sc->sc_flags & FXPF_WANTINIT) 1145 (void) fxp_init(ifp); 1146 } 1147 } 1148 } 1149 1150 #if NRND > 0 1151 if (claimed) 1152 rnd_add_uint32(&sc->rnd_source, statack); 1153 #endif 1154 return (claimed); 1155 } 1156 1157 /* 1158 * Handle transmit completion interrupts. 1159 */ 1160 void 1161 fxp_txintr(struct fxp_softc *sc) 1162 { 1163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1164 struct fxp_txdesc *txd; 1165 struct fxp_txsoft *txs; 1166 int i; 1167 u_int16_t txstat; 1168 1169 ifp->if_flags &= ~IFF_OACTIVE; 1170 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1171 i = FXP_NEXTTX(i), sc->sc_txpending--) { 1172 txd = FXP_CDTX(sc, i); 1173 txs = FXP_DSTX(sc, i); 1174 1175 FXP_CDTXSYNC(sc, i, 1176 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1177 1178 txstat = le16toh(txd->txd_txcb.cb_status); 1179 1180 if ((txstat & FXP_CB_STATUS_C) == 0) 1181 break; 1182 1183 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1184 0, txs->txs_dmamap->dm_mapsize, 1185 BUS_DMASYNC_POSTWRITE); 1186 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1187 m_freem(txs->txs_mbuf); 1188 txs->txs_mbuf = NULL; 1189 } 1190 1191 /* Update the dirty transmit buffer pointer. */ 1192 sc->sc_txdirty = i; 1193 1194 /* 1195 * Cancel the watchdog timer if there are no pending 1196 * transmissions. 1197 */ 1198 if (sc->sc_txpending == 0) 1199 ifp->if_timer = 0; 1200 } 1201 1202 void 1203 fxp_rx_hwcksum(struct mbuf *m, const struct fxp_rfa *rfa) 1204 { 1205 u_int16_t rxparsestat; 1206 u_int16_t csum_stat; 1207 u_int32_t csum_data; 1208 int csum_flags; 1209 1210 rxparsestat = le16toh(rfa->rx_parse_stat); 1211 csum_stat = le16toh(rfa->cksum_stat); 1212 if (!(rfa->rfa_status & htole16(FXP_RFA_STATUS_PARSE))) 1213 return; 1214 1215 csum_flags = 0; 1216 csum_data = 0; 1217 1218 if (csum_stat & FXP_RFDX_CS_IP_CSUM_BIT_VALID) { 1219 csum_flags = M_CSUM_IPv4; 1220 if (!(csum_stat & FXP_RFDX_CS_IP_CSUM_VALID)) 1221 csum_flags |= M_CSUM_IPv4_BAD; 1222 } 1223 1224 if (csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) { 1225 csum_flags |= (M_CSUM_TCPv4|M_CSUM_UDPv4); /* XXX */ 1226 if (!(csum_stat & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) 1227 csum_flags |= M_CSUM_TCP_UDP_BAD; 1228 } 1229 1230 m->m_pkthdr.csum_flags = csum_flags; 1231 m->m_pkthdr.csum_data = csum_data; 1232 } 1233 1234 /* 1235 * Handle receive interrupts. 1236 */ 1237 void 1238 fxp_rxintr(struct fxp_softc *sc) 1239 { 1240 struct ethercom *ec = &sc->sc_ethercom; 1241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1242 struct mbuf *m, *m0; 1243 bus_dmamap_t rxmap; 1244 struct fxp_rfa *rfa; 1245 u_int16_t len, rxstat; 1246 1247 for (;;) { 1248 m = sc->sc_rxq.ifq_head; 1249 rfa = FXP_MTORFA(m); 1250 rxmap = M_GETCTX(m, bus_dmamap_t); 1251 1252 FXP_RFASYNC(sc, m, 1253 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1254 1255 rxstat = le16toh(rfa->rfa_status); 1256 1257 if ((rxstat & FXP_RFA_STATUS_C) == 0) { 1258 /* 1259 * We have processed all of the 1260 * receive buffers. 1261 */ 1262 FXP_RFASYNC(sc, m, BUS_DMASYNC_PREREAD); 1263 return; 1264 } 1265 1266 IF_DEQUEUE(&sc->sc_rxq, m); 1267 1268 FXP_RXBUFSYNC(sc, m, BUS_DMASYNC_POSTREAD); 1269 1270 len = le16toh(rfa->actual_size) & 1271 (m->m_ext.ext_size - 1); 1272 1273 if (len < sizeof(struct ether_header)) { 1274 /* 1275 * Runt packet; drop it now. 1276 */ 1277 FXP_INIT_RFABUF(sc, m); 1278 continue; 1279 } 1280 1281 /* 1282 * If support for 802.1Q VLAN sized frames is 1283 * enabled, we need to do some additional error 1284 * checking (as we are saving bad frames, in 1285 * order to receive the larger ones). 1286 */ 1287 if ((ec->ec_capenable & ETHERCAP_VLAN_MTU) != 0 && 1288 (rxstat & (FXP_RFA_STATUS_OVERRUN| 1289 FXP_RFA_STATUS_RNR| 1290 FXP_RFA_STATUS_ALIGN| 1291 FXP_RFA_STATUS_CRC)) != 0) { 1292 FXP_INIT_RFABUF(sc, m); 1293 continue; 1294 } 1295 1296 /* Do checksum checking. */ 1297 m->m_pkthdr.csum_flags = 0; 1298 if (sc->sc_flags & FXPF_EXT_RFA) 1299 fxp_rx_hwcksum(m, rfa); 1300 1301 /* 1302 * If the packet is small enough to fit in a 1303 * single header mbuf, allocate one and copy 1304 * the data into it. This greatly reduces 1305 * memory consumption when we receive lots 1306 * of small packets. 1307 * 1308 * Otherwise, we add a new buffer to the receive 1309 * chain. If this fails, we drop the packet and 1310 * recycle the old buffer. 1311 */ 1312 if (fxp_copy_small != 0 && len <= MHLEN) { 1313 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1314 if (m0 == NULL) 1315 goto dropit; 1316 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 1317 memcpy(mtod(m0, caddr_t), 1318 mtod(m, caddr_t), len); 1319 m0->m_pkthdr.csum_flags = m->m_pkthdr.csum_flags; 1320 m0->m_pkthdr.csum_data = m->m_pkthdr.csum_data; 1321 FXP_INIT_RFABUF(sc, m); 1322 m = m0; 1323 } else { 1324 if (fxp_add_rfabuf(sc, rxmap, 1) != 0) { 1325 dropit: 1326 ifp->if_ierrors++; 1327 FXP_INIT_RFABUF(sc, m); 1328 continue; 1329 } 1330 } 1331 1332 m->m_pkthdr.rcvif = ifp; 1333 m->m_pkthdr.len = m->m_len = len; 1334 1335 #if NBPFILTER > 0 1336 /* 1337 * Pass this up to any BPF listeners, but only 1338 * pass it up the stack it its for us. 1339 */ 1340 if (ifp->if_bpf) 1341 bpf_mtap(ifp->if_bpf, m); 1342 #endif 1343 1344 /* Pass it on. */ 1345 (*ifp->if_input)(ifp, m); 1346 } 1347 } 1348 1349 /* 1350 * Update packet in/out/collision statistics. The i82557 doesn't 1351 * allow you to access these counters without doing a fairly 1352 * expensive DMA to get _all_ of the statistics it maintains, so 1353 * we do this operation here only once per second. The statistics 1354 * counters in the kernel are updated from the previous dump-stats 1355 * DMA and then a new dump-stats DMA is started. The on-chip 1356 * counters are zeroed when the DMA completes. If we can't start 1357 * the DMA immediately, we don't wait - we just prepare to read 1358 * them again next time. 1359 */ 1360 void 1361 fxp_tick(void *arg) 1362 { 1363 struct fxp_softc *sc = arg; 1364 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1365 struct fxp_stats *sp = &sc->sc_control_data->fcd_stats; 1366 int s; 1367 1368 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1369 return; 1370 1371 s = splnet(); 1372 1373 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 1374 1375 ifp->if_opackets += le32toh(sp->tx_good); 1376 ifp->if_collisions += le32toh(sp->tx_total_collisions); 1377 if (sp->rx_good) { 1378 ifp->if_ipackets += le32toh(sp->rx_good); 1379 sc->sc_rxidle = 0; 1380 } else { 1381 sc->sc_rxidle++; 1382 } 1383 ifp->if_ierrors += 1384 le32toh(sp->rx_crc_errors) + 1385 le32toh(sp->rx_alignment_errors) + 1386 le32toh(sp->rx_rnr_errors) + 1387 le32toh(sp->rx_overrun_errors); 1388 /* 1389 * If any transmit underruns occurred, bump up the transmit 1390 * threshold by another 512 bytes (64 * 8). 1391 */ 1392 if (sp->tx_underruns) { 1393 ifp->if_oerrors += le32toh(sp->tx_underruns); 1394 if (tx_threshold < 192) 1395 tx_threshold += 64; 1396 } 1397 1398 /* 1399 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1400 * then assume the receiver has locked up and attempt to clear 1401 * the condition by reprogramming the multicast filter (actually, 1402 * resetting the interface). This is a work-around for a bug in 1403 * the 82557 where the receiver locks up if it gets certain types 1404 * of garbage in the synchronization bits prior to the packet header. 1405 * This bug is supposed to only occur in 10Mbps mode, but has been 1406 * seen to occur in 100Mbps mode as well (perhaps due to a 10/100 1407 * speed transition). 1408 */ 1409 if (sc->sc_rxidle > FXP_MAX_RX_IDLE) { 1410 (void) fxp_init(ifp); 1411 splx(s); 1412 return; 1413 } 1414 /* 1415 * If there is no pending command, start another stats 1416 * dump. Otherwise punt for now. 1417 */ 1418 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1419 /* 1420 * Start another stats dump. 1421 */ 1422 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1423 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1424 } else { 1425 /* 1426 * A previous command is still waiting to be accepted. 1427 * Just zero our copy of the stats and wait for the 1428 * next timer event to update them. 1429 */ 1430 /* BIG_ENDIAN: no swap required to store 0 */ 1431 sp->tx_good = 0; 1432 sp->tx_underruns = 0; 1433 sp->tx_total_collisions = 0; 1434 1435 sp->rx_good = 0; 1436 sp->rx_crc_errors = 0; 1437 sp->rx_alignment_errors = 0; 1438 sp->rx_rnr_errors = 0; 1439 sp->rx_overrun_errors = 0; 1440 } 1441 1442 if (sc->sc_flags & FXPF_MII) { 1443 /* Tick the MII clock. */ 1444 mii_tick(&sc->sc_mii); 1445 } 1446 1447 splx(s); 1448 1449 /* 1450 * Schedule another timeout one second from now. 1451 */ 1452 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1453 } 1454 1455 /* 1456 * Drain the receive queue. 1457 */ 1458 void 1459 fxp_rxdrain(struct fxp_softc *sc) 1460 { 1461 bus_dmamap_t rxmap; 1462 struct mbuf *m; 1463 1464 for (;;) { 1465 IF_DEQUEUE(&sc->sc_rxq, m); 1466 if (m == NULL) 1467 break; 1468 rxmap = M_GETCTX(m, bus_dmamap_t); 1469 bus_dmamap_unload(sc->sc_dmat, rxmap); 1470 FXP_RXMAP_PUT(sc, rxmap); 1471 m_freem(m); 1472 } 1473 } 1474 1475 /* 1476 * Stop the interface. Cancels the statistics updater and resets 1477 * the interface. 1478 */ 1479 void 1480 fxp_stop(struct ifnet *ifp, int disable) 1481 { 1482 struct fxp_softc *sc = ifp->if_softc; 1483 struct fxp_txsoft *txs; 1484 int i; 1485 1486 /* 1487 * Turn down interface (done early to avoid bad interactions 1488 * between panics, shutdown hooks, and the watchdog timer) 1489 */ 1490 ifp->if_timer = 0; 1491 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1492 1493 /* 1494 * Cancel stats updater. 1495 */ 1496 callout_stop(&sc->sc_callout); 1497 if (sc->sc_flags & FXPF_MII) { 1498 /* Down the MII. */ 1499 mii_down(&sc->sc_mii); 1500 } 1501 1502 /* 1503 * Issue software reset. This unloads any microcode that 1504 * might already be loaded. 1505 */ 1506 sc->sc_flags &= ~FXPF_UCODE_LOADED; 1507 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1508 DELAY(50); 1509 1510 /* 1511 * Release any xmit buffers. 1512 */ 1513 for (i = 0; i < FXP_NTXCB; i++) { 1514 txs = FXP_DSTX(sc, i); 1515 if (txs->txs_mbuf != NULL) { 1516 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1517 m_freem(txs->txs_mbuf); 1518 txs->txs_mbuf = NULL; 1519 } 1520 } 1521 sc->sc_txpending = 0; 1522 1523 if (disable) { 1524 fxp_rxdrain(sc); 1525 fxp_disable(sc); 1526 } 1527 1528 } 1529 1530 /* 1531 * Watchdog/transmission transmit timeout handler. Called when a 1532 * transmission is started on the interface, but no interrupt is 1533 * received before the timeout. This usually indicates that the 1534 * card has wedged for some reason. 1535 */ 1536 void 1537 fxp_watchdog(struct ifnet *ifp) 1538 { 1539 struct fxp_softc *sc = ifp->if_softc; 1540 1541 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1542 ifp->if_oerrors++; 1543 1544 (void) fxp_init(ifp); 1545 } 1546 1547 /* 1548 * Initialize the interface. Must be called at splnet(). 1549 */ 1550 int 1551 fxp_init(struct ifnet *ifp) 1552 { 1553 struct fxp_softc *sc = ifp->if_softc; 1554 struct fxp_cb_config *cbp; 1555 struct fxp_cb_ias *cb_ias; 1556 struct fxp_txdesc *txd; 1557 bus_dmamap_t rxmap; 1558 int i, prm, save_bf, lrxen, allm, error = 0; 1559 1560 if ((error = fxp_enable(sc)) != 0) 1561 goto out; 1562 1563 /* 1564 * Cancel any pending I/O 1565 */ 1566 fxp_stop(ifp, 0); 1567 1568 /* 1569 * XXX just setting sc_flags to 0 here clears any FXPF_MII 1570 * flag, and this prevents the MII from detaching resulting in 1571 * a panic. The flags field should perhaps be split in runtime 1572 * flags and more static information. For now, just clear the 1573 * only other flag set. 1574 */ 1575 1576 sc->sc_flags &= ~FXPF_WANTINIT; 1577 1578 /* 1579 * Initialize base of CBL and RFA memory. Loading with zero 1580 * sets it up for regular linear addressing. 1581 */ 1582 fxp_scb_wait(sc); 1583 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1584 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1585 1586 fxp_scb_wait(sc); 1587 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1588 1589 /* 1590 * Initialize the multicast filter. Do this now, since we might 1591 * have to setup the config block differently. 1592 */ 1593 fxp_mc_setup(sc); 1594 1595 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1596 allm = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1597 1598 /* 1599 * In order to support receiving 802.1Q VLAN frames, we have to 1600 * enable "save bad frames", since they are 4 bytes larger than 1601 * the normal Ethernet maximum frame length. On i82558 and later, 1602 * we have a better mechanism for this. 1603 */ 1604 save_bf = 0; 1605 lrxen = 0; 1606 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1607 if (sc->sc_rev < FXP_REV_82558_A4) 1608 save_bf = 1; 1609 else 1610 lrxen = 1; 1611 } 1612 1613 /* 1614 * Initialize base of dump-stats buffer. 1615 */ 1616 fxp_scb_wait(sc); 1617 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1618 sc->sc_cddma + FXP_CDSTATSOFF); 1619 FXP_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 1620 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1621 1622 cbp = &sc->sc_control_data->fcd_configcb; 1623 memset(cbp, 0, sizeof(struct fxp_cb_config)); 1624 1625 /* 1626 * Load microcode for this controller. 1627 */ 1628 fxp_load_ucode(sc); 1629 1630 /* 1631 * This copy is kind of disgusting, but there are a bunch of must be 1632 * zero and must be one bits in this structure and this is the easiest 1633 * way to initialize them all to proper values. 1634 */ 1635 memcpy(cbp, fxp_cb_config_template, sizeof(fxp_cb_config_template)); 1636 1637 /* BIG_ENDIAN: no need to swap to store 0 */ 1638 cbp->cb_status = 0; 1639 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | 1640 FXP_CB_COMMAND_EL); 1641 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1642 cbp->link_addr = 0xffffffff; /* (no) next command */ 1643 /* bytes in config block */ 1644 cbp->byte_count = (sc->sc_flags & FXPF_EXT_RFA) ? 1645 FXP_EXT_CONFIG_LEN : FXP_CONFIG_LEN; 1646 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1647 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1648 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1649 cbp->mwi_enable = (sc->sc_flags & FXPF_MWI) ? 1 : 0; 1650 cbp->type_enable = 0; /* actually reserved */ 1651 cbp->read_align_en = (sc->sc_flags & FXPF_READ_ALIGN) ? 1 : 0; 1652 cbp->end_wr_on_cl = (sc->sc_flags & FXPF_WRITE_ALIGN) ? 1 : 0; 1653 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1654 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1655 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1656 cbp->late_scb = 0; /* (don't) defer SCB update */ 1657 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1658 cbp->ci_int = 1; /* interrupt on CU idle */ 1659 cbp->ext_txcb_dis = (sc->sc_flags & FXPF_EXT_TXCB) ? 0 : 1; 1660 cbp->ext_stats_dis = 1; /* disable extended counters */ 1661 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1662 cbp->save_bf = save_bf;/* save bad frames */ 1663 cbp->disc_short_rx = !prm; /* discard short packets */ 1664 cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */ 1665 cbp->ext_rfa = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1666 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1667 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1668 /* interface mode */ 1669 cbp->mediatype = (sc->sc_flags & FXPF_MII) ? 1 : 0; 1670 cbp->csma_dis = 0; /* (don't) disable link */ 1671 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1672 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1673 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1674 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1675 cbp->mc_wake_en = 0; /* (don't) assert PME# on mcmatch */ 1676 cbp->nsai = 1; /* (don't) disable source addr insert */ 1677 cbp->preamble_length = 2; /* (7 byte) preamble */ 1678 cbp->loopback = 0; /* (don't) loopback */ 1679 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1680 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1681 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1682 cbp->promiscuous = prm; /* promiscuous mode */ 1683 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1684 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1685 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1686 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1687 cbp->crscdt = (sc->sc_flags & FXPF_MII) ? 0 : 1; 1688 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1689 cbp->padding = 1; /* (do) pad short tx packets */ 1690 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1691 cbp->long_rx_en = lrxen; /* long packet receive enable */ 1692 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1693 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1694 /* must set wake_en in PMCSR also */ 1695 cbp->force_fdx = 0; /* (don't) force full duplex */ 1696 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1697 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1698 cbp->mc_all = allm; /* accept all multicasts */ 1699 cbp->ext_rx_mode = (sc->sc_flags & FXPF_EXT_RFA) ? 1 : 0; 1700 1701 if (sc->sc_rev < FXP_REV_82558_A4) { 1702 /* 1703 * The i82557 has no hardware flow control, the values 1704 * here are the defaults for the chip. 1705 */ 1706 cbp->fc_delay_lsb = 0; 1707 cbp->fc_delay_msb = 0x40; 1708 cbp->pri_fc_thresh = 3; 1709 cbp->tx_fc_dis = 0; 1710 cbp->rx_fc_restop = 0; 1711 cbp->rx_fc_restart = 0; 1712 cbp->fc_filter = 0; 1713 cbp->pri_fc_loc = 1; 1714 } else { 1715 cbp->fc_delay_lsb = 0x1f; 1716 cbp->fc_delay_msb = 0x01; 1717 cbp->pri_fc_thresh = 3; 1718 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1719 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1720 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1721 cbp->fc_filter = !prm; /* drop FC frames to host */ 1722 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1723 } 1724 1725 FXP_CDCONFIGSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1726 1727 /* 1728 * Start the config command/DMA. 1729 */ 1730 fxp_scb_wait(sc); 1731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1732 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1733 /* ...and wait for it to complete. */ 1734 i = 1000; 1735 do { 1736 FXP_CDCONFIGSYNC(sc, 1737 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1738 DELAY(1); 1739 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1740 if (i == 0) { 1741 printf("%s at line %d: dmasync timeout\n", 1742 sc->sc_dev.dv_xname, __LINE__); 1743 return (ETIMEDOUT); 1744 } 1745 1746 /* 1747 * Initialize the station address. 1748 */ 1749 cb_ias = &sc->sc_control_data->fcd_iascb; 1750 /* BIG_ENDIAN: no need to swap to store 0 */ 1751 cb_ias->cb_status = 0; 1752 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); 1753 /* BIG_ENDIAN: no need to swap to store 0xffffffff */ 1754 cb_ias->link_addr = 0xffffffff; 1755 memcpy((void *)cb_ias->macaddr, LLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1756 1757 FXP_CDIASSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1758 1759 /* 1760 * Start the IAS (Individual Address Setup) command/DMA. 1761 */ 1762 fxp_scb_wait(sc); 1763 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1764 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1765 /* ...and wait for it to complete. */ 1766 i = 1000; 1767 do { 1768 FXP_CDIASSYNC(sc, 1769 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1770 DELAY(1); 1771 } while ((le16toh(cb_ias->cb_status) & FXP_CB_STATUS_C) == 0 && --i); 1772 if (i == 0) { 1773 printf("%s at line %d: dmasync timeout\n", 1774 sc->sc_dev.dv_xname, __LINE__); 1775 return (ETIMEDOUT); 1776 } 1777 1778 /* 1779 * Initialize the transmit descriptor ring. txlast is initialized 1780 * to the end of the list so that it will wrap around to the first 1781 * descriptor when the first packet is transmitted. 1782 */ 1783 for (i = 0; i < FXP_NTXCB; i++) { 1784 txd = FXP_CDTX(sc, i); 1785 memset(txd, 0, sizeof(*txd)); 1786 txd->txd_txcb.cb_command = 1787 htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); 1788 txd->txd_txcb.link_addr = 1789 htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(i))); 1790 if (sc->sc_flags & FXPF_EXT_TXCB) 1791 txd->txd_txcb.tbd_array_addr = 1792 htole32(FXP_CDTBDADDR(sc, i) + 1793 (2 * sizeof(struct fxp_tbd))); 1794 else 1795 txd->txd_txcb.tbd_array_addr = 1796 htole32(FXP_CDTBDADDR(sc, i)); 1797 FXP_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1798 } 1799 sc->sc_txpending = 0; 1800 sc->sc_txdirty = 0; 1801 sc->sc_txlast = FXP_NTXCB - 1; 1802 1803 /* 1804 * Initialize the receive buffer list. 1805 */ 1806 sc->sc_rxq.ifq_maxlen = FXP_NRFABUFS; 1807 while (sc->sc_rxq.ifq_len < FXP_NRFABUFS) { 1808 rxmap = FXP_RXMAP_GET(sc); 1809 if ((error = fxp_add_rfabuf(sc, rxmap, 0)) != 0) { 1810 printf("%s: unable to allocate or map rx " 1811 "buffer %d, error = %d\n", 1812 sc->sc_dev.dv_xname, 1813 sc->sc_rxq.ifq_len, error); 1814 /* 1815 * XXX Should attempt to run with fewer receive 1816 * XXX buffers instead of just failing. 1817 */ 1818 FXP_RXMAP_PUT(sc, rxmap); 1819 fxp_rxdrain(sc); 1820 goto out; 1821 } 1822 } 1823 sc->sc_rxidle = 0; 1824 1825 /* 1826 * Give the transmit ring to the chip. We do this by pointing 1827 * the chip at the last descriptor (which is a NOP|SUSPEND), and 1828 * issuing a start command. It will execute the NOP and then 1829 * suspend, pointing at the first descriptor. 1830 */ 1831 fxp_scb_wait(sc); 1832 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1833 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1834 1835 /* 1836 * Initialize receiver buffer area - RFA. 1837 */ 1838 rxmap = M_GETCTX(sc->sc_rxq.ifq_head, bus_dmamap_t); 1839 fxp_scb_wait(sc); 1840 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1841 rxmap->dm_segs[0].ds_addr + RFA_ALIGNMENT_FUDGE); 1842 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1843 1844 if (sc->sc_flags & FXPF_MII) { 1845 /* 1846 * Set current media. 1847 */ 1848 mii_mediachg(&sc->sc_mii); 1849 } 1850 1851 /* 1852 * ...all done! 1853 */ 1854 ifp->if_flags |= IFF_RUNNING; 1855 ifp->if_flags &= ~IFF_OACTIVE; 1856 1857 /* 1858 * Start the one second timer. 1859 */ 1860 callout_reset(&sc->sc_callout, hz, fxp_tick, sc); 1861 1862 /* 1863 * Attempt to start output on the interface. 1864 */ 1865 fxp_start(ifp); 1866 1867 out: 1868 if (error) { 1869 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1870 ifp->if_timer = 0; 1871 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1872 } 1873 return (error); 1874 } 1875 1876 /* 1877 * Change media according to request. 1878 */ 1879 int 1880 fxp_mii_mediachange(struct ifnet *ifp) 1881 { 1882 struct fxp_softc *sc = ifp->if_softc; 1883 1884 if (ifp->if_flags & IFF_UP) 1885 mii_mediachg(&sc->sc_mii); 1886 return (0); 1887 } 1888 1889 /* 1890 * Notify the world which media we're using. 1891 */ 1892 void 1893 fxp_mii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1894 { 1895 struct fxp_softc *sc = ifp->if_softc; 1896 1897 if (sc->sc_enabled == 0) { 1898 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 1899 ifmr->ifm_status = 0; 1900 return; 1901 } 1902 1903 mii_pollstat(&sc->sc_mii); 1904 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1905 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1906 } 1907 1908 int 1909 fxp_80c24_mediachange(struct ifnet *ifp) 1910 { 1911 1912 /* Nothing to do here. */ 1913 return (0); 1914 } 1915 1916 void 1917 fxp_80c24_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1918 { 1919 struct fxp_softc *sc = ifp->if_softc; 1920 1921 /* 1922 * Media is currently-selected media. We cannot determine 1923 * the link status. 1924 */ 1925 ifmr->ifm_status = 0; 1926 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media; 1927 } 1928 1929 /* 1930 * Add a buffer to the end of the RFA buffer list. 1931 * Return 0 if successful, error code on failure. 1932 * 1933 * The RFA struct is stuck at the beginning of mbuf cluster and the 1934 * data pointer is fixed up to point just past it. 1935 */ 1936 int 1937 fxp_add_rfabuf(struct fxp_softc *sc, bus_dmamap_t rxmap, int unload) 1938 { 1939 struct mbuf *m; 1940 int error; 1941 1942 MGETHDR(m, M_DONTWAIT, MT_DATA); 1943 if (m == NULL) 1944 return (ENOBUFS); 1945 1946 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1947 MCLGET(m, M_DONTWAIT); 1948 if ((m->m_flags & M_EXT) == 0) { 1949 m_freem(m); 1950 return (ENOBUFS); 1951 } 1952 1953 if (unload) 1954 bus_dmamap_unload(sc->sc_dmat, rxmap); 1955 1956 M_SETCTX(m, rxmap); 1957 1958 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 1959 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, 1960 BUS_DMA_READ|BUS_DMA_NOWAIT); 1961 if (error) { 1962 printf("%s: can't load rx DMA map %d, error = %d\n", 1963 sc->sc_dev.dv_xname, sc->sc_rxq.ifq_len, error); 1964 panic("fxp_add_rfabuf"); /* XXX */ 1965 } 1966 1967 FXP_INIT_RFABUF(sc, m); 1968 1969 return (0); 1970 } 1971 1972 int 1973 fxp_mdi_read(struct device *self, int phy, int reg) 1974 { 1975 struct fxp_softc *sc = (struct fxp_softc *)self; 1976 int count = 10000; 1977 int value; 1978 1979 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1980 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1981 1982 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 1983 0x10000000) == 0 && count--) 1984 DELAY(10); 1985 1986 if (count <= 0) 1987 printf("%s: fxp_mdi_read: timed out\n", sc->sc_dev.dv_xname); 1988 1989 return (value & 0xffff); 1990 } 1991 1992 void 1993 fxp_statchg(struct device *self) 1994 { 1995 1996 /* Nothing to do. */ 1997 } 1998 1999 void 2000 fxp_mdi_write(struct device *self, int phy, int reg, int value) 2001 { 2002 struct fxp_softc *sc = (struct fxp_softc *)self; 2003 int count = 10000; 2004 2005 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 2006 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 2007 (value & 0xffff)); 2008 2009 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 2010 count--) 2011 DELAY(10); 2012 2013 if (count <= 0) 2014 printf("%s: fxp_mdi_write: timed out\n", sc->sc_dev.dv_xname); 2015 } 2016 2017 int 2018 fxp_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2019 { 2020 struct fxp_softc *sc = ifp->if_softc; 2021 struct ifreq *ifr = (struct ifreq *)data; 2022 int s, error; 2023 2024 s = splnet(); 2025 2026 switch (cmd) { 2027 case SIOCSIFMEDIA: 2028 case SIOCGIFMEDIA: 2029 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 2030 break; 2031 2032 default: 2033 error = ether_ioctl(ifp, cmd, data); 2034 if (error == ENETRESET) { 2035 if (sc->sc_enabled) { 2036 /* 2037 * Multicast list has changed; set the 2038 * hardware filter accordingly. 2039 */ 2040 if (sc->sc_txpending) { 2041 sc->sc_flags |= FXPF_WANTINIT; 2042 error = 0; 2043 } else 2044 error = fxp_init(ifp); 2045 } else 2046 error = 0; 2047 } 2048 break; 2049 } 2050 2051 /* Try to get more packets going. */ 2052 if (sc->sc_enabled) 2053 fxp_start(ifp); 2054 2055 splx(s); 2056 return (error); 2057 } 2058 2059 /* 2060 * Program the multicast filter. 2061 * 2062 * This function must be called at splnet(). 2063 */ 2064 void 2065 fxp_mc_setup(struct fxp_softc *sc) 2066 { 2067 struct fxp_cb_mcs *mcsp = &sc->sc_control_data->fcd_mcscb; 2068 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2069 struct ethercom *ec = &sc->sc_ethercom; 2070 struct ether_multi *enm; 2071 struct ether_multistep step; 2072 int count, nmcasts; 2073 2074 #ifdef DIAGNOSTIC 2075 if (sc->sc_txpending) 2076 panic("fxp_mc_setup: pending transmissions"); 2077 #endif 2078 2079 ifp->if_flags &= ~IFF_ALLMULTI; 2080 2081 /* 2082 * Initialize multicast setup descriptor. 2083 */ 2084 nmcasts = 0; 2085 ETHER_FIRST_MULTI(step, ec, enm); 2086 while (enm != NULL) { 2087 /* 2088 * Check for too many multicast addresses or if we're 2089 * listening to a range. Either way, we simply have 2090 * to accept all multicasts. 2091 */ 2092 if (nmcasts >= MAXMCADDR || 2093 memcmp(enm->enm_addrlo, enm->enm_addrhi, 2094 ETHER_ADDR_LEN) != 0) { 2095 /* 2096 * Callers of this function must do the 2097 * right thing with this. If we're called 2098 * from outside fxp_init(), the caller must 2099 * detect if the state if IFF_ALLMULTI changes. 2100 * If it does, the caller must then call 2101 * fxp_init(), since allmulti is handled by 2102 * the config block. 2103 */ 2104 ifp->if_flags |= IFF_ALLMULTI; 2105 return; 2106 } 2107 memcpy((void *)&mcsp->mc_addr[nmcasts][0], enm->enm_addrlo, 2108 ETHER_ADDR_LEN); 2109 nmcasts++; 2110 ETHER_NEXT_MULTI(step, enm); 2111 } 2112 2113 /* BIG_ENDIAN: no need to swap to store 0 */ 2114 mcsp->cb_status = 0; 2115 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); 2116 mcsp->link_addr = htole32(FXP_CDTXADDR(sc, FXP_NEXTTX(sc->sc_txlast))); 2117 mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); 2118 2119 FXP_CDMCSSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2120 2121 /* 2122 * Wait until the command unit is not active. This should never 2123 * happen since nothing is queued, but make sure anyway. 2124 */ 2125 count = 100; 2126 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2127 FXP_SCB_CUS_ACTIVE && --count) 2128 DELAY(1); 2129 if (count == 0) { 2130 printf("%s at line %d: command queue timeout\n", 2131 sc->sc_dev.dv_xname, __LINE__); 2132 return; 2133 } 2134 2135 /* 2136 * Start the multicast setup command/DMA. 2137 */ 2138 fxp_scb_wait(sc); 2139 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDMCSOFF); 2140 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2141 2142 /* ...and wait for it to complete. */ 2143 count = 1000; 2144 do { 2145 FXP_CDMCSSYNC(sc, 2146 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2147 DELAY(1); 2148 } while ((le16toh(mcsp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2149 if (count == 0) { 2150 printf("%s at line %d: dmasync timeout\n", 2151 sc->sc_dev.dv_xname, __LINE__); 2152 return; 2153 } 2154 } 2155 2156 static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2157 static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2158 static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2159 static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2160 static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2161 static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2162 2163 #define UCODE(x) x, sizeof(x) 2164 2165 static const struct ucode { 2166 int32_t revision; 2167 const uint32_t *ucode; 2168 size_t length; 2169 uint16_t int_delay_offset; 2170 uint16_t bundle_max_offset; 2171 } ucode_table[] = { 2172 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), 2173 D101_CPUSAVER_DWORD, 0 }, 2174 2175 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), 2176 D101_CPUSAVER_DWORD, 0 }, 2177 2178 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2179 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2180 2181 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2182 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2183 2184 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2185 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2186 2187 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2188 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2189 2190 { 0, NULL, 0, 0, 0 } 2191 }; 2192 2193 void 2194 fxp_load_ucode(struct fxp_softc *sc) 2195 { 2196 const struct ucode *uc; 2197 struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode; 2198 int count; 2199 2200 if (sc->sc_flags & FXPF_UCODE_LOADED) 2201 return; 2202 2203 /* 2204 * Only load the uCode if the user has requested that 2205 * we do so. 2206 */ 2207 if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) { 2208 sc->sc_int_delay = 0; 2209 sc->sc_bundle_max = 0; 2210 return; 2211 } 2212 2213 for (uc = ucode_table; uc->ucode != NULL; uc++) { 2214 if (sc->sc_rev == uc->revision) 2215 break; 2216 } 2217 if (uc->ucode == NULL) 2218 return; 2219 2220 /* BIG ENDIAN: no need to swap to store 0 */ 2221 cbp->cb_status = 0; 2222 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); 2223 cbp->link_addr = 0xffffffff; /* (no) next command */ 2224 memcpy((void *) cbp->ucode, uc->ucode, uc->length); 2225 2226 if (uc->int_delay_offset) 2227 *(uint16_t *) &cbp->ucode[uc->int_delay_offset] = 2228 htole16(fxp_int_delay + (fxp_int_delay / 2)); 2229 2230 if (uc->bundle_max_offset) 2231 *(uint16_t *) &cbp->ucode[uc->bundle_max_offset] = 2232 htole16(fxp_bundle_max); 2233 2234 FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2235 2236 /* 2237 * Download the uCode to the chip. 2238 */ 2239 fxp_scb_wait(sc); 2240 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF); 2241 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2242 2243 /* ...and wait for it to complete. */ 2244 count = 10000; 2245 do { 2246 FXP_CDUCODESYNC(sc, 2247 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2248 DELAY(2); 2249 } while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count); 2250 if (count == 0) { 2251 sc->sc_int_delay = 0; 2252 sc->sc_bundle_max = 0; 2253 printf("%s: timeout loading microcode\n", 2254 sc->sc_dev.dv_xname); 2255 return; 2256 } 2257 2258 if (sc->sc_int_delay != fxp_int_delay || 2259 sc->sc_bundle_max != fxp_bundle_max) { 2260 sc->sc_int_delay = fxp_int_delay; 2261 sc->sc_bundle_max = fxp_bundle_max; 2262 printf("%s: Microcode loaded: int delay: %d usec, " 2263 "max bundle: %d\n", sc->sc_dev.dv_xname, 2264 sc->sc_int_delay, 2265 uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max); 2266 } 2267 2268 sc->sc_flags |= FXPF_UCODE_LOADED; 2269 } 2270 2271 int 2272 fxp_enable(struct fxp_softc *sc) 2273 { 2274 2275 if (sc->sc_enabled == 0 && sc->sc_enable != NULL) { 2276 if ((*sc->sc_enable)(sc) != 0) { 2277 printf("%s: device enable failed\n", 2278 sc->sc_dev.dv_xname); 2279 return (EIO); 2280 } 2281 } 2282 2283 sc->sc_enabled = 1; 2284 return (0); 2285 } 2286 2287 void 2288 fxp_disable(struct fxp_softc *sc) 2289 { 2290 2291 if (sc->sc_enabled != 0 && sc->sc_disable != NULL) { 2292 (*sc->sc_disable)(sc); 2293 sc->sc_enabled = 0; 2294 } 2295 } 2296 2297 /* 2298 * fxp_activate: 2299 * 2300 * Handle device activation/deactivation requests. 2301 */ 2302 int 2303 fxp_activate(struct device *self, enum devact act) 2304 { 2305 struct fxp_softc *sc = (void *) self; 2306 int s, error = 0; 2307 2308 s = splnet(); 2309 switch (act) { 2310 case DVACT_ACTIVATE: 2311 error = EOPNOTSUPP; 2312 break; 2313 2314 case DVACT_DEACTIVATE: 2315 if (sc->sc_flags & FXPF_MII) 2316 mii_activate(&sc->sc_mii, act, MII_PHY_ANY, 2317 MII_OFFSET_ANY); 2318 if_deactivate(&sc->sc_ethercom.ec_if); 2319 break; 2320 } 2321 splx(s); 2322 2323 return (error); 2324 } 2325 2326 /* 2327 * fxp_detach: 2328 * 2329 * Detach an i82557 interface. 2330 */ 2331 int 2332 fxp_detach(struct fxp_softc *sc) 2333 { 2334 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2335 int i; 2336 2337 /* Succeed now if there's no work to do. */ 2338 if ((sc->sc_flags & FXPF_ATTACHED) == 0) 2339 return (0); 2340 2341 /* Unhook our tick handler. */ 2342 callout_stop(&sc->sc_callout); 2343 2344 if (sc->sc_flags & FXPF_MII) { 2345 /* Detach all PHYs */ 2346 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 2347 } 2348 2349 /* Delete all remaining media. */ 2350 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 2351 2352 #if NRND > 0 2353 rnd_detach_source(&sc->rnd_source); 2354 #endif 2355 ether_ifdetach(ifp); 2356 if_detach(ifp); 2357 2358 for (i = 0; i < FXP_NRFABUFS; i++) { 2359 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmaps[i]); 2360 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmaps[i]); 2361 } 2362 2363 for (i = 0; i < FXP_NTXCB; i++) { 2364 bus_dmamap_unload(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2365 bus_dmamap_destroy(sc->sc_dmat, FXP_DSTX(sc, i)->txs_dmamap); 2366 } 2367 2368 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 2369 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 2370 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2371 sizeof(struct fxp_control_data)); 2372 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2373 2374 shutdownhook_disestablish(sc->sc_sdhook); 2375 powerhook_disestablish(sc->sc_powerhook); 2376 2377 return (0); 2378 } 2379
Indexes created Sat Sep 27 14:09:57 GMT 2025